1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 *****************************************************************************/ 66 67 #ifndef __iwl_prph_h__ 68 #define __iwl_prph_h__ 69 70 /* 71 * Registers in this file are internal, not PCI bus memory mapped. 72 * Driver accesses these via HBUS_TARG_PRPH_* registers. 73 */ 74 #define PRPH_BASE (0x00000) 75 #define PRPH_END (0xFFFFF) 76 77 /* APMG (power management) constants */ 78 #define APMG_BASE (PRPH_BASE + 0x3000) 79 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) 80 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) 81 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) 82 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) 83 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) 84 #define APMG_RFKILL_REG (APMG_BASE + 0x0014) 85 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) 86 #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) 87 #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058) 88 #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C) 89 90 #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 91 #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 92 #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 93 94 #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 95 #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 96 #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 97 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 98 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 99 #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 100 #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 101 102 #define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200) 103 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 104 #define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000) 105 106 #define APMG_RTC_INT_STT_RFKILL (0x10000000) 107 108 /* Device system time */ 109 #define DEVICE_SYSTEM_TIME_REG 0xA0206C 110 111 /* Device NMI register */ 112 #define DEVICE_SET_NMI_REG 0x00a01c30 113 #define DEVICE_SET_NMI_VAL_HW BIT(0) 114 #define DEVICE_SET_NMI_VAL_DRV BIT(7) 115 #define DEVICE_SET_NMI_8000_REG 0x00a01c24 116 #define DEVICE_SET_NMI_8000_VAL 0x1000000 117 118 /* Shared registers (0x0..0x3ff, via target indirect or periphery */ 119 #define SHR_BASE 0x00a10000 120 121 /* Shared GP1 register */ 122 #define SHR_APMG_GP1_REG 0x01dc 123 #define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG) 124 #define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004 125 #define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000 126 127 /* Shared DL_CFG register */ 128 #define SHR_APMG_DL_CFG_REG 0x01c4 129 #define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG) 130 #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0 131 #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080 132 #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100 133 134 /* Shared APMG_XTAL_CFG register */ 135 #define SHR_APMG_XTAL_CFG_REG 0x1c0 136 #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000 137 138 /* 139 * Device reset for family 8000 140 * write to bit 24 in order to reset the CPU 141 */ 142 #define RELEASE_CPU_RESET (0x300C) 143 #define RELEASE_CPU_RESET_BIT BIT(24) 144 145 /***************************************************************************** 146 * 7000/3000 series SHR DTS addresses * 147 *****************************************************************************/ 148 149 #define SHR_MISC_WFM_DTS_EN (0x00a10024) 150 #define DTSC_CFG_MODE (0x00a10604) 151 #define DTSC_VREF_AVG (0x00a10648) 152 #define DTSC_VREF5_AVG (0x00a1064c) 153 #define DTSC_CFG_MODE_PERIODIC (0x2) 154 #define DTSC_PTAT_AVG (0x00a10650) 155 156 157 /** 158 * Tx Scheduler 159 * 160 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 161 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 162 * host DRAM. It steers each frame's Tx command (which contains the frame 163 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 164 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 165 * but one DMA channel may take input from several queues. 166 * 167 * Tx DMA FIFOs have dedicated purposes. 168 * 169 * For 5000 series and up, they are used differently 170 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 171 * 172 * 0 -- EDCA BK (background) frames, lowest priority 173 * 1 -- EDCA BE (best effort) frames, normal priority 174 * 2 -- EDCA VI (video) frames, higher priority 175 * 3 -- EDCA VO (voice) and management frames, highest priority 176 * 4 -- unused 177 * 5 -- unused 178 * 6 -- unused 179 * 7 -- Commands 180 * 181 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 182 * In addition, driver can map the remaining queues to Tx DMA/FIFO 183 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 184 * 185 * The driver sets up each queue to work in one of two modes: 186 * 187 * 1) Scheduler-Ack, in which the scheduler automatically supports a 188 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 189 * contains TFDs for a unique combination of Recipient Address (RA) 190 * and Traffic Identifier (TID), that is, traffic of a given 191 * Quality-Of-Service (QOS) priority, destined for a single station. 192 * 193 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 194 * each frame within the BA window, including whether it's been transmitted, 195 * and whether it's been acknowledged by the receiving station. The device 196 * automatically processes block-acks received from the receiving STA, 197 * and reschedules un-acked frames to be retransmitted (successful 198 * Tx completion may end up being out-of-order). 199 * 200 * The driver must maintain the queue's Byte Count table in host DRAM 201 * for this mode. 202 * This mode does not support fragmentation. 203 * 204 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 205 * The device may automatically retry Tx, but will retry only one frame 206 * at a time, until receiving ACK from receiving station, or reaching 207 * retry limit and giving up. 208 * 209 * The command queue (#4/#9) must use this mode! 210 * This mode does not require use of the Byte Count table in host DRAM. 211 * 212 * Driver controls scheduler operation via 3 means: 213 * 1) Scheduler registers 214 * 2) Shared scheduler data base in internal SRAM 215 * 3) Shared data in host DRAM 216 * 217 * Initialization: 218 * 219 * When loading, driver should allocate memory for: 220 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 221 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 222 * (1024 bytes for each queue). 223 * 224 * After receiving "Alive" response from uCode, driver must initialize 225 * the scheduler (especially for queue #4/#9, the command queue, otherwise 226 * the driver can't issue commands!): 227 */ 228 #define SCD_MEM_LOWER_BOUND (0x0000) 229 230 /** 231 * Max Tx window size is the max number of contiguous TFDs that the scheduler 232 * can keep track of at one time when creating block-ack chains of frames. 233 * Note that "64" matches the number of ack bits in a block-ack packet. 234 */ 235 #define SCD_WIN_SIZE 64 236 #define SCD_FRAME_LIMIT 64 237 238 #define SCD_TXFIFO_POS_TID (0) 239 #define SCD_TXFIFO_POS_RA (4) 240 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 241 242 /* agn SCD */ 243 #define SCD_QUEUE_STTS_REG_POS_TXF (0) 244 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 245 #define SCD_QUEUE_STTS_REG_POS_WSL (4) 246 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 247 #define SCD_QUEUE_STTS_REG_MSK (0x017F0000) 248 249 #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 250 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 251 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 252 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 253 #define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 254 #define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 255 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 256 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 257 #define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0) 258 #define SCD_GP_CTRL_AUTO_ACTIVE_MODE BIT(18) 259 260 /* Context Data */ 261 #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600) 262 #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) 263 264 /* Tx status */ 265 #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) 266 #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) 267 268 /* Translation Data */ 269 #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) 270 #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808) 271 272 #define SCD_CONTEXT_QUEUE_OFFSET(x)\ 273 (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 274 275 #define SCD_TX_STTS_QUEUE_OFFSET(x)\ 276 (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 277 278 #define SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 279 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 280 281 #define SCD_BASE (PRPH_BASE + 0xa02c00) 282 283 #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0) 284 #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8) 285 #define SCD_AIT (SCD_BASE + 0x0c) 286 #define SCD_TXFACT (SCD_BASE + 0x10) 287 #define SCD_ACTIVE (SCD_BASE + 0x14) 288 #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8) 289 #define SCD_CHAINEXT_EN (SCD_BASE + 0x244) 290 #define SCD_AGGR_SEL (SCD_BASE + 0x248) 291 #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108) 292 #define SCD_GP_CTRL (SCD_BASE + 0x1a8) 293 #define SCD_EN_CTRL (SCD_BASE + 0x254) 294 295 /*********************** END TX SCHEDULER *************************************/ 296 297 /* tcp checksum offload */ 298 #define RX_EN_CSUM (0x00a00d88) 299 300 /* Oscillator clock */ 301 #define OSC_CLK (0xa04068) 302 #define OSC_CLK_FORCE_CONTROL (0x8) 303 304 #define FH_UCODE_LOAD_STATUS (0x1AF0) 305 306 /* 307 * Replacing FH_UCODE_LOAD_STATUS 308 * This register is writen by driver and is read by uCode during boot flow. 309 * Note this address is cleared after MAC reset. 310 */ 311 #define UREG_UCODE_LOAD_STATUS (0xa05c40) 312 313 #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78) 314 #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C) 315 316 #define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000) 317 #define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400) 318 319 /* Rx FIFO */ 320 #define RXF_SIZE_ADDR (0xa00c88) 321 #define RXF_RD_D_SPACE (0xa00c40) 322 #define RXF_RD_WR_PTR (0xa00c50) 323 #define RXF_RD_RD_PTR (0xa00c54) 324 #define RXF_RD_FENCE_PTR (0xa00c4c) 325 #define RXF_SET_FENCE_MODE (0xa00c14) 326 #define RXF_LD_WR2FENCE (0xa00c1c) 327 #define RXF_FIFO_RD_FENCE_INC (0xa00c68) 328 #define RXF_SIZE_BYTE_CND_POS (7) 329 #define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS) 330 #define RXF_DIFF_FROM_PREV (0x200) 331 332 #define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10) 333 #define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c) 334 335 /* Tx FIFO */ 336 #define TXF_FIFO_ITEM_CNT (0xa00438) 337 #define TXF_WR_PTR (0xa00414) 338 #define TXF_RD_PTR (0xa00410) 339 #define TXF_FENCE_PTR (0xa00418) 340 #define TXF_LOCK_FENCE (0xa00424) 341 #define TXF_LARC_NUM (0xa0043c) 342 #define TXF_READ_MODIFY_DATA (0xa00448) 343 #define TXF_READ_MODIFY_ADDR (0xa0044c) 344 345 /* UMAC Internal Tx Fifo */ 346 #define TXF_CPU2_FIFO_ITEM_CNT (0xA00538) 347 #define TXF_CPU2_WR_PTR (0xA00514) 348 #define TXF_CPU2_RD_PTR (0xA00510) 349 #define TXF_CPU2_FENCE_PTR (0xA00518) 350 #define TXF_CPU2_LOCK_FENCE (0xA00524) 351 #define TXF_CPU2_NUM (0xA0053C) 352 #define TXF_CPU2_READ_MODIFY_DATA (0xA00548) 353 #define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C) 354 355 /* Radio registers access */ 356 #define RSP_RADIO_CMD (0xa02804) 357 #define RSP_RADIO_RDDAT (0xa02814) 358 #define RADIO_RSP_ADDR_POS (6) 359 #define RADIO_RSP_RD_CMD (3) 360 361 /* FW monitor */ 362 #define MON_BUFF_SAMPLE_CTL (0xa03c00) 363 #define MON_BUFF_BASE_ADDR (0xa03c3c) 364 #define MON_BUFF_END_ADDR (0xa03c40) 365 #define MON_BUFF_WRPTR (0xa03c44) 366 #define MON_BUFF_CYCLE_CNT (0xa03c48) 367 368 #define MON_DMARB_RD_CTL_ADDR (0xa03c60) 369 #define MON_DMARB_RD_DATA_ADDR (0xa03c5c) 370 371 #define DBGC_IN_SAMPLE (0xa03c00) 372 373 /* enable the ID buf for read */ 374 #define WFPM_PS_CTL_CLR 0xA0300C 375 #define WFMP_MAC_ADDR_0 0xA03080 376 #define WFMP_MAC_ADDR_1 0xA03084 377 #define LMPM_PMG_EN 0xA01CEC 378 #define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078 379 #define RFIC_REG_RD 0xAD0470 380 #define WFPM_CTRL_REG 0xA03030 381 enum { 382 ENABLE_WFPM = BIT(31), 383 WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000, 384 }; 385 386 #define AUX_MISC_REG 0xA200B0 387 enum { 388 HW_STEP_LOCATION_BITS = 24, 389 }; 390 391 #define AUX_MISC_MASTER1_EN 0xA20818 392 enum aux_misc_master1_en { 393 AUX_MISC_MASTER1_EN_SBE_MSK = 0x1, 394 }; 395 396 #define AUX_MISC_MASTER1_SMPHR_STATUS 0xA20800 397 #define RSA_ENABLE 0xA24B08 398 #define PREG_AUX_BUS_WPROT_0 0xA04CC0 399 #define SB_CPU_1_STATUS 0xA01E30 400 #define SB_CPU_2_STATUS 0xA01E34 401 402 /* FW chicken bits */ 403 #define LMPM_CHICK 0xA01FF8 404 enum { 405 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0), 406 }; 407 408 /* FW chicken bits */ 409 #define LMPM_PAGE_PASS_NOTIF 0xA03824 410 enum { 411 LMPM_PAGE_PASS_NOTIF_POS = BIT(20), 412 }; 413 414 #define UREG_CHICK (0xA05C00) 415 #define UREG_CHICK_MSI_ENABLE BIT(24) 416 #define UREG_CHICK_MSIX_ENABLE BIT(25) 417 #endif /* __iwl_prph_h__ */ 418