1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/types.h> 8 #include <linux/slab.h> 9 #include <linux/export.h> 10 #include <linux/etherdevice.h> 11 #include <linux/pci.h> 12 #include <linux/firmware.h> 13 14 #include "iwl-drv.h" 15 #include "iwl-modparams.h" 16 #include "iwl-nvm-parse.h" 17 #include "iwl-prph.h" 18 #include "iwl-io.h" 19 #include "iwl-csr.h" 20 #include "fw/acpi.h" 21 #include "fw/api/nvm-reg.h" 22 #include "fw/api/commands.h" 23 #include "fw/api/cmdhdr.h" 24 #include "fw/img.h" 25 #include "mei/iwl-mei.h" 26 27 /* NVM offsets (in words) definitions */ 28 enum nvm_offsets { 29 /* NVM HW-Section offset (in words) definitions */ 30 SUBSYSTEM_ID = 0x0A, 31 HW_ADDR = 0x15, 32 33 /* NVM SW-Section offset (in words) definitions */ 34 NVM_SW_SECTION = 0x1C0, 35 NVM_VERSION = 0, 36 RADIO_CFG = 1, 37 SKU = 2, 38 N_HW_ADDRS = 3, 39 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 40 41 /* NVM calibration section offset (in words) definitions */ 42 NVM_CALIB_SECTION = 0x2B8, 43 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 44 45 /* NVM REGULATORY -Section offset (in words) definitions */ 46 NVM_CHANNELS_SDP = 0, 47 }; 48 49 enum ext_nvm_offsets { 50 /* NVM HW-Section offset (in words) definitions */ 51 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 52 53 /* NVM SW-Section offset (in words) definitions */ 54 NVM_VERSION_EXT_NVM = 0, 55 N_HW_ADDRS_FAMILY_8000 = 3, 56 57 /* NVM PHY_SKU-Section offset (in words) definitions */ 58 RADIO_CFG_FAMILY_EXT_NVM = 0, 59 SKU_FAMILY_8000 = 2, 60 61 /* NVM REGULATORY -Section offset (in words) definitions */ 62 NVM_CHANNELS_EXTENDED = 0, 63 NVM_LAR_OFFSET_OLD = 0x4C7, 64 NVM_LAR_OFFSET = 0x507, 65 NVM_LAR_ENABLED = 0x7, 66 }; 67 68 /* SKU Capabilities (actual values from NVM definition) */ 69 enum nvm_sku_bits { 70 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 71 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 72 NVM_SKU_CAP_11N_ENABLE = BIT(2), 73 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 74 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 75 }; 76 77 /* 78 * These are the channel numbers in the order that they are stored in the NVM 79 */ 80 static const u16 iwl_nvm_channels[] = { 81 /* 2.4 GHz */ 82 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 83 /* 5 GHz */ 84 36, 40, 44, 48, 52, 56, 60, 64, 85 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 86 149, 153, 157, 161, 165 87 }; 88 89 static const u16 iwl_ext_nvm_channels[] = { 90 /* 2.4 GHz */ 91 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 92 /* 5 GHz */ 93 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 94 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 95 149, 153, 157, 161, 165, 169, 173, 177, 181 96 }; 97 98 static const u16 iwl_uhb_nvm_channels[] = { 99 /* 2.4 GHz */ 100 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 101 /* 5 GHz */ 102 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 103 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 104 149, 153, 157, 161, 165, 169, 173, 177, 181, 105 /* 6-7 GHz */ 106 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 107 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 108 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 109 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233 110 }; 111 112 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 113 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 114 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels) 115 #define NUM_2GHZ_CHANNELS 14 116 #define NUM_5GHZ_CHANNELS 37 117 #define FIRST_2GHZ_HT_MINUS 5 118 #define LAST_2GHZ_HT_PLUS 9 119 #define N_HW_ADDR_MASK 0xF 120 121 /* rate data (static) */ 122 static struct ieee80211_rate iwl_cfg80211_rates[] = { 123 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 124 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 125 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 126 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 127 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 128 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 129 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 130 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 131 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 132 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 133 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 134 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 135 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 136 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 137 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 138 }; 139 #define RATES_24_OFFS 0 140 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 141 #define RATES_52_OFFS 4 142 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 143 144 /** 145 * enum iwl_nvm_channel_flags - channel flags in NVM 146 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 147 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 148 * @NVM_CHANNEL_ACTIVE: active scanning allowed 149 * @NVM_CHANNEL_RADAR: radar detection required 150 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 151 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 152 * on same channel on 2.4 or same UNII band on 5.2 153 * @NVM_CHANNEL_UNIFORM: uniform spreading required 154 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 155 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 156 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 157 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 158 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 159 */ 160 enum iwl_nvm_channel_flags { 161 NVM_CHANNEL_VALID = BIT(0), 162 NVM_CHANNEL_IBSS = BIT(1), 163 NVM_CHANNEL_ACTIVE = BIT(3), 164 NVM_CHANNEL_RADAR = BIT(4), 165 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 166 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 167 NVM_CHANNEL_UNIFORM = BIT(7), 168 NVM_CHANNEL_20MHZ = BIT(8), 169 NVM_CHANNEL_40MHZ = BIT(9), 170 NVM_CHANNEL_80MHZ = BIT(10), 171 NVM_CHANNEL_160MHZ = BIT(11), 172 NVM_CHANNEL_DC_HIGH = BIT(12), 173 }; 174 175 /** 176 * enum iwl_reg_capa_flags_v1 - global flags applied for the whole regulatory 177 * domain. 178 * @REG_CAPA_V1_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 179 * 2.4Ghz band is allowed. 180 * @REG_CAPA_V1_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 181 * 5Ghz band is allowed. 182 * @REG_CAPA_V1_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 183 * for this regulatory domain (valid only in 5Ghz). 184 * @REG_CAPA_V1_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 185 * for this regulatory domain (valid only in 5Ghz). 186 * @REG_CAPA_V1_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 187 * @REG_CAPA_V1_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 188 * @REG_CAPA_V1_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden 189 * for this regulatory domain (valid only in 5Ghz). 190 * @REG_CAPA_V1_DC_HIGH_ENABLED: DC HIGH allowed. 191 * @REG_CAPA_V1_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 192 */ 193 enum iwl_reg_capa_flags_v1 { 194 REG_CAPA_V1_BF_CCD_LOW_BAND = BIT(0), 195 REG_CAPA_V1_BF_CCD_HIGH_BAND = BIT(1), 196 REG_CAPA_V1_160MHZ_ALLOWED = BIT(2), 197 REG_CAPA_V1_80MHZ_ALLOWED = BIT(3), 198 REG_CAPA_V1_MCS_8_ALLOWED = BIT(4), 199 REG_CAPA_V1_MCS_9_ALLOWED = BIT(5), 200 REG_CAPA_V1_40MHZ_FORBIDDEN = BIT(7), 201 REG_CAPA_V1_DC_HIGH_ENABLED = BIT(9), 202 REG_CAPA_V1_11AX_DISABLED = BIT(10), 203 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_1 */ 204 205 /** 206 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory 207 * domain (version 2). 208 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are 209 * disabled. 210 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 211 * 2.4Ghz band is allowed. 212 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 213 * 5Ghz band is allowed. 214 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 215 * for this regulatory domain (valid only in 5Ghz). 216 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 217 * for this regulatory domain (valid only in 5Ghz). 218 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 219 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 220 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118, 221 * 126, 122) are disabled. 222 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed 223 * for this regulatory domain (uvalid only in 5Ghz). 224 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 225 */ 226 enum iwl_reg_capa_flags_v2 { 227 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0), 228 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1), 229 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2), 230 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3), 231 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4), 232 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5), 233 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6), 234 REG_CAPA_V2_WEATHER_DISABLED = BIT(7), 235 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8), 236 REG_CAPA_V2_11AX_DISABLED = BIT(10), 237 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_2 */ 238 239 /** 240 * enum iwl_reg_capa_flags_v4 - global flags applied for the whole regulatory 241 * domain. 242 * @REG_CAPA_V4_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 243 * for this regulatory domain (valid only in 5Ghz). 244 * @REG_CAPA_V4_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 245 * for this regulatory domain (valid only in 5Ghz). 246 * @REG_CAPA_V4_MCS_12_ALLOWED: 11ac with MCS 12 is allowed. 247 * @REG_CAPA_V4_MCS_13_ALLOWED: 11ac with MCS 13 is allowed. 248 * @REG_CAPA_V4_11BE_DISABLED: 11be is forbidden for this regulatory domain. 249 * @REG_CAPA_V4_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 250 * @REG_CAPA_V4_320MHZ_ALLOWED: 11be channel with a width of 320Mhz is allowed 251 * for this regulatory domain (valid only in 5GHz). 252 */ 253 enum iwl_reg_capa_flags_v4 { 254 REG_CAPA_V4_160MHZ_ALLOWED = BIT(3), 255 REG_CAPA_V4_80MHZ_ALLOWED = BIT(4), 256 REG_CAPA_V4_MCS_12_ALLOWED = BIT(5), 257 REG_CAPA_V4_MCS_13_ALLOWED = BIT(6), 258 REG_CAPA_V4_11BE_DISABLED = BIT(8), 259 REG_CAPA_V4_11AX_DISABLED = BIT(13), 260 REG_CAPA_V4_320MHZ_ALLOWED = BIT(16), 261 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_4 */ 262 263 /* 264 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the 265 * MCC update command response. 266 */ 267 #define REG_CAPA_V2_RESP_VER 6 268 269 /* API v4 for reg_capa_flags is relevant from version 8 and onwards of the 270 * MCC update command response. 271 */ 272 #define REG_CAPA_V4_RESP_VER 8 273 274 /** 275 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for 276 * handling the different APIs of reg_capa_flags. 277 * 278 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed 279 * for this regulatory domain. 280 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed 281 * for this regulatory domain (valid only in 5 and 6 Ghz). 282 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed 283 * for this regulatory domain (valid only in 5 and 6 Ghz). 284 * @allow_320mhz: 11be channel with a width of 320Mhz is allowed 285 * for this regulatory domain (valid only in 6 Ghz). 286 * @disable_11ax: 11ax is forbidden for this regulatory domain. 287 * @disable_11be: 11be is forbidden for this regulatory domain. 288 */ 289 struct iwl_reg_capa { 290 bool allow_40mhz; 291 bool allow_80mhz; 292 bool allow_160mhz; 293 bool allow_320mhz; 294 bool disable_11ax; 295 bool disable_11be; 296 }; 297 298 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 299 int chan, u32 flags) 300 { 301 #define CHECK_AND_PRINT_I(x) \ 302 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 303 304 if (!(flags & NVM_CHANNEL_VALID)) { 305 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 306 chan, flags); 307 return; 308 } 309 310 /* Note: already can print up to 101 characters, 110 is the limit! */ 311 IWL_DEBUG_DEV(dev, level, 312 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 313 chan, flags, 314 CHECK_AND_PRINT_I(VALID), 315 CHECK_AND_PRINT_I(IBSS), 316 CHECK_AND_PRINT_I(ACTIVE), 317 CHECK_AND_PRINT_I(RADAR), 318 CHECK_AND_PRINT_I(INDOOR_ONLY), 319 CHECK_AND_PRINT_I(GO_CONCURRENT), 320 CHECK_AND_PRINT_I(UNIFORM), 321 CHECK_AND_PRINT_I(20MHZ), 322 CHECK_AND_PRINT_I(40MHZ), 323 CHECK_AND_PRINT_I(80MHZ), 324 CHECK_AND_PRINT_I(160MHZ), 325 CHECK_AND_PRINT_I(DC_HIGH)); 326 #undef CHECK_AND_PRINT_I 327 } 328 329 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band, 330 u32 nvm_flags, const struct iwl_cfg *cfg) 331 { 332 u32 flags = IEEE80211_CHAN_NO_HT40; 333 334 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) { 335 if (ch_num <= LAST_2GHZ_HT_PLUS) 336 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 337 if (ch_num >= FIRST_2GHZ_HT_MINUS) 338 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 339 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 340 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 341 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 342 else 343 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 344 } 345 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 346 flags |= IEEE80211_CHAN_NO_80MHZ; 347 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 348 flags |= IEEE80211_CHAN_NO_160MHZ; 349 350 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 351 flags |= IEEE80211_CHAN_NO_IR; 352 353 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 354 flags |= IEEE80211_CHAN_NO_IR; 355 356 if (nvm_flags & NVM_CHANNEL_RADAR) 357 flags |= IEEE80211_CHAN_RADAR; 358 359 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 360 flags |= IEEE80211_CHAN_INDOOR_ONLY; 361 362 /* Set the GO concurrent flag only in case that NO_IR is set. 363 * Otherwise it is meaningless 364 */ 365 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 366 (flags & IEEE80211_CHAN_NO_IR)) 367 flags |= IEEE80211_CHAN_IR_CONCURRENT; 368 369 return flags; 370 } 371 372 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx) 373 { 374 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) { 375 return NL80211_BAND_6GHZ; 376 } 377 378 if (ch_idx >= NUM_2GHZ_CHANNELS) 379 return NL80211_BAND_5GHZ; 380 return NL80211_BAND_2GHZ; 381 } 382 383 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 384 struct iwl_nvm_data *data, 385 const void * const nvm_ch_flags, 386 u32 sbands_flags, bool v4) 387 { 388 int ch_idx; 389 int n_channels = 0; 390 struct ieee80211_channel *channel; 391 u32 ch_flags; 392 int num_of_ch; 393 const u16 *nvm_chan; 394 395 if (cfg->uhb_supported) { 396 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB; 397 nvm_chan = iwl_uhb_nvm_channels; 398 } else if (cfg->nvm_type == IWL_NVM_EXT) { 399 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 400 nvm_chan = iwl_ext_nvm_channels; 401 } else { 402 num_of_ch = IWL_NVM_NUM_CHANNELS; 403 nvm_chan = iwl_nvm_channels; 404 } 405 406 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 407 enum nl80211_band band = 408 iwl_nl80211_band_from_channel_idx(ch_idx); 409 410 if (v4) 411 ch_flags = 412 __le32_to_cpup((const __le32 *)nvm_ch_flags + ch_idx); 413 else 414 ch_flags = 415 __le16_to_cpup((const __le16 *)nvm_ch_flags + ch_idx); 416 417 if (band == NL80211_BAND_5GHZ && 418 !data->sku_cap_band_52ghz_enable) 419 continue; 420 421 /* workaround to disable wide channels in 5GHz */ 422 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 423 band == NL80211_BAND_5GHZ) { 424 ch_flags &= ~(NVM_CHANNEL_40MHZ | 425 NVM_CHANNEL_80MHZ | 426 NVM_CHANNEL_160MHZ); 427 } 428 429 if (ch_flags & NVM_CHANNEL_160MHZ) 430 data->vht160_supported = true; 431 432 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 433 !(ch_flags & NVM_CHANNEL_VALID)) { 434 /* 435 * Channels might become valid later if lar is 436 * supported, hence we still want to add them to 437 * the list of supported channels to cfg80211. 438 */ 439 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 440 nvm_chan[ch_idx], ch_flags); 441 continue; 442 } 443 444 channel = &data->channels[n_channels]; 445 n_channels++; 446 447 channel->hw_value = nvm_chan[ch_idx]; 448 channel->band = band; 449 channel->center_freq = 450 ieee80211_channel_to_frequency( 451 channel->hw_value, channel->band); 452 453 /* Initialize regulatory-based run-time data */ 454 455 /* 456 * Default value - highest tx power value. max_power 457 * is not used in mvm, and is used for backwards compatibility 458 */ 459 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 460 461 /* don't put limitations in case we're using LAR */ 462 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 463 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 464 ch_idx, band, 465 ch_flags, cfg); 466 else 467 channel->flags = 0; 468 469 /* TODO: Don't put limitations on UHB devices as we still don't 470 * have NVM for them 471 */ 472 if (cfg->uhb_supported) 473 channel->flags = 0; 474 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 475 channel->hw_value, ch_flags); 476 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 477 channel->hw_value, channel->max_power); 478 } 479 480 return n_channels; 481 } 482 483 static void iwl_init_vht_hw_capab(struct iwl_trans *trans, 484 struct iwl_nvm_data *data, 485 struct ieee80211_sta_vht_cap *vht_cap, 486 u8 tx_chains, u8 rx_chains) 487 { 488 const struct iwl_cfg *cfg = trans->cfg; 489 int num_rx_ants = num_of_ant(rx_chains); 490 int num_tx_ants = num_of_ant(tx_chains); 491 492 vht_cap->vht_supported = true; 493 494 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 495 IEEE80211_VHT_CAP_RXSTBC_1 | 496 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 497 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 498 IEEE80211_VHT_MAX_AMPDU_1024K << 499 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 500 501 if (!trans->cfg->ht_params->stbc) 502 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXSTBC_MASK; 503 504 if (data->vht160_supported) 505 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 506 IEEE80211_VHT_CAP_SHORT_GI_160; 507 508 if (cfg->vht_mu_mimo_supported) 509 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 510 511 if (cfg->ht_params->ldpc) 512 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 513 514 if (data->sku_cap_mimo_disabled) { 515 num_rx_ants = 1; 516 num_tx_ants = 1; 517 } 518 519 if (trans->cfg->ht_params->stbc && num_tx_ants > 1) 520 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 521 else 522 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 523 524 switch (iwlwifi_mod_params.amsdu_size) { 525 case IWL_AMSDU_DEF: 526 if (trans->trans_cfg->mq_rx_supported) 527 vht_cap->cap |= 528 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 529 else 530 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 531 break; 532 case IWL_AMSDU_2K: 533 if (trans->trans_cfg->mq_rx_supported) 534 vht_cap->cap |= 535 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 536 else 537 WARN(1, "RB size of 2K is not supported by this device\n"); 538 break; 539 case IWL_AMSDU_4K: 540 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 541 break; 542 case IWL_AMSDU_8K: 543 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 544 break; 545 case IWL_AMSDU_12K: 546 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 547 break; 548 default: 549 break; 550 } 551 552 vht_cap->vht_mcs.rx_mcs_map = 553 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 554 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 555 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 556 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 557 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 558 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 559 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 560 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 561 562 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 563 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 564 /* this works because NOT_SUPPORTED == 3 */ 565 vht_cap->vht_mcs.rx_mcs_map |= 566 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 567 } 568 569 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 570 571 vht_cap->vht_mcs.tx_highest |= 572 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 573 } 574 575 static const u8 iwl_vendor_caps[] = { 576 0xdd, /* vendor element */ 577 0x06, /* length */ 578 0x00, 0x17, 0x35, /* Intel OUI */ 579 0x08, /* type (Intel Capabilities) */ 580 /* followed by 16 bits of capabilities */ 581 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0) 582 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE, 583 0x00 584 }; 585 586 static const struct ieee80211_sband_iftype_data iwl_he_eht_capa[] = { 587 { 588 .types_mask = BIT(NL80211_IFTYPE_STATION), 589 .he_cap = { 590 .has_he = true, 591 .he_cap_elem = { 592 .mac_cap_info[0] = 593 IEEE80211_HE_MAC_CAP0_HTC_HE, 594 .mac_cap_info[1] = 595 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 596 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 597 .mac_cap_info[2] = 598 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP, 599 .mac_cap_info[3] = 600 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 601 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS, 602 .mac_cap_info[4] = 603 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU | 604 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 605 .mac_cap_info[5] = 606 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 607 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 608 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU | 609 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS | 610 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, 611 .phy_cap_info[1] = 612 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 613 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 614 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 615 .phy_cap_info[2] = 616 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 617 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 618 .phy_cap_info[3] = 619 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 620 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 621 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 622 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 623 .phy_cap_info[4] = 624 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 625 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 626 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 627 .phy_cap_info[6] = 628 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 629 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB | 630 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 631 .phy_cap_info[7] = 632 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 633 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 634 .phy_cap_info[8] = 635 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 636 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 637 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 638 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 639 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 640 .phy_cap_info[9] = 641 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 642 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 643 (IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED << 644 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS), 645 .phy_cap_info[10] = 646 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF, 647 }, 648 /* 649 * Set default Tx/Rx HE MCS NSS Support field. 650 * Indicate support for up to 2 spatial streams and all 651 * MCS, without any special cases 652 */ 653 .he_mcs_nss_supp = { 654 .rx_mcs_80 = cpu_to_le16(0xfffa), 655 .tx_mcs_80 = cpu_to_le16(0xfffa), 656 .rx_mcs_160 = cpu_to_le16(0xfffa), 657 .tx_mcs_160 = cpu_to_le16(0xfffa), 658 .rx_mcs_80p80 = cpu_to_le16(0xffff), 659 .tx_mcs_80p80 = cpu_to_le16(0xffff), 660 }, 661 /* 662 * Set default PPE thresholds, with PPET16 set to 0, 663 * PPET8 set to 7 664 */ 665 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 666 }, 667 .eht_cap = { 668 .has_eht = true, 669 .eht_cap_elem = { 670 .mac_cap_info[0] = 671 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 672 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 673 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 674 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2, 675 .phy_cap_info[0] = 676 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ | 677 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 678 IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO | 679 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE | 680 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK, 681 .phy_cap_info[1] = 682 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK | 683 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK, 684 .phy_cap_info[3] = 685 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 686 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 687 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 688 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 689 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 690 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK | 691 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK, 692 693 .phy_cap_info[4] = 694 IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO | 695 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 696 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI, 697 .phy_cap_info[5] = 698 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | 699 IEEE80211_EHT_PHY_CAP5_TX_LESS_242_TONE_RU_SUPP | 700 IEEE80211_EHT_PHY_CAP5_RX_LESS_242_TONE_RU_SUPP | 701 IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT, 702 .phy_cap_info[6] = 703 IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK | 704 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP, 705 .phy_cap_info[8] = 706 IEEE80211_EHT_PHY_CAP8_RX_1024QAM_WIDER_BW_DL_OFDMA | 707 IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA, 708 }, 709 710 /* For all MCS and bandwidth, set 2 NSS for both Tx and 711 * Rx - note we don't set the only_20mhz, but due to this 712 * being a union, it gets set correctly anyway. 713 */ 714 .eht_mcs_nss_supp = { 715 .bw._80 = { 716 .rx_tx_mcs9_max_nss = 0x22, 717 .rx_tx_mcs11_max_nss = 0x22, 718 .rx_tx_mcs13_max_nss = 0x22, 719 }, 720 .bw._160 = { 721 .rx_tx_mcs9_max_nss = 0x22, 722 .rx_tx_mcs11_max_nss = 0x22, 723 .rx_tx_mcs13_max_nss = 0x22, 724 }, 725 .bw._320 = { 726 .rx_tx_mcs9_max_nss = 0x22, 727 .rx_tx_mcs11_max_nss = 0x22, 728 .rx_tx_mcs13_max_nss = 0x22, 729 }, 730 }, 731 732 /* 733 * PPE thresholds for NSS = 2, and RU index bitmap set 734 * to 0xc. 735 */ 736 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 } 737 }, 738 }, 739 { 740 .types_mask = BIT(NL80211_IFTYPE_AP), 741 .he_cap = { 742 .has_he = true, 743 .he_cap_elem = { 744 .mac_cap_info[0] = 745 IEEE80211_HE_MAC_CAP0_HTC_HE, 746 .mac_cap_info[1] = 747 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 748 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 749 .mac_cap_info[3] = 750 IEEE80211_HE_MAC_CAP3_OMI_CONTROL, 751 .phy_cap_info[1] = 752 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 753 .phy_cap_info[2] = 754 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 755 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 756 .phy_cap_info[3] = 757 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 758 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 759 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 760 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 761 .phy_cap_info[6] = 762 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 763 .phy_cap_info[7] = 764 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 765 .phy_cap_info[8] = 766 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 767 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 768 .phy_cap_info[9] = 769 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED 770 << IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS, 771 }, 772 /* 773 * Set default Tx/Rx HE MCS NSS Support field. 774 * Indicate support for up to 2 spatial streams and all 775 * MCS, without any special cases 776 */ 777 .he_mcs_nss_supp = { 778 .rx_mcs_80 = cpu_to_le16(0xfffa), 779 .tx_mcs_80 = cpu_to_le16(0xfffa), 780 .rx_mcs_160 = cpu_to_le16(0xfffa), 781 .tx_mcs_160 = cpu_to_le16(0xfffa), 782 .rx_mcs_80p80 = cpu_to_le16(0xffff), 783 .tx_mcs_80p80 = cpu_to_le16(0xffff), 784 }, 785 /* 786 * Set default PPE thresholds, with PPET16 set to 0, 787 * PPET8 set to 7 788 */ 789 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 790 }, 791 .eht_cap = { 792 .has_eht = true, 793 .eht_cap_elem = { 794 .mac_cap_info[0] = 795 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 796 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 797 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 798 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2, 799 .phy_cap_info[0] = 800 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ | 801 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI, 802 .phy_cap_info[5] = 803 IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT, 804 }, 805 806 /* For all MCS and bandwidth, set 2 NSS for both Tx and 807 * Rx - note we don't set the only_20mhz, but due to this 808 * being a union, it gets set correctly anyway. 809 */ 810 .eht_mcs_nss_supp = { 811 .bw._80 = { 812 .rx_tx_mcs9_max_nss = 0x22, 813 .rx_tx_mcs11_max_nss = 0x22, 814 .rx_tx_mcs13_max_nss = 0x22, 815 }, 816 .bw._160 = { 817 .rx_tx_mcs9_max_nss = 0x22, 818 .rx_tx_mcs11_max_nss = 0x22, 819 .rx_tx_mcs13_max_nss = 0x22, 820 }, 821 .bw._320 = { 822 .rx_tx_mcs9_max_nss = 0x22, 823 .rx_tx_mcs11_max_nss = 0x22, 824 .rx_tx_mcs13_max_nss = 0x22, 825 }, 826 }, 827 828 /* 829 * PPE thresholds for NSS = 2, and RU index bitmap set 830 * to 0xc. 831 */ 832 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 } 833 }, 834 }, 835 }; 836 837 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans, 838 struct iwl_nvm_data *data, 839 struct ieee80211_supported_band *sband, 840 u8 tx_chains, u8 rx_chains) 841 { 842 struct ieee80211_sta_ht_cap ht_cap; 843 struct ieee80211_sta_vht_cap vht_cap = {}; 844 struct ieee80211_sband_iftype_data *iftype_data; 845 u16 he_6ghz_capa = 0; 846 u32 exp; 847 int i; 848 849 if (sband->band != NL80211_BAND_6GHZ) 850 return; 851 852 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */ 853 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ, 854 tx_chains, rx_chains); 855 WARN_ON(!ht_cap.ht_supported); 856 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains); 857 WARN_ON(!vht_cap.vht_supported); 858 859 he_6ghz_capa |= 860 u16_encode_bits(ht_cap.ampdu_density, 861 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START); 862 exp = u32_get_bits(vht_cap.cap, 863 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK); 864 he_6ghz_capa |= 865 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP); 866 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK); 867 he_6ghz_capa |= 868 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 869 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */ 870 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN) 871 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS; 872 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN) 873 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 874 875 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa); 876 877 /* we know it's writable - we set it before ourselves */ 878 iftype_data = (void *)(uintptr_t)sband->iftype_data; 879 for (i = 0; i < sband->n_iftype_data; i++) 880 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa); 881 } 882 883 static void 884 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans, 885 struct iwl_nvm_data *data, 886 struct ieee80211_supported_band *sband, 887 struct ieee80211_sband_iftype_data *iftype_data, 888 u8 tx_chains, u8 rx_chains, 889 const struct iwl_fw *fw) 890 { 891 bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP); 892 bool no_320; 893 894 no_320 = !trans->trans_cfg->integrated && 895 trans->pcie_link_speed < PCI_EXP_LNKSTA_CLS_8_0GB; 896 897 if (!data->sku_cap_11be_enable || iwlwifi_mod_params.disable_11be) 898 iftype_data->eht_cap.has_eht = false; 899 900 /* Advertise an A-MPDU exponent extension based on 901 * operating band 902 */ 903 if (sband->band == NL80211_BAND_6GHZ && iftype_data->eht_cap.has_eht) 904 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 905 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 906 else if (sband->band != NL80211_BAND_2GHZ) 907 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 908 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1; 909 else 910 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 911 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 912 913 switch (sband->band) { 914 case NL80211_BAND_2GHZ: 915 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 916 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 917 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] |= 918 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 919 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 920 break; 921 case NL80211_BAND_6GHZ: 922 if (!no_320) { 923 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |= 924 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 925 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[1] |= 926 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK; 927 } 928 fallthrough; 929 case NL80211_BAND_5GHZ: 930 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 931 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 932 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 933 break; 934 default: 935 WARN_ON(1); 936 break; 937 } 938 939 if ((tx_chains & rx_chains) == ANT_AB) { 940 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 941 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ; 942 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |= 943 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 944 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2; 945 if (!is_ap) { 946 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 947 IEEE80211_HE_PHY_CAP7_MAX_NC_2; 948 949 if (iftype_data->eht_cap.has_eht) { 950 /* 951 * Set the number of sounding dimensions for each 952 * bandwidth to 1 to indicate the maximal supported 953 * value of TXVECTOR parameter NUM_STS of 2 954 */ 955 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] |= 0x49; 956 957 /* 958 * Set the MAX NC to 1 to indicate sounding feedback of 959 * 2 supported by the beamfomee. 960 */ 961 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] |= 0x10; 962 } 963 } 964 } else { 965 if (iftype_data->eht_cap.has_eht) { 966 struct ieee80211_eht_mcs_nss_supp *mcs_nss = 967 &iftype_data->eht_cap.eht_mcs_nss_supp; 968 969 memset(mcs_nss, 0x11, sizeof(*mcs_nss)); 970 } 971 972 if (!is_ap) { 973 /* If not 2x2, we need to indicate 1x1 in the 974 * Midamble RX Max NSTS - but not for AP mode 975 */ 976 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &= 977 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 978 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 979 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 980 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 981 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 982 } 983 } 984 985 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210 && !is_ap) 986 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 987 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 988 989 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 990 case IWL_CFG_RF_TYPE_GF: 991 case IWL_CFG_RF_TYPE_MR: 992 case IWL_CFG_RF_TYPE_MS: 993 case IWL_CFG_RF_TYPE_FM: 994 case IWL_CFG_RF_TYPE_WH: 995 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 996 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 997 if (!is_ap) 998 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 999 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1000 break; 1001 } 1002 1003 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL && 1004 iftype_data->eht_cap.has_eht) { 1005 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] &= 1006 ~(IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 1007 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 1008 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2); 1009 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[3] &= 1010 ~(IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO | 1011 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1012 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1013 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1014 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 1015 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK); 1016 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] &= 1017 ~(IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO | 1018 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP); 1019 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] &= 1020 ~IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK; 1021 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[6] &= 1022 ~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK | 1023 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP); 1024 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] |= 1025 IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF; 1026 } 1027 1028 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT)) 1029 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |= 1030 IEEE80211_HE_MAC_CAP2_BCAST_TWT; 1031 1032 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1033 !is_ap) { 1034 iftype_data->vendor_elems.data = iwl_vendor_caps; 1035 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps); 1036 } 1037 1038 if (!trans->cfg->ht_params->stbc) { 1039 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 1040 ~IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1041 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] &= 1042 ~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1043 } 1044 } 1045 1046 static void iwl_init_he_hw_capab(struct iwl_trans *trans, 1047 struct iwl_nvm_data *data, 1048 struct ieee80211_supported_band *sband, 1049 u8 tx_chains, u8 rx_chains, 1050 const struct iwl_fw *fw) 1051 { 1052 struct ieee80211_sband_iftype_data *iftype_data; 1053 int i; 1054 1055 /* should only initialize once */ 1056 if (WARN_ON(sband->iftype_data)) 1057 return; 1058 1059 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_eht_capa)); 1060 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_eht_capa)); 1061 BUILD_BUG_ON(sizeof(data->iftd.uhb) != sizeof(iwl_he_eht_capa)); 1062 1063 switch (sband->band) { 1064 case NL80211_BAND_2GHZ: 1065 iftype_data = data->iftd.low; 1066 break; 1067 case NL80211_BAND_5GHZ: 1068 iftype_data = data->iftd.high; 1069 break; 1070 case NL80211_BAND_6GHZ: 1071 iftype_data = data->iftd.uhb; 1072 break; 1073 default: 1074 WARN_ON(1); 1075 return; 1076 } 1077 1078 memcpy(iftype_data, iwl_he_eht_capa, sizeof(iwl_he_eht_capa)); 1079 1080 sband->iftype_data = iftype_data; 1081 sband->n_iftype_data = ARRAY_SIZE(iwl_he_eht_capa); 1082 1083 for (i = 0; i < sband->n_iftype_data; i++) 1084 iwl_nvm_fixup_sband_iftd(trans, data, sband, &iftype_data[i], 1085 tx_chains, rx_chains, fw); 1086 1087 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains); 1088 } 1089 1090 static void iwl_init_sbands(struct iwl_trans *trans, 1091 struct iwl_nvm_data *data, 1092 const void *nvm_ch_flags, u8 tx_chains, 1093 u8 rx_chains, u32 sbands_flags, bool v4, 1094 const struct iwl_fw *fw) 1095 { 1096 struct device *dev = trans->dev; 1097 const struct iwl_cfg *cfg = trans->cfg; 1098 int n_channels; 1099 int n_used = 0; 1100 struct ieee80211_supported_band *sband; 1101 1102 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 1103 sbands_flags, v4); 1104 sband = &data->bands[NL80211_BAND_2GHZ]; 1105 sband->band = NL80211_BAND_2GHZ; 1106 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 1107 sband->n_bitrates = N_RATES_24; 1108 n_used += iwl_init_sband_channels(data, sband, n_channels, 1109 NL80211_BAND_2GHZ); 1110 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 1111 tx_chains, rx_chains); 1112 1113 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1114 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1115 fw); 1116 1117 sband = &data->bands[NL80211_BAND_5GHZ]; 1118 sband->band = NL80211_BAND_5GHZ; 1119 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 1120 sband->n_bitrates = N_RATES_52; 1121 n_used += iwl_init_sband_channels(data, sband, n_channels, 1122 NL80211_BAND_5GHZ); 1123 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 1124 tx_chains, rx_chains); 1125 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 1126 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 1127 tx_chains, rx_chains); 1128 1129 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1130 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1131 fw); 1132 1133 /* 6GHz band. */ 1134 sband = &data->bands[NL80211_BAND_6GHZ]; 1135 sband->band = NL80211_BAND_6GHZ; 1136 /* use the same rates as 5GHz band */ 1137 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 1138 sband->n_bitrates = N_RATES_52; 1139 n_used += iwl_init_sband_channels(data, sband, n_channels, 1140 NL80211_BAND_6GHZ); 1141 1142 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1143 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1144 fw); 1145 else 1146 sband->n_channels = 0; 1147 if (n_channels != n_used) 1148 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 1149 n_used, n_channels); 1150 } 1151 1152 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 1153 const __le16 *phy_sku) 1154 { 1155 if (cfg->nvm_type != IWL_NVM_EXT) 1156 return le16_to_cpup(nvm_sw + SKU); 1157 1158 return le32_to_cpup((const __le32 *)(phy_sku + SKU_FAMILY_8000)); 1159 } 1160 1161 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 1162 { 1163 if (cfg->nvm_type != IWL_NVM_EXT) 1164 return le16_to_cpup(nvm_sw + NVM_VERSION); 1165 else 1166 return le32_to_cpup((const __le32 *)(nvm_sw + 1167 NVM_VERSION_EXT_NVM)); 1168 } 1169 1170 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 1171 const __le16 *phy_sku) 1172 { 1173 if (cfg->nvm_type != IWL_NVM_EXT) 1174 return le16_to_cpup(nvm_sw + RADIO_CFG); 1175 1176 return le32_to_cpup((const __le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 1177 1178 } 1179 1180 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 1181 { 1182 int n_hw_addr; 1183 1184 if (cfg->nvm_type != IWL_NVM_EXT) 1185 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 1186 1187 n_hw_addr = le32_to_cpup((const __le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 1188 1189 return n_hw_addr & N_HW_ADDR_MASK; 1190 } 1191 1192 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 1193 struct iwl_nvm_data *data, 1194 u32 radio_cfg) 1195 { 1196 if (cfg->nvm_type != IWL_NVM_EXT) { 1197 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 1198 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 1199 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 1200 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 1201 return; 1202 } 1203 1204 /* set the radio configuration for family 8000 */ 1205 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 1206 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 1207 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 1208 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 1209 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 1210 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 1211 } 1212 1213 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 1214 { 1215 const u8 *hw_addr; 1216 1217 hw_addr = (const u8 *)&mac_addr0; 1218 dest[0] = hw_addr[3]; 1219 dest[1] = hw_addr[2]; 1220 dest[2] = hw_addr[1]; 1221 dest[3] = hw_addr[0]; 1222 1223 hw_addr = (const u8 *)&mac_addr1; 1224 dest[4] = hw_addr[1]; 1225 dest[5] = hw_addr[0]; 1226 } 1227 1228 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 1229 struct iwl_nvm_data *data) 1230 { 1231 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, 1232 CSR_MAC_ADDR0_STRAP(trans))); 1233 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, 1234 CSR_MAC_ADDR1_STRAP(trans))); 1235 1236 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1237 /* 1238 * If the OEM fused a valid address, use it instead of the one in the 1239 * OTP 1240 */ 1241 if (is_valid_ether_addr(data->hw_addr)) 1242 return; 1243 1244 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans))); 1245 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans))); 1246 1247 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1248 } 1249 1250 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 1251 const struct iwl_cfg *cfg, 1252 struct iwl_nvm_data *data, 1253 const __le16 *mac_override, 1254 const __be16 *nvm_hw) 1255 { 1256 const u8 *hw_addr; 1257 1258 if (mac_override) { 1259 static const u8 reserved_mac[] = { 1260 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 1261 }; 1262 1263 hw_addr = (const u8 *)(mac_override + 1264 MAC_ADDRESS_OVERRIDE_EXT_NVM); 1265 1266 /* 1267 * Store the MAC address from MAO section. 1268 * No byte swapping is required in MAO section 1269 */ 1270 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 1271 1272 /* 1273 * Force the use of the OTP MAC address in case of reserved MAC 1274 * address in the NVM, or if address is given but invalid. 1275 */ 1276 if (is_valid_ether_addr(data->hw_addr) && 1277 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 1278 return; 1279 1280 IWL_ERR(trans, 1281 "mac address from nvm override section is not valid\n"); 1282 } 1283 1284 if (nvm_hw) { 1285 /* read the mac address from WFMP registers */ 1286 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 1287 WFMP_MAC_ADDR_0)); 1288 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 1289 WFMP_MAC_ADDR_1)); 1290 1291 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1292 1293 return; 1294 } 1295 1296 IWL_ERR(trans, "mac address is not found\n"); 1297 } 1298 1299 static int iwl_set_hw_address(struct iwl_trans *trans, 1300 const struct iwl_cfg *cfg, 1301 struct iwl_nvm_data *data, const __be16 *nvm_hw, 1302 const __le16 *mac_override) 1303 { 1304 if (cfg->mac_addr_from_csr) { 1305 iwl_set_hw_address_from_csr(trans, data); 1306 } else if (cfg->nvm_type != IWL_NVM_EXT) { 1307 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 1308 1309 /* The byte order is little endian 16 bit, meaning 214365 */ 1310 data->hw_addr[0] = hw_addr[1]; 1311 data->hw_addr[1] = hw_addr[0]; 1312 data->hw_addr[2] = hw_addr[3]; 1313 data->hw_addr[3] = hw_addr[2]; 1314 data->hw_addr[4] = hw_addr[5]; 1315 data->hw_addr[5] = hw_addr[4]; 1316 } else { 1317 iwl_set_hw_address_family_8000(trans, cfg, data, 1318 mac_override, nvm_hw); 1319 } 1320 1321 if (!is_valid_ether_addr(data->hw_addr)) { 1322 IWL_ERR(trans, "no valid mac address was found\n"); 1323 return -EINVAL; 1324 } 1325 1326 if (!trans->csme_own) 1327 IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n", 1328 data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR)); 1329 1330 return 0; 1331 } 1332 1333 static bool 1334 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1335 const __be16 *nvm_hw) 1336 { 1337 /* 1338 * Workaround a bug in Indonesia SKUs where the regulatory in 1339 * some 7000-family OTPs erroneously allow wide channels in 1340 * 5GHz. To check for Indonesia, we take the SKU value from 1341 * bits 1-4 in the subsystem ID and check if it is either 5 or 1342 * 9. In those cases, we need to force-disable wide channels 1343 * in 5GHz otherwise the FW will throw a sysassert when we try 1344 * to use them. 1345 */ 1346 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1347 /* 1348 * Unlike the other sections in the NVM, the hw 1349 * section uses big-endian. 1350 */ 1351 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 1352 u8 sku = (subsystem_id & 0x1e) >> 1; 1353 1354 if (sku == 5 || sku == 9) { 1355 IWL_DEBUG_EEPROM(trans->dev, 1356 "disabling wide channels in 5GHz (0x%0x %d)\n", 1357 subsystem_id, sku); 1358 return true; 1359 } 1360 } 1361 1362 return false; 1363 } 1364 1365 struct iwl_nvm_data * 1366 iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1367 const struct iwl_mei_nvm *mei_nvm, 1368 const struct iwl_fw *fw) 1369 { 1370 struct iwl_nvm_data *data; 1371 u32 sbands_flags = 0; 1372 u8 rx_chains = fw->valid_rx_ant; 1373 u8 tx_chains = fw->valid_rx_ant; 1374 1375 if (cfg->uhb_supported) 1376 data = kzalloc(struct_size(data, channels, 1377 IWL_NVM_NUM_CHANNELS_UHB), 1378 GFP_KERNEL); 1379 else 1380 data = kzalloc(struct_size(data, channels, 1381 IWL_NVM_NUM_CHANNELS_EXT), 1382 GFP_KERNEL); 1383 if (!data) 1384 return NULL; 1385 1386 BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) != 1387 IWL_NVM_NUM_CHANNELS_UHB); 1388 data->nvm_version = mei_nvm->nvm_version; 1389 1390 iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg); 1391 if (data->valid_tx_ant) 1392 tx_chains &= data->valid_tx_ant; 1393 if (data->valid_rx_ant) 1394 rx_chains &= data->valid_rx_ant; 1395 1396 data->sku_cap_mimo_disabled = false; 1397 data->sku_cap_band_24ghz_enable = true; 1398 data->sku_cap_band_52ghz_enable = true; 1399 data->sku_cap_11n_enable = 1400 !(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL); 1401 data->sku_cap_11ac_enable = true; 1402 data->sku_cap_11ax_enable = 1403 mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT; 1404 1405 data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT; 1406 1407 data->n_hw_addrs = mei_nvm->n_hw_addrs; 1408 /* If no valid mac address was found - bail out */ 1409 if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) { 1410 kfree(data); 1411 return NULL; 1412 } 1413 1414 if (data->lar_enabled && 1415 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1416 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1417 1418 iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains, 1419 sbands_flags, true, fw); 1420 1421 return data; 1422 } 1423 IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data); 1424 1425 struct iwl_nvm_data * 1426 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1427 const struct iwl_fw *fw, 1428 const __be16 *nvm_hw, const __le16 *nvm_sw, 1429 const __le16 *nvm_calib, const __le16 *regulatory, 1430 const __le16 *mac_override, const __le16 *phy_sku, 1431 u8 tx_chains, u8 rx_chains) 1432 { 1433 struct iwl_nvm_data *data; 1434 bool lar_enabled; 1435 u32 sku, radio_cfg; 1436 u32 sbands_flags = 0; 1437 u16 lar_config; 1438 const __le16 *ch_section; 1439 1440 if (cfg->uhb_supported) 1441 data = kzalloc(struct_size(data, channels, 1442 IWL_NVM_NUM_CHANNELS_UHB), 1443 GFP_KERNEL); 1444 else if (cfg->nvm_type != IWL_NVM_EXT) 1445 data = kzalloc(struct_size(data, channels, 1446 IWL_NVM_NUM_CHANNELS), 1447 GFP_KERNEL); 1448 else 1449 data = kzalloc(struct_size(data, channels, 1450 IWL_NVM_NUM_CHANNELS_EXT), 1451 GFP_KERNEL); 1452 if (!data) 1453 return NULL; 1454 1455 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 1456 1457 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 1458 iwl_set_radio_cfg(cfg, data, radio_cfg); 1459 if (data->valid_tx_ant) 1460 tx_chains &= data->valid_tx_ant; 1461 if (data->valid_rx_ant) 1462 rx_chains &= data->valid_rx_ant; 1463 1464 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 1465 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 1466 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 1467 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 1468 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1469 data->sku_cap_11n_enable = false; 1470 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 1471 (sku & NVM_SKU_CAP_11AC_ENABLE); 1472 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 1473 1474 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 1475 1476 if (cfg->nvm_type != IWL_NVM_EXT) { 1477 /* Checking for required sections */ 1478 if (!nvm_calib) { 1479 IWL_ERR(trans, 1480 "Can't parse empty Calib NVM sections\n"); 1481 kfree(data); 1482 return NULL; 1483 } 1484 1485 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 1486 ®ulatory[NVM_CHANNELS_SDP] : 1487 &nvm_sw[NVM_CHANNELS]; 1488 1489 /* in family 8000 Xtal calibration values moved to OTP */ 1490 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 1491 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 1492 lar_enabled = true; 1493 } else { 1494 u16 lar_offset = data->nvm_version < 0xE39 ? 1495 NVM_LAR_OFFSET_OLD : 1496 NVM_LAR_OFFSET; 1497 1498 lar_config = le16_to_cpup(regulatory + lar_offset); 1499 data->lar_enabled = !!(lar_config & 1500 NVM_LAR_ENABLED); 1501 lar_enabled = data->lar_enabled; 1502 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1503 } 1504 1505 /* If no valid mac address was found - bail out */ 1506 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1507 kfree(data); 1508 return NULL; 1509 } 1510 1511 if (lar_enabled && 1512 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1513 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1514 1515 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw)) 1516 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1517 1518 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains, 1519 sbands_flags, false, fw); 1520 data->calib_version = 255; 1521 1522 return data; 1523 } 1524 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1525 1526 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan, 1527 int ch_idx, u16 nvm_flags, 1528 struct iwl_reg_capa reg_capa, 1529 const struct iwl_cfg *cfg) 1530 { 1531 u32 flags = NL80211_RRF_NO_HT40; 1532 1533 if (ch_idx < NUM_2GHZ_CHANNELS && 1534 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1535 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1536 flags &= ~NL80211_RRF_NO_HT40PLUS; 1537 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1538 flags &= ~NL80211_RRF_NO_HT40MINUS; 1539 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 1540 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1541 flags &= ~NL80211_RRF_NO_HT40PLUS; 1542 else 1543 flags &= ~NL80211_RRF_NO_HT40MINUS; 1544 } 1545 1546 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1547 flags |= NL80211_RRF_NO_80MHZ; 1548 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1549 flags |= NL80211_RRF_NO_160MHZ; 1550 1551 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1552 flags |= NL80211_RRF_NO_IR; 1553 1554 if (nvm_flags & NVM_CHANNEL_RADAR) 1555 flags |= NL80211_RRF_DFS; 1556 1557 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1558 flags |= NL80211_RRF_NO_OUTDOOR; 1559 1560 /* Set the GO concurrent flag only in case that NO_IR is set. 1561 * Otherwise it is meaningless 1562 */ 1563 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1564 (flags & NL80211_RRF_NO_IR)) 1565 flags |= NL80211_RRF_GO_CONCURRENT; 1566 1567 /* 1568 * reg_capa is per regulatory domain so apply it for every channel 1569 */ 1570 if (ch_idx >= NUM_2GHZ_CHANNELS) { 1571 if (!reg_capa.allow_40mhz) 1572 flags |= NL80211_RRF_NO_HT40; 1573 1574 if (!reg_capa.allow_80mhz) 1575 flags |= NL80211_RRF_NO_80MHZ; 1576 1577 if (!reg_capa.allow_160mhz) 1578 flags |= NL80211_RRF_NO_160MHZ; 1579 1580 if (!reg_capa.allow_320mhz) 1581 flags |= NL80211_RRF_NO_320MHZ; 1582 } 1583 1584 if (reg_capa.disable_11ax) 1585 flags |= NL80211_RRF_NO_HE; 1586 1587 if (reg_capa.disable_11be) 1588 flags |= NL80211_RRF_NO_EHT; 1589 1590 return flags; 1591 } 1592 1593 static struct iwl_reg_capa iwl_get_reg_capa(u32 flags, u8 resp_ver) 1594 { 1595 struct iwl_reg_capa reg_capa = {}; 1596 1597 if (resp_ver >= REG_CAPA_V4_RESP_VER) { 1598 reg_capa.allow_40mhz = true; 1599 reg_capa.allow_80mhz = flags & REG_CAPA_V4_80MHZ_ALLOWED; 1600 reg_capa.allow_160mhz = flags & REG_CAPA_V4_160MHZ_ALLOWED; 1601 reg_capa.allow_320mhz = flags & REG_CAPA_V4_320MHZ_ALLOWED; 1602 reg_capa.disable_11ax = flags & REG_CAPA_V4_11AX_DISABLED; 1603 reg_capa.disable_11be = flags & REG_CAPA_V4_11BE_DISABLED; 1604 } else if (resp_ver >= REG_CAPA_V2_RESP_VER) { 1605 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED; 1606 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED; 1607 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED; 1608 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED; 1609 } else { 1610 reg_capa.allow_40mhz = !(flags & REG_CAPA_V1_40MHZ_FORBIDDEN); 1611 reg_capa.allow_80mhz = flags & REG_CAPA_V1_80MHZ_ALLOWED; 1612 reg_capa.allow_160mhz = flags & REG_CAPA_V1_160MHZ_ALLOWED; 1613 reg_capa.disable_11ax = flags & REG_CAPA_V1_11AX_DISABLED; 1614 } 1615 return reg_capa; 1616 } 1617 1618 struct ieee80211_regdomain * 1619 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1620 int num_of_ch, __le32 *channels, u16 fw_mcc, 1621 u16 geo_info, u32 cap, u8 resp_ver) 1622 { 1623 int ch_idx; 1624 u16 ch_flags; 1625 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1626 const u16 *nvm_chan; 1627 struct ieee80211_regdomain *regd, *copy_rd; 1628 struct ieee80211_reg_rule *rule; 1629 enum nl80211_band band; 1630 int center_freq, prev_center_freq = 0; 1631 int valid_rules = 0; 1632 bool new_rule; 1633 int max_num_ch; 1634 struct iwl_reg_capa reg_capa; 1635 1636 if (cfg->uhb_supported) { 1637 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB; 1638 nvm_chan = iwl_uhb_nvm_channels; 1639 } else if (cfg->nvm_type == IWL_NVM_EXT) { 1640 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT; 1641 nvm_chan = iwl_ext_nvm_channels; 1642 } else { 1643 max_num_ch = IWL_NVM_NUM_CHANNELS; 1644 nvm_chan = iwl_nvm_channels; 1645 } 1646 1647 if (num_of_ch > max_num_ch) { 1648 IWL_DEBUG_DEV(dev, IWL_DL_LAR, 1649 "Num of channels (%d) is greater than expected. Truncating to %d\n", 1650 num_of_ch, max_num_ch); 1651 num_of_ch = max_num_ch; 1652 } 1653 1654 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1655 return ERR_PTR(-EINVAL); 1656 1657 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1658 num_of_ch); 1659 1660 /* build a regdomain rule for every valid channel */ 1661 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL); 1662 if (!regd) 1663 return ERR_PTR(-ENOMEM); 1664 1665 /* set alpha2 from FW. */ 1666 regd->alpha2[0] = fw_mcc >> 8; 1667 regd->alpha2[1] = fw_mcc & 0xff; 1668 1669 /* parse regulatory capability flags */ 1670 reg_capa = iwl_get_reg_capa(cap, resp_ver); 1671 1672 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1673 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1674 band = iwl_nl80211_band_from_channel_idx(ch_idx); 1675 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1676 band); 1677 new_rule = false; 1678 1679 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1680 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1681 nvm_chan[ch_idx], ch_flags); 1682 continue; 1683 } 1684 1685 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1686 ch_flags, reg_capa, 1687 cfg); 1688 1689 /* we can't continue the same rule */ 1690 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1691 center_freq - prev_center_freq > 20) { 1692 valid_rules++; 1693 new_rule = true; 1694 } 1695 1696 rule = ®d->reg_rules[valid_rules - 1]; 1697 1698 if (new_rule) 1699 rule->freq_range.start_freq_khz = 1700 MHZ_TO_KHZ(center_freq - 10); 1701 1702 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1703 1704 /* this doesn't matter - not used by FW */ 1705 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1706 rule->power_rule.max_eirp = 1707 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1708 1709 rule->flags = reg_rule_flags; 1710 1711 /* rely on auto-calculation to merge BW of contiguous chans */ 1712 rule->flags |= NL80211_RRF_AUTO_BW; 1713 rule->freq_range.max_bandwidth_khz = 0; 1714 1715 prev_center_freq = center_freq; 1716 prev_reg_rule_flags = reg_rule_flags; 1717 1718 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1719 nvm_chan[ch_idx], ch_flags); 1720 1721 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1722 band == NL80211_BAND_2GHZ) 1723 continue; 1724 1725 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1726 } 1727 1728 /* 1729 * Certain firmware versions might report no valid channels 1730 * if booted in RF-kill, i.e. not all calibrations etc. are 1731 * running. We'll get out of this situation later when the 1732 * rfkill is removed and we update the regdomain again, but 1733 * since cfg80211 doesn't accept an empty regdomain, add a 1734 * dummy (unusable) rule here in this case so we can init. 1735 */ 1736 if (!valid_rules) { 1737 valid_rules = 1; 1738 rule = ®d->reg_rules[valid_rules - 1]; 1739 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412); 1740 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413); 1741 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1); 1742 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1743 rule->power_rule.max_eirp = 1744 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1745 } 1746 1747 regd->n_reg_rules = valid_rules; 1748 1749 /* 1750 * Narrow down regdom for unused regulatory rules to prevent hole 1751 * between reg rules to wmm rules. 1752 */ 1753 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules), 1754 GFP_KERNEL); 1755 if (!copy_rd) 1756 copy_rd = ERR_PTR(-ENOMEM); 1757 1758 kfree(regd); 1759 return copy_rd; 1760 } 1761 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1762 1763 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1764 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1765 #define MAX_NVM_FILE_LEN 16384 1766 1767 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1768 unsigned int len) 1769 { 1770 #define IWL_4165_DEVICE_ID 0x5501 1771 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1772 1773 if (section == NVM_SECTION_TYPE_PHY_SKU && 1774 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1775 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1776 /* OTP 0x52 bug work around: it's a 1x1 device */ 1777 data[3] = ANT_B | (ANT_B << 4); 1778 } 1779 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1780 1781 /* 1782 * Reads external NVM from a file into mvm->nvm_sections 1783 * 1784 * HOW TO CREATE THE NVM FILE FORMAT: 1785 * ------------------------------ 1786 * 1. create hex file, format: 1787 * 3800 -> header 1788 * 0000 -> header 1789 * 5a40 -> data 1790 * 1791 * rev - 6 bit (word1) 1792 * len - 10 bit (word1) 1793 * id - 4 bit (word2) 1794 * rsv - 12 bit (word2) 1795 * 1796 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1797 * 1798 * 3. create binary file from the hex file 1799 * 1800 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1801 */ 1802 int iwl_read_external_nvm(struct iwl_trans *trans, 1803 const char *nvm_file_name, 1804 struct iwl_nvm_section *nvm_sections) 1805 { 1806 int ret, section_size; 1807 u16 section_id; 1808 const struct firmware *fw_entry; 1809 const struct { 1810 __le16 word1; 1811 __le16 word2; 1812 u8 data[]; 1813 } *file_sec; 1814 const u8 *eof; 1815 u8 *temp; 1816 int max_section_size; 1817 const __le32 *dword_buff; 1818 1819 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1820 #define NVM_WORD2_ID(x) (x >> 12) 1821 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1822 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1823 #define NVM_HEADER_0 (0x2A504C54) 1824 #define NVM_HEADER_1 (0x4E564D2A) 1825 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1826 1827 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1828 1829 /* Maximal size depends on NVM version */ 1830 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1831 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1832 else 1833 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1834 1835 /* 1836 * Obtain NVM image via request_firmware. Since we already used 1837 * request_firmware_nowait() for the firmware binary load and only 1838 * get here after that we assume the NVM request can be satisfied 1839 * synchronously. 1840 */ 1841 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1842 if (ret) { 1843 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1844 nvm_file_name, ret); 1845 return ret; 1846 } 1847 1848 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1849 nvm_file_name, fw_entry->size); 1850 1851 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1852 IWL_ERR(trans, "NVM file too large\n"); 1853 ret = -EINVAL; 1854 goto out; 1855 } 1856 1857 eof = fw_entry->data + fw_entry->size; 1858 dword_buff = (const __le32 *)fw_entry->data; 1859 1860 /* some NVM file will contain a header. 1861 * The header is identified by 2 dwords header as follow: 1862 * dword[0] = 0x2A504C54 1863 * dword[1] = 0x4E564D2A 1864 * 1865 * This header must be skipped when providing the NVM data to the FW. 1866 */ 1867 if (fw_entry->size > NVM_HEADER_SIZE && 1868 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1869 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1870 file_sec = (const void *)(fw_entry->data + NVM_HEADER_SIZE); 1871 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1872 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1873 le32_to_cpu(dword_buff[3])); 1874 1875 /* nvm file validation, dword_buff[2] holds the file version */ 1876 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1877 trans->hw_rev_step == SILICON_C_STEP && 1878 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1879 ret = -EFAULT; 1880 goto out; 1881 } 1882 } else { 1883 file_sec = (const void *)fw_entry->data; 1884 } 1885 1886 while (true) { 1887 if (file_sec->data > eof) { 1888 IWL_ERR(trans, 1889 "ERROR - NVM file too short for section header\n"); 1890 ret = -EINVAL; 1891 break; 1892 } 1893 1894 /* check for EOF marker */ 1895 if (!file_sec->word1 && !file_sec->word2) { 1896 ret = 0; 1897 break; 1898 } 1899 1900 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1901 section_size = 1902 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1903 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1904 } else { 1905 section_size = 2 * EXT_NVM_WORD2_LEN( 1906 le16_to_cpu(file_sec->word2)); 1907 section_id = EXT_NVM_WORD1_ID( 1908 le16_to_cpu(file_sec->word1)); 1909 } 1910 1911 if (section_size > max_section_size) { 1912 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1913 section_size); 1914 ret = -EINVAL; 1915 break; 1916 } 1917 1918 if (!section_size) { 1919 IWL_ERR(trans, "ERROR - section empty\n"); 1920 ret = -EINVAL; 1921 break; 1922 } 1923 1924 if (file_sec->data + section_size > eof) { 1925 IWL_ERR(trans, 1926 "ERROR - NVM file too short for section (%d bytes)\n", 1927 section_size); 1928 ret = -EINVAL; 1929 break; 1930 } 1931 1932 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1933 "Invalid NVM section ID %d\n", section_id)) { 1934 ret = -EINVAL; 1935 break; 1936 } 1937 1938 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1939 if (!temp) { 1940 ret = -ENOMEM; 1941 break; 1942 } 1943 1944 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1945 1946 kfree(nvm_sections[section_id].data); 1947 nvm_sections[section_id].data = temp; 1948 nvm_sections[section_id].length = section_size; 1949 1950 /* advance to the next section */ 1951 file_sec = (const void *)(file_sec->data + section_size); 1952 } 1953 out: 1954 release_firmware(fw_entry); 1955 return ret; 1956 } 1957 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1958 1959 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1960 const struct iwl_fw *fw) 1961 { 1962 struct iwl_nvm_get_info cmd = {}; 1963 struct iwl_nvm_data *nvm; 1964 struct iwl_host_cmd hcmd = { 1965 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1966 .data = { &cmd, }, 1967 .len = { sizeof(cmd) }, 1968 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1969 }; 1970 int ret; 1971 bool empty_otp; 1972 u32 mac_flags; 1973 u32 sbands_flags = 0; 1974 /* 1975 * All the values in iwl_nvm_get_info_rsp v4 are the same as 1976 * in v3, except for the channel profile part of the 1977 * regulatory. So we can just access the new struct, with the 1978 * exception of the latter. 1979 */ 1980 struct iwl_nvm_get_info_rsp *rsp; 1981 struct iwl_nvm_get_info_rsp_v3 *rsp_v3; 1982 bool v4 = fw_has_api(&fw->ucode_capa, 1983 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO); 1984 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3); 1985 void *channel_profile; 1986 1987 ret = iwl_trans_send_cmd(trans, &hcmd); 1988 if (ret) 1989 return ERR_PTR(ret); 1990 1991 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size, 1992 "Invalid payload len in NVM response from FW %d", 1993 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1994 ret = -EINVAL; 1995 goto out; 1996 } 1997 1998 rsp = (void *)hcmd.resp_pkt->data; 1999 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 2000 NVM_GENERAL_FLAGS_EMPTY_OTP); 2001 if (empty_otp) 2002 IWL_INFO(trans, "OTP is empty\n"); 2003 2004 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL); 2005 if (!nvm) { 2006 ret = -ENOMEM; 2007 goto out; 2008 } 2009 2010 iwl_set_hw_address_from_csr(trans, nvm); 2011 /* TODO: if platform NVM has MAC address - override it here */ 2012 2013 if (!is_valid_ether_addr(nvm->hw_addr)) { 2014 IWL_ERR(trans, "no valid mac address was found\n"); 2015 ret = -EINVAL; 2016 goto err_free; 2017 } 2018 2019 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 2020 2021 /* Initialize general data */ 2022 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 2023 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 2024 if (nvm->n_hw_addrs == 0) 2025 IWL_WARN(trans, 2026 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 2027 empty_otp); 2028 2029 /* Initialize MAC sku data */ 2030 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 2031 nvm->sku_cap_11ac_enable = 2032 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 2033 nvm->sku_cap_11n_enable = 2034 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 2035 nvm->sku_cap_11ax_enable = 2036 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 2037 nvm->sku_cap_band_24ghz_enable = 2038 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 2039 nvm->sku_cap_band_52ghz_enable = 2040 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 2041 nvm->sku_cap_mimo_disabled = 2042 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 2043 if (CSR_HW_RFID_TYPE(trans->hw_rf_id) == IWL_CFG_RF_TYPE_FM) 2044 nvm->sku_cap_11be_enable = true; 2045 2046 /* Initialize PHY sku data */ 2047 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 2048 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 2049 2050 if (le32_to_cpu(rsp->regulatory.lar_enabled) && 2051 fw_has_capa(&fw->ucode_capa, 2052 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) { 2053 nvm->lar_enabled = true; 2054 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 2055 } 2056 2057 rsp_v3 = (void *)rsp; 2058 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile : 2059 (void *)rsp_v3->regulatory.channel_profile; 2060 2061 iwl_init_sbands(trans, nvm, 2062 channel_profile, 2063 nvm->valid_tx_ant & fw->valid_tx_ant, 2064 nvm->valid_rx_ant & fw->valid_rx_ant, 2065 sbands_flags, v4, fw); 2066 2067 iwl_free_resp(&hcmd); 2068 return nvm; 2069 2070 err_free: 2071 kfree(nvm); 2072 out: 2073 iwl_free_resp(&hcmd); 2074 return ERR_PTR(ret); 2075 } 2076 IWL_EXPORT_SYMBOL(iwl_get_nvm); 2077