1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2023, 2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/types.h> 8 #include <linux/slab.h> 9 #include <linux/export.h> 10 #include <linux/etherdevice.h> 11 #include <linux/pci.h> 12 #include <linux/firmware.h> 13 14 #include "iwl-drv.h" 15 #include "iwl-modparams.h" 16 #include "iwl-nvm-parse.h" 17 #include "iwl-prph.h" 18 #include "iwl-io.h" 19 #include "iwl-csr.h" 20 #include "fw/acpi.h" 21 #include "fw/api/nvm-reg.h" 22 #include "fw/api/commands.h" 23 #include "fw/api/cmdhdr.h" 24 #include "fw/img.h" 25 #include "mei/iwl-mei.h" 26 27 /* NVM offsets (in words) definitions */ 28 enum nvm_offsets { 29 /* NVM HW-Section offset (in words) definitions */ 30 SUBSYSTEM_ID = 0x0A, 31 HW_ADDR = 0x15, 32 33 /* NVM SW-Section offset (in words) definitions */ 34 NVM_SW_SECTION = 0x1C0, 35 NVM_VERSION = 0, 36 RADIO_CFG = 1, 37 SKU = 2, 38 N_HW_ADDRS = 3, 39 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 40 41 /* NVM REGULATORY -Section offset (in words) definitions */ 42 NVM_CHANNELS_SDP = 0, 43 }; 44 45 enum ext_nvm_offsets { 46 /* NVM HW-Section offset (in words) definitions */ 47 48 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 49 50 /* NVM SW-Section offset (in words) definitions */ 51 NVM_VERSION_EXT_NVM = 0, 52 N_HW_ADDRS_FAMILY_8000 = 3, 53 54 /* NVM PHY_SKU-Section offset (in words) definitions */ 55 RADIO_CFG_FAMILY_EXT_NVM = 0, 56 SKU_FAMILY_8000 = 2, 57 58 /* NVM REGULATORY -Section offset (in words) definitions */ 59 NVM_CHANNELS_EXTENDED = 0, 60 NVM_LAR_OFFSET_OLD = 0x4C7, 61 NVM_LAR_OFFSET = 0x507, 62 NVM_LAR_ENABLED = 0x7, 63 }; 64 65 /* SKU Capabilities (actual values from NVM definition) */ 66 enum nvm_sku_bits { 67 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 68 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 69 NVM_SKU_CAP_11N_ENABLE = BIT(2), 70 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 71 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 72 }; 73 74 /* 75 * These are the channel numbers in the order that they are stored in the NVM 76 */ 77 static const u16 iwl_nvm_channels[] = { 78 /* 2.4 GHz */ 79 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 80 /* 5 GHz */ 81 36, 40, 44, 48, 52, 56, 60, 64, 82 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 83 149, 153, 157, 161, 165 84 }; 85 86 static const u16 iwl_ext_nvm_channels[] = { 87 /* 2.4 GHz */ 88 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 89 /* 5 GHz */ 90 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 91 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 92 149, 153, 157, 161, 165, 169, 173, 177, 181 93 }; 94 95 static const u16 iwl_uhb_nvm_channels[] = { 96 /* 2.4 GHz */ 97 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 98 /* 5 GHz */ 99 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 100 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 101 149, 153, 157, 161, 165, 169, 173, 177, 181, 102 /* 6-7 GHz */ 103 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 104 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 105 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 106 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233 107 }; 108 109 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 110 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 111 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels) 112 #define NUM_2GHZ_CHANNELS 14 113 #define NUM_5GHZ_CHANNELS 37 114 #define FIRST_2GHZ_HT_MINUS 5 115 #define LAST_2GHZ_HT_PLUS 9 116 #define N_HW_ADDR_MASK 0xF 117 118 /* rate data (static) */ 119 static struct ieee80211_rate iwl_cfg80211_rates[] = { 120 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 121 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 122 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 123 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 124 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 125 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 126 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 127 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 128 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 129 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 130 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 131 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 132 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 133 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 134 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 135 }; 136 #define RATES_24_OFFS 0 137 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 138 #define RATES_52_OFFS 4 139 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 140 141 /** 142 * enum iwl_nvm_channel_flags - channel flags in NVM 143 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 144 * @NVM_CHANNEL_IBSS: usable as an IBSS channel and deprecated 145 * when %IWL_NVM_SBANDS_FLAGS_LAR enabled. 146 * @NVM_CHANNEL_ACTIVE: active scanning allowed and allows IBSS 147 * when %IWL_NVM_SBANDS_FLAGS_LAR enabled. 148 * @NVM_CHANNEL_RADAR: radar detection required 149 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 150 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 151 * on same channel on 2.4 or same UNII band on 5.2 152 * @NVM_CHANNEL_UNIFORM: uniform spreading required 153 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 154 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 155 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 156 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 157 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 158 * @NVM_CHANNEL_VLP: client support connection to UHB VLP AP 159 * @NVM_CHANNEL_AFC: client support connection to UHB AFC AP 160 */ 161 enum iwl_nvm_channel_flags { 162 NVM_CHANNEL_VALID = BIT(0), 163 NVM_CHANNEL_IBSS = BIT(1), 164 NVM_CHANNEL_ACTIVE = BIT(3), 165 NVM_CHANNEL_RADAR = BIT(4), 166 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 167 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 168 NVM_CHANNEL_UNIFORM = BIT(7), 169 NVM_CHANNEL_20MHZ = BIT(8), 170 NVM_CHANNEL_40MHZ = BIT(9), 171 NVM_CHANNEL_80MHZ = BIT(10), 172 NVM_CHANNEL_160MHZ = BIT(11), 173 NVM_CHANNEL_DC_HIGH = BIT(12), 174 NVM_CHANNEL_VLP = BIT(13), 175 NVM_CHANNEL_AFC = BIT(14), 176 }; 177 178 /** 179 * enum iwl_reg_capa_flags_v1 - global flags applied for the whole regulatory 180 * domain. 181 * @REG_CAPA_V1_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 182 * 2.4Ghz band is allowed. 183 * @REG_CAPA_V1_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 184 * 5Ghz band is allowed. 185 * @REG_CAPA_V1_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 186 * for this regulatory domain (valid only in 5Ghz). 187 * @REG_CAPA_V1_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 188 * for this regulatory domain (valid only in 5Ghz). 189 * @REG_CAPA_V1_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 190 * @REG_CAPA_V1_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 191 * @REG_CAPA_V1_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden 192 * for this regulatory domain (valid only in 5Ghz). 193 * @REG_CAPA_V1_DC_HIGH_ENABLED: DC HIGH allowed. 194 * @REG_CAPA_V1_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 195 */ 196 enum iwl_reg_capa_flags_v1 { 197 REG_CAPA_V1_BF_CCD_LOW_BAND = BIT(0), 198 REG_CAPA_V1_BF_CCD_HIGH_BAND = BIT(1), 199 REG_CAPA_V1_160MHZ_ALLOWED = BIT(2), 200 REG_CAPA_V1_80MHZ_ALLOWED = BIT(3), 201 REG_CAPA_V1_MCS_8_ALLOWED = BIT(4), 202 REG_CAPA_V1_MCS_9_ALLOWED = BIT(5), 203 REG_CAPA_V1_40MHZ_FORBIDDEN = BIT(7), 204 REG_CAPA_V1_DC_HIGH_ENABLED = BIT(9), 205 REG_CAPA_V1_11AX_DISABLED = BIT(10), 206 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_1 */ 207 208 /** 209 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory 210 * domain (version 2). 211 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are 212 * disabled. 213 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 214 * 2.4Ghz band is allowed. 215 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 216 * 5Ghz band is allowed. 217 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 218 * for this regulatory domain (valid only in 5Ghz). 219 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 220 * for this regulatory domain (valid only in 5Ghz). 221 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 222 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 223 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118, 224 * 126, 122) are disabled. 225 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed 226 * for this regulatory domain (uvalid only in 5Ghz). 227 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 228 */ 229 enum iwl_reg_capa_flags_v2 { 230 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0), 231 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1), 232 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2), 233 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3), 234 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4), 235 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5), 236 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6), 237 REG_CAPA_V2_WEATHER_DISABLED = BIT(7), 238 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8), 239 REG_CAPA_V2_11AX_DISABLED = BIT(10), 240 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_2 */ 241 242 /** 243 * enum iwl_reg_capa_flags_v4 - global flags applied for the whole regulatory 244 * domain. 245 * @REG_CAPA_V4_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 246 * for this regulatory domain (valid only in 5Ghz). 247 * @REG_CAPA_V4_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 248 * for this regulatory domain (valid only in 5Ghz). 249 * @REG_CAPA_V4_MCS_12_ALLOWED: 11ac with MCS 12 is allowed. 250 * @REG_CAPA_V4_MCS_13_ALLOWED: 11ac with MCS 13 is allowed. 251 * @REG_CAPA_V4_11BE_DISABLED: 11be is forbidden for this regulatory domain. 252 * @REG_CAPA_V4_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 253 * @REG_CAPA_V4_320MHZ_ALLOWED: 11be channel with a width of 320Mhz is allowed 254 * for this regulatory domain (valid only in 5GHz). 255 */ 256 enum iwl_reg_capa_flags_v4 { 257 REG_CAPA_V4_160MHZ_ALLOWED = BIT(3), 258 REG_CAPA_V4_80MHZ_ALLOWED = BIT(4), 259 REG_CAPA_V4_MCS_12_ALLOWED = BIT(5), 260 REG_CAPA_V4_MCS_13_ALLOWED = BIT(6), 261 REG_CAPA_V4_11BE_DISABLED = BIT(8), 262 REG_CAPA_V4_11AX_DISABLED = BIT(13), 263 REG_CAPA_V4_320MHZ_ALLOWED = BIT(16), 264 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_4 */ 265 266 /* 267 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the 268 * MCC update command response. 269 */ 270 #define REG_CAPA_V2_RESP_VER 6 271 272 /* API v4 for reg_capa_flags is relevant from version 8 and onwards of the 273 * MCC update command response. 274 */ 275 #define REG_CAPA_V4_RESP_VER 8 276 277 /** 278 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for 279 * handling the different APIs of reg_capa_flags. 280 * 281 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed 282 * for this regulatory domain. 283 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed 284 * for this regulatory domain (valid only in 5 and 6 Ghz). 285 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed 286 * for this regulatory domain (valid only in 5 and 6 Ghz). 287 * @allow_320mhz: 11be channel with a width of 320Mhz is allowed 288 * for this regulatory domain (valid only in 6 Ghz). 289 * @disable_11ax: 11ax is forbidden for this regulatory domain. 290 * @disable_11be: 11be is forbidden for this regulatory domain. 291 */ 292 struct iwl_reg_capa { 293 bool allow_40mhz; 294 bool allow_80mhz; 295 bool allow_160mhz; 296 bool allow_320mhz; 297 bool disable_11ax; 298 bool disable_11be; 299 }; 300 301 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 302 int chan, u32 flags) 303 { 304 #define CHECK_AND_PRINT_I(x) \ 305 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 306 307 if (!(flags & NVM_CHANNEL_VALID)) { 308 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 309 chan, flags); 310 return; 311 } 312 313 /* Note: already can print up to 101 characters, 110 is the limit! */ 314 IWL_DEBUG_DEV(dev, level, 315 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 316 chan, flags, 317 CHECK_AND_PRINT_I(VALID), 318 CHECK_AND_PRINT_I(IBSS), 319 CHECK_AND_PRINT_I(ACTIVE), 320 CHECK_AND_PRINT_I(RADAR), 321 CHECK_AND_PRINT_I(INDOOR_ONLY), 322 CHECK_AND_PRINT_I(GO_CONCURRENT), 323 CHECK_AND_PRINT_I(UNIFORM), 324 CHECK_AND_PRINT_I(20MHZ), 325 CHECK_AND_PRINT_I(40MHZ), 326 CHECK_AND_PRINT_I(80MHZ), 327 CHECK_AND_PRINT_I(160MHZ), 328 CHECK_AND_PRINT_I(DC_HIGH), 329 CHECK_AND_PRINT_I(VLP), 330 CHECK_AND_PRINT_I(AFC)); 331 #undef CHECK_AND_PRINT_I 332 } 333 334 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band, 335 u32 nvm_flags, const struct iwl_cfg *cfg) 336 { 337 u32 flags = IEEE80211_CHAN_NO_HT40; 338 339 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) { 340 if (ch_num <= LAST_2GHZ_HT_PLUS) 341 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 342 if (ch_num >= FIRST_2GHZ_HT_MINUS) 343 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 344 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 345 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 346 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 347 else 348 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 349 } 350 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 351 flags |= IEEE80211_CHAN_NO_80MHZ; 352 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 353 flags |= IEEE80211_CHAN_NO_160MHZ; 354 355 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 356 flags |= IEEE80211_CHAN_NO_IR; 357 358 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 359 flags |= IEEE80211_CHAN_NO_IR; 360 361 if (nvm_flags & NVM_CHANNEL_RADAR) 362 flags |= IEEE80211_CHAN_RADAR; 363 364 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 365 flags |= IEEE80211_CHAN_INDOOR_ONLY; 366 367 /* Set the GO concurrent flag only in case that NO_IR is set. 368 * Otherwise it is meaningless 369 */ 370 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 371 (flags & IEEE80211_CHAN_NO_IR)) 372 flags |= IEEE80211_CHAN_IR_CONCURRENT; 373 374 /* Set the AP type for the UHB case. */ 375 if (nvm_flags & NVM_CHANNEL_VLP) 376 flags |= IEEE80211_CHAN_ALLOW_6GHZ_VLP_AP; 377 else 378 flags |= IEEE80211_CHAN_NO_6GHZ_VLP_CLIENT; 379 if (!(nvm_flags & NVM_CHANNEL_AFC)) 380 flags |= IEEE80211_CHAN_NO_6GHZ_AFC_CLIENT; 381 382 return flags; 383 } 384 385 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx) 386 { 387 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) { 388 return NL80211_BAND_6GHZ; 389 } 390 391 if (ch_idx >= NUM_2GHZ_CHANNELS) 392 return NL80211_BAND_5GHZ; 393 return NL80211_BAND_2GHZ; 394 } 395 396 static int iwl_init_channel_map(struct iwl_trans *trans, 397 const struct iwl_fw *fw, 398 struct iwl_nvm_data *data, 399 const void * const nvm_ch_flags, 400 u32 sbands_flags, bool v4) 401 { 402 const struct iwl_cfg *cfg = trans->cfg; 403 struct device *dev = trans->dev; 404 int ch_idx; 405 int n_channels = 0; 406 struct ieee80211_channel *channel; 407 u32 ch_flags; 408 int num_of_ch; 409 const u16 *nvm_chan; 410 411 if (cfg->uhb_supported) { 412 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB; 413 nvm_chan = iwl_uhb_nvm_channels; 414 } else if (cfg->nvm_type == IWL_NVM_EXT) { 415 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 416 nvm_chan = iwl_ext_nvm_channels; 417 } else { 418 num_of_ch = IWL_NVM_NUM_CHANNELS; 419 nvm_chan = iwl_nvm_channels; 420 } 421 422 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 423 enum nl80211_band band = 424 iwl_nl80211_band_from_channel_idx(ch_idx); 425 426 if (v4) 427 ch_flags = 428 __le32_to_cpup((const __le32 *)nvm_ch_flags + ch_idx); 429 else 430 ch_flags = 431 __le16_to_cpup((const __le16 *)nvm_ch_flags + ch_idx); 432 433 if (band == NL80211_BAND_5GHZ && 434 !data->sku_cap_band_52ghz_enable) 435 continue; 436 437 /* workaround to disable wide channels in 5GHz */ 438 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 439 band == NL80211_BAND_5GHZ) { 440 ch_flags &= ~(NVM_CHANNEL_40MHZ | 441 NVM_CHANNEL_80MHZ | 442 NVM_CHANNEL_160MHZ); 443 } 444 445 if (ch_flags & NVM_CHANNEL_160MHZ) 446 data->vht160_supported = true; 447 448 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 449 !(ch_flags & NVM_CHANNEL_VALID)) { 450 /* 451 * Channels might become valid later if lar is 452 * supported, hence we still want to add them to 453 * the list of supported channels to cfg80211. 454 */ 455 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 456 nvm_chan[ch_idx], ch_flags); 457 continue; 458 } 459 460 channel = &data->channels[n_channels]; 461 n_channels++; 462 463 channel->hw_value = nvm_chan[ch_idx]; 464 channel->band = band; 465 channel->center_freq = 466 ieee80211_channel_to_frequency( 467 channel->hw_value, channel->band); 468 469 /* Initialize regulatory-based run-time data */ 470 471 /* 472 * Default value - highest tx power value. max_power 473 * is not used in mvm, and is used for backwards compatibility 474 */ 475 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 476 477 /* don't put limitations in case we're using LAR */ 478 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 479 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 480 ch_idx, band, 481 ch_flags, cfg); 482 else 483 channel->flags = 0; 484 485 if (fw_has_capa(&fw->ucode_capa, 486 IWL_UCODE_TLV_CAPA_MONITOR_PASSIVE_CHANS)) 487 channel->flags |= IEEE80211_CHAN_CAN_MONITOR; 488 489 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 490 channel->hw_value, ch_flags); 491 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 492 channel->hw_value, channel->max_power); 493 } 494 495 return n_channels; 496 } 497 498 static void iwl_init_vht_hw_capab(struct iwl_trans *trans, 499 struct iwl_nvm_data *data, 500 struct ieee80211_sta_vht_cap *vht_cap, 501 u8 tx_chains, u8 rx_chains) 502 { 503 const struct iwl_cfg *cfg = trans->cfg; 504 int num_rx_ants = num_of_ant(rx_chains); 505 int num_tx_ants = num_of_ant(tx_chains); 506 507 vht_cap->vht_supported = true; 508 509 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 510 IEEE80211_VHT_CAP_RXSTBC_1 | 511 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 512 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 513 IEEE80211_VHT_MAX_AMPDU_1024K << 514 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 515 516 if (!trans->cfg->ht_params->stbc) 517 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXSTBC_MASK; 518 519 if (data->vht160_supported) 520 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 521 IEEE80211_VHT_CAP_SHORT_GI_160; 522 523 if (cfg->vht_mu_mimo_supported) 524 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 525 526 if (cfg->ht_params->ldpc) 527 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 528 529 if (data->sku_cap_mimo_disabled) { 530 num_rx_ants = 1; 531 num_tx_ants = 1; 532 } 533 534 if (trans->cfg->ht_params->stbc && num_tx_ants > 1) 535 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 536 else 537 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 538 539 switch (iwlwifi_mod_params.amsdu_size) { 540 case IWL_AMSDU_DEF: 541 if (trans->trans_cfg->mq_rx_supported) 542 vht_cap->cap |= 543 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 544 else 545 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 546 break; 547 case IWL_AMSDU_2K: 548 if (trans->trans_cfg->mq_rx_supported) 549 vht_cap->cap |= 550 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 551 else 552 WARN(1, "RB size of 2K is not supported by this device\n"); 553 break; 554 case IWL_AMSDU_4K: 555 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 556 break; 557 case IWL_AMSDU_8K: 558 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 559 break; 560 case IWL_AMSDU_12K: 561 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 562 break; 563 default: 564 break; 565 } 566 567 vht_cap->vht_mcs.rx_mcs_map = 568 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 569 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 570 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 571 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 572 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 573 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 574 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 575 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 576 577 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 578 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 579 /* this works because NOT_SUPPORTED == 3 */ 580 vht_cap->vht_mcs.rx_mcs_map |= 581 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 582 } 583 584 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 585 586 vht_cap->vht_mcs.tx_highest |= 587 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 588 } 589 590 static const u8 iwl_vendor_caps[] = { 591 0xdd, /* vendor element */ 592 0x06, /* length */ 593 0x00, 0x17, 0x35, /* Intel OUI */ 594 0x08, /* type (Intel Capabilities) */ 595 /* followed by 16 bits of capabilities */ 596 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0) 597 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE, 598 0x00 599 }; 600 601 static const struct ieee80211_sband_iftype_data iwl_he_eht_capa[] = { 602 { 603 .types_mask = BIT(NL80211_IFTYPE_STATION) | 604 BIT(NL80211_IFTYPE_P2P_CLIENT), 605 .he_cap = { 606 .has_he = true, 607 .he_cap_elem = { 608 .mac_cap_info[0] = 609 IEEE80211_HE_MAC_CAP0_HTC_HE, 610 .mac_cap_info[1] = 611 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 612 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 613 .mac_cap_info[2] = 614 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP, 615 .mac_cap_info[3] = 616 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 617 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS, 618 .mac_cap_info[4] = 619 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU | 620 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 621 .mac_cap_info[5] = 622 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 623 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 624 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU | 625 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS | 626 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, 627 .phy_cap_info[1] = 628 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 629 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 630 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 631 .phy_cap_info[2] = 632 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 633 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 634 .phy_cap_info[3] = 635 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 636 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 637 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 638 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 639 .phy_cap_info[4] = 640 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 641 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 642 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 643 .phy_cap_info[6] = 644 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 645 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB | 646 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 647 .phy_cap_info[7] = 648 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 649 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 650 .phy_cap_info[8] = 651 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 652 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 653 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 654 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 655 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 656 .phy_cap_info[9] = 657 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 658 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 659 (IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED << 660 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS), 661 .phy_cap_info[10] = 662 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF, 663 }, 664 /* 665 * Set default Tx/Rx HE MCS NSS Support field. 666 * Indicate support for up to 2 spatial streams and all 667 * MCS, without any special cases 668 */ 669 .he_mcs_nss_supp = { 670 .rx_mcs_80 = cpu_to_le16(0xfffa), 671 .tx_mcs_80 = cpu_to_le16(0xfffa), 672 .rx_mcs_160 = cpu_to_le16(0xfffa), 673 .tx_mcs_160 = cpu_to_le16(0xfffa), 674 .rx_mcs_80p80 = cpu_to_le16(0xffff), 675 .tx_mcs_80p80 = cpu_to_le16(0xffff), 676 }, 677 /* 678 * Set default PPE thresholds, with PPET16 set to 0, 679 * PPET8 set to 7 680 */ 681 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 682 }, 683 .eht_cap = { 684 .has_eht = true, 685 .eht_cap_elem = { 686 .mac_cap_info[0] = 687 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 688 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 689 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 690 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2 | 691 IEEE80211_EHT_MAC_CAP0_SCS_TRAFFIC_DESC, 692 .mac_cap_info[1] = 693 IEEE80211_EHT_MAC_CAP1_UNSOL_EPCS_PRIO_ACCESS, 694 .phy_cap_info[0] = 695 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ | 696 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 697 IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO | 698 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE | 699 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK, 700 .phy_cap_info[1] = 701 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK | 702 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK, 703 .phy_cap_info[3] = 704 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 705 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 706 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 707 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 708 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 709 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK | 710 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK, 711 712 .phy_cap_info[4] = 713 IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO | 714 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 715 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI, 716 .phy_cap_info[5] = 717 FIELD_PREP_CONST(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK, 718 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US) | 719 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | 720 IEEE80211_EHT_PHY_CAP5_TX_LESS_242_TONE_RU_SUPP | 721 IEEE80211_EHT_PHY_CAP5_RX_LESS_242_TONE_RU_SUPP, 722 .phy_cap_info[6] = 723 IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK | 724 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP, 725 .phy_cap_info[8] = 726 IEEE80211_EHT_PHY_CAP8_RX_1024QAM_WIDER_BW_DL_OFDMA | 727 IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA, 728 }, 729 730 /* For all MCS and bandwidth, set 2 NSS for both Tx and 731 * Rx - note we don't set the only_20mhz, but due to this 732 * being a union, it gets set correctly anyway. 733 */ 734 .eht_mcs_nss_supp = { 735 .bw._80 = { 736 .rx_tx_mcs9_max_nss = 0x22, 737 .rx_tx_mcs11_max_nss = 0x22, 738 .rx_tx_mcs13_max_nss = 0x22, 739 }, 740 .bw._160 = { 741 .rx_tx_mcs9_max_nss = 0x22, 742 .rx_tx_mcs11_max_nss = 0x22, 743 .rx_tx_mcs13_max_nss = 0x22, 744 }, 745 .bw._320 = { 746 .rx_tx_mcs9_max_nss = 0x22, 747 .rx_tx_mcs11_max_nss = 0x22, 748 .rx_tx_mcs13_max_nss = 0x22, 749 }, 750 }, 751 752 /* 753 * PPE thresholds for NSS = 2, and RU index bitmap set 754 * to 0xc. 755 * Note: just for stating what we want, not present in 756 * the transmitted data due to not including 757 * IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT. 758 */ 759 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 } 760 }, 761 }, 762 { 763 .types_mask = BIT(NL80211_IFTYPE_AP) | 764 BIT(NL80211_IFTYPE_P2P_GO), 765 .he_cap = { 766 .has_he = true, 767 .he_cap_elem = { 768 .mac_cap_info[0] = 769 IEEE80211_HE_MAC_CAP0_HTC_HE, 770 .mac_cap_info[1] = 771 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 772 .mac_cap_info[3] = 773 IEEE80211_HE_MAC_CAP3_OMI_CONTROL, 774 .phy_cap_info[1] = 775 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 776 .phy_cap_info[2] = 777 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 778 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 779 .phy_cap_info[3] = 780 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 781 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 782 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 783 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 784 .phy_cap_info[6] = 785 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 786 .phy_cap_info[7] = 787 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 788 .phy_cap_info[8] = 789 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 790 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 791 .phy_cap_info[9] = 792 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED 793 << IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS, 794 }, 795 /* 796 * Set default Tx/Rx HE MCS NSS Support field. 797 * Indicate support for up to 2 spatial streams and all 798 * MCS, without any special cases 799 */ 800 .he_mcs_nss_supp = { 801 .rx_mcs_80 = cpu_to_le16(0xfffa), 802 .tx_mcs_80 = cpu_to_le16(0xfffa), 803 .rx_mcs_160 = cpu_to_le16(0xfffa), 804 .tx_mcs_160 = cpu_to_le16(0xfffa), 805 .rx_mcs_80p80 = cpu_to_le16(0xffff), 806 .tx_mcs_80p80 = cpu_to_le16(0xffff), 807 }, 808 /* 809 * Set default PPE thresholds, with PPET16 set to 0, 810 * PPET8 set to 7 811 */ 812 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 813 }, 814 .eht_cap = { 815 .has_eht = true, 816 .eht_cap_elem = { 817 .mac_cap_info[0] = 818 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 819 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 820 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2, 821 .phy_cap_info[0] = 822 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ | 823 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI, 824 .phy_cap_info[5] = 825 FIELD_PREP_CONST(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK, 826 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US), 827 }, 828 829 /* For all MCS and bandwidth, set 2 NSS for both Tx and 830 * Rx - note we don't set the only_20mhz, but due to this 831 * being a union, it gets set correctly anyway. 832 */ 833 .eht_mcs_nss_supp = { 834 .bw._80 = { 835 .rx_tx_mcs9_max_nss = 0x22, 836 .rx_tx_mcs11_max_nss = 0x22, 837 .rx_tx_mcs13_max_nss = 0x22, 838 }, 839 .bw._160 = { 840 .rx_tx_mcs9_max_nss = 0x22, 841 .rx_tx_mcs11_max_nss = 0x22, 842 .rx_tx_mcs13_max_nss = 0x22, 843 }, 844 .bw._320 = { 845 .rx_tx_mcs9_max_nss = 0x22, 846 .rx_tx_mcs11_max_nss = 0x22, 847 .rx_tx_mcs13_max_nss = 0x22, 848 }, 849 }, 850 851 /* 852 * PPE thresholds for NSS = 2, and RU index bitmap set 853 * to 0xc. 854 * Note: just for stating what we want, not present in 855 * the transmitted data due to not including 856 * IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT. 857 */ 858 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 } 859 }, 860 }, 861 }; 862 863 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans, 864 struct iwl_nvm_data *data, 865 struct ieee80211_supported_band *sband, 866 u8 tx_chains, u8 rx_chains) 867 { 868 struct ieee80211_sta_ht_cap ht_cap; 869 struct ieee80211_sta_vht_cap vht_cap = {}; 870 struct ieee80211_sband_iftype_data *iftype_data; 871 u16 he_6ghz_capa = 0; 872 u32 exp; 873 int i; 874 875 if (sband->band != NL80211_BAND_6GHZ) 876 return; 877 878 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */ 879 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ, 880 tx_chains, rx_chains); 881 WARN_ON(!ht_cap.ht_supported); 882 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains); 883 WARN_ON(!vht_cap.vht_supported); 884 885 he_6ghz_capa |= 886 u16_encode_bits(ht_cap.ampdu_density, 887 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START); 888 exp = u32_get_bits(vht_cap.cap, 889 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK); 890 he_6ghz_capa |= 891 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP); 892 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK); 893 he_6ghz_capa |= 894 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 895 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */ 896 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN) 897 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS; 898 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN) 899 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 900 901 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa); 902 903 /* we know it's writable - we set it before ourselves */ 904 iftype_data = (void *)(uintptr_t)sband->iftype_data; 905 for (i = 0; i < sband->n_iftype_data; i++) 906 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa); 907 } 908 909 static void 910 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans, 911 struct iwl_nvm_data *data, 912 struct ieee80211_supported_band *sband, 913 struct ieee80211_sband_iftype_data *iftype_data, 914 u8 tx_chains, u8 rx_chains, 915 const struct iwl_fw *fw) 916 { 917 bool is_ap = iftype_data->types_mask & (BIT(NL80211_IFTYPE_AP) | 918 BIT(NL80211_IFTYPE_P2P_GO)); 919 bool slow_pcie = (!trans->trans_cfg->integrated && 920 trans->pcie_link_speed < PCI_EXP_LNKSTA_CLS_8_0GB); 921 922 if (!data->sku_cap_11be_enable || iwlwifi_mod_params.disable_11be) 923 iftype_data->eht_cap.has_eht = false; 924 925 /* Advertise an A-MPDU exponent extension based on 926 * operating band 927 */ 928 if (sband->band == NL80211_BAND_6GHZ && iftype_data->eht_cap.has_eht) 929 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 930 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 931 else if (sband->band != NL80211_BAND_2GHZ) 932 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 933 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1; 934 else 935 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 936 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 937 938 switch (sband->band) { 939 case NL80211_BAND_2GHZ: 940 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 941 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 942 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] |= 943 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 944 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 945 break; 946 case NL80211_BAND_6GHZ: 947 if (!trans->reduced_cap_sku && 948 trans->bw_limit >= 320) { 949 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |= 950 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 951 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[1] |= 952 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK; 953 } 954 fallthrough; 955 case NL80211_BAND_5GHZ: 956 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 957 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 958 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 959 break; 960 default: 961 WARN_ON(1); 962 break; 963 } 964 965 if ((tx_chains & rx_chains) == ANT_AB) { 966 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 967 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ; 968 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |= 969 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 970 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2; 971 if (!is_ap) { 972 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 973 IEEE80211_HE_PHY_CAP7_MAX_NC_2; 974 975 if (iftype_data->eht_cap.has_eht) { 976 /* 977 * Set the number of sounding dimensions for each 978 * bandwidth to 1 to indicate the maximal supported 979 * value of TXVECTOR parameter NUM_STS of 2 980 */ 981 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] |= 0x49; 982 983 /* 984 * Set the MAX NC to 1 to indicate sounding feedback of 985 * 2 supported by the beamfomee. 986 */ 987 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] |= 0x10; 988 } 989 } 990 991 if (slow_pcie) { 992 struct ieee80211_eht_mcs_nss_supp *mcs_nss = 993 &iftype_data->eht_cap.eht_mcs_nss_supp; 994 995 mcs_nss->bw._320.rx_tx_mcs11_max_nss = 0; 996 mcs_nss->bw._320.rx_tx_mcs13_max_nss = 0; 997 } 998 } else { 999 struct ieee80211_he_mcs_nss_supp *he_mcs_nss_supp = 1000 &iftype_data->he_cap.he_mcs_nss_supp; 1001 1002 if (iftype_data->eht_cap.has_eht) { 1003 struct ieee80211_eht_mcs_nss_supp *mcs_nss = 1004 &iftype_data->eht_cap.eht_mcs_nss_supp; 1005 1006 memset(mcs_nss, 0x11, sizeof(*mcs_nss)); 1007 } 1008 1009 if (!is_ap) { 1010 /* If not 2x2, we need to indicate 1x1 in the 1011 * Midamble RX Max NSTS - but not for AP mode 1012 */ 1013 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &= 1014 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 1015 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 1016 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 1017 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 1018 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 1019 } 1020 1021 he_mcs_nss_supp->rx_mcs_80 |= 1022 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2); 1023 he_mcs_nss_supp->tx_mcs_80 |= 1024 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2); 1025 he_mcs_nss_supp->rx_mcs_160 |= 1026 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2); 1027 he_mcs_nss_supp->tx_mcs_160 |= 1028 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2); 1029 he_mcs_nss_supp->rx_mcs_80p80 |= 1030 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2); 1031 he_mcs_nss_supp->tx_mcs_80p80 |= 1032 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2); 1033 } 1034 1035 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210 && !is_ap) 1036 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 1037 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 1038 1039 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 1040 case IWL_CFG_RF_TYPE_GF: 1041 case IWL_CFG_RF_TYPE_FM: 1042 case IWL_CFG_RF_TYPE_WH: 1043 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 1044 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 1045 if (!is_ap) 1046 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 1047 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1048 break; 1049 } 1050 1051 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL && 1052 iftype_data->eht_cap.has_eht) { 1053 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] &= 1054 ~(IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 | 1055 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2); 1056 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[3] &= 1057 ~(IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO | 1058 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1059 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1060 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1061 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 1062 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK | 1063 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK); 1064 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] &= 1065 ~(IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO | 1066 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP); 1067 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] &= 1068 ~IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK; 1069 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[6] &= 1070 ~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK | 1071 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP); 1072 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] |= 1073 IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF; 1074 } 1075 1076 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT)) 1077 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |= 1078 IEEE80211_HE_MAC_CAP2_BCAST_TWT; 1079 1080 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1081 !is_ap) { 1082 iftype_data->vendor_elems.data = iwl_vendor_caps; 1083 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps); 1084 } 1085 1086 if (!trans->cfg->ht_params->stbc) { 1087 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 1088 ~IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1089 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] &= 1090 ~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1091 } 1092 1093 if (trans->step_urm) { 1094 iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs11_max_nss = 0; 1095 iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs13_max_nss = 0; 1096 } 1097 1098 if (trans->bw_limit < 160) 1099 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] &= 1100 ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1101 1102 if (trans->bw_limit < 320 || trans->reduced_cap_sku) { 1103 memset(&iftype_data->eht_cap.eht_mcs_nss_supp.bw._320, 0, 1104 sizeof(iftype_data->eht_cap.eht_mcs_nss_supp.bw._320)); 1105 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] &= 1106 ~IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK; 1107 } 1108 1109 if (trans->reduced_cap_sku) { 1110 iftype_data->eht_cap.eht_mcs_nss_supp.bw._80.rx_tx_mcs13_max_nss = 0; 1111 iftype_data->eht_cap.eht_mcs_nss_supp.bw._160.rx_tx_mcs13_max_nss = 0; 1112 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[8] &= 1113 ~IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA; 1114 } 1115 } 1116 1117 static void iwl_init_he_hw_capab(struct iwl_trans *trans, 1118 struct iwl_nvm_data *data, 1119 struct ieee80211_supported_band *sband, 1120 u8 tx_chains, u8 rx_chains, 1121 const struct iwl_fw *fw) 1122 { 1123 struct ieee80211_sband_iftype_data *iftype_data; 1124 int i; 1125 1126 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_eht_capa)); 1127 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_eht_capa)); 1128 BUILD_BUG_ON(sizeof(data->iftd.uhb) != sizeof(iwl_he_eht_capa)); 1129 1130 switch (sband->band) { 1131 case NL80211_BAND_2GHZ: 1132 iftype_data = data->iftd.low; 1133 break; 1134 case NL80211_BAND_5GHZ: 1135 iftype_data = data->iftd.high; 1136 break; 1137 case NL80211_BAND_6GHZ: 1138 iftype_data = data->iftd.uhb; 1139 break; 1140 default: 1141 WARN_ON(1); 1142 return; 1143 } 1144 1145 memcpy(iftype_data, iwl_he_eht_capa, sizeof(iwl_he_eht_capa)); 1146 1147 _ieee80211_set_sband_iftype_data(sband, iftype_data, 1148 ARRAY_SIZE(iwl_he_eht_capa)); 1149 1150 for (i = 0; i < sband->n_iftype_data; i++) 1151 iwl_nvm_fixup_sband_iftd(trans, data, sband, &iftype_data[i], 1152 tx_chains, rx_chains, fw); 1153 1154 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains); 1155 } 1156 1157 void iwl_reinit_cab(struct iwl_trans *trans, struct iwl_nvm_data *data, 1158 u8 tx_chains, u8 rx_chains, const struct iwl_fw *fw) 1159 { 1160 struct ieee80211_supported_band *sband; 1161 1162 sband = &data->bands[NL80211_BAND_2GHZ]; 1163 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 1164 tx_chains, rx_chains); 1165 1166 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1167 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1168 fw); 1169 1170 sband = &data->bands[NL80211_BAND_5GHZ]; 1171 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 1172 tx_chains, rx_chains); 1173 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 1174 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 1175 tx_chains, rx_chains); 1176 1177 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1178 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1179 fw); 1180 1181 sband = &data->bands[NL80211_BAND_6GHZ]; 1182 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1183 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1184 fw); 1185 } 1186 IWL_EXPORT_SYMBOL(iwl_reinit_cab); 1187 1188 static void iwl_init_sbands(struct iwl_trans *trans, 1189 struct iwl_nvm_data *data, 1190 const void *nvm_ch_flags, u8 tx_chains, 1191 u8 rx_chains, u32 sbands_flags, bool v4, 1192 const struct iwl_fw *fw) 1193 { 1194 struct device *dev = trans->dev; 1195 int n_channels; 1196 int n_used = 0; 1197 struct ieee80211_supported_band *sband; 1198 1199 n_channels = iwl_init_channel_map(trans, fw, data, nvm_ch_flags, 1200 sbands_flags, v4); 1201 sband = &data->bands[NL80211_BAND_2GHZ]; 1202 sband->band = NL80211_BAND_2GHZ; 1203 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 1204 sband->n_bitrates = N_RATES_24; 1205 n_used += iwl_init_sband_channels(data, sband, n_channels, 1206 NL80211_BAND_2GHZ); 1207 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 1208 tx_chains, rx_chains); 1209 1210 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1211 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1212 fw); 1213 1214 sband = &data->bands[NL80211_BAND_5GHZ]; 1215 sband->band = NL80211_BAND_5GHZ; 1216 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 1217 sband->n_bitrates = N_RATES_52; 1218 n_used += iwl_init_sband_channels(data, sband, n_channels, 1219 NL80211_BAND_5GHZ); 1220 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 1221 tx_chains, rx_chains); 1222 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 1223 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 1224 tx_chains, rx_chains); 1225 1226 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1227 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1228 fw); 1229 1230 /* 6GHz band. */ 1231 sband = &data->bands[NL80211_BAND_6GHZ]; 1232 sband->band = NL80211_BAND_6GHZ; 1233 /* use the same rates as 5GHz band */ 1234 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 1235 sband->n_bitrates = N_RATES_52; 1236 n_used += iwl_init_sband_channels(data, sband, n_channels, 1237 NL80211_BAND_6GHZ); 1238 1239 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 1240 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 1241 fw); 1242 else 1243 sband->n_channels = 0; 1244 if (n_channels != n_used) 1245 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 1246 n_used, n_channels); 1247 } 1248 1249 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 1250 const __le16 *phy_sku) 1251 { 1252 if (cfg->nvm_type != IWL_NVM_EXT) 1253 return le16_to_cpup(nvm_sw + SKU); 1254 1255 return le32_to_cpup((const __le32 *)(phy_sku + SKU_FAMILY_8000)); 1256 } 1257 1258 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 1259 { 1260 if (cfg->nvm_type != IWL_NVM_EXT) 1261 return le16_to_cpup(nvm_sw + NVM_VERSION); 1262 else 1263 return le32_to_cpup((const __le32 *)(nvm_sw + 1264 NVM_VERSION_EXT_NVM)); 1265 } 1266 1267 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 1268 const __le16 *phy_sku) 1269 { 1270 if (cfg->nvm_type != IWL_NVM_EXT) 1271 return le16_to_cpup(nvm_sw + RADIO_CFG); 1272 1273 return le32_to_cpup((const __le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 1274 1275 } 1276 1277 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 1278 { 1279 int n_hw_addr; 1280 1281 if (cfg->nvm_type != IWL_NVM_EXT) 1282 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 1283 1284 n_hw_addr = le32_to_cpup((const __le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 1285 1286 return n_hw_addr & N_HW_ADDR_MASK; 1287 } 1288 1289 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 1290 struct iwl_nvm_data *data, 1291 u32 radio_cfg) 1292 { 1293 if (cfg->nvm_type != IWL_NVM_EXT) { 1294 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 1295 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 1296 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 1297 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 1298 return; 1299 } 1300 1301 /* set the radio configuration for family 8000 */ 1302 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 1303 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 1304 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 1305 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 1306 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 1307 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 1308 } 1309 1310 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 1311 { 1312 const u8 *hw_addr; 1313 1314 hw_addr = (const u8 *)&mac_addr0; 1315 dest[0] = hw_addr[3]; 1316 dest[1] = hw_addr[2]; 1317 dest[2] = hw_addr[1]; 1318 dest[3] = hw_addr[0]; 1319 1320 hw_addr = (const u8 *)&mac_addr1; 1321 dest[4] = hw_addr[1]; 1322 dest[5] = hw_addr[0]; 1323 } 1324 1325 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 1326 struct iwl_nvm_data *data) 1327 { 1328 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, 1329 CSR_MAC_ADDR0_STRAP(trans))); 1330 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, 1331 CSR_MAC_ADDR1_STRAP(trans))); 1332 1333 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1334 /* 1335 * If the OEM fused a valid address, use it instead of the one in the 1336 * OTP 1337 */ 1338 if (is_valid_ether_addr(data->hw_addr)) 1339 return; 1340 1341 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans))); 1342 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans))); 1343 1344 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1345 } 1346 1347 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 1348 const struct iwl_cfg *cfg, 1349 struct iwl_nvm_data *data, 1350 const __le16 *mac_override, 1351 const __be16 *nvm_hw) 1352 { 1353 const u8 *hw_addr; 1354 1355 if (mac_override) { 1356 static const u8 reserved_mac[] = { 1357 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 1358 }; 1359 1360 hw_addr = (const u8 *)(mac_override + 1361 MAC_ADDRESS_OVERRIDE_EXT_NVM); 1362 1363 /* 1364 * Store the MAC address from MAO section. 1365 * No byte swapping is required in MAO section 1366 */ 1367 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 1368 1369 /* 1370 * Force the use of the OTP MAC address in case of reserved MAC 1371 * address in the NVM, or if address is given but invalid. 1372 */ 1373 if (is_valid_ether_addr(data->hw_addr) && 1374 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 1375 return; 1376 1377 IWL_ERR(trans, 1378 "mac address from nvm override section is not valid\n"); 1379 } 1380 1381 if (nvm_hw) { 1382 /* read the mac address from WFMP registers */ 1383 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 1384 WFMP_MAC_ADDR_0)); 1385 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 1386 WFMP_MAC_ADDR_1)); 1387 1388 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1389 1390 return; 1391 } 1392 1393 IWL_ERR(trans, "mac address is not found\n"); 1394 } 1395 1396 static int iwl_set_hw_address(struct iwl_trans *trans, 1397 const struct iwl_cfg *cfg, 1398 struct iwl_nvm_data *data, const __be16 *nvm_hw, 1399 const __le16 *mac_override) 1400 { 1401 if (cfg->mac_addr_from_csr) { 1402 iwl_set_hw_address_from_csr(trans, data); 1403 } else if (cfg->nvm_type != IWL_NVM_EXT) { 1404 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 1405 1406 /* The byte order is little endian 16 bit, meaning 214365 */ 1407 data->hw_addr[0] = hw_addr[1]; 1408 data->hw_addr[1] = hw_addr[0]; 1409 data->hw_addr[2] = hw_addr[3]; 1410 data->hw_addr[3] = hw_addr[2]; 1411 data->hw_addr[4] = hw_addr[5]; 1412 data->hw_addr[5] = hw_addr[4]; 1413 } else { 1414 iwl_set_hw_address_family_8000(trans, cfg, data, 1415 mac_override, nvm_hw); 1416 } 1417 1418 if (!is_valid_ether_addr(data->hw_addr)) { 1419 IWL_ERR(trans, "no valid mac address was found\n"); 1420 return -EINVAL; 1421 } 1422 1423 if (!trans->csme_own) 1424 IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n", 1425 data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR)); 1426 1427 return 0; 1428 } 1429 1430 static bool 1431 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1432 const __be16 *nvm_hw) 1433 { 1434 /* 1435 * Workaround a bug in Indonesia SKUs where the regulatory in 1436 * some 7000-family OTPs erroneously allow wide channels in 1437 * 5GHz. To check for Indonesia, we take the SKU value from 1438 * bits 1-4 in the subsystem ID and check if it is either 5 or 1439 * 9. In those cases, we need to force-disable wide channels 1440 * in 5GHz otherwise the FW will throw a sysassert when we try 1441 * to use them. 1442 */ 1443 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1444 /* 1445 * Unlike the other sections in the NVM, the hw 1446 * section uses big-endian. 1447 */ 1448 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 1449 u8 sku = (subsystem_id & 0x1e) >> 1; 1450 1451 if (sku == 5 || sku == 9) { 1452 IWL_DEBUG_EEPROM(trans->dev, 1453 "disabling wide channels in 5GHz (0x%0x %d)\n", 1454 subsystem_id, sku); 1455 return true; 1456 } 1457 } 1458 1459 return false; 1460 } 1461 1462 struct iwl_nvm_data * 1463 iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1464 const struct iwl_mei_nvm *mei_nvm, 1465 const struct iwl_fw *fw, u8 tx_ant, u8 rx_ant) 1466 { 1467 struct iwl_nvm_data *data; 1468 u32 sbands_flags = 0; 1469 u8 rx_chains = fw->valid_rx_ant; 1470 u8 tx_chains = fw->valid_rx_ant; 1471 1472 if (cfg->uhb_supported) 1473 data = kzalloc(struct_size(data, channels, 1474 IWL_NVM_NUM_CHANNELS_UHB), 1475 GFP_KERNEL); 1476 else 1477 data = kzalloc(struct_size(data, channels, 1478 IWL_NVM_NUM_CHANNELS_EXT), 1479 GFP_KERNEL); 1480 if (!data) 1481 return NULL; 1482 1483 BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) != 1484 IWL_NVM_NUM_CHANNELS_UHB); 1485 data->nvm_version = mei_nvm->nvm_version; 1486 1487 iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg); 1488 if (data->valid_tx_ant) 1489 tx_chains &= data->valid_tx_ant; 1490 if (data->valid_rx_ant) 1491 rx_chains &= data->valid_rx_ant; 1492 if (tx_ant) 1493 tx_chains &= tx_ant; 1494 if (rx_ant) 1495 rx_chains &= rx_ant; 1496 1497 data->sku_cap_mimo_disabled = false; 1498 data->sku_cap_band_24ghz_enable = true; 1499 data->sku_cap_band_52ghz_enable = true; 1500 data->sku_cap_11n_enable = 1501 !(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL); 1502 data->sku_cap_11ac_enable = true; 1503 data->sku_cap_11ax_enable = 1504 mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT; 1505 1506 data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT; 1507 1508 data->n_hw_addrs = mei_nvm->n_hw_addrs; 1509 /* If no valid mac address was found - bail out */ 1510 if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) { 1511 kfree(data); 1512 return NULL; 1513 } 1514 1515 if (data->lar_enabled && 1516 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1517 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1518 1519 iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains, 1520 sbands_flags, true, fw); 1521 1522 return data; 1523 } 1524 IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data); 1525 1526 struct iwl_nvm_data * 1527 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1528 const struct iwl_fw *fw, 1529 const __be16 *nvm_hw, const __le16 *nvm_sw, 1530 const __le16 *nvm_calib, const __le16 *regulatory, 1531 const __le16 *mac_override, const __le16 *phy_sku, 1532 u8 tx_chains, u8 rx_chains) 1533 { 1534 struct iwl_nvm_data *data; 1535 bool lar_enabled; 1536 u32 sku, radio_cfg; 1537 u32 sbands_flags = 0; 1538 u16 lar_config; 1539 const __le16 *ch_section; 1540 1541 if (cfg->uhb_supported) 1542 data = kzalloc(struct_size(data, channels, 1543 IWL_NVM_NUM_CHANNELS_UHB), 1544 GFP_KERNEL); 1545 else if (cfg->nvm_type != IWL_NVM_EXT) 1546 data = kzalloc(struct_size(data, channels, 1547 IWL_NVM_NUM_CHANNELS), 1548 GFP_KERNEL); 1549 else 1550 data = kzalloc(struct_size(data, channels, 1551 IWL_NVM_NUM_CHANNELS_EXT), 1552 GFP_KERNEL); 1553 if (!data) 1554 return NULL; 1555 1556 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 1557 1558 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 1559 iwl_set_radio_cfg(cfg, data, radio_cfg); 1560 if (data->valid_tx_ant) 1561 tx_chains &= data->valid_tx_ant; 1562 if (data->valid_rx_ant) 1563 rx_chains &= data->valid_rx_ant; 1564 1565 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 1566 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 1567 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 1568 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 1569 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1570 data->sku_cap_11n_enable = false; 1571 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 1572 (sku & NVM_SKU_CAP_11AC_ENABLE); 1573 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 1574 1575 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 1576 1577 if (cfg->nvm_type != IWL_NVM_EXT) { 1578 /* Checking for required sections */ 1579 if (!nvm_calib) { 1580 IWL_ERR(trans, 1581 "Can't parse empty Calib NVM sections\n"); 1582 kfree(data); 1583 return NULL; 1584 } 1585 1586 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 1587 ®ulatory[NVM_CHANNELS_SDP] : 1588 &nvm_sw[NVM_CHANNELS]; 1589 1590 lar_enabled = true; 1591 } else { 1592 u16 lar_offset = data->nvm_version < 0xE39 ? 1593 NVM_LAR_OFFSET_OLD : 1594 NVM_LAR_OFFSET; 1595 1596 lar_config = le16_to_cpup(regulatory + lar_offset); 1597 data->lar_enabled = !!(lar_config & 1598 NVM_LAR_ENABLED); 1599 lar_enabled = data->lar_enabled; 1600 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1601 } 1602 1603 /* If no valid mac address was found - bail out */ 1604 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1605 kfree(data); 1606 return NULL; 1607 } 1608 1609 if (lar_enabled && 1610 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1611 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1612 1613 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw)) 1614 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1615 1616 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains, 1617 sbands_flags, false, fw); 1618 data->calib_version = 255; 1619 1620 return data; 1621 } 1622 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1623 1624 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan, 1625 int ch_idx, u16 nvm_flags, 1626 struct iwl_reg_capa reg_capa, 1627 const struct iwl_cfg *cfg) 1628 { 1629 u32 flags = NL80211_RRF_NO_HT40; 1630 1631 if (ch_idx < NUM_2GHZ_CHANNELS && 1632 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1633 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1634 flags &= ~NL80211_RRF_NO_HT40PLUS; 1635 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1636 flags &= ~NL80211_RRF_NO_HT40MINUS; 1637 } else if (ch_idx < NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS && 1638 nvm_flags & NVM_CHANNEL_40MHZ) { 1639 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1640 flags &= ~NL80211_RRF_NO_HT40PLUS; 1641 else 1642 flags &= ~NL80211_RRF_NO_HT40MINUS; 1643 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 1644 flags &= ~NL80211_RRF_NO_HT40PLUS; 1645 flags &= ~NL80211_RRF_NO_HT40MINUS; 1646 } 1647 1648 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1649 flags |= NL80211_RRF_NO_80MHZ; 1650 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1651 flags |= NL80211_RRF_NO_160MHZ; 1652 1653 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1654 flags |= NL80211_RRF_NO_IR; 1655 1656 if (nvm_flags & NVM_CHANNEL_RADAR) 1657 flags |= NL80211_RRF_DFS; 1658 1659 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1660 flags |= NL80211_RRF_NO_OUTDOOR; 1661 1662 /* Set the GO concurrent flag only in case that NO_IR is set. 1663 * Otherwise it is meaningless 1664 */ 1665 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT)) { 1666 if (flags & NL80211_RRF_NO_IR) 1667 flags |= NL80211_RRF_GO_CONCURRENT; 1668 if (flags & NL80211_RRF_DFS) { 1669 flags |= NL80211_RRF_DFS_CONCURRENT; 1670 /* Our device doesn't set active bit for DFS channels 1671 * however, once marked as DFS no-ir is not needed. 1672 */ 1673 flags &= ~NL80211_RRF_NO_IR; 1674 } 1675 } 1676 1677 /* Set the AP type for the UHB case. */ 1678 if (nvm_flags & NVM_CHANNEL_VLP) 1679 flags |= NL80211_RRF_ALLOW_6GHZ_VLP_AP; 1680 else 1681 flags |= NL80211_RRF_NO_6GHZ_VLP_CLIENT; 1682 1683 if (!(nvm_flags & NVM_CHANNEL_AFC)) 1684 flags |= NL80211_RRF_NO_6GHZ_AFC_CLIENT; 1685 1686 /* 1687 * reg_capa is per regulatory domain so apply it for every channel 1688 */ 1689 if (ch_idx >= NUM_2GHZ_CHANNELS) { 1690 if (!reg_capa.allow_40mhz) 1691 flags |= NL80211_RRF_NO_HT40; 1692 1693 if (!reg_capa.allow_80mhz) 1694 flags |= NL80211_RRF_NO_80MHZ; 1695 1696 if (!reg_capa.allow_160mhz) 1697 flags |= NL80211_RRF_NO_160MHZ; 1698 1699 if (!reg_capa.allow_320mhz) 1700 flags |= NL80211_RRF_NO_320MHZ; 1701 } 1702 1703 if (reg_capa.disable_11ax) 1704 flags |= NL80211_RRF_NO_HE; 1705 1706 if (reg_capa.disable_11be) 1707 flags |= NL80211_RRF_NO_EHT; 1708 1709 return flags; 1710 } 1711 1712 static struct iwl_reg_capa iwl_get_reg_capa(u32 flags, u8 resp_ver) 1713 { 1714 struct iwl_reg_capa reg_capa = {}; 1715 1716 if (resp_ver >= REG_CAPA_V4_RESP_VER) { 1717 reg_capa.allow_40mhz = true; 1718 reg_capa.allow_80mhz = flags & REG_CAPA_V4_80MHZ_ALLOWED; 1719 reg_capa.allow_160mhz = flags & REG_CAPA_V4_160MHZ_ALLOWED; 1720 reg_capa.allow_320mhz = flags & REG_CAPA_V4_320MHZ_ALLOWED; 1721 reg_capa.disable_11ax = flags & REG_CAPA_V4_11AX_DISABLED; 1722 reg_capa.disable_11be = flags & REG_CAPA_V4_11BE_DISABLED; 1723 } else if (resp_ver >= REG_CAPA_V2_RESP_VER) { 1724 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED; 1725 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED; 1726 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED; 1727 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED; 1728 } else { 1729 reg_capa.allow_40mhz = !(flags & REG_CAPA_V1_40MHZ_FORBIDDEN); 1730 reg_capa.allow_80mhz = flags & REG_CAPA_V1_80MHZ_ALLOWED; 1731 reg_capa.allow_160mhz = flags & REG_CAPA_V1_160MHZ_ALLOWED; 1732 reg_capa.disable_11ax = flags & REG_CAPA_V1_11AX_DISABLED; 1733 } 1734 return reg_capa; 1735 } 1736 1737 struct ieee80211_regdomain * 1738 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1739 int num_of_ch, __le32 *channels, u16 fw_mcc, 1740 u16 geo_info, u32 cap, u8 resp_ver) 1741 { 1742 int ch_idx; 1743 u16 ch_flags; 1744 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1745 const u16 *nvm_chan; 1746 struct ieee80211_regdomain *regd, *copy_rd; 1747 struct ieee80211_reg_rule *rule; 1748 int center_freq, prev_center_freq = 0; 1749 int valid_rules = 0; 1750 bool new_rule; 1751 int max_num_ch; 1752 struct iwl_reg_capa reg_capa; 1753 1754 if (cfg->uhb_supported) { 1755 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB; 1756 nvm_chan = iwl_uhb_nvm_channels; 1757 } else if (cfg->nvm_type == IWL_NVM_EXT) { 1758 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT; 1759 nvm_chan = iwl_ext_nvm_channels; 1760 } else { 1761 max_num_ch = IWL_NVM_NUM_CHANNELS; 1762 nvm_chan = iwl_nvm_channels; 1763 } 1764 1765 if (num_of_ch > max_num_ch) { 1766 IWL_DEBUG_DEV(dev, IWL_DL_LAR, 1767 "Num of channels (%d) is greater than expected. Truncating to %d\n", 1768 num_of_ch, max_num_ch); 1769 num_of_ch = max_num_ch; 1770 } 1771 1772 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1773 return ERR_PTR(-EINVAL); 1774 1775 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1776 num_of_ch); 1777 1778 /* build a regdomain rule for every valid channel */ 1779 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL); 1780 if (!regd) 1781 return ERR_PTR(-ENOMEM); 1782 1783 /* set alpha2 from FW. */ 1784 regd->alpha2[0] = fw_mcc >> 8; 1785 regd->alpha2[1] = fw_mcc & 0xff; 1786 1787 /* parse regulatory capability flags */ 1788 reg_capa = iwl_get_reg_capa(cap, resp_ver); 1789 1790 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1791 enum nl80211_band band = 1792 iwl_nl80211_band_from_channel_idx(ch_idx); 1793 1794 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1795 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1796 band); 1797 new_rule = false; 1798 1799 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1800 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1801 nvm_chan[ch_idx], ch_flags); 1802 continue; 1803 } 1804 1805 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1806 ch_flags, reg_capa, 1807 cfg); 1808 1809 /* we can't continue the same rule */ 1810 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1811 center_freq - prev_center_freq > 20) { 1812 valid_rules++; 1813 new_rule = true; 1814 } 1815 1816 rule = ®d->reg_rules[valid_rules - 1]; 1817 1818 if (new_rule) 1819 rule->freq_range.start_freq_khz = 1820 MHZ_TO_KHZ(center_freq - 10); 1821 1822 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1823 1824 /* this doesn't matter - not used by FW */ 1825 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1826 rule->power_rule.max_eirp = 1827 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1828 1829 rule->flags = reg_rule_flags; 1830 1831 /* rely on auto-calculation to merge BW of contiguous chans */ 1832 rule->flags |= NL80211_RRF_AUTO_BW; 1833 rule->freq_range.max_bandwidth_khz = 0; 1834 1835 prev_center_freq = center_freq; 1836 prev_reg_rule_flags = reg_rule_flags; 1837 1838 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1839 nvm_chan[ch_idx], ch_flags); 1840 1841 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1842 band == NL80211_BAND_2GHZ) 1843 continue; 1844 1845 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1846 } 1847 1848 /* 1849 * Certain firmware versions might report no valid channels 1850 * if booted in RF-kill, i.e. not all calibrations etc. are 1851 * running. We'll get out of this situation later when the 1852 * rfkill is removed and we update the regdomain again, but 1853 * since cfg80211 doesn't accept an empty regdomain, add a 1854 * dummy (unusable) rule here in this case so we can init. 1855 */ 1856 if (!valid_rules) { 1857 valid_rules = 1; 1858 rule = ®d->reg_rules[valid_rules - 1]; 1859 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412); 1860 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413); 1861 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1); 1862 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1863 rule->power_rule.max_eirp = 1864 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1865 } 1866 1867 regd->n_reg_rules = valid_rules; 1868 1869 /* 1870 * Narrow down regdom for unused regulatory rules to prevent hole 1871 * between reg rules to wmm rules. 1872 */ 1873 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules), 1874 GFP_KERNEL); 1875 if (!copy_rd) 1876 copy_rd = ERR_PTR(-ENOMEM); 1877 1878 kfree(regd); 1879 return copy_rd; 1880 } 1881 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1882 1883 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1884 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1885 #define MAX_NVM_FILE_LEN 16384 1886 1887 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1888 unsigned int len) 1889 { 1890 #define IWL_4165_DEVICE_ID 0x5501 1891 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1892 1893 if (section == NVM_SECTION_TYPE_PHY_SKU && 1894 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1895 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1896 /* OTP 0x52 bug work around: it's a 1x1 device */ 1897 data[3] = ANT_B | (ANT_B << 4); 1898 } 1899 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1900 1901 /* 1902 * Reads external NVM from a file into mvm->nvm_sections 1903 * 1904 * HOW TO CREATE THE NVM FILE FORMAT: 1905 * ------------------------------ 1906 * 1. create hex file, format: 1907 * 3800 -> header 1908 * 0000 -> header 1909 * 5a40 -> data 1910 * 1911 * rev - 6 bit (word1) 1912 * len - 10 bit (word1) 1913 * id - 4 bit (word2) 1914 * rsv - 12 bit (word2) 1915 * 1916 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1917 * 1918 * 3. create binary file from the hex file 1919 * 1920 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1921 */ 1922 int iwl_read_external_nvm(struct iwl_trans *trans, 1923 const char *nvm_file_name, 1924 struct iwl_nvm_section *nvm_sections) 1925 { 1926 int ret, section_size; 1927 u16 section_id; 1928 const struct firmware *fw_entry; 1929 const struct { 1930 __le16 word1; 1931 __le16 word2; 1932 u8 data[]; 1933 } *file_sec; 1934 const u8 *eof; 1935 u8 *temp; 1936 int max_section_size; 1937 const __le32 *dword_buff; 1938 1939 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1940 #define NVM_WORD2_ID(x) (x >> 12) 1941 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1942 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1943 #define NVM_HEADER_0 (0x2A504C54) 1944 #define NVM_HEADER_1 (0x4E564D2A) 1945 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1946 1947 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1948 1949 /* Maximal size depends on NVM version */ 1950 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1951 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1952 else 1953 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1954 1955 /* 1956 * Obtain NVM image via request_firmware. Since we already used 1957 * request_firmware_nowait() for the firmware binary load and only 1958 * get here after that we assume the NVM request can be satisfied 1959 * synchronously. 1960 */ 1961 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1962 if (ret) { 1963 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1964 nvm_file_name, ret); 1965 return ret; 1966 } 1967 1968 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1969 nvm_file_name, fw_entry->size); 1970 1971 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1972 IWL_ERR(trans, "NVM file too large\n"); 1973 ret = -EINVAL; 1974 goto out; 1975 } 1976 1977 eof = fw_entry->data + fw_entry->size; 1978 dword_buff = (const __le32 *)fw_entry->data; 1979 1980 /* some NVM file will contain a header. 1981 * The header is identified by 2 dwords header as follow: 1982 * dword[0] = 0x2A504C54 1983 * dword[1] = 0x4E564D2A 1984 * 1985 * This header must be skipped when providing the NVM data to the FW. 1986 */ 1987 if (fw_entry->size > NVM_HEADER_SIZE && 1988 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1989 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1990 file_sec = (const void *)(fw_entry->data + NVM_HEADER_SIZE); 1991 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1992 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1993 le32_to_cpu(dword_buff[3])); 1994 1995 /* nvm file validation, dword_buff[2] holds the file version */ 1996 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1997 trans->hw_rev_step == SILICON_C_STEP && 1998 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1999 ret = -EFAULT; 2000 goto out; 2001 } 2002 } else { 2003 file_sec = (const void *)fw_entry->data; 2004 } 2005 2006 while (true) { 2007 if (file_sec->data > eof) { 2008 IWL_ERR(trans, 2009 "ERROR - NVM file too short for section header\n"); 2010 ret = -EINVAL; 2011 break; 2012 } 2013 2014 /* check for EOF marker */ 2015 if (!file_sec->word1 && !file_sec->word2) { 2016 ret = 0; 2017 break; 2018 } 2019 2020 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 2021 section_size = 2022 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 2023 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 2024 } else { 2025 section_size = 2 * EXT_NVM_WORD2_LEN( 2026 le16_to_cpu(file_sec->word2)); 2027 section_id = EXT_NVM_WORD1_ID( 2028 le16_to_cpu(file_sec->word1)); 2029 } 2030 2031 if (section_size > max_section_size) { 2032 IWL_ERR(trans, "ERROR - section too large (%d)\n", 2033 section_size); 2034 ret = -EINVAL; 2035 break; 2036 } 2037 2038 if (!section_size) { 2039 IWL_ERR(trans, "ERROR - section empty\n"); 2040 ret = -EINVAL; 2041 break; 2042 } 2043 2044 if (file_sec->data + section_size > eof) { 2045 IWL_ERR(trans, 2046 "ERROR - NVM file too short for section (%d bytes)\n", 2047 section_size); 2048 ret = -EINVAL; 2049 break; 2050 } 2051 2052 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 2053 "Invalid NVM section ID %d\n", section_id)) { 2054 ret = -EINVAL; 2055 break; 2056 } 2057 2058 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 2059 if (!temp) { 2060 ret = -ENOMEM; 2061 break; 2062 } 2063 2064 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 2065 2066 kfree(nvm_sections[section_id].data); 2067 nvm_sections[section_id].data = temp; 2068 nvm_sections[section_id].length = section_size; 2069 2070 /* advance to the next section */ 2071 file_sec = (const void *)(file_sec->data + section_size); 2072 } 2073 out: 2074 release_firmware(fw_entry); 2075 return ret; 2076 } 2077 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 2078 2079 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 2080 const struct iwl_fw *fw, 2081 u8 set_tx_ant, u8 set_rx_ant) 2082 { 2083 struct iwl_nvm_get_info cmd = {}; 2084 struct iwl_nvm_data *nvm; 2085 struct iwl_host_cmd hcmd = { 2086 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 2087 .data = { &cmd, }, 2088 .len = { sizeof(cmd) }, 2089 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 2090 }; 2091 int ret; 2092 bool empty_otp; 2093 u32 mac_flags; 2094 u32 sbands_flags = 0; 2095 u8 tx_ant; 2096 u8 rx_ant; 2097 2098 /* 2099 * All the values in iwl_nvm_get_info_rsp v4 are the same as 2100 * in v3, except for the channel profile part of the 2101 * regulatory. So we can just access the new struct, with the 2102 * exception of the latter. 2103 */ 2104 struct iwl_nvm_get_info_rsp *rsp; 2105 struct iwl_nvm_get_info_rsp_v3 *rsp_v3; 2106 bool v4 = fw_has_api(&fw->ucode_capa, 2107 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO); 2108 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3); 2109 void *channel_profile; 2110 2111 ret = iwl_trans_send_cmd(trans, &hcmd); 2112 if (ret) 2113 return ERR_PTR(ret); 2114 2115 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size, 2116 "Invalid payload len in NVM response from FW %d", 2117 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 2118 ret = -EINVAL; 2119 goto out; 2120 } 2121 2122 rsp = (void *)hcmd.resp_pkt->data; 2123 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 2124 NVM_GENERAL_FLAGS_EMPTY_OTP); 2125 if (empty_otp) 2126 IWL_INFO(trans, "OTP is empty\n"); 2127 2128 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL); 2129 if (!nvm) { 2130 ret = -ENOMEM; 2131 goto out; 2132 } 2133 2134 iwl_set_hw_address_from_csr(trans, nvm); 2135 /* TODO: if platform NVM has MAC address - override it here */ 2136 2137 if (!is_valid_ether_addr(nvm->hw_addr)) { 2138 IWL_ERR(trans, "no valid mac address was found\n"); 2139 ret = -EINVAL; 2140 goto err_free; 2141 } 2142 2143 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 2144 2145 /* Initialize general data */ 2146 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 2147 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 2148 if (nvm->n_hw_addrs == 0) 2149 IWL_WARN(trans, 2150 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 2151 empty_otp); 2152 2153 /* Initialize MAC sku data */ 2154 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 2155 nvm->sku_cap_11ac_enable = 2156 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 2157 nvm->sku_cap_11n_enable = 2158 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 2159 nvm->sku_cap_11ax_enable = 2160 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 2161 nvm->sku_cap_band_24ghz_enable = 2162 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 2163 nvm->sku_cap_band_52ghz_enable = 2164 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 2165 nvm->sku_cap_mimo_disabled = 2166 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 2167 if (CSR_HW_RFID_TYPE(trans->hw_rf_id) >= IWL_CFG_RF_TYPE_FM) 2168 nvm->sku_cap_11be_enable = true; 2169 2170 /* Initialize PHY sku data */ 2171 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 2172 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 2173 2174 if (le32_to_cpu(rsp->regulatory.lar_enabled) && 2175 fw_has_capa(&fw->ucode_capa, 2176 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) { 2177 nvm->lar_enabled = true; 2178 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 2179 } 2180 2181 rsp_v3 = (void *)rsp; 2182 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile : 2183 (void *)rsp_v3->regulatory.channel_profile; 2184 2185 tx_ant = nvm->valid_tx_ant & fw->valid_tx_ant; 2186 rx_ant = nvm->valid_rx_ant & fw->valid_rx_ant; 2187 2188 if (set_tx_ant) 2189 tx_ant &= set_tx_ant; 2190 if (set_rx_ant) 2191 rx_ant &= set_rx_ant; 2192 2193 iwl_init_sbands(trans, nvm, channel_profile, tx_ant, rx_ant, 2194 sbands_flags, v4, fw); 2195 2196 iwl_free_resp(&hcmd); 2197 return nvm; 2198 2199 err_free: 2200 kfree(nvm); 2201 out: 2202 iwl_free_resp(&hcmd); 2203 return ERR_PTR(ret); 2204 } 2205 IWL_EXPORT_SYMBOL(iwl_get_nvm); 2206