1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/types.h> 8 #include <linux/slab.h> 9 #include <linux/export.h> 10 #include <linux/etherdevice.h> 11 #include <linux/pci.h> 12 #include <linux/firmware.h> 13 14 #include "iwl-drv.h" 15 #include "iwl-modparams.h" 16 #include "iwl-nvm-parse.h" 17 #include "iwl-prph.h" 18 #include "iwl-io.h" 19 #include "iwl-csr.h" 20 #include "fw/acpi.h" 21 #include "fw/api/nvm-reg.h" 22 #include "fw/api/commands.h" 23 #include "fw/api/cmdhdr.h" 24 #include "fw/img.h" 25 #include "mei/iwl-mei.h" 26 27 /* NVM offsets (in words) definitions */ 28 enum nvm_offsets { 29 /* NVM HW-Section offset (in words) definitions */ 30 SUBSYSTEM_ID = 0x0A, 31 HW_ADDR = 0x15, 32 33 /* NVM SW-Section offset (in words) definitions */ 34 NVM_SW_SECTION = 0x1C0, 35 NVM_VERSION = 0, 36 RADIO_CFG = 1, 37 SKU = 2, 38 N_HW_ADDRS = 3, 39 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 40 41 /* NVM calibration section offset (in words) definitions */ 42 NVM_CALIB_SECTION = 0x2B8, 43 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 44 45 /* NVM REGULATORY -Section offset (in words) definitions */ 46 NVM_CHANNELS_SDP = 0, 47 }; 48 49 enum ext_nvm_offsets { 50 /* NVM HW-Section offset (in words) definitions */ 51 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 52 53 /* NVM SW-Section offset (in words) definitions */ 54 NVM_VERSION_EXT_NVM = 0, 55 N_HW_ADDRS_FAMILY_8000 = 3, 56 57 /* NVM PHY_SKU-Section offset (in words) definitions */ 58 RADIO_CFG_FAMILY_EXT_NVM = 0, 59 SKU_FAMILY_8000 = 2, 60 61 /* NVM REGULATORY -Section offset (in words) definitions */ 62 NVM_CHANNELS_EXTENDED = 0, 63 NVM_LAR_OFFSET_OLD = 0x4C7, 64 NVM_LAR_OFFSET = 0x507, 65 NVM_LAR_ENABLED = 0x7, 66 }; 67 68 /* SKU Capabilities (actual values from NVM definition) */ 69 enum nvm_sku_bits { 70 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 71 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 72 NVM_SKU_CAP_11N_ENABLE = BIT(2), 73 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 74 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 75 }; 76 77 /* 78 * These are the channel numbers in the order that they are stored in the NVM 79 */ 80 static const u16 iwl_nvm_channels[] = { 81 /* 2.4 GHz */ 82 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 83 /* 5 GHz */ 84 36, 40, 44 , 48, 52, 56, 60, 64, 85 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 86 149, 153, 157, 161, 165 87 }; 88 89 static const u16 iwl_ext_nvm_channels[] = { 90 /* 2.4 GHz */ 91 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 92 /* 5 GHz */ 93 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 94 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 95 149, 153, 157, 161, 165, 169, 173, 177, 181 96 }; 97 98 static const u16 iwl_uhb_nvm_channels[] = { 99 /* 2.4 GHz */ 100 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 101 /* 5 GHz */ 102 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 103 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 104 149, 153, 157, 161, 165, 169, 173, 177, 181, 105 /* 6-7 GHz */ 106 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 107 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 108 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185, 109 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233 110 }; 111 112 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 113 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 114 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels) 115 #define NUM_2GHZ_CHANNELS 14 116 #define NUM_5GHZ_CHANNELS 37 117 #define FIRST_2GHZ_HT_MINUS 5 118 #define LAST_2GHZ_HT_PLUS 9 119 #define N_HW_ADDR_MASK 0xF 120 121 /* rate data (static) */ 122 static struct ieee80211_rate iwl_cfg80211_rates[] = { 123 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 124 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 125 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 126 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 127 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 128 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 129 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 130 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 131 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 132 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 133 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 134 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 135 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 136 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 137 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 138 }; 139 #define RATES_24_OFFS 0 140 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 141 #define RATES_52_OFFS 4 142 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 143 144 /** 145 * enum iwl_nvm_channel_flags - channel flags in NVM 146 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 147 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 148 * @NVM_CHANNEL_ACTIVE: active scanning allowed 149 * @NVM_CHANNEL_RADAR: radar detection required 150 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 151 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 152 * on same channel on 2.4 or same UNII band on 5.2 153 * @NVM_CHANNEL_UNIFORM: uniform spreading required 154 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 155 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 156 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 157 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 158 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 159 */ 160 enum iwl_nvm_channel_flags { 161 NVM_CHANNEL_VALID = BIT(0), 162 NVM_CHANNEL_IBSS = BIT(1), 163 NVM_CHANNEL_ACTIVE = BIT(3), 164 NVM_CHANNEL_RADAR = BIT(4), 165 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 166 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 167 NVM_CHANNEL_UNIFORM = BIT(7), 168 NVM_CHANNEL_20MHZ = BIT(8), 169 NVM_CHANNEL_40MHZ = BIT(9), 170 NVM_CHANNEL_80MHZ = BIT(10), 171 NVM_CHANNEL_160MHZ = BIT(11), 172 NVM_CHANNEL_DC_HIGH = BIT(12), 173 }; 174 175 /** 176 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory 177 * domain. 178 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 179 * 2.4Ghz band is allowed. 180 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 181 * 5Ghz band is allowed. 182 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 183 * for this regulatory domain (valid only in 5Ghz). 184 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 185 * for this regulatory domain (valid only in 5Ghz). 186 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 187 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 188 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden 189 * for this regulatory domain (valid only in 5Ghz). 190 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed. 191 * @REG_CAPA_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 192 */ 193 enum iwl_reg_capa_flags { 194 REG_CAPA_BF_CCD_LOW_BAND = BIT(0), 195 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1), 196 REG_CAPA_160MHZ_ALLOWED = BIT(2), 197 REG_CAPA_80MHZ_ALLOWED = BIT(3), 198 REG_CAPA_MCS_8_ALLOWED = BIT(4), 199 REG_CAPA_MCS_9_ALLOWED = BIT(5), 200 REG_CAPA_40MHZ_FORBIDDEN = BIT(7), 201 REG_CAPA_DC_HIGH_ENABLED = BIT(9), 202 REG_CAPA_11AX_DISABLED = BIT(10), 203 }; 204 205 /** 206 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory 207 * domain (version 2). 208 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are 209 * disabled. 210 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the 211 * 2.4Ghz band is allowed. 212 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the 213 * 5Ghz band is allowed. 214 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed 215 * for this regulatory domain (valid only in 5Ghz). 216 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed 217 * for this regulatory domain (valid only in 5Ghz). 218 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed. 219 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed. 220 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118, 221 * 126, 122) are disabled. 222 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed 223 * for this regulatory domain (uvalid only in 5Ghz). 224 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain. 225 */ 226 enum iwl_reg_capa_flags_v2 { 227 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0), 228 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1), 229 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2), 230 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3), 231 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4), 232 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5), 233 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6), 234 REG_CAPA_V2_WEATHER_DISABLED = BIT(7), 235 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8), 236 REG_CAPA_V2_11AX_DISABLED = BIT(10), 237 }; 238 239 /* 240 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the 241 * MCC update command response. 242 */ 243 #define REG_CAPA_V2_RESP_VER 6 244 245 /** 246 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for 247 * handling the different APIs of reg_capa_flags. 248 * 249 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed 250 * for this regulatory domain (valid only in 5Ghz). 251 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed 252 * for this regulatory domain (valid only in 5Ghz). 253 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed 254 * for this regulatory domain (valid only in 5Ghz). 255 * @disable_11ax: 11ax is forbidden for this regulatory domain. 256 */ 257 struct iwl_reg_capa { 258 u16 allow_40mhz; 259 u16 allow_80mhz; 260 u16 allow_160mhz; 261 u16 disable_11ax; 262 }; 263 264 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 265 int chan, u32 flags) 266 { 267 #define CHECK_AND_PRINT_I(x) \ 268 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 269 270 if (!(flags & NVM_CHANNEL_VALID)) { 271 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 272 chan, flags); 273 return; 274 } 275 276 /* Note: already can print up to 101 characters, 110 is the limit! */ 277 IWL_DEBUG_DEV(dev, level, 278 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 279 chan, flags, 280 CHECK_AND_PRINT_I(VALID), 281 CHECK_AND_PRINT_I(IBSS), 282 CHECK_AND_PRINT_I(ACTIVE), 283 CHECK_AND_PRINT_I(RADAR), 284 CHECK_AND_PRINT_I(INDOOR_ONLY), 285 CHECK_AND_PRINT_I(GO_CONCURRENT), 286 CHECK_AND_PRINT_I(UNIFORM), 287 CHECK_AND_PRINT_I(20MHZ), 288 CHECK_AND_PRINT_I(40MHZ), 289 CHECK_AND_PRINT_I(80MHZ), 290 CHECK_AND_PRINT_I(160MHZ), 291 CHECK_AND_PRINT_I(DC_HIGH)); 292 #undef CHECK_AND_PRINT_I 293 } 294 295 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band, 296 u32 nvm_flags, const struct iwl_cfg *cfg) 297 { 298 u32 flags = IEEE80211_CHAN_NO_HT40; 299 300 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) { 301 if (ch_num <= LAST_2GHZ_HT_PLUS) 302 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 303 if (ch_num >= FIRST_2GHZ_HT_MINUS) 304 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 305 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 306 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 307 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 308 else 309 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 310 } 311 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 312 flags |= IEEE80211_CHAN_NO_80MHZ; 313 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 314 flags |= IEEE80211_CHAN_NO_160MHZ; 315 316 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 317 flags |= IEEE80211_CHAN_NO_IR; 318 319 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 320 flags |= IEEE80211_CHAN_NO_IR; 321 322 if (nvm_flags & NVM_CHANNEL_RADAR) 323 flags |= IEEE80211_CHAN_RADAR; 324 325 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 326 flags |= IEEE80211_CHAN_INDOOR_ONLY; 327 328 /* Set the GO concurrent flag only in case that NO_IR is set. 329 * Otherwise it is meaningless 330 */ 331 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 332 (flags & IEEE80211_CHAN_NO_IR)) 333 flags |= IEEE80211_CHAN_IR_CONCURRENT; 334 335 return flags; 336 } 337 338 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx) 339 { 340 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) { 341 return NL80211_BAND_6GHZ; 342 } 343 344 if (ch_idx >= NUM_2GHZ_CHANNELS) 345 return NL80211_BAND_5GHZ; 346 return NL80211_BAND_2GHZ; 347 } 348 349 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 350 struct iwl_nvm_data *data, 351 const void * const nvm_ch_flags, 352 u32 sbands_flags, bool v4) 353 { 354 int ch_idx; 355 int n_channels = 0; 356 struct ieee80211_channel *channel; 357 u32 ch_flags; 358 int num_of_ch; 359 const u16 *nvm_chan; 360 361 if (cfg->uhb_supported) { 362 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB; 363 nvm_chan = iwl_uhb_nvm_channels; 364 } else if (cfg->nvm_type == IWL_NVM_EXT) { 365 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 366 nvm_chan = iwl_ext_nvm_channels; 367 } else { 368 num_of_ch = IWL_NVM_NUM_CHANNELS; 369 nvm_chan = iwl_nvm_channels; 370 } 371 372 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 373 enum nl80211_band band = 374 iwl_nl80211_band_from_channel_idx(ch_idx); 375 376 if (v4) 377 ch_flags = 378 __le32_to_cpup((const __le32 *)nvm_ch_flags + ch_idx); 379 else 380 ch_flags = 381 __le16_to_cpup((const __le16 *)nvm_ch_flags + ch_idx); 382 383 if (band == NL80211_BAND_5GHZ && 384 !data->sku_cap_band_52ghz_enable) 385 continue; 386 387 /* workaround to disable wide channels in 5GHz */ 388 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 389 band == NL80211_BAND_5GHZ) { 390 ch_flags &= ~(NVM_CHANNEL_40MHZ | 391 NVM_CHANNEL_80MHZ | 392 NVM_CHANNEL_160MHZ); 393 } 394 395 if (ch_flags & NVM_CHANNEL_160MHZ) 396 data->vht160_supported = true; 397 398 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 399 !(ch_flags & NVM_CHANNEL_VALID)) { 400 /* 401 * Channels might become valid later if lar is 402 * supported, hence we still want to add them to 403 * the list of supported channels to cfg80211. 404 */ 405 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 406 nvm_chan[ch_idx], ch_flags); 407 continue; 408 } 409 410 channel = &data->channels[n_channels]; 411 n_channels++; 412 413 channel->hw_value = nvm_chan[ch_idx]; 414 channel->band = band; 415 channel->center_freq = 416 ieee80211_channel_to_frequency( 417 channel->hw_value, channel->band); 418 419 /* Initialize regulatory-based run-time data */ 420 421 /* 422 * Default value - highest tx power value. max_power 423 * is not used in mvm, and is used for backwards compatibility 424 */ 425 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 426 427 /* don't put limitations in case we're using LAR */ 428 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 429 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 430 ch_idx, band, 431 ch_flags, cfg); 432 else 433 channel->flags = 0; 434 435 /* TODO: Don't put limitations on UHB devices as we still don't 436 * have NVM for them 437 */ 438 if (cfg->uhb_supported) 439 channel->flags = 0; 440 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 441 channel->hw_value, ch_flags); 442 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 443 channel->hw_value, channel->max_power); 444 } 445 446 return n_channels; 447 } 448 449 static void iwl_init_vht_hw_capab(struct iwl_trans *trans, 450 struct iwl_nvm_data *data, 451 struct ieee80211_sta_vht_cap *vht_cap, 452 u8 tx_chains, u8 rx_chains) 453 { 454 const struct iwl_cfg *cfg = trans->cfg; 455 int num_rx_ants = num_of_ant(rx_chains); 456 int num_tx_ants = num_of_ant(tx_chains); 457 458 vht_cap->vht_supported = true; 459 460 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 461 IEEE80211_VHT_CAP_RXSTBC_1 | 462 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 463 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 464 IEEE80211_VHT_MAX_AMPDU_1024K << 465 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 466 467 if (data->vht160_supported) 468 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 469 IEEE80211_VHT_CAP_SHORT_GI_160; 470 471 if (cfg->vht_mu_mimo_supported) 472 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 473 474 if (cfg->ht_params->ldpc) 475 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 476 477 if (data->sku_cap_mimo_disabled) { 478 num_rx_ants = 1; 479 num_tx_ants = 1; 480 } 481 482 if (num_tx_ants > 1) 483 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 484 else 485 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 486 487 switch (iwlwifi_mod_params.amsdu_size) { 488 case IWL_AMSDU_DEF: 489 if (trans->trans_cfg->mq_rx_supported) 490 vht_cap->cap |= 491 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 492 else 493 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 494 break; 495 case IWL_AMSDU_2K: 496 if (trans->trans_cfg->mq_rx_supported) 497 vht_cap->cap |= 498 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 499 else 500 WARN(1, "RB size of 2K is not supported by this device\n"); 501 break; 502 case IWL_AMSDU_4K: 503 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 504 break; 505 case IWL_AMSDU_8K: 506 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 507 break; 508 case IWL_AMSDU_12K: 509 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 510 break; 511 default: 512 break; 513 } 514 515 vht_cap->vht_mcs.rx_mcs_map = 516 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 517 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 518 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 519 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 520 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 521 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 522 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 523 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 524 525 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 526 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 527 /* this works because NOT_SUPPORTED == 3 */ 528 vht_cap->vht_mcs.rx_mcs_map |= 529 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 530 } 531 532 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 533 534 vht_cap->vht_mcs.tx_highest |= 535 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 536 } 537 538 static const u8 iwl_vendor_caps[] = { 539 0xdd, /* vendor element */ 540 0x06, /* length */ 541 0x00, 0x17, 0x35, /* Intel OUI */ 542 0x08, /* type (Intel Capabilities) */ 543 /* followed by 16 bits of capabilities */ 544 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0) 545 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE, 546 0x00 547 }; 548 549 static const struct ieee80211_sband_iftype_data iwl_he_capa[] = { 550 { 551 .types_mask = BIT(NL80211_IFTYPE_STATION), 552 .he_cap = { 553 .has_he = true, 554 .he_cap_elem = { 555 .mac_cap_info[0] = 556 IEEE80211_HE_MAC_CAP0_HTC_HE, 557 .mac_cap_info[1] = 558 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 559 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 560 .mac_cap_info[2] = 561 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP, 562 .mac_cap_info[3] = 563 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 564 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS, 565 .mac_cap_info[4] = 566 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU | 567 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 568 .mac_cap_info[5] = 569 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 570 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 571 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU | 572 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS | 573 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX, 574 .phy_cap_info[0] = 575 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 576 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 577 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 578 .phy_cap_info[1] = 579 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 580 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 581 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 582 .phy_cap_info[2] = 583 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 584 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 585 .phy_cap_info[3] = 586 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 587 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 588 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 589 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 590 .phy_cap_info[4] = 591 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 592 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 593 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 594 .phy_cap_info[6] = 595 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 596 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB | 597 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 598 .phy_cap_info[7] = 599 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 600 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 601 .phy_cap_info[8] = 602 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 603 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 604 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 605 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 606 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 607 .phy_cap_info[9] = 608 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 609 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 610 (IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED << 611 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS), 612 .phy_cap_info[10] = 613 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF, 614 }, 615 /* 616 * Set default Tx/Rx HE MCS NSS Support field. 617 * Indicate support for up to 2 spatial streams and all 618 * MCS, without any special cases 619 */ 620 .he_mcs_nss_supp = { 621 .rx_mcs_80 = cpu_to_le16(0xfffa), 622 .tx_mcs_80 = cpu_to_le16(0xfffa), 623 .rx_mcs_160 = cpu_to_le16(0xfffa), 624 .tx_mcs_160 = cpu_to_le16(0xfffa), 625 .rx_mcs_80p80 = cpu_to_le16(0xffff), 626 .tx_mcs_80p80 = cpu_to_le16(0xffff), 627 }, 628 /* 629 * Set default PPE thresholds, with PPET16 set to 0, 630 * PPET8 set to 7 631 */ 632 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 633 }, 634 }, 635 { 636 .types_mask = BIT(NL80211_IFTYPE_AP), 637 .he_cap = { 638 .has_he = true, 639 .he_cap_elem = { 640 .mac_cap_info[0] = 641 IEEE80211_HE_MAC_CAP0_HTC_HE, 642 .mac_cap_info[1] = 643 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 644 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 645 .mac_cap_info[3] = 646 IEEE80211_HE_MAC_CAP3_OMI_CONTROL, 647 .phy_cap_info[0] = 648 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 649 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G, 650 .phy_cap_info[1] = 651 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD, 652 .phy_cap_info[2] = 653 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 654 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US, 655 .phy_cap_info[3] = 656 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 657 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 658 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 659 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 660 .phy_cap_info[6] = 661 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 662 .phy_cap_info[7] = 663 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI, 664 .phy_cap_info[8] = 665 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 666 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242, 667 .phy_cap_info[9] = 668 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED 669 << IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS, 670 }, 671 /* 672 * Set default Tx/Rx HE MCS NSS Support field. 673 * Indicate support for up to 2 spatial streams and all 674 * MCS, without any special cases 675 */ 676 .he_mcs_nss_supp = { 677 .rx_mcs_80 = cpu_to_le16(0xfffa), 678 .tx_mcs_80 = cpu_to_le16(0xfffa), 679 .rx_mcs_160 = cpu_to_le16(0xfffa), 680 .tx_mcs_160 = cpu_to_le16(0xfffa), 681 .rx_mcs_80p80 = cpu_to_le16(0xffff), 682 .tx_mcs_80p80 = cpu_to_le16(0xffff), 683 }, 684 /* 685 * Set default PPE thresholds, with PPET16 set to 0, 686 * PPET8 set to 7 687 */ 688 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 689 }, 690 }, 691 }; 692 693 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans, 694 struct iwl_nvm_data *data, 695 struct ieee80211_supported_band *sband, 696 u8 tx_chains, u8 rx_chains) 697 { 698 struct ieee80211_sta_ht_cap ht_cap; 699 struct ieee80211_sta_vht_cap vht_cap = {}; 700 struct ieee80211_sband_iftype_data *iftype_data; 701 u16 he_6ghz_capa = 0; 702 u32 exp; 703 int i; 704 705 if (sband->band != NL80211_BAND_6GHZ) 706 return; 707 708 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */ 709 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ, 710 tx_chains, rx_chains); 711 WARN_ON(!ht_cap.ht_supported); 712 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains); 713 WARN_ON(!vht_cap.vht_supported); 714 715 he_6ghz_capa |= 716 u16_encode_bits(ht_cap.ampdu_density, 717 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START); 718 exp = u32_get_bits(vht_cap.cap, 719 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK); 720 he_6ghz_capa |= 721 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP); 722 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK); 723 he_6ghz_capa |= 724 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 725 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */ 726 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN) 727 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS; 728 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN) 729 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 730 731 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa); 732 733 /* we know it's writable - we set it before ourselves */ 734 iftype_data = (void *)(uintptr_t)sband->iftype_data; 735 for (i = 0; i < sband->n_iftype_data; i++) 736 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa); 737 } 738 739 static void 740 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans, 741 struct ieee80211_supported_band *sband, 742 struct ieee80211_sband_iftype_data *iftype_data, 743 u8 tx_chains, u8 rx_chains, 744 const struct iwl_fw *fw) 745 { 746 bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP); 747 748 /* Advertise an A-MPDU exponent extension based on 749 * operating band 750 */ 751 if (sband->band != NL80211_BAND_2GHZ) 752 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 753 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1; 754 else 755 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |= 756 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 757 758 if (is_ap && iwlwifi_mod_params.nvm_file) 759 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |= 760 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 761 762 if ((tx_chains & rx_chains) == ANT_AB) { 763 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |= 764 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ; 765 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |= 766 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 767 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2; 768 if (!is_ap) 769 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 770 IEEE80211_HE_PHY_CAP7_MAX_NC_2; 771 } else if (!is_ap) { 772 /* If not 2x2, we need to indicate 1x1 in the 773 * Midamble RX Max NSTS - but not for AP mode 774 */ 775 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &= 776 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 777 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &= 778 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 779 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |= 780 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 781 } 782 783 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 784 case IWL_CFG_RF_TYPE_GF: 785 case IWL_CFG_RF_TYPE_MR: 786 case IWL_CFG_RF_TYPE_MS: 787 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 788 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 789 if (!is_ap) 790 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |= 791 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 792 break; 793 } 794 795 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT)) 796 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |= 797 IEEE80211_HE_MAC_CAP2_BCAST_TWT; 798 799 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 800 !is_ap) { 801 iftype_data->vendor_elems.data = iwl_vendor_caps; 802 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps); 803 } 804 } 805 806 static void iwl_init_he_hw_capab(struct iwl_trans *trans, 807 struct iwl_nvm_data *data, 808 struct ieee80211_supported_band *sband, 809 u8 tx_chains, u8 rx_chains, 810 const struct iwl_fw *fw) 811 { 812 struct ieee80211_sband_iftype_data *iftype_data; 813 int i; 814 815 /* should only initialize once */ 816 if (WARN_ON(sband->iftype_data)) 817 return; 818 819 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_capa)); 820 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_capa)); 821 822 switch (sband->band) { 823 case NL80211_BAND_2GHZ: 824 iftype_data = data->iftd.low; 825 break; 826 case NL80211_BAND_5GHZ: 827 case NL80211_BAND_6GHZ: 828 iftype_data = data->iftd.high; 829 break; 830 default: 831 WARN_ON(1); 832 return; 833 } 834 835 memcpy(iftype_data, iwl_he_capa, sizeof(iwl_he_capa)); 836 837 sband->iftype_data = iftype_data; 838 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa); 839 840 for (i = 0; i < sband->n_iftype_data; i++) 841 iwl_nvm_fixup_sband_iftd(trans, sband, &iftype_data[i], 842 tx_chains, rx_chains, fw); 843 844 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains); 845 } 846 847 static void iwl_init_sbands(struct iwl_trans *trans, 848 struct iwl_nvm_data *data, 849 const void *nvm_ch_flags, u8 tx_chains, 850 u8 rx_chains, u32 sbands_flags, bool v4, 851 const struct iwl_fw *fw) 852 { 853 struct device *dev = trans->dev; 854 const struct iwl_cfg *cfg = trans->cfg; 855 int n_channels; 856 int n_used = 0; 857 struct ieee80211_supported_band *sband; 858 859 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 860 sbands_flags, v4); 861 sband = &data->bands[NL80211_BAND_2GHZ]; 862 sband->band = NL80211_BAND_2GHZ; 863 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 864 sband->n_bitrates = N_RATES_24; 865 n_used += iwl_init_sband_channels(data, sband, n_channels, 866 NL80211_BAND_2GHZ); 867 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 868 tx_chains, rx_chains); 869 870 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 871 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 872 fw); 873 874 sband = &data->bands[NL80211_BAND_5GHZ]; 875 sband->band = NL80211_BAND_5GHZ; 876 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 877 sband->n_bitrates = N_RATES_52; 878 n_used += iwl_init_sband_channels(data, sband, n_channels, 879 NL80211_BAND_5GHZ); 880 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 881 tx_chains, rx_chains); 882 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 883 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap, 884 tx_chains, rx_chains); 885 886 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 887 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 888 fw); 889 890 /* 6GHz band. */ 891 sband = &data->bands[NL80211_BAND_6GHZ]; 892 sband->band = NL80211_BAND_6GHZ; 893 /* use the same rates as 5GHz band */ 894 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 895 sband->n_bitrates = N_RATES_52; 896 n_used += iwl_init_sband_channels(data, sband, n_channels, 897 NL80211_BAND_6GHZ); 898 899 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 900 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains, 901 fw); 902 else 903 sband->n_channels = 0; 904 if (n_channels != n_used) 905 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 906 n_used, n_channels); 907 } 908 909 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 910 const __le16 *phy_sku) 911 { 912 if (cfg->nvm_type != IWL_NVM_EXT) 913 return le16_to_cpup(nvm_sw + SKU); 914 915 return le32_to_cpup((const __le32 *)(phy_sku + SKU_FAMILY_8000)); 916 } 917 918 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 919 { 920 if (cfg->nvm_type != IWL_NVM_EXT) 921 return le16_to_cpup(nvm_sw + NVM_VERSION); 922 else 923 return le32_to_cpup((const __le32 *)(nvm_sw + 924 NVM_VERSION_EXT_NVM)); 925 } 926 927 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 928 const __le16 *phy_sku) 929 { 930 if (cfg->nvm_type != IWL_NVM_EXT) 931 return le16_to_cpup(nvm_sw + RADIO_CFG); 932 933 return le32_to_cpup((const __le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 934 935 } 936 937 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 938 { 939 int n_hw_addr; 940 941 if (cfg->nvm_type != IWL_NVM_EXT) 942 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 943 944 n_hw_addr = le32_to_cpup((const __le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 945 946 return n_hw_addr & N_HW_ADDR_MASK; 947 } 948 949 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 950 struct iwl_nvm_data *data, 951 u32 radio_cfg) 952 { 953 if (cfg->nvm_type != IWL_NVM_EXT) { 954 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 955 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 956 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 957 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 958 return; 959 } 960 961 /* set the radio configuration for family 8000 */ 962 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 963 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 964 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 965 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 966 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 967 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 968 } 969 970 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 971 { 972 const u8 *hw_addr; 973 974 hw_addr = (const u8 *)&mac_addr0; 975 dest[0] = hw_addr[3]; 976 dest[1] = hw_addr[2]; 977 dest[2] = hw_addr[1]; 978 dest[3] = hw_addr[0]; 979 980 hw_addr = (const u8 *)&mac_addr1; 981 dest[4] = hw_addr[1]; 982 dest[5] = hw_addr[0]; 983 } 984 985 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 986 struct iwl_nvm_data *data) 987 { 988 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans, 989 CSR_MAC_ADDR0_STRAP(trans))); 990 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans, 991 CSR_MAC_ADDR1_STRAP(trans))); 992 993 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 994 /* 995 * If the OEM fused a valid address, use it instead of the one in the 996 * OTP 997 */ 998 if (is_valid_ether_addr(data->hw_addr)) 999 return; 1000 1001 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans))); 1002 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans))); 1003 1004 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1005 } 1006 1007 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 1008 const struct iwl_cfg *cfg, 1009 struct iwl_nvm_data *data, 1010 const __le16 *mac_override, 1011 const __be16 *nvm_hw) 1012 { 1013 const u8 *hw_addr; 1014 1015 if (mac_override) { 1016 static const u8 reserved_mac[] = { 1017 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 1018 }; 1019 1020 hw_addr = (const u8 *)(mac_override + 1021 MAC_ADDRESS_OVERRIDE_EXT_NVM); 1022 1023 /* 1024 * Store the MAC address from MAO section. 1025 * No byte swapping is required in MAO section 1026 */ 1027 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 1028 1029 /* 1030 * Force the use of the OTP MAC address in case of reserved MAC 1031 * address in the NVM, or if address is given but invalid. 1032 */ 1033 if (is_valid_ether_addr(data->hw_addr) && 1034 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 1035 return; 1036 1037 IWL_ERR(trans, 1038 "mac address from nvm override section is not valid\n"); 1039 } 1040 1041 if (nvm_hw) { 1042 /* read the mac address from WFMP registers */ 1043 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 1044 WFMP_MAC_ADDR_0)); 1045 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 1046 WFMP_MAC_ADDR_1)); 1047 1048 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 1049 1050 return; 1051 } 1052 1053 IWL_ERR(trans, "mac address is not found\n"); 1054 } 1055 1056 static int iwl_set_hw_address(struct iwl_trans *trans, 1057 const struct iwl_cfg *cfg, 1058 struct iwl_nvm_data *data, const __be16 *nvm_hw, 1059 const __le16 *mac_override) 1060 { 1061 if (cfg->mac_addr_from_csr) { 1062 iwl_set_hw_address_from_csr(trans, data); 1063 } else if (cfg->nvm_type != IWL_NVM_EXT) { 1064 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 1065 1066 /* The byte order is little endian 16 bit, meaning 214365 */ 1067 data->hw_addr[0] = hw_addr[1]; 1068 data->hw_addr[1] = hw_addr[0]; 1069 data->hw_addr[2] = hw_addr[3]; 1070 data->hw_addr[3] = hw_addr[2]; 1071 data->hw_addr[4] = hw_addr[5]; 1072 data->hw_addr[5] = hw_addr[4]; 1073 } else { 1074 iwl_set_hw_address_family_8000(trans, cfg, data, 1075 mac_override, nvm_hw); 1076 } 1077 1078 if (!is_valid_ether_addr(data->hw_addr)) { 1079 IWL_ERR(trans, "no valid mac address was found\n"); 1080 return -EINVAL; 1081 } 1082 1083 if (!trans->csme_own) 1084 IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n", 1085 data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR)); 1086 1087 return 0; 1088 } 1089 1090 static bool 1091 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1092 const __be16 *nvm_hw) 1093 { 1094 /* 1095 * Workaround a bug in Indonesia SKUs where the regulatory in 1096 * some 7000-family OTPs erroneously allow wide channels in 1097 * 5GHz. To check for Indonesia, we take the SKU value from 1098 * bits 1-4 in the subsystem ID and check if it is either 5 or 1099 * 9. In those cases, we need to force-disable wide channels 1100 * in 5GHz otherwise the FW will throw a sysassert when we try 1101 * to use them. 1102 */ 1103 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1104 /* 1105 * Unlike the other sections in the NVM, the hw 1106 * section uses big-endian. 1107 */ 1108 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 1109 u8 sku = (subsystem_id & 0x1e) >> 1; 1110 1111 if (sku == 5 || sku == 9) { 1112 IWL_DEBUG_EEPROM(trans->dev, 1113 "disabling wide channels in 5GHz (0x%0x %d)\n", 1114 subsystem_id, sku); 1115 return true; 1116 } 1117 } 1118 1119 return false; 1120 } 1121 1122 struct iwl_nvm_data * 1123 iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1124 const struct iwl_mei_nvm *mei_nvm, 1125 const struct iwl_fw *fw) 1126 { 1127 struct iwl_nvm_data *data; 1128 u32 sbands_flags = 0; 1129 u8 rx_chains = fw->valid_rx_ant; 1130 u8 tx_chains = fw->valid_rx_ant; 1131 1132 if (cfg->uhb_supported) 1133 data = kzalloc(struct_size(data, channels, 1134 IWL_NVM_NUM_CHANNELS_UHB), 1135 GFP_KERNEL); 1136 else 1137 data = kzalloc(struct_size(data, channels, 1138 IWL_NVM_NUM_CHANNELS_EXT), 1139 GFP_KERNEL); 1140 if (!data) 1141 return NULL; 1142 1143 BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) != 1144 IWL_NVM_NUM_CHANNELS_UHB); 1145 data->nvm_version = mei_nvm->nvm_version; 1146 1147 iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg); 1148 if (data->valid_tx_ant) 1149 tx_chains &= data->valid_tx_ant; 1150 if (data->valid_rx_ant) 1151 rx_chains &= data->valid_rx_ant; 1152 1153 data->sku_cap_mimo_disabled = false; 1154 data->sku_cap_band_24ghz_enable = true; 1155 data->sku_cap_band_52ghz_enable = true; 1156 data->sku_cap_11n_enable = 1157 !(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL); 1158 data->sku_cap_11ac_enable = true; 1159 data->sku_cap_11ax_enable = 1160 mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT; 1161 1162 data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT; 1163 1164 data->n_hw_addrs = mei_nvm->n_hw_addrs; 1165 /* If no valid mac address was found - bail out */ 1166 if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) { 1167 kfree(data); 1168 return NULL; 1169 } 1170 1171 if (data->lar_enabled && 1172 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1173 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1174 1175 iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains, 1176 sbands_flags, true, fw); 1177 1178 return data; 1179 } 1180 IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data); 1181 1182 struct iwl_nvm_data * 1183 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1184 const struct iwl_fw *fw, 1185 const __be16 *nvm_hw, const __le16 *nvm_sw, 1186 const __le16 *nvm_calib, const __le16 *regulatory, 1187 const __le16 *mac_override, const __le16 *phy_sku, 1188 u8 tx_chains, u8 rx_chains) 1189 { 1190 struct iwl_nvm_data *data; 1191 bool lar_enabled; 1192 u32 sku, radio_cfg; 1193 u32 sbands_flags = 0; 1194 u16 lar_config; 1195 const __le16 *ch_section; 1196 1197 if (cfg->uhb_supported) 1198 data = kzalloc(struct_size(data, channels, 1199 IWL_NVM_NUM_CHANNELS_UHB), 1200 GFP_KERNEL); 1201 else if (cfg->nvm_type != IWL_NVM_EXT) 1202 data = kzalloc(struct_size(data, channels, 1203 IWL_NVM_NUM_CHANNELS), 1204 GFP_KERNEL); 1205 else 1206 data = kzalloc(struct_size(data, channels, 1207 IWL_NVM_NUM_CHANNELS_EXT), 1208 GFP_KERNEL); 1209 if (!data) 1210 return NULL; 1211 1212 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 1213 1214 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 1215 iwl_set_radio_cfg(cfg, data, radio_cfg); 1216 if (data->valid_tx_ant) 1217 tx_chains &= data->valid_tx_ant; 1218 if (data->valid_rx_ant) 1219 rx_chains &= data->valid_rx_ant; 1220 1221 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 1222 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 1223 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 1224 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 1225 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1226 data->sku_cap_11n_enable = false; 1227 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 1228 (sku & NVM_SKU_CAP_11AC_ENABLE); 1229 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 1230 1231 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 1232 1233 if (cfg->nvm_type != IWL_NVM_EXT) { 1234 /* Checking for required sections */ 1235 if (!nvm_calib) { 1236 IWL_ERR(trans, 1237 "Can't parse empty Calib NVM sections\n"); 1238 kfree(data); 1239 return NULL; 1240 } 1241 1242 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 1243 ®ulatory[NVM_CHANNELS_SDP] : 1244 &nvm_sw[NVM_CHANNELS]; 1245 1246 /* in family 8000 Xtal calibration values moved to OTP */ 1247 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 1248 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 1249 lar_enabled = true; 1250 } else { 1251 u16 lar_offset = data->nvm_version < 0xE39 ? 1252 NVM_LAR_OFFSET_OLD : 1253 NVM_LAR_OFFSET; 1254 1255 lar_config = le16_to_cpup(regulatory + lar_offset); 1256 data->lar_enabled = !!(lar_config & 1257 NVM_LAR_ENABLED); 1258 lar_enabled = data->lar_enabled; 1259 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1260 } 1261 1262 /* If no valid mac address was found - bail out */ 1263 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1264 kfree(data); 1265 return NULL; 1266 } 1267 1268 if (lar_enabled && 1269 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) 1270 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1271 1272 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw)) 1273 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1274 1275 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains, 1276 sbands_flags, false, fw); 1277 data->calib_version = 255; 1278 1279 return data; 1280 } 1281 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1282 1283 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan, 1284 int ch_idx, u16 nvm_flags, 1285 struct iwl_reg_capa reg_capa, 1286 const struct iwl_cfg *cfg) 1287 { 1288 u32 flags = NL80211_RRF_NO_HT40; 1289 1290 if (ch_idx < NUM_2GHZ_CHANNELS && 1291 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1292 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1293 flags &= ~NL80211_RRF_NO_HT40PLUS; 1294 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1295 flags &= ~NL80211_RRF_NO_HT40MINUS; 1296 } else if (nvm_flags & NVM_CHANNEL_40MHZ) { 1297 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1298 flags &= ~NL80211_RRF_NO_HT40PLUS; 1299 else 1300 flags &= ~NL80211_RRF_NO_HT40MINUS; 1301 } 1302 1303 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1304 flags |= NL80211_RRF_NO_80MHZ; 1305 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1306 flags |= NL80211_RRF_NO_160MHZ; 1307 1308 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1309 flags |= NL80211_RRF_NO_IR; 1310 1311 if (nvm_flags & NVM_CHANNEL_RADAR) 1312 flags |= NL80211_RRF_DFS; 1313 1314 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1315 flags |= NL80211_RRF_NO_OUTDOOR; 1316 1317 /* Set the GO concurrent flag only in case that NO_IR is set. 1318 * Otherwise it is meaningless 1319 */ 1320 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1321 (flags & NL80211_RRF_NO_IR)) 1322 flags |= NL80211_RRF_GO_CONCURRENT; 1323 1324 /* 1325 * reg_capa is per regulatory domain so apply it for every channel 1326 */ 1327 if (ch_idx >= NUM_2GHZ_CHANNELS) { 1328 if (!reg_capa.allow_40mhz) 1329 flags |= NL80211_RRF_NO_HT40; 1330 1331 if (!reg_capa.allow_80mhz) 1332 flags |= NL80211_RRF_NO_80MHZ; 1333 1334 if (!reg_capa.allow_160mhz) 1335 flags |= NL80211_RRF_NO_160MHZ; 1336 } 1337 if (reg_capa.disable_11ax) 1338 flags |= NL80211_RRF_NO_HE; 1339 1340 return flags; 1341 } 1342 1343 static struct iwl_reg_capa iwl_get_reg_capa(u16 flags, u8 resp_ver) 1344 { 1345 struct iwl_reg_capa reg_capa; 1346 1347 if (resp_ver >= REG_CAPA_V2_RESP_VER) { 1348 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED; 1349 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED; 1350 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED; 1351 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED; 1352 } else { 1353 reg_capa.allow_40mhz = !(flags & REG_CAPA_40MHZ_FORBIDDEN); 1354 reg_capa.allow_80mhz = flags & REG_CAPA_80MHZ_ALLOWED; 1355 reg_capa.allow_160mhz = flags & REG_CAPA_160MHZ_ALLOWED; 1356 reg_capa.disable_11ax = flags & REG_CAPA_11AX_DISABLED; 1357 } 1358 return reg_capa; 1359 } 1360 1361 struct ieee80211_regdomain * 1362 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1363 int num_of_ch, __le32 *channels, u16 fw_mcc, 1364 u16 geo_info, u16 cap, u8 resp_ver) 1365 { 1366 int ch_idx; 1367 u16 ch_flags; 1368 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1369 const u16 *nvm_chan; 1370 struct ieee80211_regdomain *regd, *copy_rd; 1371 struct ieee80211_reg_rule *rule; 1372 enum nl80211_band band; 1373 int center_freq, prev_center_freq = 0; 1374 int valid_rules = 0; 1375 bool new_rule; 1376 int max_num_ch; 1377 struct iwl_reg_capa reg_capa; 1378 1379 if (cfg->uhb_supported) { 1380 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB; 1381 nvm_chan = iwl_uhb_nvm_channels; 1382 } else if (cfg->nvm_type == IWL_NVM_EXT) { 1383 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT; 1384 nvm_chan = iwl_ext_nvm_channels; 1385 } else { 1386 max_num_ch = IWL_NVM_NUM_CHANNELS; 1387 nvm_chan = iwl_nvm_channels; 1388 } 1389 1390 if (num_of_ch > max_num_ch) { 1391 IWL_DEBUG_DEV(dev, IWL_DL_LAR, 1392 "Num of channels (%d) is greater than expected. Truncating to %d\n", 1393 num_of_ch, max_num_ch); 1394 num_of_ch = max_num_ch; 1395 } 1396 1397 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1398 return ERR_PTR(-EINVAL); 1399 1400 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1401 num_of_ch); 1402 1403 /* build a regdomain rule for every valid channel */ 1404 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL); 1405 if (!regd) 1406 return ERR_PTR(-ENOMEM); 1407 1408 /* set alpha2 from FW. */ 1409 regd->alpha2[0] = fw_mcc >> 8; 1410 regd->alpha2[1] = fw_mcc & 0xff; 1411 1412 /* parse regulatory capability flags */ 1413 reg_capa = iwl_get_reg_capa(cap, resp_ver); 1414 1415 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1416 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1417 band = iwl_nl80211_band_from_channel_idx(ch_idx); 1418 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1419 band); 1420 new_rule = false; 1421 1422 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1423 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1424 nvm_chan[ch_idx], ch_flags); 1425 continue; 1426 } 1427 1428 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1429 ch_flags, reg_capa, 1430 cfg); 1431 1432 /* we can't continue the same rule */ 1433 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1434 center_freq - prev_center_freq > 20) { 1435 valid_rules++; 1436 new_rule = true; 1437 } 1438 1439 rule = ®d->reg_rules[valid_rules - 1]; 1440 1441 if (new_rule) 1442 rule->freq_range.start_freq_khz = 1443 MHZ_TO_KHZ(center_freq - 10); 1444 1445 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1446 1447 /* this doesn't matter - not used by FW */ 1448 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1449 rule->power_rule.max_eirp = 1450 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1451 1452 rule->flags = reg_rule_flags; 1453 1454 /* rely on auto-calculation to merge BW of contiguous chans */ 1455 rule->flags |= NL80211_RRF_AUTO_BW; 1456 rule->freq_range.max_bandwidth_khz = 0; 1457 1458 prev_center_freq = center_freq; 1459 prev_reg_rule_flags = reg_rule_flags; 1460 1461 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1462 nvm_chan[ch_idx], ch_flags); 1463 1464 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1465 band == NL80211_BAND_2GHZ) 1466 continue; 1467 1468 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1469 } 1470 1471 /* 1472 * Certain firmware versions might report no valid channels 1473 * if booted in RF-kill, i.e. not all calibrations etc. are 1474 * running. We'll get out of this situation later when the 1475 * rfkill is removed and we update the regdomain again, but 1476 * since cfg80211 doesn't accept an empty regdomain, add a 1477 * dummy (unusable) rule here in this case so we can init. 1478 */ 1479 if (!valid_rules) { 1480 valid_rules = 1; 1481 rule = ®d->reg_rules[valid_rules - 1]; 1482 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412); 1483 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413); 1484 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1); 1485 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1486 rule->power_rule.max_eirp = 1487 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1488 } 1489 1490 regd->n_reg_rules = valid_rules; 1491 1492 /* 1493 * Narrow down regdom for unused regulatory rules to prevent hole 1494 * between reg rules to wmm rules. 1495 */ 1496 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules), 1497 GFP_KERNEL); 1498 if (!copy_rd) 1499 copy_rd = ERR_PTR(-ENOMEM); 1500 1501 kfree(regd); 1502 return copy_rd; 1503 } 1504 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1505 1506 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1507 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1508 #define MAX_NVM_FILE_LEN 16384 1509 1510 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1511 unsigned int len) 1512 { 1513 #define IWL_4165_DEVICE_ID 0x5501 1514 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1515 1516 if (section == NVM_SECTION_TYPE_PHY_SKU && 1517 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1518 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1519 /* OTP 0x52 bug work around: it's a 1x1 device */ 1520 data[3] = ANT_B | (ANT_B << 4); 1521 } 1522 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1523 1524 /* 1525 * Reads external NVM from a file into mvm->nvm_sections 1526 * 1527 * HOW TO CREATE THE NVM FILE FORMAT: 1528 * ------------------------------ 1529 * 1. create hex file, format: 1530 * 3800 -> header 1531 * 0000 -> header 1532 * 5a40 -> data 1533 * 1534 * rev - 6 bit (word1) 1535 * len - 10 bit (word1) 1536 * id - 4 bit (word2) 1537 * rsv - 12 bit (word2) 1538 * 1539 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1540 * 1541 * 3. create binary file from the hex file 1542 * 1543 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1544 */ 1545 int iwl_read_external_nvm(struct iwl_trans *trans, 1546 const char *nvm_file_name, 1547 struct iwl_nvm_section *nvm_sections) 1548 { 1549 int ret, section_size; 1550 u16 section_id; 1551 const struct firmware *fw_entry; 1552 const struct { 1553 __le16 word1; 1554 __le16 word2; 1555 u8 data[]; 1556 } *file_sec; 1557 const u8 *eof; 1558 u8 *temp; 1559 int max_section_size; 1560 const __le32 *dword_buff; 1561 1562 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1563 #define NVM_WORD2_ID(x) (x >> 12) 1564 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1565 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1566 #define NVM_HEADER_0 (0x2A504C54) 1567 #define NVM_HEADER_1 (0x4E564D2A) 1568 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1569 1570 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1571 1572 /* Maximal size depends on NVM version */ 1573 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1574 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1575 else 1576 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1577 1578 /* 1579 * Obtain NVM image via request_firmware. Since we already used 1580 * request_firmware_nowait() for the firmware binary load and only 1581 * get here after that we assume the NVM request can be satisfied 1582 * synchronously. 1583 */ 1584 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1585 if (ret) { 1586 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1587 nvm_file_name, ret); 1588 return ret; 1589 } 1590 1591 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1592 nvm_file_name, fw_entry->size); 1593 1594 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1595 IWL_ERR(trans, "NVM file too large\n"); 1596 ret = -EINVAL; 1597 goto out; 1598 } 1599 1600 eof = fw_entry->data + fw_entry->size; 1601 dword_buff = (const __le32 *)fw_entry->data; 1602 1603 /* some NVM file will contain a header. 1604 * The header is identified by 2 dwords header as follow: 1605 * dword[0] = 0x2A504C54 1606 * dword[1] = 0x4E564D2A 1607 * 1608 * This header must be skipped when providing the NVM data to the FW. 1609 */ 1610 if (fw_entry->size > NVM_HEADER_SIZE && 1611 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1612 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1613 file_sec = (const void *)(fw_entry->data + NVM_HEADER_SIZE); 1614 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1615 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1616 le32_to_cpu(dword_buff[3])); 1617 1618 /* nvm file validation, dword_buff[2] holds the file version */ 1619 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1620 trans->hw_rev_step == SILICON_C_STEP && 1621 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1622 ret = -EFAULT; 1623 goto out; 1624 } 1625 } else { 1626 file_sec = (const void *)fw_entry->data; 1627 } 1628 1629 while (true) { 1630 if (file_sec->data > eof) { 1631 IWL_ERR(trans, 1632 "ERROR - NVM file too short for section header\n"); 1633 ret = -EINVAL; 1634 break; 1635 } 1636 1637 /* check for EOF marker */ 1638 if (!file_sec->word1 && !file_sec->word2) { 1639 ret = 0; 1640 break; 1641 } 1642 1643 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1644 section_size = 1645 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1646 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1647 } else { 1648 section_size = 2 * EXT_NVM_WORD2_LEN( 1649 le16_to_cpu(file_sec->word2)); 1650 section_id = EXT_NVM_WORD1_ID( 1651 le16_to_cpu(file_sec->word1)); 1652 } 1653 1654 if (section_size > max_section_size) { 1655 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1656 section_size); 1657 ret = -EINVAL; 1658 break; 1659 } 1660 1661 if (!section_size) { 1662 IWL_ERR(trans, "ERROR - section empty\n"); 1663 ret = -EINVAL; 1664 break; 1665 } 1666 1667 if (file_sec->data + section_size > eof) { 1668 IWL_ERR(trans, 1669 "ERROR - NVM file too short for section (%d bytes)\n", 1670 section_size); 1671 ret = -EINVAL; 1672 break; 1673 } 1674 1675 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1676 "Invalid NVM section ID %d\n", section_id)) { 1677 ret = -EINVAL; 1678 break; 1679 } 1680 1681 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1682 if (!temp) { 1683 ret = -ENOMEM; 1684 break; 1685 } 1686 1687 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1688 1689 kfree(nvm_sections[section_id].data); 1690 nvm_sections[section_id].data = temp; 1691 nvm_sections[section_id].length = section_size; 1692 1693 /* advance to the next section */ 1694 file_sec = (const void *)(file_sec->data + section_size); 1695 } 1696 out: 1697 release_firmware(fw_entry); 1698 return ret; 1699 } 1700 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1701 1702 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1703 const struct iwl_fw *fw) 1704 { 1705 struct iwl_nvm_get_info cmd = {}; 1706 struct iwl_nvm_data *nvm; 1707 struct iwl_host_cmd hcmd = { 1708 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1709 .data = { &cmd, }, 1710 .len = { sizeof(cmd) }, 1711 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1712 }; 1713 int ret; 1714 bool empty_otp; 1715 u32 mac_flags; 1716 u32 sbands_flags = 0; 1717 /* 1718 * All the values in iwl_nvm_get_info_rsp v4 are the same as 1719 * in v3, except for the channel profile part of the 1720 * regulatory. So we can just access the new struct, with the 1721 * exception of the latter. 1722 */ 1723 struct iwl_nvm_get_info_rsp *rsp; 1724 struct iwl_nvm_get_info_rsp_v3 *rsp_v3; 1725 bool v4 = fw_has_api(&fw->ucode_capa, 1726 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO); 1727 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3); 1728 void *channel_profile; 1729 1730 ret = iwl_trans_send_cmd(trans, &hcmd); 1731 if (ret) 1732 return ERR_PTR(ret); 1733 1734 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size, 1735 "Invalid payload len in NVM response from FW %d", 1736 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1737 ret = -EINVAL; 1738 goto out; 1739 } 1740 1741 rsp = (void *)hcmd.resp_pkt->data; 1742 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1743 NVM_GENERAL_FLAGS_EMPTY_OTP); 1744 if (empty_otp) 1745 IWL_INFO(trans, "OTP is empty\n"); 1746 1747 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL); 1748 if (!nvm) { 1749 ret = -ENOMEM; 1750 goto out; 1751 } 1752 1753 iwl_set_hw_address_from_csr(trans, nvm); 1754 /* TODO: if platform NVM has MAC address - override it here */ 1755 1756 if (!is_valid_ether_addr(nvm->hw_addr)) { 1757 IWL_ERR(trans, "no valid mac address was found\n"); 1758 ret = -EINVAL; 1759 goto err_free; 1760 } 1761 1762 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1763 1764 /* Initialize general data */ 1765 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1766 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1767 if (nvm->n_hw_addrs == 0) 1768 IWL_WARN(trans, 1769 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1770 empty_otp); 1771 1772 /* Initialize MAC sku data */ 1773 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1774 nvm->sku_cap_11ac_enable = 1775 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1776 nvm->sku_cap_11n_enable = 1777 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1778 nvm->sku_cap_11ax_enable = 1779 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1780 nvm->sku_cap_band_24ghz_enable = 1781 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1782 nvm->sku_cap_band_52ghz_enable = 1783 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1784 nvm->sku_cap_mimo_disabled = 1785 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1786 1787 /* Initialize PHY sku data */ 1788 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1789 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1790 1791 if (le32_to_cpu(rsp->regulatory.lar_enabled) && 1792 fw_has_capa(&fw->ucode_capa, 1793 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) { 1794 nvm->lar_enabled = true; 1795 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1796 } 1797 1798 rsp_v3 = (void *)rsp; 1799 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile : 1800 (void *)rsp_v3->regulatory.channel_profile; 1801 1802 iwl_init_sbands(trans, nvm, 1803 channel_profile, 1804 nvm->valid_tx_ant & fw->valid_tx_ant, 1805 nvm->valid_rx_ant & fw->valid_rx_ant, 1806 sbands_flags, v4, fw); 1807 1808 iwl_free_resp(&hcmd); 1809 return nvm; 1810 1811 err_free: 1812 kfree(nvm); 1813 out: 1814 iwl_free_resp(&hcmd); 1815 return ERR_PTR(ret); 1816 } 1817 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1818