1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 *****************************************************************************/ 63 #include <linux/types.h> 64 #include <linux/slab.h> 65 #include <linux/export.h> 66 #include <linux/etherdevice.h> 67 #include <linux/pci.h> 68 #include <linux/firmware.h> 69 70 #include "iwl-drv.h" 71 #include "iwl-modparams.h" 72 #include "iwl-nvm-parse.h" 73 #include "iwl-prph.h" 74 #include "iwl-io.h" 75 #include "iwl-csr.h" 76 #include "fw/acpi.h" 77 #include "fw/api/nvm-reg.h" 78 #include "fw/api/commands.h" 79 #include "fw/api/cmdhdr.h" 80 #include "fw/img.h" 81 82 /* NVM offsets (in words) definitions */ 83 enum nvm_offsets { 84 /* NVM HW-Section offset (in words) definitions */ 85 SUBSYSTEM_ID = 0x0A, 86 HW_ADDR = 0x15, 87 88 /* NVM SW-Section offset (in words) definitions */ 89 NVM_SW_SECTION = 0x1C0, 90 NVM_VERSION = 0, 91 RADIO_CFG = 1, 92 SKU = 2, 93 N_HW_ADDRS = 3, 94 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION, 95 96 /* NVM calibration section offset (in words) definitions */ 97 NVM_CALIB_SECTION = 0x2B8, 98 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION, 99 100 /* NVM REGULATORY -Section offset (in words) definitions */ 101 NVM_CHANNELS_SDP = 0, 102 }; 103 104 enum ext_nvm_offsets { 105 /* NVM HW-Section offset (in words) definitions */ 106 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1, 107 108 /* NVM SW-Section offset (in words) definitions */ 109 NVM_VERSION_EXT_NVM = 0, 110 RADIO_CFG_FAMILY_EXT_NVM = 0, 111 SKU_FAMILY_8000 = 2, 112 N_HW_ADDRS_FAMILY_8000 = 3, 113 114 /* NVM REGULATORY -Section offset (in words) definitions */ 115 NVM_CHANNELS_EXTENDED = 0, 116 NVM_LAR_OFFSET_OLD = 0x4C7, 117 NVM_LAR_OFFSET = 0x507, 118 NVM_LAR_ENABLED = 0x7, 119 }; 120 121 /* SKU Capabilities (actual values from NVM definition) */ 122 enum nvm_sku_bits { 123 NVM_SKU_CAP_BAND_24GHZ = BIT(0), 124 NVM_SKU_CAP_BAND_52GHZ = BIT(1), 125 NVM_SKU_CAP_11N_ENABLE = BIT(2), 126 NVM_SKU_CAP_11AC_ENABLE = BIT(3), 127 NVM_SKU_CAP_MIMO_DISABLE = BIT(5), 128 }; 129 130 /* 131 * These are the channel numbers in the order that they are stored in the NVM 132 */ 133 static const u8 iwl_nvm_channels[] = { 134 /* 2.4 GHz */ 135 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 136 /* 5 GHz */ 137 36, 40, 44 , 48, 52, 56, 60, 64, 138 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 139 149, 153, 157, 161, 165 140 }; 141 142 static const u8 iwl_ext_nvm_channels[] = { 143 /* 2.4 GHz */ 144 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 145 /* 5 GHz */ 146 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 147 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148 149, 153, 157, 161, 165, 169, 173, 177, 181 149 }; 150 151 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels) 152 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels) 153 #define NUM_2GHZ_CHANNELS 14 154 #define NUM_2GHZ_CHANNELS_EXT 14 155 #define FIRST_2GHZ_HT_MINUS 5 156 #define LAST_2GHZ_HT_PLUS 9 157 #define LAST_5GHZ_HT 165 158 #define LAST_5GHZ_HT_FAMILY_8000 181 159 #define N_HW_ADDR_MASK 0xF 160 161 /* rate data (static) */ 162 static struct ieee80211_rate iwl_cfg80211_rates[] = { 163 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 164 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 165 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 166 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 167 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 168 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 169 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 170 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 171 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 172 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 173 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 174 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 175 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 176 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 177 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 178 }; 179 #define RATES_24_OFFS 0 180 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 181 #define RATES_52_OFFS 4 182 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 183 184 /** 185 * enum iwl_nvm_channel_flags - channel flags in NVM 186 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo 187 * @NVM_CHANNEL_IBSS: usable as an IBSS channel 188 * @NVM_CHANNEL_ACTIVE: active scanning allowed 189 * @NVM_CHANNEL_RADAR: radar detection required 190 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 191 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 192 * on same channel on 2.4 or same UNII band on 5.2 193 * @NVM_CHANNEL_UNIFORM: uniform spreading required 194 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay 195 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay 196 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay 197 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay 198 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 199 */ 200 enum iwl_nvm_channel_flags { 201 NVM_CHANNEL_VALID = BIT(0), 202 NVM_CHANNEL_IBSS = BIT(1), 203 NVM_CHANNEL_ACTIVE = BIT(3), 204 NVM_CHANNEL_RADAR = BIT(4), 205 NVM_CHANNEL_INDOOR_ONLY = BIT(5), 206 NVM_CHANNEL_GO_CONCURRENT = BIT(6), 207 NVM_CHANNEL_UNIFORM = BIT(7), 208 NVM_CHANNEL_20MHZ = BIT(8), 209 NVM_CHANNEL_40MHZ = BIT(9), 210 NVM_CHANNEL_80MHZ = BIT(10), 211 NVM_CHANNEL_160MHZ = BIT(11), 212 NVM_CHANNEL_DC_HIGH = BIT(12), 213 }; 214 215 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level, 216 int chan, u16 flags) 217 { 218 #define CHECK_AND_PRINT_I(x) \ 219 ((flags & NVM_CHANNEL_##x) ? " " #x : "") 220 221 if (!(flags & NVM_CHANNEL_VALID)) { 222 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n", 223 chan, flags); 224 return; 225 } 226 227 /* Note: already can print up to 101 characters, 110 is the limit! */ 228 IWL_DEBUG_DEV(dev, level, 229 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n", 230 chan, flags, 231 CHECK_AND_PRINT_I(VALID), 232 CHECK_AND_PRINT_I(IBSS), 233 CHECK_AND_PRINT_I(ACTIVE), 234 CHECK_AND_PRINT_I(RADAR), 235 CHECK_AND_PRINT_I(INDOOR_ONLY), 236 CHECK_AND_PRINT_I(GO_CONCURRENT), 237 CHECK_AND_PRINT_I(UNIFORM), 238 CHECK_AND_PRINT_I(20MHZ), 239 CHECK_AND_PRINT_I(40MHZ), 240 CHECK_AND_PRINT_I(80MHZ), 241 CHECK_AND_PRINT_I(160MHZ), 242 CHECK_AND_PRINT_I(DC_HIGH)); 243 #undef CHECK_AND_PRINT_I 244 } 245 246 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz, 247 u16 nvm_flags, const struct iwl_cfg *cfg) 248 { 249 u32 flags = IEEE80211_CHAN_NO_HT40; 250 u32 last_5ghz_ht = LAST_5GHZ_HT; 251 252 if (cfg->nvm_type == IWL_NVM_EXT) 253 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000; 254 255 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) { 256 if (ch_num <= LAST_2GHZ_HT_PLUS) 257 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 258 if (ch_num >= FIRST_2GHZ_HT_MINUS) 259 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 260 } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) { 261 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 262 flags &= ~IEEE80211_CHAN_NO_HT40PLUS; 263 else 264 flags &= ~IEEE80211_CHAN_NO_HT40MINUS; 265 } 266 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 267 flags |= IEEE80211_CHAN_NO_80MHZ; 268 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 269 flags |= IEEE80211_CHAN_NO_160MHZ; 270 271 if (!(nvm_flags & NVM_CHANNEL_IBSS)) 272 flags |= IEEE80211_CHAN_NO_IR; 273 274 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 275 flags |= IEEE80211_CHAN_NO_IR; 276 277 if (nvm_flags & NVM_CHANNEL_RADAR) 278 flags |= IEEE80211_CHAN_RADAR; 279 280 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 281 flags |= IEEE80211_CHAN_INDOOR_ONLY; 282 283 /* Set the GO concurrent flag only in case that NO_IR is set. 284 * Otherwise it is meaningless 285 */ 286 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 287 (flags & IEEE80211_CHAN_NO_IR)) 288 flags |= IEEE80211_CHAN_IR_CONCURRENT; 289 290 return flags; 291 } 292 293 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 294 struct iwl_nvm_data *data, 295 const __le16 * const nvm_ch_flags, 296 u32 sbands_flags) 297 { 298 int ch_idx; 299 int n_channels = 0; 300 struct ieee80211_channel *channel; 301 u16 ch_flags; 302 int num_of_ch, num_2ghz_channels; 303 const u8 *nvm_chan; 304 305 if (cfg->nvm_type != IWL_NVM_EXT) { 306 num_of_ch = IWL_NVM_NUM_CHANNELS; 307 nvm_chan = &iwl_nvm_channels[0]; 308 num_2ghz_channels = NUM_2GHZ_CHANNELS; 309 } else { 310 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT; 311 nvm_chan = &iwl_ext_nvm_channels[0]; 312 num_2ghz_channels = NUM_2GHZ_CHANNELS_EXT; 313 } 314 315 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 316 bool is_5ghz = (ch_idx >= num_2ghz_channels); 317 318 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx); 319 320 if (is_5ghz && !data->sku_cap_band_52ghz_enable) 321 continue; 322 323 /* workaround to disable wide channels in 5GHz */ 324 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) && 325 is_5ghz) { 326 ch_flags &= ~(NVM_CHANNEL_40MHZ | 327 NVM_CHANNEL_80MHZ | 328 NVM_CHANNEL_160MHZ); 329 } 330 331 if (ch_flags & NVM_CHANNEL_160MHZ) 332 data->vht160_supported = true; 333 334 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) && 335 !(ch_flags & NVM_CHANNEL_VALID)) { 336 /* 337 * Channels might become valid later if lar is 338 * supported, hence we still want to add them to 339 * the list of supported channels to cfg80211. 340 */ 341 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 342 nvm_chan[ch_idx], ch_flags); 343 continue; 344 } 345 346 channel = &data->channels[n_channels]; 347 n_channels++; 348 349 channel->hw_value = nvm_chan[ch_idx]; 350 channel->band = is_5ghz ? 351 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ; 352 channel->center_freq = 353 ieee80211_channel_to_frequency( 354 channel->hw_value, channel->band); 355 356 /* Initialize regulatory-based run-time data */ 357 358 /* 359 * Default value - highest tx power value. max_power 360 * is not used in mvm, and is used for backwards compatibility 361 */ 362 channel->max_power = IWL_DEFAULT_MAX_TX_POWER; 363 364 /* don't put limitations in case we're using LAR */ 365 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR)) 366 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx], 367 ch_idx, is_5ghz, 368 ch_flags, cfg); 369 else 370 channel->flags = 0; 371 372 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM, 373 channel->hw_value, ch_flags); 374 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n", 375 channel->hw_value, channel->max_power); 376 } 377 378 return n_channels; 379 } 380 381 static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg, 382 struct iwl_nvm_data *data, 383 struct ieee80211_sta_vht_cap *vht_cap, 384 u8 tx_chains, u8 rx_chains) 385 { 386 int num_rx_ants = num_of_ant(rx_chains); 387 int num_tx_ants = num_of_ant(tx_chains); 388 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?: 389 IEEE80211_VHT_MAX_AMPDU_1024K); 390 391 vht_cap->vht_supported = true; 392 393 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 | 394 IEEE80211_VHT_CAP_RXSTBC_1 | 395 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 396 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT | 397 max_ampdu_exponent << 398 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT; 399 400 if (data->vht160_supported) 401 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 402 IEEE80211_VHT_CAP_SHORT_GI_160; 403 404 if (cfg->vht_mu_mimo_supported) 405 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 406 407 if (cfg->ht_params->ldpc) 408 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 409 410 if (data->sku_cap_mimo_disabled) { 411 num_rx_ants = 1; 412 num_tx_ants = 1; 413 } 414 415 if (num_tx_ants > 1) 416 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 417 else 418 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN; 419 420 switch (iwlwifi_mod_params.amsdu_size) { 421 case IWL_AMSDU_DEF: 422 if (cfg->mq_rx_supported) 423 vht_cap->cap |= 424 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 425 else 426 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 427 break; 428 case IWL_AMSDU_2K: 429 if (cfg->mq_rx_supported) 430 vht_cap->cap |= 431 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 432 else 433 WARN(1, "RB size of 2K is not supported by this device\n"); 434 break; 435 case IWL_AMSDU_4K: 436 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895; 437 break; 438 case IWL_AMSDU_8K: 439 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991; 440 break; 441 case IWL_AMSDU_12K: 442 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454; 443 break; 444 default: 445 break; 446 } 447 448 vht_cap->vht_mcs.rx_mcs_map = 449 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 450 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 | 451 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 452 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 453 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 454 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 455 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 456 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14); 457 458 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) { 459 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN; 460 /* this works because NOT_SUPPORTED == 3 */ 461 vht_cap->vht_mcs.rx_mcs_map |= 462 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2); 463 } 464 465 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map; 466 } 467 468 static struct ieee80211_sband_iftype_data iwl_he_capa[] = { 469 { 470 .types_mask = BIT(NL80211_IFTYPE_STATION), 471 .he_cap = { 472 .has_he = true, 473 .he_cap_elem = { 474 .mac_cap_info[0] = 475 IEEE80211_HE_MAC_CAP0_HTC_HE | 476 IEEE80211_HE_MAC_CAP0_TWT_REQ, 477 .mac_cap_info[1] = 478 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 479 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 480 .mac_cap_info[2] = 481 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP | 482 IEEE80211_HE_MAC_CAP2_MU_CASCADING | 483 IEEE80211_HE_MAC_CAP2_ACK_EN, 484 .mac_cap_info[3] = 485 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 486 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2, 487 .mac_cap_info[4] = 488 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU | 489 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39, 490 .mac_cap_info[5] = 491 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 | 492 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 | 493 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU, 494 .phy_cap_info[0] = 495 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 496 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 497 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 498 .phy_cap_info[1] = 499 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK | 500 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 501 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 502 IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS, 503 .phy_cap_info[2] = 504 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 505 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 506 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 507 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 508 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO, 509 .phy_cap_info[3] = 510 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 511 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 512 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 513 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 514 .phy_cap_info[4] = 515 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 516 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 517 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 518 .phy_cap_info[5] = 519 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 520 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2 | 521 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 522 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK, 523 .phy_cap_info[6] = 524 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 525 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 526 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB | 527 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB | 528 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 529 IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO | 530 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 531 .phy_cap_info[7] = 532 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR | 533 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 534 IEEE80211_HE_PHY_CAP7_MAX_NC_1, 535 .phy_cap_info[8] = 536 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 537 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 538 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 539 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 540 IEEE80211_HE_PHY_CAP8_DCM_MAX_BW_160_OR_80P80_MHZ, 541 .phy_cap_info[9] = 542 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 543 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 544 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB, 545 }, 546 /* 547 * Set default Tx/Rx HE MCS NSS Support field. 548 * Indicate support for up to 2 spatial streams and all 549 * MCS, without any special cases 550 */ 551 .he_mcs_nss_supp = { 552 .rx_mcs_80 = cpu_to_le16(0xfffa), 553 .tx_mcs_80 = cpu_to_le16(0xfffa), 554 .rx_mcs_160 = cpu_to_le16(0xfffa), 555 .tx_mcs_160 = cpu_to_le16(0xfffa), 556 .rx_mcs_80p80 = cpu_to_le16(0xffff), 557 .tx_mcs_80p80 = cpu_to_le16(0xffff), 558 }, 559 /* 560 * Set default PPE thresholds, with PPET16 set to 0, 561 * PPET8 set to 7 562 */ 563 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 564 }, 565 }, 566 { 567 .types_mask = BIT(NL80211_IFTYPE_AP), 568 .he_cap = { 569 .has_he = true, 570 .he_cap_elem = { 571 .mac_cap_info[0] = 572 IEEE80211_HE_MAC_CAP0_HTC_HE, 573 .mac_cap_info[1] = 574 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US | 575 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8, 576 .mac_cap_info[2] = 577 IEEE80211_HE_MAC_CAP2_BSR | 578 IEEE80211_HE_MAC_CAP2_MU_CASCADING | 579 IEEE80211_HE_MAC_CAP2_ACK_EN, 580 .mac_cap_info[3] = 581 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 582 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2, 583 .mac_cap_info[4] = 584 IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU, 585 .phy_cap_info[0] = 586 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | 587 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 588 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G, 589 .phy_cap_info[1] = 590 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 591 IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS, 592 .phy_cap_info[2] = 593 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 594 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 595 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ, 596 .phy_cap_info[3] = 597 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK | 598 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 | 599 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK | 600 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1, 601 .phy_cap_info[4] = 602 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 603 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 | 604 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8, 605 .phy_cap_info[5] = 606 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 | 607 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2 | 608 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 609 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK, 610 .phy_cap_info[6] = 611 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 612 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 613 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, 614 .phy_cap_info[7] = 615 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 616 IEEE80211_HE_PHY_CAP7_MAX_NC_1, 617 .phy_cap_info[8] = 618 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 619 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 620 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 621 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 622 IEEE80211_HE_PHY_CAP8_DCM_MAX_BW_160_OR_80P80_MHZ, 623 .phy_cap_info[9] = 624 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 625 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB, 626 }, 627 /* 628 * Set default Tx/Rx HE MCS NSS Support field. 629 * Indicate support for up to 2 spatial streams and all 630 * MCS, without any special cases 631 */ 632 .he_mcs_nss_supp = { 633 .rx_mcs_80 = cpu_to_le16(0xfffa), 634 .tx_mcs_80 = cpu_to_le16(0xfffa), 635 .rx_mcs_160 = cpu_to_le16(0xfffa), 636 .tx_mcs_160 = cpu_to_le16(0xfffa), 637 .rx_mcs_80p80 = cpu_to_le16(0xffff), 638 .tx_mcs_80p80 = cpu_to_le16(0xffff), 639 }, 640 /* 641 * Set default PPE thresholds, with PPET16 set to 0, 642 * PPET8 set to 7 643 */ 644 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71}, 645 }, 646 }, 647 }; 648 649 static void iwl_init_he_hw_capab(struct ieee80211_supported_band *sband, 650 u8 tx_chains, u8 rx_chains) 651 { 652 if (sband->band == NL80211_BAND_2GHZ || 653 sband->band == NL80211_BAND_5GHZ) 654 sband->iftype_data = iwl_he_capa; 655 else 656 return; 657 658 sband->n_iftype_data = ARRAY_SIZE(iwl_he_capa); 659 660 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */ 661 if ((tx_chains & rx_chains) != ANT_AB) { 662 int i; 663 664 for (i = 0; i < sband->n_iftype_data; i++) { 665 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[1] &= 666 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS; 667 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[2] &= 668 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS; 669 iwl_he_capa[i].he_cap.he_cap_elem.phy_cap_info[7] &= 670 ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 671 } 672 } 673 } 674 675 static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg, 676 struct iwl_nvm_data *data, 677 const __le16 *nvm_ch_flags, u8 tx_chains, 678 u8 rx_chains, u32 sbands_flags) 679 { 680 int n_channels; 681 int n_used = 0; 682 struct ieee80211_supported_band *sband; 683 684 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags, 685 sbands_flags); 686 sband = &data->bands[NL80211_BAND_2GHZ]; 687 sband->band = NL80211_BAND_2GHZ; 688 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 689 sband->n_bitrates = N_RATES_24; 690 n_used += iwl_init_sband_channels(data, sband, n_channels, 691 NL80211_BAND_2GHZ); 692 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ, 693 tx_chains, rx_chains); 694 695 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 696 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 697 698 sband = &data->bands[NL80211_BAND_5GHZ]; 699 sband->band = NL80211_BAND_5GHZ; 700 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 701 sband->n_bitrates = N_RATES_52; 702 n_used += iwl_init_sband_channels(data, sband, n_channels, 703 NL80211_BAND_5GHZ); 704 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ, 705 tx_chains, rx_chains); 706 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac) 707 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap, 708 tx_chains, rx_chains); 709 710 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax) 711 iwl_init_he_hw_capab(sband, tx_chains, rx_chains); 712 713 if (n_channels != n_used) 714 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n", 715 n_used, n_channels); 716 } 717 718 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 719 const __le16 *phy_sku) 720 { 721 if (cfg->nvm_type != IWL_NVM_EXT) 722 return le16_to_cpup(nvm_sw + SKU); 723 724 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000)); 725 } 726 727 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 728 { 729 if (cfg->nvm_type != IWL_NVM_EXT) 730 return le16_to_cpup(nvm_sw + NVM_VERSION); 731 else 732 return le32_to_cpup((__le32 *)(nvm_sw + 733 NVM_VERSION_EXT_NVM)); 734 } 735 736 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw, 737 const __le16 *phy_sku) 738 { 739 if (cfg->nvm_type != IWL_NVM_EXT) 740 return le16_to_cpup(nvm_sw + RADIO_CFG); 741 742 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM)); 743 744 } 745 746 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw) 747 { 748 int n_hw_addr; 749 750 if (cfg->nvm_type != IWL_NVM_EXT) 751 return le16_to_cpup(nvm_sw + N_HW_ADDRS); 752 753 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000)); 754 755 return n_hw_addr & N_HW_ADDR_MASK; 756 } 757 758 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg, 759 struct iwl_nvm_data *data, 760 u32 radio_cfg) 761 { 762 if (cfg->nvm_type != IWL_NVM_EXT) { 763 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg); 764 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg); 765 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg); 766 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg); 767 return; 768 } 769 770 /* set the radio configuration for family 8000 */ 771 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg); 772 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg); 773 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg); 774 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg); 775 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg); 776 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg); 777 } 778 779 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest) 780 { 781 const u8 *hw_addr; 782 783 hw_addr = (const u8 *)&mac_addr0; 784 dest[0] = hw_addr[3]; 785 dest[1] = hw_addr[2]; 786 dest[2] = hw_addr[1]; 787 dest[3] = hw_addr[0]; 788 789 hw_addr = (const u8 *)&mac_addr1; 790 dest[4] = hw_addr[1]; 791 dest[5] = hw_addr[0]; 792 } 793 794 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans, 795 struct iwl_nvm_data *data) 796 { 797 __le32 mac_addr0 = 798 cpu_to_le32(iwl_read32(trans, 799 trans->cfg->csr->mac_addr0_strap)); 800 __le32 mac_addr1 = 801 cpu_to_le32(iwl_read32(trans, 802 trans->cfg->csr->mac_addr1_strap)); 803 804 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 805 /* 806 * If the OEM fused a valid address, use it instead of the one in the 807 * OTP 808 */ 809 if (is_valid_ether_addr(data->hw_addr)) 810 return; 811 812 mac_addr0 = cpu_to_le32(iwl_read32(trans, 813 trans->cfg->csr->mac_addr0_otp)); 814 mac_addr1 = cpu_to_le32(iwl_read32(trans, 815 trans->cfg->csr->mac_addr1_otp)); 816 817 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 818 } 819 820 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans, 821 const struct iwl_cfg *cfg, 822 struct iwl_nvm_data *data, 823 const __le16 *mac_override, 824 const __be16 *nvm_hw) 825 { 826 const u8 *hw_addr; 827 828 if (mac_override) { 829 static const u8 reserved_mac[] = { 830 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 831 }; 832 833 hw_addr = (const u8 *)(mac_override + 834 MAC_ADDRESS_OVERRIDE_EXT_NVM); 835 836 /* 837 * Store the MAC address from MAO section. 838 * No byte swapping is required in MAO section 839 */ 840 memcpy(data->hw_addr, hw_addr, ETH_ALEN); 841 842 /* 843 * Force the use of the OTP MAC address in case of reserved MAC 844 * address in the NVM, or if address is given but invalid. 845 */ 846 if (is_valid_ether_addr(data->hw_addr) && 847 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0) 848 return; 849 850 IWL_ERR(trans, 851 "mac address from nvm override section is not valid\n"); 852 } 853 854 if (nvm_hw) { 855 /* read the mac address from WFMP registers */ 856 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans, 857 WFMP_MAC_ADDR_0)); 858 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans, 859 WFMP_MAC_ADDR_1)); 860 861 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr); 862 863 return; 864 } 865 866 IWL_ERR(trans, "mac address is not found\n"); 867 } 868 869 static int iwl_set_hw_address(struct iwl_trans *trans, 870 const struct iwl_cfg *cfg, 871 struct iwl_nvm_data *data, const __be16 *nvm_hw, 872 const __le16 *mac_override) 873 { 874 if (cfg->mac_addr_from_csr) { 875 iwl_set_hw_address_from_csr(trans, data); 876 } else if (cfg->nvm_type != IWL_NVM_EXT) { 877 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR); 878 879 /* The byte order is little endian 16 bit, meaning 214365 */ 880 data->hw_addr[0] = hw_addr[1]; 881 data->hw_addr[1] = hw_addr[0]; 882 data->hw_addr[2] = hw_addr[3]; 883 data->hw_addr[3] = hw_addr[2]; 884 data->hw_addr[4] = hw_addr[5]; 885 data->hw_addr[5] = hw_addr[4]; 886 } else { 887 iwl_set_hw_address_family_8000(trans, cfg, data, 888 mac_override, nvm_hw); 889 } 890 891 if (!is_valid_ether_addr(data->hw_addr)) { 892 IWL_ERR(trans, "no valid mac address was found\n"); 893 return -EINVAL; 894 } 895 896 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr); 897 898 return 0; 899 } 900 901 static bool 902 iwl_nvm_no_wide_in_5ghz(struct device *dev, const struct iwl_cfg *cfg, 903 const __be16 *nvm_hw) 904 { 905 /* 906 * Workaround a bug in Indonesia SKUs where the regulatory in 907 * some 7000-family OTPs erroneously allow wide channels in 908 * 5GHz. To check for Indonesia, we take the SKU value from 909 * bits 1-4 in the subsystem ID and check if it is either 5 or 910 * 9. In those cases, we need to force-disable wide channels 911 * in 5GHz otherwise the FW will throw a sysassert when we try 912 * to use them. 913 */ 914 if (cfg->device_family == IWL_DEVICE_FAMILY_7000) { 915 /* 916 * Unlike the other sections in the NVM, the hw 917 * section uses big-endian. 918 */ 919 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID); 920 u8 sku = (subsystem_id & 0x1e) >> 1; 921 922 if (sku == 5 || sku == 9) { 923 IWL_DEBUG_EEPROM(dev, 924 "disabling wide channels in 5GHz (0x%0x %d)\n", 925 subsystem_id, sku); 926 return true; 927 } 928 } 929 930 return false; 931 } 932 933 struct iwl_nvm_data * 934 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 935 const __be16 *nvm_hw, const __le16 *nvm_sw, 936 const __le16 *nvm_calib, const __le16 *regulatory, 937 const __le16 *mac_override, const __le16 *phy_sku, 938 u8 tx_chains, u8 rx_chains, bool lar_fw_supported) 939 { 940 struct device *dev = trans->dev; 941 struct iwl_nvm_data *data; 942 bool lar_enabled; 943 u32 sku, radio_cfg; 944 u32 sbands_flags = 0; 945 u16 lar_config; 946 const __le16 *ch_section; 947 948 if (cfg->nvm_type != IWL_NVM_EXT) 949 data = kzalloc(sizeof(*data) + 950 sizeof(struct ieee80211_channel) * 951 IWL_NVM_NUM_CHANNELS, 952 GFP_KERNEL); 953 else 954 data = kzalloc(sizeof(*data) + 955 sizeof(struct ieee80211_channel) * 956 IWL_NVM_NUM_CHANNELS_EXT, 957 GFP_KERNEL); 958 if (!data) 959 return NULL; 960 961 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw); 962 963 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku); 964 iwl_set_radio_cfg(cfg, data, radio_cfg); 965 if (data->valid_tx_ant) 966 tx_chains &= data->valid_tx_ant; 967 if (data->valid_rx_ant) 968 rx_chains &= data->valid_rx_ant; 969 970 sku = iwl_get_sku(cfg, nvm_sw, phy_sku); 971 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ; 972 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ; 973 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE; 974 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 975 data->sku_cap_11n_enable = false; 976 data->sku_cap_11ac_enable = data->sku_cap_11n_enable && 977 (sku & NVM_SKU_CAP_11AC_ENABLE); 978 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE; 979 980 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw); 981 982 if (cfg->nvm_type != IWL_NVM_EXT) { 983 /* Checking for required sections */ 984 if (!nvm_calib) { 985 IWL_ERR(trans, 986 "Can't parse empty Calib NVM sections\n"); 987 kfree(data); 988 return NULL; 989 } 990 991 ch_section = cfg->nvm_type == IWL_NVM_SDP ? 992 ®ulatory[NVM_CHANNELS_SDP] : 993 &nvm_sw[NVM_CHANNELS]; 994 995 /* in family 8000 Xtal calibration values moved to OTP */ 996 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB); 997 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1); 998 lar_enabled = true; 999 } else { 1000 u16 lar_offset = data->nvm_version < 0xE39 ? 1001 NVM_LAR_OFFSET_OLD : 1002 NVM_LAR_OFFSET; 1003 1004 lar_config = le16_to_cpup(regulatory + lar_offset); 1005 data->lar_enabled = !!(lar_config & 1006 NVM_LAR_ENABLED); 1007 lar_enabled = data->lar_enabled; 1008 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED]; 1009 } 1010 1011 /* If no valid mac address was found - bail out */ 1012 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) { 1013 kfree(data); 1014 return NULL; 1015 } 1016 1017 if (lar_fw_supported && lar_enabled) 1018 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1019 1020 if (iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw)) 1021 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ; 1022 1023 iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains, 1024 sbands_flags); 1025 data->calib_version = 255; 1026 1027 return data; 1028 } 1029 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data); 1030 1031 static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan, 1032 int ch_idx, u16 nvm_flags, 1033 const struct iwl_cfg *cfg) 1034 { 1035 u32 flags = NL80211_RRF_NO_HT40; 1036 u32 last_5ghz_ht = LAST_5GHZ_HT; 1037 1038 if (cfg->nvm_type == IWL_NVM_EXT) 1039 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000; 1040 1041 if (ch_idx < NUM_2GHZ_CHANNELS && 1042 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1043 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS) 1044 flags &= ~NL80211_RRF_NO_HT40PLUS; 1045 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS) 1046 flags &= ~NL80211_RRF_NO_HT40MINUS; 1047 } else if (nvm_chan[ch_idx] <= last_5ghz_ht && 1048 (nvm_flags & NVM_CHANNEL_40MHZ)) { 1049 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0) 1050 flags &= ~NL80211_RRF_NO_HT40PLUS; 1051 else 1052 flags &= ~NL80211_RRF_NO_HT40MINUS; 1053 } 1054 1055 if (!(nvm_flags & NVM_CHANNEL_80MHZ)) 1056 flags |= NL80211_RRF_NO_80MHZ; 1057 if (!(nvm_flags & NVM_CHANNEL_160MHZ)) 1058 flags |= NL80211_RRF_NO_160MHZ; 1059 1060 if (!(nvm_flags & NVM_CHANNEL_ACTIVE)) 1061 flags |= NL80211_RRF_NO_IR; 1062 1063 if (nvm_flags & NVM_CHANNEL_RADAR) 1064 flags |= NL80211_RRF_DFS; 1065 1066 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY) 1067 flags |= NL80211_RRF_NO_OUTDOOR; 1068 1069 /* Set the GO concurrent flag only in case that NO_IR is set. 1070 * Otherwise it is meaningless 1071 */ 1072 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) && 1073 (flags & NL80211_RRF_NO_IR)) 1074 flags |= NL80211_RRF_GO_CONCURRENT; 1075 1076 return flags; 1077 } 1078 1079 struct regdb_ptrs { 1080 struct ieee80211_wmm_rule *rule; 1081 u32 token; 1082 }; 1083 1084 struct ieee80211_regdomain * 1085 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg, 1086 int num_of_ch, __le32 *channels, u16 fw_mcc, 1087 u16 geo_info) 1088 { 1089 int ch_idx; 1090 u16 ch_flags; 1091 u32 reg_rule_flags, prev_reg_rule_flags = 0; 1092 const u8 *nvm_chan = cfg->nvm_type == IWL_NVM_EXT ? 1093 iwl_ext_nvm_channels : iwl_nvm_channels; 1094 struct ieee80211_regdomain *regd, *copy_rd; 1095 int size_of_regd, regd_to_copy; 1096 struct ieee80211_reg_rule *rule; 1097 struct regdb_ptrs *regdb_ptrs; 1098 enum nl80211_band band; 1099 int center_freq, prev_center_freq = 0; 1100 int valid_rules = 0; 1101 bool new_rule; 1102 int max_num_ch = cfg->nvm_type == IWL_NVM_EXT ? 1103 IWL_NVM_NUM_CHANNELS_EXT : IWL_NVM_NUM_CHANNELS; 1104 1105 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES)) 1106 return ERR_PTR(-EINVAL); 1107 1108 if (WARN_ON(num_of_ch > max_num_ch)) 1109 num_of_ch = max_num_ch; 1110 1111 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n", 1112 num_of_ch); 1113 1114 /* build a regdomain rule for every valid channel */ 1115 size_of_regd = 1116 sizeof(struct ieee80211_regdomain) + 1117 num_of_ch * sizeof(struct ieee80211_reg_rule); 1118 1119 regd = kzalloc(size_of_regd, GFP_KERNEL); 1120 if (!regd) 1121 return ERR_PTR(-ENOMEM); 1122 1123 regdb_ptrs = kcalloc(num_of_ch, sizeof(*regdb_ptrs), GFP_KERNEL); 1124 if (!regdb_ptrs) { 1125 copy_rd = ERR_PTR(-ENOMEM); 1126 goto out; 1127 } 1128 1129 /* set alpha2 from FW. */ 1130 regd->alpha2[0] = fw_mcc >> 8; 1131 regd->alpha2[1] = fw_mcc & 0xff; 1132 1133 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) { 1134 ch_flags = (u16)__le32_to_cpup(channels + ch_idx); 1135 band = (ch_idx < NUM_2GHZ_CHANNELS) ? 1136 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1137 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx], 1138 band); 1139 new_rule = false; 1140 1141 if (!(ch_flags & NVM_CHANNEL_VALID)) { 1142 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1143 nvm_chan[ch_idx], ch_flags); 1144 continue; 1145 } 1146 1147 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx, 1148 ch_flags, cfg); 1149 1150 /* we can't continue the same rule */ 1151 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags || 1152 center_freq - prev_center_freq > 20) { 1153 valid_rules++; 1154 new_rule = true; 1155 } 1156 1157 rule = ®d->reg_rules[valid_rules - 1]; 1158 1159 if (new_rule) 1160 rule->freq_range.start_freq_khz = 1161 MHZ_TO_KHZ(center_freq - 10); 1162 1163 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10); 1164 1165 /* this doesn't matter - not used by FW */ 1166 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6); 1167 rule->power_rule.max_eirp = 1168 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER); 1169 1170 rule->flags = reg_rule_flags; 1171 1172 /* rely on auto-calculation to merge BW of contiguous chans */ 1173 rule->flags |= NL80211_RRF_AUTO_BW; 1174 rule->freq_range.max_bandwidth_khz = 0; 1175 1176 prev_center_freq = center_freq; 1177 prev_reg_rule_flags = reg_rule_flags; 1178 1179 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR, 1180 nvm_chan[ch_idx], ch_flags); 1181 1182 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) || 1183 band == NL80211_BAND_2GHZ) 1184 continue; 1185 1186 reg_query_regdb_wmm(regd->alpha2, center_freq, rule); 1187 } 1188 1189 regd->n_reg_rules = valid_rules; 1190 1191 /* 1192 * Narrow down regdom for unused regulatory rules to prevent hole 1193 * between reg rules to wmm rules. 1194 */ 1195 regd_to_copy = sizeof(struct ieee80211_regdomain) + 1196 valid_rules * sizeof(struct ieee80211_reg_rule); 1197 1198 copy_rd = kmemdup(regd, regd_to_copy, GFP_KERNEL); 1199 if (!copy_rd) { 1200 copy_rd = ERR_PTR(-ENOMEM); 1201 goto out; 1202 } 1203 1204 out: 1205 kfree(regdb_ptrs); 1206 kfree(regd); 1207 return copy_rd; 1208 } 1209 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info); 1210 1211 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58 1212 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc 1213 #define MAX_NVM_FILE_LEN 16384 1214 1215 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data, 1216 unsigned int len) 1217 { 1218 #define IWL_4165_DEVICE_ID 0x5501 1219 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5) 1220 1221 if (section == NVM_SECTION_TYPE_PHY_SKU && 1222 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 && 1223 (data[4] & NVM_SKU_CAP_MIMO_DISABLE)) 1224 /* OTP 0x52 bug work around: it's a 1x1 device */ 1225 data[3] = ANT_B | (ANT_B << 4); 1226 } 1227 IWL_EXPORT_SYMBOL(iwl_nvm_fixups); 1228 1229 /* 1230 * Reads external NVM from a file into mvm->nvm_sections 1231 * 1232 * HOW TO CREATE THE NVM FILE FORMAT: 1233 * ------------------------------ 1234 * 1. create hex file, format: 1235 * 3800 -> header 1236 * 0000 -> header 1237 * 5a40 -> data 1238 * 1239 * rev - 6 bit (word1) 1240 * len - 10 bit (word1) 1241 * id - 4 bit (word2) 1242 * rsv - 12 bit (word2) 1243 * 1244 * 2. flip 8bits with 8 bits per line to get the right NVM file format 1245 * 1246 * 3. create binary file from the hex file 1247 * 1248 * 4. save as "iNVM_xxx.bin" under /lib/firmware 1249 */ 1250 int iwl_read_external_nvm(struct iwl_trans *trans, 1251 const char *nvm_file_name, 1252 struct iwl_nvm_section *nvm_sections) 1253 { 1254 int ret, section_size; 1255 u16 section_id; 1256 const struct firmware *fw_entry; 1257 const struct { 1258 __le16 word1; 1259 __le16 word2; 1260 u8 data[]; 1261 } *file_sec; 1262 const u8 *eof; 1263 u8 *temp; 1264 int max_section_size; 1265 const __le32 *dword_buff; 1266 1267 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF)) 1268 #define NVM_WORD2_ID(x) (x >> 12) 1269 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8)) 1270 #define EXT_NVM_WORD1_ID(x) ((x) >> 4) 1271 #define NVM_HEADER_0 (0x2A504C54) 1272 #define NVM_HEADER_1 (0x4E564D2A) 1273 #define NVM_HEADER_SIZE (4 * sizeof(u32)) 1274 1275 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n"); 1276 1277 /* Maximal size depends on NVM version */ 1278 if (trans->cfg->nvm_type != IWL_NVM_EXT) 1279 max_section_size = IWL_MAX_NVM_SECTION_SIZE; 1280 else 1281 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE; 1282 1283 /* 1284 * Obtain NVM image via request_firmware. Since we already used 1285 * request_firmware_nowait() for the firmware binary load and only 1286 * get here after that we assume the NVM request can be satisfied 1287 * synchronously. 1288 */ 1289 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev); 1290 if (ret) { 1291 IWL_ERR(trans, "ERROR: %s isn't available %d\n", 1292 nvm_file_name, ret); 1293 return ret; 1294 } 1295 1296 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n", 1297 nvm_file_name, fw_entry->size); 1298 1299 if (fw_entry->size > MAX_NVM_FILE_LEN) { 1300 IWL_ERR(trans, "NVM file too large\n"); 1301 ret = -EINVAL; 1302 goto out; 1303 } 1304 1305 eof = fw_entry->data + fw_entry->size; 1306 dword_buff = (__le32 *)fw_entry->data; 1307 1308 /* some NVM file will contain a header. 1309 * The header is identified by 2 dwords header as follow: 1310 * dword[0] = 0x2A504C54 1311 * dword[1] = 0x4E564D2A 1312 * 1313 * This header must be skipped when providing the NVM data to the FW. 1314 */ 1315 if (fw_entry->size > NVM_HEADER_SIZE && 1316 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) && 1317 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) { 1318 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE); 1319 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2])); 1320 IWL_INFO(trans, "NVM Manufacturing date %08X\n", 1321 le32_to_cpu(dword_buff[3])); 1322 1323 /* nvm file validation, dword_buff[2] holds the file version */ 1324 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 && 1325 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP && 1326 le32_to_cpu(dword_buff[2]) < 0xE4A) { 1327 ret = -EFAULT; 1328 goto out; 1329 } 1330 } else { 1331 file_sec = (void *)fw_entry->data; 1332 } 1333 1334 while (true) { 1335 if (file_sec->data > eof) { 1336 IWL_ERR(trans, 1337 "ERROR - NVM file too short for section header\n"); 1338 ret = -EINVAL; 1339 break; 1340 } 1341 1342 /* check for EOF marker */ 1343 if (!file_sec->word1 && !file_sec->word2) { 1344 ret = 0; 1345 break; 1346 } 1347 1348 if (trans->cfg->nvm_type != IWL_NVM_EXT) { 1349 section_size = 1350 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1)); 1351 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2)); 1352 } else { 1353 section_size = 2 * EXT_NVM_WORD2_LEN( 1354 le16_to_cpu(file_sec->word2)); 1355 section_id = EXT_NVM_WORD1_ID( 1356 le16_to_cpu(file_sec->word1)); 1357 } 1358 1359 if (section_size > max_section_size) { 1360 IWL_ERR(trans, "ERROR - section too large (%d)\n", 1361 section_size); 1362 ret = -EINVAL; 1363 break; 1364 } 1365 1366 if (!section_size) { 1367 IWL_ERR(trans, "ERROR - section empty\n"); 1368 ret = -EINVAL; 1369 break; 1370 } 1371 1372 if (file_sec->data + section_size > eof) { 1373 IWL_ERR(trans, 1374 "ERROR - NVM file too short for section (%d bytes)\n", 1375 section_size); 1376 ret = -EINVAL; 1377 break; 1378 } 1379 1380 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS, 1381 "Invalid NVM section ID %d\n", section_id)) { 1382 ret = -EINVAL; 1383 break; 1384 } 1385 1386 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL); 1387 if (!temp) { 1388 ret = -ENOMEM; 1389 break; 1390 } 1391 1392 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size); 1393 1394 kfree(nvm_sections[section_id].data); 1395 nvm_sections[section_id].data = temp; 1396 nvm_sections[section_id].length = section_size; 1397 1398 /* advance to the next section */ 1399 file_sec = (void *)(file_sec->data + section_size); 1400 } 1401 out: 1402 release_firmware(fw_entry); 1403 return ret; 1404 } 1405 IWL_EXPORT_SYMBOL(iwl_read_external_nvm); 1406 1407 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans, 1408 const struct iwl_fw *fw) 1409 { 1410 struct iwl_nvm_get_info cmd = {}; 1411 struct iwl_nvm_get_info_rsp *rsp; 1412 struct iwl_nvm_data *nvm; 1413 struct iwl_host_cmd hcmd = { 1414 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL, 1415 .data = { &cmd, }, 1416 .len = { sizeof(cmd) }, 1417 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO) 1418 }; 1419 int ret; 1420 bool lar_fw_supported = !iwlwifi_mod_params.lar_disable && 1421 fw_has_capa(&fw->ucode_capa, 1422 IWL_UCODE_TLV_CAPA_LAR_SUPPORT); 1423 bool empty_otp; 1424 u32 mac_flags; 1425 u32 sbands_flags = 0; 1426 1427 ret = iwl_trans_send_cmd(trans, &hcmd); 1428 if (ret) 1429 return ERR_PTR(ret); 1430 1431 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp), 1432 "Invalid payload len in NVM response from FW %d", 1433 iwl_rx_packet_payload_len(hcmd.resp_pkt))) { 1434 ret = -EINVAL; 1435 goto out; 1436 } 1437 1438 rsp = (void *)hcmd.resp_pkt->data; 1439 empty_otp = !!(le32_to_cpu(rsp->general.flags) & 1440 NVM_GENERAL_FLAGS_EMPTY_OTP); 1441 if (empty_otp) 1442 IWL_INFO(trans, "OTP is empty\n"); 1443 1444 nvm = kzalloc(sizeof(*nvm) + 1445 sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS, 1446 GFP_KERNEL); 1447 if (!nvm) { 1448 ret = -ENOMEM; 1449 goto out; 1450 } 1451 1452 iwl_set_hw_address_from_csr(trans, nvm); 1453 /* TODO: if platform NVM has MAC address - override it here */ 1454 1455 if (!is_valid_ether_addr(nvm->hw_addr)) { 1456 IWL_ERR(trans, "no valid mac address was found\n"); 1457 ret = -EINVAL; 1458 goto err_free; 1459 } 1460 1461 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr); 1462 1463 /* Initialize general data */ 1464 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version); 1465 nvm->n_hw_addrs = rsp->general.n_hw_addrs; 1466 if (nvm->n_hw_addrs == 0) 1467 IWL_WARN(trans, 1468 "Firmware declares no reserved mac addresses. OTP is empty: %d\n", 1469 empty_otp); 1470 1471 /* Initialize MAC sku data */ 1472 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags); 1473 nvm->sku_cap_11ac_enable = 1474 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED); 1475 nvm->sku_cap_11n_enable = 1476 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED); 1477 nvm->sku_cap_11ax_enable = 1478 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED); 1479 nvm->sku_cap_band_24ghz_enable = 1480 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED); 1481 nvm->sku_cap_band_52ghz_enable = 1482 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED); 1483 nvm->sku_cap_mimo_disabled = 1484 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED); 1485 1486 /* Initialize PHY sku data */ 1487 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains); 1488 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains); 1489 1490 if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) { 1491 nvm->lar_enabled = true; 1492 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR; 1493 } 1494 1495 iwl_init_sbands(trans->dev, trans->cfg, nvm, 1496 rsp->regulatory.channel_profile, 1497 nvm->valid_tx_ant & fw->valid_tx_ant, 1498 nvm->valid_rx_ant & fw->valid_rx_ant, 1499 sbands_flags); 1500 1501 iwl_free_resp(&hcmd); 1502 return nvm; 1503 1504 err_free: 1505 kfree(nvm); 1506 out: 1507 iwl_free_resp(&hcmd); 1508 return ERR_PTR(ret); 1509 } 1510 IWL_EXPORT_SYMBOL(iwl_get_nvm); 1511