1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 10 * Copyright(c) 2018 - 2019 Intel Corporation 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * The full GNU General Public License is included in this distribution 22 * in the file called COPYING. 23 * 24 * Contact Information: 25 * Intel Linux Wireless <linuxwifi@intel.com> 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 * 28 * BSD LICENSE 29 * 30 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 31 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 32 * Copyright(c) 2018 - 2019 Intel Corporation 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 39 * * Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * * Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in 43 * the documentation and/or other materials provided with the 44 * distribution. 45 * * Neither the name Intel Corporation nor the names of its 46 * contributors may be used to endorse or promote products derived 47 * from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 *****************************************************************************/ 62 #ifndef __iwl_fh_h__ 63 #define __iwl_fh_h__ 64 65 #include <linux/types.h> 66 #include <linux/bitfield.h> 67 68 #include "iwl-trans.h" 69 70 /****************************/ 71 /* Flow Handler Definitions */ 72 /****************************/ 73 74 /** 75 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 76 * Addresses are offsets from device's PCI hardware base address. 77 */ 78 #define FH_MEM_LOWER_BOUND (0x1000) 79 #define FH_MEM_UPPER_BOUND (0x2000) 80 #define FH_MEM_LOWER_BOUND_GEN2 (0xa06000) 81 #define FH_MEM_UPPER_BOUND_GEN2 (0xa08000) 82 83 /** 84 * Keep-Warm (KW) buffer base address. 85 * 86 * Driver must allocate a 4KByte buffer that is for keeping the 87 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 88 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 89 * from going into a power-savings mode that would cause higher DRAM latency, 90 * and possible data over/under-runs, before all Tx/Rx is complete. 91 * 92 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 93 * of the buffer, which must be 4K aligned. Once this is set up, the device 94 * automatically invokes keep-warm accesses when normal accesses might not 95 * be sufficient to maintain fast DRAM response. 96 * 97 * Bit fields: 98 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 99 */ 100 #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) 101 102 103 /** 104 * TFD Circular Buffers Base (CBBC) addresses 105 * 106 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 107 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 108 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 109 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 110 * aligned (address bits 0-7 must be 0). 111 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 112 * for them are in different places. 113 * 114 * Bit fields in each pointer register: 115 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 116 */ 117 #define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 118 #define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 119 #define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0) 120 #define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 121 #define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20) 122 #define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) 123 /* 22000 TFD table address, 64 bit */ 124 #define TFH_TFDQ_CBB_TABLE (0x1C00) 125 126 /* Find TFD CB base pointer for given queue */ 127 static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans, 128 unsigned int chnl) 129 { 130 if (trans->trans_cfg->use_tfh) { 131 WARN_ON_ONCE(chnl >= 64); 132 return TFH_TFDQ_CBB_TABLE + 8 * chnl; 133 } 134 if (chnl < 16) 135 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 136 if (chnl < 20) 137 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 138 WARN_ON_ONCE(chnl >= 32); 139 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 140 } 141 142 /* 22000 configuration registers */ 143 144 /* 145 * TFH Configuration register. 146 * 147 * BIT fields: 148 * 149 * Bits 3:0: 150 * Define the maximum number of pending read requests. 151 * Maximum configuration value allowed is 0xC 152 * Bits 9:8: 153 * Define the maximum transfer size. (64 / 128 / 256) 154 * Bit 10: 155 * When bit is set and transfer size is set to 128B, the TFH will enable 156 * reading chunks of more than 64B only if the read address is aligned to 128B. 157 * In case of DRAM read address which is not aligned to 128B, the TFH will 158 * enable transfer size which doesn't cross 64B DRAM address boundary. 159 */ 160 #define TFH_TRANSFER_MODE (0x1F40) 161 #define TFH_TRANSFER_MAX_PENDING_REQ 0xc 162 #define TFH_CHUNK_SIZE_128 BIT(8) 163 #define TFH_CHUNK_SPLIT_MODE BIT(10) 164 /* 165 * Defines the offset address in dwords referring from the beginning of the 166 * Tx CMD which will be updated in DRAM. 167 * Note that the TFH offset address for Tx CMD update is always referring to 168 * the start of the TFD first TB. 169 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID 170 */ 171 #define TFH_TXCMD_UPDATE_CFG (0x1F48) 172 /* 173 * Controls TX DMA operation 174 * 175 * BIT fields: 176 * 177 * Bits 31:30: Enable the SRAM DMA channel. 178 * Turning on bit 31 will kick the SRAM2DRAM DMA. 179 * Note that the sram2dram may be enabled only after configuring the DRAM and 180 * SRAM addresses registers and the byte count register. 181 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When 182 * set to 1 - interrupt is sent to the driver 183 * Bit 0: Indicates the snoop configuration 184 */ 185 #define TFH_SRV_DMA_CHNL0_CTRL (0x1F60) 186 #define TFH_SRV_DMA_SNOOP BIT(0) 187 #define TFH_SRV_DMA_TO_DRIVER BIT(24) 188 #define TFH_SRV_DMA_START BIT(31) 189 190 /* Defines the DMA SRAM write start address to transfer a data block */ 191 #define TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64) 192 193 /* Defines the 64bits DRAM start address to read the DMA data block from */ 194 #define TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68) 195 196 /* 197 * Defines the number of bytes to transfer from DRAM to SRAM. 198 * Note that this register may be configured with non-dword aligned size. 199 */ 200 #define TFH_SRV_DMA_CHNL0_BC (0x1F70) 201 202 /** 203 * Rx SRAM Control and Status Registers (RSCSR) 204 * 205 * These registers provide handshake between driver and device for the Rx queue 206 * (this queue handles *all* command responses, notifications, Rx data, etc. 207 * sent from uCode to host driver). Unlike Tx, there is only one Rx 208 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 209 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 210 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 211 * mapping between RBDs and RBs. 212 * 213 * Driver must allocate host DRAM memory for the following, and set the 214 * physical address of each into device registers: 215 * 216 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 217 * entries (although any power of 2, up to 4096, is selectable by driver). 218 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 219 * (typically 4K, although 8K or 16K are also selectable by driver). 220 * Driver sets up RB size and number of RBDs in the CB via Rx config 221 * register FH_MEM_RCSR_CHNL0_CONFIG_REG. 222 * 223 * Bit fields within one RBD: 224 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 225 * 226 * Driver sets physical address [35:8] of base of RBD circular buffer 227 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 228 * 229 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 230 * (RBs) have been filled, via a "write pointer", actually the index of 231 * the RB's corresponding RBD within the circular buffer. Driver sets 232 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 233 * 234 * Bit fields in lower dword of Rx status buffer (upper dword not used 235 * by driver: 236 * 31-12: Not used by driver 237 * 11- 0: Index of last filled Rx buffer descriptor 238 * (device writes, driver reads this value) 239 * 240 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 241 * enter pointers to these RBs into contiguous RBD circular buffer entries, 242 * and update the device's "write" index register, 243 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 244 * 245 * This "write" index corresponds to the *next* RBD that the driver will make 246 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 247 * the circular buffer. This value should initially be 0 (before preparing any 248 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 249 * wrap back to 0 at the end of the circular buffer (but don't wrap before 250 * "read" index has advanced past 1! See below). 251 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 252 * 253 * As the device fills RBs (referenced from contiguous RBDs within the circular 254 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 255 * to tell the driver the index of the latest filled RBD. The driver must 256 * read this "read" index from DRAM after receiving an Rx interrupt from device 257 * 258 * The driver must also internally keep track of a third index, which is the 259 * next RBD to process. When receiving an Rx interrupt, driver should process 260 * all filled but unprocessed RBs up to, but not including, the RB 261 * corresponding to the "read" index. For example, if "read" index becomes "1", 262 * driver may process the RB pointed to by RBD 0. Depending on volume of 263 * traffic, there may be many RBs to process. 264 * 265 * If read index == write index, device thinks there is no room to put new data. 266 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 267 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 268 * and "read" indexes; that is, make sure that there are no more than 254 269 * buffers waiting to be filled. 270 */ 271 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 272 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 273 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) 274 275 /** 276 * Physical base address of 8-byte Rx Status buffer. 277 * Bit fields: 278 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 279 */ 280 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) 281 282 /** 283 * Physical base address of Rx Buffer Descriptor Circular Buffer. 284 * Bit fields: 285 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 286 */ 287 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) 288 289 /** 290 * Rx write pointer (index, really!). 291 * Bit fields: 292 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 293 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 294 */ 295 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) 296 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 297 298 #define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) 299 #define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 300 301 /** 302 * Rx Config/Status Registers (RCSR) 303 * Rx Config Reg for channel 0 (only channel used) 304 * 305 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 306 * normal operation (see bit fields). 307 * 308 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 309 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for 310 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 311 * 312 * Bit fields: 313 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 314 * '10' operate normally 315 * 29-24: reserved 316 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 317 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 318 * 19-18: reserved 319 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 320 * '10' 12K, '11' 16K. 321 * 15-14: reserved 322 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 323 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 324 * typical value 0x10 (about 1/2 msec) 325 * 3- 0: reserved 326 */ 327 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 328 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) 329 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) 330 331 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) 332 #define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8) 333 #define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10) 334 335 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 336 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 337 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 338 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 339 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 340 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 341 342 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 343 #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 344 #define RX_RB_TIMEOUT (0x11) 345 346 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 347 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 348 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 349 350 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 351 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 352 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 353 #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 354 355 #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 356 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 357 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 358 359 /** 360 * Rx Shared Status Registers (RSSR) 361 * 362 * After stopping Rx DMA channel (writing 0 to 363 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 364 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 365 * 366 * Bit fields: 367 * 24: 1 = Channel 0 is idle 368 * 369 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 370 * contain default values that should not be altered by the driver. 371 */ 372 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) 373 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 374 375 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) 376 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) 377 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 378 (FH_MEM_RSSR_LOWER_BOUND + 0x008) 379 380 #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 381 382 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 383 #define FH_MEM_TB_MAX_LENGTH (0x00020000) 384 385 /* 9000 rx series registers */ 386 387 #define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 388 #define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 389 /* Write index table */ 390 #define RFH_Q0_FRBDCB_WIDX 0xA08080 391 #define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4) 392 /* Write index table - shadow registers */ 393 #define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 394 #define RFH_Q_FRBDCB_WIDX_TRG(q) (RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 395 /* Read index table */ 396 #define RFH_Q0_FRBDCB_RIDX 0xA080C0 397 #define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4) 398 /* Used list table */ 399 #define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 400 #define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8) 401 /* Write index table */ 402 #define RFH_Q0_URBDCB_WIDX 0xA08180 403 #define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4) 404 #define RFH_Q0_URBDCB_VAID 0xA081C0 405 #define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4) 406 /* stts */ 407 #define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 408 #define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 409 410 #define RFH_Q0_ORB_WPTR_LSB 0xA08280 411 #define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8) 412 #define RFH_RBDBUF_RBD0_LSB 0xA08300 413 #define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8) 414 415 /** 416 * RFH Status Register 417 * 418 * Bit fields: 419 * 420 * Bit 29: RBD_FETCH_IDLE 421 * This status flag is set by the RFH when there is no active RBD fetch from 422 * DRAM. 423 * Once the RFH RBD controller starts fetching (or when there is a pending 424 * RBD read response from DRAM), this flag is immediately turned off. 425 * 426 * Bit 30: SRAM_DMA_IDLE 427 * This status flag is set by the RFH when there is no active transaction from 428 * SRAM to DRAM. 429 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 430 * 431 * Bit 31: RXF_DMA_IDLE 432 * This status flag is set by the RFH when there is no active transaction from 433 * RXF to DRAM. 434 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 435 */ 436 #define RFH_GEN_STATUS 0xA09808 437 #define RFH_GEN_STATUS_GEN3 0xA07824 438 #define RBD_FETCH_IDLE BIT(29) 439 #define SRAM_DMA_IDLE BIT(30) 440 #define RXF_DMA_IDLE BIT(31) 441 442 /* DMA configuration */ 443 #define RFH_RXF_DMA_CFG 0xA09820 444 #define RFH_RXF_DMA_CFG_GEN3 0xA07880 445 /* RB size */ 446 #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 447 #define RFH_RXF_DMA_RB_SIZE_POS 16 448 #define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS) 449 #define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS) 450 #define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS) 451 #define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS) 452 #define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS) 453 #define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS) 454 #define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS) 455 #define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS) 456 #define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS) 457 #define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS) 458 /* RB Circular Buffer size:defines the table sizes in RBD units */ 459 #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 460 #define RFH_RXF_DMA_RBDCB_SIZE_POS 20 461 #define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS) 462 #define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS) 463 #define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS) 464 #define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) 465 #define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) 466 #define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS) 467 #define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS) 468 #define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS) 469 #define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS) 470 #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 471 #define RFH_RXF_DMA_MIN_RB_SIZE_POS 24 472 #define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS) 473 #define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 474 #define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 475 #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 476 #define RFH_DMA_EN_ENABLE_VAL BIT(31) 477 478 #define RFH_RXF_RXQ_ACTIVE 0xA0980C 479 480 #define RFH_GEN_CFG 0xA09800 481 #define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0) 482 #define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1) 483 #define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4) 484 #define RFH_GEN_CFG_RB_CHUNK_SIZE_128 1 485 #define RFH_GEN_CFG_RB_CHUNK_SIZE_64 0 486 /* the driver assumes everywhere that the default RXQ is 0 */ 487 #define RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 488 #define RFH_GEN_CFG_VAL(_n, _v) FIELD_PREP(RFH_GEN_CFG_ ## _n, _v) 489 490 /* end of 9000 rx series registers */ 491 492 /* TFDB Area - TFDs buffer table */ 493 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 494 #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 495 #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) 496 #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 497 #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 498 499 /** 500 * Transmit DMA Channel Control/Status Registers (TCSR) 501 * 502 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 503 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 504 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 505 * 506 * To use a Tx DMA channel, driver must initialize its 507 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 508 * 509 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 510 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 511 * 512 * All other bits should be 0. 513 * 514 * Bit fields: 515 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 516 * '10' operate normally 517 * 29- 4: Reserved, set to "0" 518 * 3: Enable internal DMA requests (1, normal operation), disable (0) 519 * 2- 0: Reserved, set to "0" 520 */ 521 #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 522 #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) 523 524 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 525 #define FH_TCSR_CHNL_NUM (8) 526 527 /* TCSR: tx_config register values */ 528 #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 529 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 530 #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 531 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 532 #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 533 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 534 535 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 536 #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 537 538 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 539 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 540 541 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 542 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 543 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 544 545 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 546 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 547 #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 548 549 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 550 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 551 #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 552 553 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 554 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 555 #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 556 557 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 558 #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 559 560 /** 561 * Tx Shared Status Registers (TSSR) 562 * 563 * After stopping Tx DMA channel (writing 0 to 564 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 565 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 566 * (channel's buffers empty | no pending requests). 567 * 568 * Bit fields: 569 * 31-24: 1 = Channel buffers empty (channel 7:0) 570 * 23-16: 1 = No pending requests (channel 7:0) 571 */ 572 #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) 573 #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) 574 575 #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) 576 577 /** 578 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 579 * 31: Indicates an address error when accessed to internal memory 580 * uCode/driver must write "1" in order to clear this flag 581 * 30: Indicates that Host did not send the expected number of dwords to FH 582 * uCode/driver must write "1" in order to clear this flag 583 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 584 * command was received from the scheduler while the TRB was already full 585 * with previous command 586 * uCode/driver must write "1" in order to clear this flag 587 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 588 * bit is set, it indicates that the FH has received a full indication 589 * from the RTC TxFIFO and the current value of the TxCredit counter was 590 * not equal to zero. This mean that the credit mechanism was not 591 * synchronized to the TxFIFO status 592 * uCode/driver must write "1" in order to clear this flag 593 */ 594 #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) 595 #define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008) 596 597 #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 598 599 /* Tx service channels */ 600 #define FH_SRVC_CHNL (9) 601 #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) 602 #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 603 #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 604 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 605 606 #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) 607 #define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4) 608 609 /* Instruct FH to increment the retry count of a packet when 610 * it is brought from the memory to TX-FIFO 611 */ 612 #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 613 614 #define MQ_RX_TABLE_SIZE 512 615 #define MQ_RX_TABLE_MASK (MQ_RX_TABLE_SIZE - 1) 616 #define MQ_RX_NUM_RBDS (MQ_RX_TABLE_SIZE - 1) 617 #define RX_POOL_SIZE (MQ_RX_NUM_RBDS + \ 618 IWL_MAX_RX_HW_QUEUES * \ 619 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC)) 620 /* cb size is the exponent */ 621 #define RX_QUEUE_CB_SIZE(x) ilog2(x) 622 623 #define RX_QUEUE_SIZE 256 624 #define RX_QUEUE_MASK 255 625 #define RX_QUEUE_SIZE_LOG 8 626 627 /** 628 * struct iwl_rb_status - reserve buffer status 629 * host memory mapped FH registers 630 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 631 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 632 * @finished_rb_num [0:11] - Indicates the index of the current RB 633 * in which the last frame was written to 634 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 635 * which was transferred 636 */ 637 struct iwl_rb_status { 638 __le16 closed_rb_num; 639 __le16 closed_fr_num; 640 __le16 finished_rb_num; 641 __le16 finished_fr_nam; 642 __le32 __unused; 643 } __packed; 644 645 646 #define TFD_QUEUE_SIZE_MAX (256) 647 #define TFD_QUEUE_SIZE_MAX_GEN3 (65536) 648 /* cb size is the exponent - 3 */ 649 #define TFD_QUEUE_CB_SIZE(x) (ilog2(x) - 3) 650 #define TFD_QUEUE_SIZE_BC_DUP (64) 651 #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) 652 #define TFD_QUEUE_BC_SIZE_GEN3 (TFD_QUEUE_SIZE_MAX_GEN3 + \ 653 TFD_QUEUE_SIZE_BC_DUP) 654 #define IWL_TX_DMA_MASK DMA_BIT_MASK(36) 655 #define IWL_NUM_OF_TBS 20 656 #define IWL_TFH_NUM_TBS 25 657 658 static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr) 659 { 660 return (sizeof(addr) > sizeof(u32) ? upper_32_bits(addr) : 0) & 0xF; 661 } 662 663 /** 664 * enum iwl_tfd_tb_hi_n_len - TB hi_n_len bits 665 * @TB_HI_N_LEN_ADDR_HI_MSK: high 4 bits (to make it 36) of DMA address 666 * @TB_HI_N_LEN_LEN_MSK: length of the TB 667 */ 668 enum iwl_tfd_tb_hi_n_len { 669 TB_HI_N_LEN_ADDR_HI_MSK = 0xf, 670 TB_HI_N_LEN_LEN_MSK = 0xfff0, 671 }; 672 673 /** 674 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor 675 * 676 * This structure contains dma address and length of transmission address 677 * 678 * @lo: low [31:0] portion of the dma address of TX buffer 679 * every even is unaligned on 16 bit boundary 680 * @hi_n_len: &enum iwl_tfd_tb_hi_n_len 681 */ 682 struct iwl_tfd_tb { 683 __le32 lo; 684 __le16 hi_n_len; 685 } __packed; 686 687 /** 688 * struct iwl_tfh_tb transmit buffer descriptor within transmit frame descriptor 689 * 690 * This structure contains dma address and length of transmission address 691 * 692 * @tb_len length of the tx buffer 693 * @addr 64 bits dma address 694 */ 695 struct iwl_tfh_tb { 696 __le16 tb_len; 697 __le64 addr; 698 } __packed; 699 700 /** 701 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 702 * Both driver and device share these circular buffers, each of which must be 703 * contiguous 256 TFDs. 704 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes 705 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes 706 * 707 * Driver must indicate the physical address of the base of each 708 * circular buffer via the FH_MEM_CBBC_QUEUE registers. 709 * 710 * Each TFD contains pointer/size information for up to 20 / 25 data buffers 711 * in host DRAM. These buffers collectively contain the (one) frame described 712 * by the TFD. Each buffer must be a single contiguous block of memory within 713 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 714 * of (4K - 4). The concatenates all of a TFD's buffers into a single 715 * Tx frame, up to 8 KBytes in size. 716 * 717 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 718 */ 719 720 /** 721 * struct iwl_tfd - Transmit Frame Descriptor (TFD) 722 * @ __reserved1[3] reserved 723 * @ num_tbs 0-4 number of active tbs 724 * 5 reserved 725 * 6-7 padding (not used) 726 * @ tbs[20] transmit frame buffer descriptors 727 * @ __pad padding 728 */ 729 struct iwl_tfd { 730 u8 __reserved1[3]; 731 u8 num_tbs; 732 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; 733 __le32 __pad; 734 } __packed; 735 736 /** 737 * struct iwl_tfh_tfd - Transmit Frame Descriptor (TFD) 738 * @ num_tbs 0-4 number of active tbs 739 * 5 -15 reserved 740 * @ tbs[25] transmit frame buffer descriptors 741 * @ __pad padding 742 */ 743 struct iwl_tfh_tfd { 744 __le16 num_tbs; 745 struct iwl_tfh_tb tbs[IWL_TFH_NUM_TBS]; 746 __le32 __pad; 747 } __packed; 748 749 /* Keep Warm Size */ 750 #define IWL_KW_SIZE 0x1000 /* 4k */ 751 752 /* Fixed (non-configurable) rx data from phy */ 753 754 /** 755 * struct iwlagn_schedq_bc_tbl scheduler byte count table 756 * base physical address provided by SCD_DRAM_BASE_ADDR 757 * For devices up to 22000: 758 * @tfd_offset 0-12 - tx command byte count 759 * 12-16 - station index 760 * For 22000: 761 * @tfd_offset 0-12 - tx command byte count 762 * 12-13 - number of 64 byte chunks 763 * 14-16 - reserved 764 */ 765 struct iwlagn_scd_bc_tbl { 766 __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; 767 } __packed; 768 769 /** 770 * struct iwl_gen3_bc_tbl scheduler byte count table gen3 771 * For AX210 and on: 772 * @tfd_offset: 0-12 - tx command byte count 773 * 12-13 - number of 64 byte chunks 774 * 14-16 - reserved 775 */ 776 struct iwl_gen3_bc_tbl { 777 __le16 tfd_offset[TFD_QUEUE_BC_SIZE_GEN3]; 778 } __packed; 779 780 #endif /* !__iwl_fh_h__ */ 781