1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2023-2025 Intel Corporation 4 */ 5 6 #ifndef __fw_regulatory_h__ 7 #define __fw_regulatory_h__ 8 9 #include "fw/img.h" 10 #include "fw/api/commands.h" 11 #include "fw/api/power.h" 12 #include "fw/api/phy.h" 13 #include "fw/api/config.h" 14 #include "fw/api/nvm-reg.h" 15 #include "iwl-trans.h" 16 17 #define BIOS_SAR_MAX_PROFILE_NUM 4 18 /* 19 * Each SAR profile has (up to, depends on the table revision) 4 chains: 20 * chain A, chain B, chain A when in CDB, chain B when in CDB 21 */ 22 #define BIOS_SAR_MAX_CHAINS_PER_PROFILE 4 23 #define BIOS_SAR_NUM_CHAINS 2 24 #define BIOS_SAR_MAX_SUB_BANDS_NUM 11 25 26 #define BIOS_GEO_NUM_CHAINS 2 27 #define BIOS_GEO_MAX_NUM_BANDS 3 28 #define BIOS_GEO_MAX_PROFILE_NUM 8 29 #define BIOS_GEO_MIN_PROFILE_NUM 3 30 31 #define IWL_SAR_ENABLE_MSK BIT(0) 32 33 /* PPAG gain value bounds in 1/8 dBm */ 34 #define IWL_PPAG_MIN_LB -16 35 #define IWL_PPAG_MAX_LB 24 36 #define IWL_PPAG_MIN_HB -16 37 #define IWL_PPAG_MAX_HB 40 38 39 #define IWL_PPAG_ETSI_CHINA_MASK 3 40 #define IWL_PPAG_REV3_MASK 0x7FF 41 42 #define IWL_WTAS_ENABLED_MSK BIT(0) 43 #define IWL_WTAS_OVERRIDE_IEC_MSK BIT(1) 44 #define IWL_WTAS_ENABLE_IEC_MSK BIT(2) 45 #define IWL_WTAS_CANADA_UHB_MSK BIT(15) 46 #define IWL_WTAS_USA_UHB_MSK BIT(16) 47 48 struct iwl_tas_selection_data { 49 u8 override_tas_iec:1, 50 enable_tas_iec:1, 51 usa_tas_uhb_allowed:1, 52 canada_tas_uhb_allowed:1; 53 }; 54 55 #define BIOS_MCC_CHINA 0x434e 56 57 /* 58 * The profile for revision 2 is a superset of revision 1, which is in 59 * turn a superset of revision 0. So we can store all revisions 60 * inside revision 2, which is what we represent here. 61 */ 62 63 /* 64 * struct iwl_sar_profile_chain - per-chain values of a SAR profile 65 * @subbands: the SAR value for each subband 66 */ 67 struct iwl_sar_profile_chain { 68 u8 subbands[BIOS_SAR_MAX_SUB_BANDS_NUM]; 69 }; 70 71 /* 72 * struct iwl_sar_profile - SAR profile from SAR tables 73 * @enabled: whether the profile is enabled or not 74 * @chains: per-chain SAR values 75 */ 76 struct iwl_sar_profile { 77 bool enabled; 78 struct iwl_sar_profile_chain chains[BIOS_SAR_MAX_CHAINS_PER_PROFILE]; 79 }; 80 81 /* Same thing as with SAR, all revisions fit in revision 2 */ 82 83 /* 84 * struct iwl_geo_profile_band - per-band geo SAR offsets 85 * @max: the max tx power allowed for the band 86 * @chains: SAR offsets values for each chain 87 */ 88 struct iwl_geo_profile_band { 89 u8 max; 90 u8 chains[BIOS_GEO_NUM_CHAINS]; 91 }; 92 93 /* 94 * struct iwl_geo_profile - geo profile 95 * @bands: per-band table of the SAR offsets 96 */ 97 struct iwl_geo_profile { 98 struct iwl_geo_profile_band bands[BIOS_GEO_MAX_NUM_BANDS]; 99 }; 100 101 /* Same thing as with SAR, all revisions fit in revision 2 */ 102 struct iwl_ppag_chain { 103 s8 subbands[BIOS_SAR_MAX_SUB_BANDS_NUM]; 104 }; 105 106 struct iwl_tas_data { 107 u8 block_list_size; 108 u16 block_list_array[IWL_WTAS_BLACK_LIST_MAX]; 109 u8 table_source; 110 u8 table_revision; 111 u32 tas_selection; 112 }; 113 114 /* For DSM revision 0 and 4 */ 115 enum iwl_dsm_funcs { 116 DSM_FUNC_QUERY = 0, 117 DSM_FUNC_DISABLE_SRD = 1, 118 DSM_FUNC_ENABLE_INDONESIA_5G2 = 2, 119 DSM_FUNC_ENABLE_6E = 3, 120 DSM_FUNC_REGULATORY_CONFIG = 4, 121 DSM_FUNC_11AX_ENABLEMENT = 6, 122 DSM_FUNC_ENABLE_UNII4_CHAN = 7, 123 DSM_FUNC_ACTIVATE_CHANNEL = 8, 124 DSM_FUNC_FORCE_DISABLE_CHANNELS = 9, 125 DSM_FUNC_ENERGY_DETECTION_THRESHOLD = 10, 126 DSM_FUNC_RFI_CONFIG = 11, 127 DSM_FUNC_ENABLE_11BE = 12, 128 DSM_FUNC_NUM_FUNCS = 13, 129 }; 130 131 enum iwl_dsm_values_srd { 132 DSM_VALUE_SRD_ACTIVE, 133 DSM_VALUE_SRD_PASSIVE, 134 DSM_VALUE_SRD_DISABLE, 135 DSM_VALUE_SRD_MAX 136 }; 137 138 enum iwl_dsm_values_indonesia { 139 DSM_VALUE_INDONESIA_DISABLE, 140 DSM_VALUE_INDONESIA_ENABLE, 141 DSM_VALUE_INDONESIA_RESERVED, 142 DSM_VALUE_INDONESIA_MAX 143 }; 144 145 enum iwl_dsm_unii4_bitmap { 146 DSM_VALUE_UNII4_US_OVERRIDE_MSK = BIT(0), 147 DSM_VALUE_UNII4_US_EN_MSK = BIT(1), 148 DSM_VALUE_UNII4_ETSI_OVERRIDE_MSK = BIT(2), 149 DSM_VALUE_UNII4_ETSI_EN_MSK = BIT(3), 150 DSM_VALUE_UNII4_CANADA_OVERRIDE_MSK = BIT(4), 151 DSM_VALUE_UNII4_CANADA_EN_MSK = BIT(5), 152 }; 153 154 #define DSM_UNII4_ALLOW_BITMAP (DSM_VALUE_UNII4_US_OVERRIDE_MSK |\ 155 DSM_VALUE_UNII4_US_EN_MSK |\ 156 DSM_VALUE_UNII4_ETSI_OVERRIDE_MSK |\ 157 DSM_VALUE_UNII4_ETSI_EN_MSK |\ 158 DSM_VALUE_UNII4_CANADA_OVERRIDE_MSK |\ 159 DSM_VALUE_UNII4_CANADA_EN_MSK) 160 161 #define DSM_11AX_ALLOW_BITMAP 0xF 162 #define DSM_EDT_ALLOWED_BITMAP 0x7ffff0 163 #define DSM_FORCE_DISABLE_CHANNELS_ALLOWED_BITMAP 0x7FF 164 165 enum iwl_dsm_values_rfi { 166 DSM_VALUE_RFI_DLVR_DISABLE = BIT(0), 167 DSM_VALUE_RFI_DDR_DISABLE = BIT(1), 168 }; 169 170 #define DSM_VALUE_RFI_DISABLE (DSM_VALUE_RFI_DLVR_DISABLE |\ 171 DSM_VALUE_RFI_DDR_DISABLE) 172 173 bool iwl_rfi_is_enabled_in_bios(struct iwl_fw_runtime *fwrt); 174 175 enum iwl_dsm_masks_reg { 176 DSM_MASK_CHINA_22_REG = BIT(2) 177 }; 178 179 struct iwl_fw_runtime; 180 181 bool iwl_sar_geo_support(struct iwl_fw_runtime *fwrt); 182 183 int iwl_sar_geo_fill_table(struct iwl_fw_runtime *fwrt, 184 struct iwl_per_chain_offset *table, 185 u32 n_bands, u32 n_profiles); 186 187 int iwl_sar_fill_profile(struct iwl_fw_runtime *fwrt, 188 __le16 *per_chain, u32 n_tables, u32 n_subbands, 189 int prof_a, int prof_b); 190 191 int iwl_fill_ppag_table(struct iwl_fw_runtime *fwrt, 192 union iwl_ppag_table_cmd *cmd, 193 int *cmd_size); 194 195 bool iwl_is_ppag_approved(struct iwl_fw_runtime *fwrt); 196 197 bool iwl_is_tas_approved(void); 198 bool iwl_add_mcc_to_tas_block_list(u16 *list, u8 *size, u16 mcc); 199 200 struct iwl_tas_selection_data 201 iwl_parse_tas_selection(const u32 tas_selection, const u8 tbl_rev); 202 203 int iwl_bios_get_wrds_table(struct iwl_fw_runtime *fwrt); 204 205 int iwl_bios_get_ewrd_table(struct iwl_fw_runtime *fwrt); 206 207 int iwl_bios_get_wgds_table(struct iwl_fw_runtime *fwrt); 208 209 int iwl_bios_get_ppag_table(struct iwl_fw_runtime *fwrt); 210 211 int iwl_bios_get_tas_table(struct iwl_fw_runtime *fwrt, 212 struct iwl_tas_data *data); 213 214 int iwl_bios_get_pwr_limit(struct iwl_fw_runtime *fwrt, 215 u64 *dflt_pwr_limit); 216 217 int iwl_bios_get_mcc(struct iwl_fw_runtime *fwrt, char *mcc); 218 int iwl_bios_get_eckv(struct iwl_fw_runtime *fwrt, u32 *ext_clk); 219 int iwl_bios_get_wbem(struct iwl_fw_runtime *fwrt, u32 *value); 220 221 __le32 iwl_get_lari_config_bitmap(struct iwl_fw_runtime *fwrt); 222 int iwl_fill_lari_config(struct iwl_fw_runtime *fwrt, 223 struct iwl_lari_config_change_cmd *cmd, 224 size_t *cmd_size); 225 226 int iwl_bios_get_dsm(struct iwl_fw_runtime *fwrt, enum iwl_dsm_funcs func, 227 u32 *value); 228 229 static inline u32 iwl_bios_get_ppag_flags(const u32 ppag_modes, 230 const u8 ppag_bios_rev) 231 { 232 /* For revision 4 and above driver is pipe */ 233 if (ppag_bios_rev >= 4) 234 return ppag_modes; 235 236 return ppag_modes & (ppag_bios_rev < 3 ? IWL_PPAG_ETSI_CHINA_MASK : 237 IWL_PPAG_REV3_MASK); 238 } 239 240 bool iwl_puncturing_is_allowed_in_bios(u32 puncturing, u16 mcc); 241 242 #define IWL_DSBR_FW_MODIFIED_URM_MASK BIT(8) 243 #define IWL_DSBR_PERMANENT_URM_MASK BIT(9) 244 245 int iwl_bios_get_dsbr(struct iwl_fw_runtime *fwrt, u32 *value); 246 int iwl_bios_get_phy_filters(struct iwl_fw_runtime *fwrt); 247 248 static inline void iwl_bios_setup_step(struct iwl_trans *trans, 249 struct iwl_fw_runtime *fwrt) 250 { 251 u32 dsbr; 252 253 if (!trans->mac_cfg->integrated) 254 return; 255 256 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ) 257 return; 258 259 if (iwl_bios_get_dsbr(fwrt, &dsbr)) 260 dsbr = 0; 261 262 trans->conf.dsbr_urm_fw_dependent = 263 !!(dsbr & IWL_DSBR_FW_MODIFIED_URM_MASK); 264 trans->conf.dsbr_urm_permanent = 265 !!(dsbr & IWL_DSBR_PERMANENT_URM_MASK); 266 } 267 #endif /* __fw_regulatory_h__ */ 268