1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "iwl-fh.h" 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @fwrt_len: length of the valid data in fwrt_ptr 23 */ 24 struct iwl_fw_dump_ptrs { 25 struct iwl_trans_dump_data *trans_ptr; 26 void *fwrt_ptr; 27 u32 fwrt_len; 28 }; 29 30 #define RADIO_REG_MAX_READ 0x2ad 31 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 32 struct iwl_fw_error_dump_data **dump_data) 33 { 34 u8 *pos = (void *)(*dump_data)->data; 35 int i; 36 37 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 38 39 if (!iwl_trans_grab_nic_access(fwrt->trans)) 40 return; 41 42 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 43 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 44 45 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 46 u32 rd_cmd = RADIO_RSP_RD_CMD; 47 48 rd_cmd |= i << RADIO_RSP_ADDR_POS; 49 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 50 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 51 52 pos++; 53 } 54 55 *dump_data = iwl_fw_error_next_data(*dump_data); 56 57 iwl_trans_release_nic_access(fwrt->trans); 58 } 59 60 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 61 struct iwl_fw_error_dump_data **dump_data, 62 int size, u32 offset, int fifo_num) 63 { 64 struct iwl_fw_error_dump_fifo *fifo_hdr; 65 u32 *fifo_data; 66 u32 fifo_len; 67 int i; 68 69 fifo_hdr = (void *)(*dump_data)->data; 70 fifo_data = (void *)fifo_hdr->data; 71 fifo_len = size; 72 73 /* No need to try to read the data if the length is 0 */ 74 if (fifo_len == 0) 75 return; 76 77 /* Add a TLV for the RXF */ 78 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 79 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 80 81 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 82 fifo_hdr->available_bytes = 83 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 84 RXF_RD_D_SPACE + offset)); 85 fifo_hdr->wr_ptr = 86 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 87 RXF_RD_WR_PTR + offset)); 88 fifo_hdr->rd_ptr = 89 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 90 RXF_RD_RD_PTR + offset)); 91 fifo_hdr->fence_ptr = 92 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 93 RXF_RD_FENCE_PTR + offset)); 94 fifo_hdr->fence_mode = 95 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 96 RXF_SET_FENCE_MODE + offset)); 97 98 /* Lock fence */ 99 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 100 /* Set fence pointer to the same place like WR pointer */ 101 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 102 /* Set fence offset */ 103 iwl_trans_write_prph(fwrt->trans, 104 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 105 106 /* Read FIFO */ 107 fifo_len /= sizeof(u32); /* Size in DWORDS */ 108 for (i = 0; i < fifo_len; i++) 109 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 110 RXF_FIFO_RD_FENCE_INC + 111 offset); 112 *dump_data = iwl_fw_error_next_data(*dump_data); 113 } 114 115 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 116 struct iwl_fw_error_dump_data **dump_data, 117 int size, u32 offset, int fifo_num) 118 { 119 struct iwl_fw_error_dump_fifo *fifo_hdr; 120 u32 *fifo_data; 121 u32 fifo_len; 122 int i; 123 124 fifo_hdr = (void *)(*dump_data)->data; 125 fifo_data = (void *)fifo_hdr->data; 126 fifo_len = size; 127 128 /* No need to try to read the data if the length is 0 */ 129 if (fifo_len == 0) 130 return; 131 132 /* Add a TLV for the FIFO */ 133 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 134 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 135 136 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 137 fifo_hdr->available_bytes = 138 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 139 TXF_FIFO_ITEM_CNT + offset)); 140 fifo_hdr->wr_ptr = 141 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 142 TXF_WR_PTR + offset)); 143 fifo_hdr->rd_ptr = 144 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 145 TXF_RD_PTR + offset)); 146 fifo_hdr->fence_ptr = 147 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 148 TXF_FENCE_PTR + offset)); 149 fifo_hdr->fence_mode = 150 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 151 TXF_LOCK_FENCE + offset)); 152 153 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 154 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 155 TXF_WR_PTR + offset); 156 157 /* Dummy-read to advance the read pointer to the head */ 158 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 159 160 /* Read FIFO */ 161 for (i = 0; i < fifo_len / sizeof(u32); i++) 162 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 163 TXF_READ_MODIFY_DATA + 164 offset); 165 166 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 167 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 168 fifo_data, fifo_len); 169 170 *dump_data = iwl_fw_error_next_data(*dump_data); 171 } 172 173 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 174 struct iwl_fw_error_dump_data **dump_data) 175 { 176 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 177 178 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 179 180 if (!iwl_trans_grab_nic_access(fwrt->trans)) 181 return; 182 183 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 184 /* Pull RXF1 */ 185 iwl_fwrt_dump_rxf(fwrt, dump_data, 186 cfg->lmac[0].rxfifo1_size, 0, 0); 187 /* Pull RXF2 */ 188 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 189 RXF_DIFF_FROM_PREV + 190 fwrt->trans->mac_cfg->umac_prph_offset, 1); 191 /* Pull LMAC2 RXF1 */ 192 if (fwrt->smem_cfg.num_lmacs > 1) 193 iwl_fwrt_dump_rxf(fwrt, dump_data, 194 cfg->lmac[1].rxfifo1_size, 195 LMAC2_PRPH_OFFSET, 2); 196 } 197 198 iwl_trans_release_nic_access(fwrt->trans); 199 } 200 201 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 202 struct iwl_fw_error_dump_data **dump_data) 203 { 204 struct iwl_fw_error_dump_fifo *fifo_hdr; 205 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 206 u32 *fifo_data; 207 u32 fifo_len; 208 int i, j; 209 210 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 211 212 if (!iwl_trans_grab_nic_access(fwrt->trans)) 213 return; 214 215 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 216 /* Pull TXF data from LMAC1 */ 217 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 218 /* Mark the number of TXF we're pulling now */ 219 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 220 iwl_fwrt_dump_txf(fwrt, dump_data, 221 cfg->lmac[0].txfifo_size[i], 0, i); 222 } 223 224 /* Pull TXF data from LMAC2 */ 225 if (fwrt->smem_cfg.num_lmacs > 1) { 226 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 227 i++) { 228 /* Mark the number of TXF we're pulling now */ 229 iwl_trans_write_prph(fwrt->trans, 230 TXF_LARC_NUM + 231 LMAC2_PRPH_OFFSET, i); 232 iwl_fwrt_dump_txf(fwrt, dump_data, 233 cfg->lmac[1].txfifo_size[i], 234 LMAC2_PRPH_OFFSET, 235 i + cfg->num_txfifo_entries); 236 } 237 } 238 } 239 240 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 241 fw_has_capa(&fwrt->fw->ucode_capa, 242 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 243 /* Pull UMAC internal TXF data from all TXFs */ 244 for (i = 0; 245 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 246 i++) { 247 fifo_hdr = (void *)(*dump_data)->data; 248 fifo_data = (void *)fifo_hdr->data; 249 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 250 251 /* No need to try to read the data if the length is 0 */ 252 if (fifo_len == 0) 253 continue; 254 255 /* Add a TLV for the internal FIFOs */ 256 (*dump_data)->type = 257 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 258 (*dump_data)->len = 259 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 260 261 fifo_hdr->fifo_num = cpu_to_le32(i); 262 263 /* Mark the number of TXF we're pulling now */ 264 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 265 fwrt->smem_cfg.num_txfifo_entries); 266 267 fifo_hdr->available_bytes = 268 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 269 TXF_CPU2_FIFO_ITEM_CNT)); 270 fifo_hdr->wr_ptr = 271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 272 TXF_CPU2_WR_PTR)); 273 fifo_hdr->rd_ptr = 274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 275 TXF_CPU2_RD_PTR)); 276 fifo_hdr->fence_ptr = 277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 278 TXF_CPU2_FENCE_PTR)); 279 fifo_hdr->fence_mode = 280 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 281 TXF_CPU2_LOCK_FENCE)); 282 283 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 284 iwl_trans_write_prph(fwrt->trans, 285 TXF_CPU2_READ_MODIFY_ADDR, 286 TXF_CPU2_WR_PTR); 287 288 /* Dummy-read to advance the read pointer to head */ 289 iwl_trans_read_prph(fwrt->trans, 290 TXF_CPU2_READ_MODIFY_DATA); 291 292 /* Read FIFO */ 293 fifo_len /= sizeof(u32); /* Size in DWORDS */ 294 for (j = 0; j < fifo_len; j++) 295 fifo_data[j] = 296 iwl_trans_read_prph(fwrt->trans, 297 TXF_CPU2_READ_MODIFY_DATA); 298 *dump_data = iwl_fw_error_next_data(*dump_data); 299 } 300 } 301 302 iwl_trans_release_nic_access(fwrt->trans); 303 } 304 305 struct iwl_prph_range { 306 u32 start, end; 307 }; 308 309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 310 { .start = 0x00a00000, .end = 0x00a00000 }, 311 { .start = 0x00a0000c, .end = 0x00a00024 }, 312 { .start = 0x00a0002c, .end = 0x00a0003c }, 313 { .start = 0x00a00410, .end = 0x00a00418 }, 314 { .start = 0x00a00420, .end = 0x00a00420 }, 315 { .start = 0x00a00428, .end = 0x00a00428 }, 316 { .start = 0x00a00430, .end = 0x00a0043c }, 317 { .start = 0x00a00444, .end = 0x00a00444 }, 318 { .start = 0x00a004c0, .end = 0x00a004cc }, 319 { .start = 0x00a004d8, .end = 0x00a004d8 }, 320 { .start = 0x00a004e0, .end = 0x00a004f0 }, 321 { .start = 0x00a00840, .end = 0x00a00840 }, 322 { .start = 0x00a00850, .end = 0x00a00858 }, 323 { .start = 0x00a01004, .end = 0x00a01008 }, 324 { .start = 0x00a01010, .end = 0x00a01010 }, 325 { .start = 0x00a01018, .end = 0x00a01018 }, 326 { .start = 0x00a01024, .end = 0x00a01024 }, 327 { .start = 0x00a0102c, .end = 0x00a01034 }, 328 { .start = 0x00a0103c, .end = 0x00a01040 }, 329 { .start = 0x00a01048, .end = 0x00a01094 }, 330 { .start = 0x00a01c00, .end = 0x00a01c20 }, 331 { .start = 0x00a01c58, .end = 0x00a01c58 }, 332 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 333 { .start = 0x00a01c28, .end = 0x00a01c54 }, 334 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 335 { .start = 0x00a01c60, .end = 0x00a01cdc }, 336 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 337 { .start = 0x00a01d18, .end = 0x00a01d20 }, 338 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 339 { .start = 0x00a01d40, .end = 0x00a01d5c }, 340 { .start = 0x00a01d80, .end = 0x00a01d80 }, 341 { .start = 0x00a01d98, .end = 0x00a01d9c }, 342 { .start = 0x00a01da8, .end = 0x00a01da8 }, 343 { .start = 0x00a01db8, .end = 0x00a01df4 }, 344 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 345 { .start = 0x00a01e00, .end = 0x00a01e2c }, 346 { .start = 0x00a01e40, .end = 0x00a01e60 }, 347 { .start = 0x00a01e68, .end = 0x00a01e6c }, 348 { .start = 0x00a01e74, .end = 0x00a01e74 }, 349 { .start = 0x00a01e84, .end = 0x00a01e90 }, 350 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 351 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 352 { .start = 0x00a01f00, .end = 0x00a01f1c }, 353 { .start = 0x00a01f44, .end = 0x00a01ffc }, 354 { .start = 0x00a02000, .end = 0x00a02048 }, 355 { .start = 0x00a02068, .end = 0x00a020f0 }, 356 { .start = 0x00a02100, .end = 0x00a02118 }, 357 { .start = 0x00a02140, .end = 0x00a0214c }, 358 { .start = 0x00a02168, .end = 0x00a0218c }, 359 { .start = 0x00a021c0, .end = 0x00a021c0 }, 360 { .start = 0x00a02400, .end = 0x00a02410 }, 361 { .start = 0x00a02418, .end = 0x00a02420 }, 362 { .start = 0x00a02428, .end = 0x00a0242c }, 363 { .start = 0x00a02434, .end = 0x00a02434 }, 364 { .start = 0x00a02440, .end = 0x00a02460 }, 365 { .start = 0x00a02468, .end = 0x00a024b0 }, 366 { .start = 0x00a024c8, .end = 0x00a024cc }, 367 { .start = 0x00a02500, .end = 0x00a02504 }, 368 { .start = 0x00a0250c, .end = 0x00a02510 }, 369 { .start = 0x00a02540, .end = 0x00a02554 }, 370 { .start = 0x00a02580, .end = 0x00a025f4 }, 371 { .start = 0x00a02600, .end = 0x00a0260c }, 372 { .start = 0x00a02648, .end = 0x00a02650 }, 373 { .start = 0x00a02680, .end = 0x00a02680 }, 374 { .start = 0x00a026c0, .end = 0x00a026d0 }, 375 { .start = 0x00a02700, .end = 0x00a0270c }, 376 { .start = 0x00a02804, .end = 0x00a02804 }, 377 { .start = 0x00a02818, .end = 0x00a0281c }, 378 { .start = 0x00a02c00, .end = 0x00a02db4 }, 379 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 380 { .start = 0x00a03000, .end = 0x00a03014 }, 381 { .start = 0x00a0301c, .end = 0x00a0302c }, 382 { .start = 0x00a03034, .end = 0x00a03038 }, 383 { .start = 0x00a03040, .end = 0x00a03048 }, 384 { .start = 0x00a03060, .end = 0x00a03068 }, 385 { .start = 0x00a03070, .end = 0x00a03074 }, 386 { .start = 0x00a0307c, .end = 0x00a0307c }, 387 { .start = 0x00a03080, .end = 0x00a03084 }, 388 { .start = 0x00a0308c, .end = 0x00a03090 }, 389 { .start = 0x00a03098, .end = 0x00a03098 }, 390 { .start = 0x00a030a0, .end = 0x00a030a0 }, 391 { .start = 0x00a030a8, .end = 0x00a030b4 }, 392 { .start = 0x00a030bc, .end = 0x00a030bc }, 393 { .start = 0x00a030c0, .end = 0x00a0312c }, 394 { .start = 0x00a03c00, .end = 0x00a03c5c }, 395 { .start = 0x00a04400, .end = 0x00a04454 }, 396 { .start = 0x00a04460, .end = 0x00a04474 }, 397 { .start = 0x00a044c0, .end = 0x00a044ec }, 398 { .start = 0x00a04500, .end = 0x00a04504 }, 399 { .start = 0x00a04510, .end = 0x00a04538 }, 400 { .start = 0x00a04540, .end = 0x00a04548 }, 401 { .start = 0x00a04560, .end = 0x00a0457c }, 402 { .start = 0x00a04590, .end = 0x00a04598 }, 403 { .start = 0x00a045c0, .end = 0x00a045f4 }, 404 }; 405 406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 407 { .start = 0x00a05c00, .end = 0x00a05c18 }, 408 { .start = 0x00a05400, .end = 0x00a056e8 }, 409 { .start = 0x00a08000, .end = 0x00a098bc }, 410 { .start = 0x00a02400, .end = 0x00a02758 }, 411 { .start = 0x00a04764, .end = 0x00a0476c }, 412 { .start = 0x00a04770, .end = 0x00a04774 }, 413 { .start = 0x00a04620, .end = 0x00a04624 }, 414 }; 415 416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 417 { .start = 0x00a00000, .end = 0x00a00000 }, 418 { .start = 0x00a0000c, .end = 0x00a00024 }, 419 { .start = 0x00a0002c, .end = 0x00a00034 }, 420 { .start = 0x00a0003c, .end = 0x00a0003c }, 421 { .start = 0x00a00410, .end = 0x00a00418 }, 422 { .start = 0x00a00420, .end = 0x00a00420 }, 423 { .start = 0x00a00428, .end = 0x00a00428 }, 424 { .start = 0x00a00430, .end = 0x00a0043c }, 425 { .start = 0x00a00444, .end = 0x00a00444 }, 426 { .start = 0x00a00840, .end = 0x00a00840 }, 427 { .start = 0x00a00850, .end = 0x00a00858 }, 428 { .start = 0x00a01004, .end = 0x00a01008 }, 429 { .start = 0x00a01010, .end = 0x00a01010 }, 430 { .start = 0x00a01018, .end = 0x00a01018 }, 431 { .start = 0x00a01024, .end = 0x00a01024 }, 432 { .start = 0x00a0102c, .end = 0x00a01034 }, 433 { .start = 0x00a0103c, .end = 0x00a01040 }, 434 { .start = 0x00a01048, .end = 0x00a01050 }, 435 { .start = 0x00a01058, .end = 0x00a01058 }, 436 { .start = 0x00a01060, .end = 0x00a01070 }, 437 { .start = 0x00a0108c, .end = 0x00a0108c }, 438 { .start = 0x00a01c20, .end = 0x00a01c28 }, 439 { .start = 0x00a01d10, .end = 0x00a01d10 }, 440 { .start = 0x00a01e28, .end = 0x00a01e2c }, 441 { .start = 0x00a01e60, .end = 0x00a01e60 }, 442 { .start = 0x00a01e80, .end = 0x00a01e80 }, 443 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 444 { .start = 0x00a02000, .end = 0x00a0201c }, 445 { .start = 0x00a02024, .end = 0x00a02024 }, 446 { .start = 0x00a02040, .end = 0x00a02048 }, 447 { .start = 0x00a020c0, .end = 0x00a020e0 }, 448 { .start = 0x00a02400, .end = 0x00a02404 }, 449 { .start = 0x00a0240c, .end = 0x00a02414 }, 450 { .start = 0x00a0241c, .end = 0x00a0243c }, 451 { .start = 0x00a02448, .end = 0x00a024bc }, 452 { .start = 0x00a024c4, .end = 0x00a024cc }, 453 { .start = 0x00a02508, .end = 0x00a02508 }, 454 { .start = 0x00a02510, .end = 0x00a02514 }, 455 { .start = 0x00a0251c, .end = 0x00a0251c }, 456 { .start = 0x00a0252c, .end = 0x00a0255c }, 457 { .start = 0x00a02564, .end = 0x00a025a0 }, 458 { .start = 0x00a025a8, .end = 0x00a025b4 }, 459 { .start = 0x00a025c0, .end = 0x00a025c0 }, 460 { .start = 0x00a025e8, .end = 0x00a025f4 }, 461 { .start = 0x00a02c08, .end = 0x00a02c18 }, 462 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 463 { .start = 0x00a02c68, .end = 0x00a02c78 }, 464 { .start = 0x00a03000, .end = 0x00a03000 }, 465 { .start = 0x00a03010, .end = 0x00a03014 }, 466 { .start = 0x00a0301c, .end = 0x00a0302c }, 467 { .start = 0x00a03034, .end = 0x00a03038 }, 468 { .start = 0x00a03040, .end = 0x00a03044 }, 469 { .start = 0x00a03060, .end = 0x00a03068 }, 470 { .start = 0x00a03070, .end = 0x00a03070 }, 471 { .start = 0x00a0307c, .end = 0x00a03084 }, 472 { .start = 0x00a0308c, .end = 0x00a03090 }, 473 { .start = 0x00a03098, .end = 0x00a03098 }, 474 { .start = 0x00a030a0, .end = 0x00a030a0 }, 475 { .start = 0x00a030a8, .end = 0x00a030b4 }, 476 { .start = 0x00a030bc, .end = 0x00a030c0 }, 477 { .start = 0x00a030c8, .end = 0x00a030f4 }, 478 { .start = 0x00a03100, .end = 0x00a0312c }, 479 { .start = 0x00a03c00, .end = 0x00a03c5c }, 480 { .start = 0x00a04400, .end = 0x00a04454 }, 481 { .start = 0x00a04460, .end = 0x00a04474 }, 482 { .start = 0x00a044c0, .end = 0x00a044ec }, 483 { .start = 0x00a04500, .end = 0x00a04504 }, 484 { .start = 0x00a04510, .end = 0x00a04538 }, 485 { .start = 0x00a04540, .end = 0x00a04548 }, 486 { .start = 0x00a04560, .end = 0x00a04560 }, 487 { .start = 0x00a04570, .end = 0x00a0457c }, 488 { .start = 0x00a04590, .end = 0x00a04590 }, 489 { .start = 0x00a04598, .end = 0x00a04598 }, 490 { .start = 0x00a045c0, .end = 0x00a045f4 }, 491 { .start = 0x00a05c18, .end = 0x00a05c1c }, 492 { .start = 0x00a0c000, .end = 0x00a0c018 }, 493 { .start = 0x00a0c020, .end = 0x00a0c028 }, 494 { .start = 0x00a0c038, .end = 0x00a0c094 }, 495 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 496 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 497 { .start = 0x00a0c150, .end = 0x00a0c174 }, 498 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 499 { .start = 0x00a0c190, .end = 0x00a0c198 }, 500 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 501 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 502 }; 503 504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 505 { .start = 0x00d03c00, .end = 0x00d03c64 }, 506 { .start = 0x00d05c18, .end = 0x00d05c1c }, 507 { .start = 0x00d0c000, .end = 0x00d0c174 }, 508 }; 509 510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 511 u32 len_bytes, __le32 *data) 512 { 513 u32 i; 514 515 for (i = 0; i < len_bytes; i += 4) 516 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 517 } 518 519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 520 const struct iwl_prph_range *iwl_prph_dump_addr, 521 u32 range_len, void *ptr) 522 { 523 struct iwl_fw_error_dump_prph *prph; 524 struct iwl_trans *trans = fwrt->trans; 525 struct iwl_fw_error_dump_data **data = 526 (struct iwl_fw_error_dump_data **)ptr; 527 u32 i; 528 529 if (!data) 530 return; 531 532 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 533 534 if (!iwl_trans_grab_nic_access(trans)) 535 return; 536 537 for (i = 0; i < range_len; i++) { 538 /* The range includes both boundaries */ 539 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 540 iwl_prph_dump_addr[i].start + 4; 541 542 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 543 (*data)->len = cpu_to_le32(sizeof(*prph) + 544 num_bytes_in_chunk); 545 prph = (void *)(*data)->data; 546 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 547 548 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 549 /* our range is inclusive, hence + 4 */ 550 iwl_prph_dump_addr[i].end - 551 iwl_prph_dump_addr[i].start + 4, 552 (void *)prph->data); 553 554 *data = iwl_fw_error_next_data(*data); 555 } 556 557 iwl_trans_release_nic_access(trans); 558 } 559 560 /* 561 * alloc_sgtable - allocates (chained) scatterlist in the given size, 562 * fills it with pages and returns it 563 * @size: the size (in bytes) of the table 564 */ 565 static struct scatterlist *alloc_sgtable(ssize_t size) 566 { 567 struct scatterlist *result = NULL, *prev; 568 int nents, i, n_prev; 569 570 nents = DIV_ROUND_UP(size, PAGE_SIZE); 571 572 #define N_ENTRIES_PER_PAGE (PAGE_SIZE / sizeof(*result)) 573 /* 574 * We need an additional entry for table chaining, 575 * this ensures the loop can finish i.e. we can 576 * fit at least two entries per page (obviously, 577 * many more really fit.) 578 */ 579 BUILD_BUG_ON(N_ENTRIES_PER_PAGE < 2); 580 581 while (nents > 0) { 582 struct scatterlist *new, *iter; 583 int n_fill, n_alloc; 584 585 if (nents <= N_ENTRIES_PER_PAGE) { 586 /* last needed table */ 587 n_fill = nents; 588 n_alloc = nents; 589 nents = 0; 590 } else { 591 /* fill a page with entries */ 592 n_alloc = N_ENTRIES_PER_PAGE; 593 /* reserve one for chaining */ 594 n_fill = n_alloc - 1; 595 nents -= n_fill; 596 } 597 598 new = kcalloc(n_alloc, sizeof(*new), GFP_KERNEL); 599 if (!new) { 600 if (result) 601 _devcd_free_sgtable(result); 602 return NULL; 603 } 604 sg_init_table(new, n_alloc); 605 606 if (!result) 607 result = new; 608 else 609 sg_chain(prev, n_prev, new); 610 prev = new; 611 n_prev = n_alloc; 612 613 for_each_sg(new, iter, n_fill, i) { 614 struct page *new_page = alloc_page(GFP_KERNEL); 615 616 if (!new_page) { 617 _devcd_free_sgtable(result); 618 return NULL; 619 } 620 621 sg_set_page(iter, new_page, PAGE_SIZE, 0); 622 } 623 } 624 625 return result; 626 } 627 628 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 629 const struct iwl_prph_range *iwl_prph_dump_addr, 630 u32 range_len, void *ptr) 631 { 632 u32 *prph_len = (u32 *)ptr; 633 int i, num_bytes_in_chunk; 634 635 if (!prph_len) 636 return; 637 638 for (i = 0; i < range_len; i++) { 639 /* The range includes both boundaries */ 640 num_bytes_in_chunk = 641 iwl_prph_dump_addr[i].end - 642 iwl_prph_dump_addr[i].start + 4; 643 644 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 645 sizeof(struct iwl_fw_error_dump_prph) + 646 num_bytes_in_chunk; 647 } 648 } 649 650 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 651 void (*handler)(struct iwl_fw_runtime *, 652 const struct iwl_prph_range *, 653 u32, void *)) 654 { 655 u32 range_len; 656 657 if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 658 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 659 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 660 } else if (fwrt->trans->mac_cfg->device_family >= 661 IWL_DEVICE_FAMILY_22000) { 662 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 663 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 664 } else { 665 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 666 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 667 668 if (fwrt->trans->mac_cfg->mq_rx_supported) { 669 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 670 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 671 } 672 } 673 } 674 675 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 676 struct iwl_fw_error_dump_data **dump_data, 677 u32 len, u32 ofs, u32 type) 678 { 679 struct iwl_fw_error_dump_mem *dump_mem; 680 681 if (!len) 682 return; 683 684 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 685 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 686 dump_mem = (void *)(*dump_data)->data; 687 dump_mem->type = cpu_to_le32(type); 688 dump_mem->offset = cpu_to_le32(ofs); 689 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 690 *dump_data = iwl_fw_error_next_data(*dump_data); 691 692 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 693 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 694 dump_mem->data, len); 695 696 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 697 } 698 699 #define ADD_LEN(len, item_len, const_len) \ 700 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 701 while (0) 702 703 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 704 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 705 { 706 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 707 sizeof(struct iwl_fw_error_dump_fifo); 708 u32 fifo_len = 0; 709 int i; 710 711 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 712 return 0; 713 714 /* Count RXF2 size */ 715 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 716 717 /* Count RXF1 sizes */ 718 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 719 mem_cfg->num_lmacs = MAX_NUM_LMAC; 720 721 for (i = 0; i < mem_cfg->num_lmacs; i++) 722 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 723 724 return fifo_len; 725 } 726 727 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 728 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 729 { 730 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 731 sizeof(struct iwl_fw_error_dump_fifo); 732 u32 fifo_len = 0; 733 int i; 734 735 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 736 goto dump_internal_txf; 737 738 /* Count TXF sizes */ 739 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 740 mem_cfg->num_lmacs = MAX_NUM_LMAC; 741 742 for (i = 0; i < mem_cfg->num_lmacs; i++) { 743 int j; 744 745 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 746 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 747 hdr_len); 748 } 749 750 dump_internal_txf: 751 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 752 fw_has_capa(&fwrt->fw->ucode_capa, 753 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 754 goto out; 755 756 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 757 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 758 759 out: 760 return fifo_len; 761 } 762 763 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 764 struct iwl_fw_error_dump_data **data) 765 { 766 int i; 767 768 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 769 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 770 struct iwl_fw_error_dump_paging *paging; 771 struct page *pages = 772 fwrt->fw_paging_db[i].fw_paging_block; 773 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 774 775 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 776 (*data)->len = cpu_to_le32(sizeof(*paging) + 777 PAGING_BLOCK_SIZE); 778 paging = (void *)(*data)->data; 779 paging->index = cpu_to_le32(i); 780 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 781 PAGING_BLOCK_SIZE, 782 DMA_BIDIRECTIONAL); 783 memcpy(paging->data, page_address(pages), 784 PAGING_BLOCK_SIZE); 785 dma_sync_single_for_device(fwrt->trans->dev, addr, 786 PAGING_BLOCK_SIZE, 787 DMA_BIDIRECTIONAL); 788 (*data) = iwl_fw_error_next_data(*data); 789 790 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 791 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 792 fwrt->fw_paging_db[i].fw_offs, 793 paging->data, 794 PAGING_BLOCK_SIZE); 795 } 796 } 797 798 static struct iwl_fw_error_dump_file * 799 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 800 struct iwl_fw_dump_ptrs *fw_error_dump, 801 struct iwl_fwrt_dump_data *data) 802 { 803 struct iwl_fw_error_dump_file *dump_file; 804 struct iwl_fw_error_dump_data *dump_data; 805 struct iwl_fw_error_dump_info *dump_info; 806 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 807 struct iwl_fw_error_dump_trigger_desc *dump_trig; 808 u32 sram_len, sram_ofs; 809 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 810 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 811 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 812 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->mac_cfg->base->smem_len; 813 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 814 0 : fwrt->trans->cfg->dccm2_len; 815 int i; 816 817 /* SRAM - include stack CCM if driver knows the values for it */ 818 if (!fwrt->trans->cfg->dccm_offset || 819 !fwrt->trans->cfg->dccm_len) { 820 const struct fw_img *img; 821 822 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 823 return NULL; 824 img = &fwrt->fw->img[fwrt->cur_fw_img]; 825 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 826 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 827 } else { 828 sram_ofs = fwrt->trans->cfg->dccm_offset; 829 sram_len = fwrt->trans->cfg->dccm_len; 830 } 831 832 /* reading RXF/TXF sizes */ 833 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 834 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 835 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 836 837 /* Make room for PRPH registers */ 838 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 839 iwl_fw_prph_handler(fwrt, &prph_len, 840 iwl_fw_get_prph_len); 841 842 if (fwrt->trans->mac_cfg->device_family == 843 IWL_DEVICE_FAMILY_7000 && 844 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 845 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 846 } 847 848 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 849 850 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 851 file_len += sizeof(*dump_data) + sizeof(*dump_info); 852 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 853 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 854 855 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 856 size_t hdr_len = sizeof(*dump_data) + 857 sizeof(struct iwl_fw_error_dump_mem); 858 859 /* Dump SRAM only if no mem_tlvs */ 860 if (!fwrt->fw->dbg.n_mem_tlv) 861 ADD_LEN(file_len, sram_len, hdr_len); 862 863 /* Make room for all mem types that exist */ 864 ADD_LEN(file_len, smem_len, hdr_len); 865 ADD_LEN(file_len, sram2_len, hdr_len); 866 867 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 868 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 869 } 870 871 /* Make room for fw's virtual image pages, if it exists */ 872 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 873 file_len += fwrt->num_of_paging_blk * 874 (sizeof(*dump_data) + 875 sizeof(struct iwl_fw_error_dump_paging) + 876 PAGING_BLOCK_SIZE); 877 878 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 879 file_len += sizeof(*dump_data) + 880 fwrt->trans->mac_cfg->base->d3_debug_data_length * 2; 881 } 882 883 /* If we only want a monitor dump, reset the file length */ 884 if (data->monitor_only) { 885 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 886 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 887 } 888 889 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 890 data->desc) 891 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 892 data->desc->len; 893 894 dump_file = vzalloc(file_len); 895 if (!dump_file) 896 return NULL; 897 898 fw_error_dump->fwrt_ptr = dump_file; 899 900 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 901 dump_data = (void *)dump_file->data; 902 903 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 904 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 905 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 906 dump_info = (void *)dump_data->data; 907 dump_info->hw_type = 908 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->info.hw_rev)); 909 dump_info->hw_step = 910 cpu_to_le32(fwrt->trans->info.hw_rev_step); 911 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 912 sizeof(dump_info->fw_human_readable)); 913 strscpy_pad(dump_info->dev_human_readable, 914 fwrt->trans->info.name, 915 sizeof(dump_info->dev_human_readable)); 916 strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name, 917 sizeof(dump_info->bus_human_readable)); 918 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 919 dump_info->lmac_err_id[0] = 920 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 921 if (fwrt->smem_cfg.num_lmacs > 1) 922 dump_info->lmac_err_id[1] = 923 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 924 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 925 926 dump_data = iwl_fw_error_next_data(dump_data); 927 } 928 929 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 930 /* Dump shared memory configuration */ 931 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 932 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 933 dump_smem_cfg = (void *)dump_data->data; 934 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 935 dump_smem_cfg->num_txfifo_entries = 936 cpu_to_le32(mem_cfg->num_txfifo_entries); 937 for (i = 0; i < MAX_NUM_LMAC; i++) { 938 int j; 939 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 940 941 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 942 dump_smem_cfg->lmac[i].txfifo_size[j] = 943 cpu_to_le32(txf_size[j]); 944 dump_smem_cfg->lmac[i].rxfifo1_size = 945 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 946 } 947 dump_smem_cfg->rxfifo2_size = 948 cpu_to_le32(mem_cfg->rxfifo2_size); 949 dump_smem_cfg->internal_txfifo_addr = 950 cpu_to_le32(mem_cfg->internal_txfifo_addr); 951 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 952 dump_smem_cfg->internal_txfifo_size[i] = 953 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 954 } 955 956 dump_data = iwl_fw_error_next_data(dump_data); 957 } 958 959 /* We only dump the FIFOs if the FW is in error state */ 960 if (fifo_len) { 961 iwl_fw_dump_rxf(fwrt, &dump_data); 962 iwl_fw_dump_txf(fwrt, &dump_data); 963 } 964 965 if (radio_len) 966 iwl_read_radio_regs(fwrt, &dump_data); 967 968 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 969 data->desc) { 970 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 971 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 972 data->desc->len); 973 dump_trig = (void *)dump_data->data; 974 memcpy(dump_trig, &data->desc->trig_desc, 975 sizeof(*dump_trig) + data->desc->len); 976 977 dump_data = iwl_fw_error_next_data(dump_data); 978 } 979 980 /* In case we only want monitor dump, skip to dump trasport data */ 981 if (data->monitor_only) 982 goto out; 983 984 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 985 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 986 fwrt->fw->dbg.mem_tlv; 987 988 if (!fwrt->fw->dbg.n_mem_tlv) 989 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 990 IWL_FW_ERROR_DUMP_MEM_SRAM); 991 992 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 993 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 994 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 995 996 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 997 le32_to_cpu(fw_dbg_mem[i].data_type)); 998 } 999 1000 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1001 fwrt->trans->mac_cfg->base->smem_offset, 1002 IWL_FW_ERROR_DUMP_MEM_SMEM); 1003 1004 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1005 fwrt->trans->cfg->dccm2_offset, 1006 IWL_FW_ERROR_DUMP_MEM_SRAM); 1007 } 1008 1009 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1010 u32 addr = fwrt->trans->mac_cfg->base->d3_debug_data_base_addr; 1011 size_t data_size = fwrt->trans->mac_cfg->base->d3_debug_data_length; 1012 1013 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1014 dump_data->len = cpu_to_le32(data_size * 2); 1015 1016 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1017 1018 kfree(fwrt->dump.d3_debug_data); 1019 fwrt->dump.d3_debug_data = NULL; 1020 1021 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1022 dump_data->data + data_size, 1023 data_size); 1024 1025 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 1026 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 1027 dump_data->data + data_size, 1028 data_size); 1029 1030 dump_data = iwl_fw_error_next_data(dump_data); 1031 } 1032 1033 /* Dump fw's virtual image */ 1034 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1035 iwl_dump_paging(fwrt, &dump_data); 1036 1037 if (prph_len) 1038 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1039 1040 out: 1041 dump_file->file_len = cpu_to_le32(file_len); 1042 return dump_file; 1043 } 1044 1045 /** 1046 * struct iwl_dump_ini_region_data - region data 1047 * @reg_tlv: region TLV 1048 * @dump_data: dump data 1049 */ 1050 struct iwl_dump_ini_region_data { 1051 struct iwl_ucode_tlv *reg_tlv; 1052 struct iwl_fwrt_dump_data *dump_data; 1053 }; 1054 1055 static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt, 1056 void *range_ptr, u32 addr, 1057 __le32 size) 1058 { 1059 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1060 __le32 *val = range->data; 1061 int i; 1062 1063 range->internal_base_addr = cpu_to_le32(addr); 1064 range->range_data_size = size; 1065 for (i = 0; i < le32_to_cpu(size); i += 4) 1066 *val++ = cpu_to_le32(iwl_read_prph(fwrt->trans, addr + i)); 1067 1068 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1069 } 1070 1071 static int 1072 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1073 struct iwl_dump_ini_region_data *reg_data, 1074 void *range_ptr, u32 range_len, int idx) 1075 { 1076 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1077 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1078 le32_to_cpu(reg->dev_addr.offset); 1079 1080 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1081 reg->dev_addr.size); 1082 } 1083 1084 static int 1085 iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime *fwrt, 1086 struct iwl_dump_ini_region_data *reg_data, 1087 void *range_ptr, u32 range_len, int idx) 1088 { 1089 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1090 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1091 u32 addr = le32_to_cpu(reg->dev_addr_range.offset) + 1092 le32_to_cpu(pairs[idx].addr); 1093 1094 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1095 pairs[idx].size); 1096 } 1097 1098 static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt, 1099 void *range_ptr, u32 addr, 1100 __le32 size, __le32 offset) 1101 { 1102 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1103 __le32 *val = range->data; 1104 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1105 u32 indirect_rd_addr = WMAL_MRSPF_1; 1106 u32 prph_val; 1107 u32 dphy_state; 1108 u32 dphy_addr; 1109 int i; 1110 1111 range->internal_base_addr = cpu_to_le32(addr); 1112 range->range_data_size = size; 1113 1114 if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1115 indirect_wr_addr = WMAL_INDRCT_CMD1; 1116 1117 indirect_wr_addr += le32_to_cpu(offset); 1118 indirect_rd_addr += le32_to_cpu(offset); 1119 1120 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1121 return -EBUSY; 1122 1123 dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1124 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1125 1126 for (i = 0; i < le32_to_cpu(size); i += 4) { 1127 if (dphy_state == HBUS_TIMEOUT || 1128 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1129 WFPM_PHYRF_STATE_ON) { 1130 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1131 continue; 1132 } 1133 1134 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1135 WMAL_INDRCT_CMD(addr + i)); 1136 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1137 indirect_rd_addr); 1138 *val++ = cpu_to_le32(prph_val); 1139 } 1140 1141 iwl_trans_release_nic_access(fwrt->trans); 1142 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1143 } 1144 1145 static int 1146 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1147 struct iwl_dump_ini_region_data *reg_data, 1148 void *range_ptr, u32 range_len, int idx) 1149 { 1150 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1151 u32 addr = le32_to_cpu(reg->addrs[idx]); 1152 1153 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1154 reg->dev_addr.size, 1155 reg->dev_addr.offset); 1156 } 1157 1158 static int 1159 iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime *fwrt, 1160 struct iwl_dump_ini_region_data *reg_data, 1161 void *range_ptr, u32 range_len, int idx) 1162 { 1163 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1164 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1165 u32 addr = le32_to_cpu(pairs[idx].addr); 1166 1167 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1168 pairs[idx].size, 1169 reg->dev_addr_range.offset); 1170 } 1171 1172 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1173 struct iwl_dump_ini_region_data *reg_data, 1174 void *range_ptr, u32 range_len, int idx) 1175 { 1176 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1177 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1178 __le32 *val = range->data; 1179 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1180 le32_to_cpu(reg->dev_addr.offset); 1181 int i; 1182 1183 range->internal_base_addr = cpu_to_le32(addr); 1184 range->range_data_size = reg->dev_addr.size; 1185 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1186 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1187 1188 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1189 } 1190 1191 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1192 struct iwl_dump_ini_region_data *reg_data, 1193 void *range_ptr, u32 range_len, int idx) 1194 { 1195 struct iwl_trans *trans = fwrt->trans; 1196 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1197 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1198 __le32 *val = range->data; 1199 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1200 le32_to_cpu(reg->dev_addr.offset); 1201 int i; 1202 1203 range->internal_base_addr = cpu_to_le32(addr); 1204 range->range_data_size = reg->dev_addr.size; 1205 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1206 int ret; 1207 u32 tmp; 1208 1209 ret = iwl_trans_read_config32(trans, addr + i, &tmp); 1210 if (ret < 0) 1211 return ret; 1212 1213 *val++ = cpu_to_le32(tmp); 1214 } 1215 1216 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1217 } 1218 1219 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1220 struct iwl_dump_ini_region_data *reg_data, 1221 void *range_ptr, u32 range_len, int idx) 1222 { 1223 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1224 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1225 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1226 le32_to_cpu(reg->dev_addr.offset); 1227 1228 range->internal_base_addr = cpu_to_le32(addr); 1229 range->range_data_size = reg->dev_addr.size; 1230 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1231 le32_to_cpu(reg->dev_addr.size)); 1232 1233 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1234 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1235 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1236 range->data, 1237 le32_to_cpu(reg->dev_addr.size)); 1238 1239 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1240 } 1241 1242 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1243 void *range_ptr, u32 range_len, int idx) 1244 { 1245 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1246 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1247 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1248 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1249 1250 range->page_num = cpu_to_le32(idx); 1251 range->range_data_size = cpu_to_le32(page_size); 1252 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1253 DMA_BIDIRECTIONAL); 1254 memcpy(range->data, page_address(page), page_size); 1255 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1256 DMA_BIDIRECTIONAL); 1257 1258 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1259 } 1260 1261 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1262 struct iwl_dump_ini_region_data *reg_data, 1263 void *range_ptr, u32 range_len, int idx) 1264 { 1265 struct iwl_fw_ini_error_dump_range *range; 1266 u32 page_size; 1267 1268 /* all paged index start from 1 to skip CSS section */ 1269 idx++; 1270 1271 if (!fwrt->trans->mac_cfg->gen2) 1272 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1273 1274 range = range_ptr; 1275 page_size = fwrt->trans->init_dram.paging[idx].size; 1276 1277 range->page_num = cpu_to_le32(idx); 1278 range->range_data_size = cpu_to_le32(page_size); 1279 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1280 page_size); 1281 1282 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1283 } 1284 1285 static int 1286 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1287 struct iwl_dump_ini_region_data *reg_data, 1288 void *range_ptr, u32 range_len, int idx) 1289 { 1290 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1291 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1292 struct iwl_dram_data *frag; 1293 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1294 1295 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1296 1297 range->dram_base_addr = cpu_to_le64(frag->physical); 1298 range->range_data_size = cpu_to_le32(frag->size); 1299 1300 memcpy(range->data, frag->block, frag->size); 1301 1302 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1303 } 1304 1305 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1306 struct iwl_dump_ini_region_data *reg_data, 1307 void *range_ptr, u32 range_len, int idx) 1308 { 1309 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1310 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1311 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1312 1313 range->internal_base_addr = cpu_to_le32(addr); 1314 range->range_data_size = reg->internal_buffer.size; 1315 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1316 le32_to_cpu(reg->internal_buffer.size)); 1317 1318 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1319 } 1320 1321 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1322 struct iwl_dump_ini_region_data *reg_data, int idx) 1323 { 1324 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1325 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1326 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1327 int txf_num = cfg->num_txfifo_entries; 1328 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1329 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1330 1331 if (!idx) { 1332 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1333 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1334 le32_to_cpu(reg->fifos.offset)); 1335 return false; 1336 } 1337 1338 iter->internal_txf = 0; 1339 iter->fifo_size = 0; 1340 iter->fifo = -1; 1341 if (le32_to_cpu(reg->fifos.offset)) 1342 iter->lmac = 1; 1343 else 1344 iter->lmac = 0; 1345 } 1346 1347 if (!iter->internal_txf) { 1348 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1349 iter->fifo_size = 1350 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1351 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1352 return true; 1353 } 1354 iter->fifo--; 1355 } 1356 1357 iter->internal_txf = 1; 1358 1359 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1360 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1361 return false; 1362 1363 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1364 iter->fifo_size = 1365 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1366 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1367 return true; 1368 } 1369 1370 return false; 1371 } 1372 1373 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1374 struct iwl_dump_ini_region_data *reg_data, 1375 void *range_ptr, u32 range_len, int idx) 1376 { 1377 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1378 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1379 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1380 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1381 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1382 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1383 u32 registers_size = registers_num * sizeof(*reg_dump); 1384 __le32 *data; 1385 int i; 1386 1387 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1388 return -EIO; 1389 1390 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1391 return -EBUSY; 1392 1393 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1394 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1395 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1396 1397 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1398 1399 /* 1400 * read txf registers. for each register, write to the dump the 1401 * register address and its value 1402 */ 1403 for (i = 0; i < registers_num; i++) { 1404 addr = le32_to_cpu(reg->addrs[i]) + offs; 1405 1406 reg_dump->addr = cpu_to_le32(addr); 1407 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1408 addr)); 1409 1410 reg_dump++; 1411 } 1412 1413 if (reg->fifos.hdr_only) { 1414 range->range_data_size = cpu_to_le32(registers_size); 1415 goto out; 1416 } 1417 1418 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1419 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1420 TXF_WR_PTR + offs); 1421 1422 /* Dummy-read to advance the read pointer to the head */ 1423 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1424 1425 /* Read FIFO */ 1426 addr = TXF_READ_MODIFY_DATA + offs; 1427 data = (void *)reg_dump; 1428 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1429 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1430 1431 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1432 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1433 reg_dump, iter->fifo_size); 1434 1435 out: 1436 iwl_trans_release_nic_access(fwrt->trans); 1437 1438 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1439 } 1440 1441 static int 1442 iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt, 1443 struct iwl_dump_ini_region_data *reg_data, 1444 void *range_ptr, u32 range_len, int idx) 1445 { 1446 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1447 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1448 __le32 *val = range->data; 1449 __le32 offset = reg->dev_addr.offset; 1450 u32 indirect_rd_wr_addr = DPHYIP_INDIRECT; 1451 u32 addr = le32_to_cpu(reg->addrs[idx]); 1452 u32 dphy_state, dphy_addr, prph_val; 1453 int i; 1454 1455 range->internal_base_addr = cpu_to_le32(addr); 1456 range->range_data_size = reg->dev_addr.size; 1457 1458 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1459 return -EBUSY; 1460 1461 indirect_rd_wr_addr += le32_to_cpu(offset); 1462 1463 dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1464 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1465 1466 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1467 if (dphy_state == HBUS_TIMEOUT || 1468 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1469 WFPM_PHYRF_STATE_ON) { 1470 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1471 continue; 1472 } 1473 1474 iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr, 1475 addr + i); 1476 /* wait a bit for value to be ready in register */ 1477 udelay(1); 1478 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1479 indirect_rd_wr_addr); 1480 *val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >> 1481 DPHYIP_INDIRECT_RD_SHIFT); 1482 } 1483 1484 iwl_trans_release_nic_access(fwrt->trans); 1485 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1486 } 1487 1488 struct iwl_ini_rxf_data { 1489 u32 fifo_num; 1490 u32 size; 1491 u32 offset; 1492 }; 1493 1494 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1495 struct iwl_dump_ini_region_data *reg_data, 1496 struct iwl_ini_rxf_data *data) 1497 { 1498 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1499 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1500 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1501 u8 fifo_idx; 1502 1503 if (!data) 1504 return; 1505 1506 memset(data, 0, sizeof(*data)); 1507 1508 /* make sure only one bit is set in only one fid */ 1509 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1510 "fid1=%x, fid2=%x\n", fid1, fid2)) 1511 return; 1512 1513 if (fid1) { 1514 fifo_idx = ffs(fid1) - 1; 1515 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1516 fifo_idx)) 1517 return; 1518 1519 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1520 data->fifo_num = fifo_idx; 1521 } else { 1522 u8 max_idx; 1523 1524 fifo_idx = ffs(fid2) - 1; 1525 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1526 SHARED_MEM_CFG_CMD, 0) <= 3) 1527 max_idx = 0; 1528 else 1529 max_idx = 1; 1530 1531 if (WARN_ONCE(fifo_idx > max_idx, 1532 "invalid umac fifo idx %d", fifo_idx)) 1533 return; 1534 1535 /* use bit 31 to distinguish between umac and lmac rxf while 1536 * parsing the dump 1537 */ 1538 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1539 1540 switch (fifo_idx) { 1541 case 0: 1542 data->size = fwrt->smem_cfg.rxfifo2_size; 1543 data->offset = iwl_umac_prph(fwrt->trans, 1544 RXF_DIFF_FROM_PREV); 1545 break; 1546 case 1: 1547 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1548 data->offset = iwl_umac_prph(fwrt->trans, 1549 RXF2C_DIFF_FROM_PREV); 1550 break; 1551 } 1552 } 1553 } 1554 1555 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1556 struct iwl_dump_ini_region_data *reg_data, 1557 void *range_ptr, u32 range_len, int idx) 1558 { 1559 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1560 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1561 struct iwl_ini_rxf_data rxf_data; 1562 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1563 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1564 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1565 u32 registers_size = registers_num * sizeof(*reg_dump); 1566 __le32 *data; 1567 int i; 1568 1569 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1570 if (!rxf_data.size) 1571 return -EIO; 1572 1573 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1574 return -EBUSY; 1575 1576 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1577 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1578 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1579 1580 /* 1581 * read rxf registers. for each register, write to the dump the 1582 * register address and its value 1583 */ 1584 for (i = 0; i < registers_num; i++) { 1585 addr = le32_to_cpu(reg->addrs[i]) + offs; 1586 1587 reg_dump->addr = cpu_to_le32(addr); 1588 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1589 addr)); 1590 1591 reg_dump++; 1592 } 1593 1594 if (reg->fifos.hdr_only) { 1595 range->range_data_size = cpu_to_le32(registers_size); 1596 goto out; 1597 } 1598 1599 offs = rxf_data.offset; 1600 1601 /* Lock fence */ 1602 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1603 /* Set fence pointer to the same place like WR pointer */ 1604 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1605 /* Set fence offset */ 1606 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1607 0x0); 1608 1609 /* Read FIFO */ 1610 addr = RXF_FIFO_RD_FENCE_INC + offs; 1611 data = (void *)reg_dump; 1612 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1613 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1614 1615 out: 1616 iwl_trans_release_nic_access(fwrt->trans); 1617 1618 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1619 } 1620 1621 static int 1622 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1623 struct iwl_dump_ini_region_data *reg_data, 1624 void *range_ptr, u32 range_len, int idx) 1625 { 1626 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1627 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1628 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1629 u32 addr = le32_to_cpu(err_table->base_addr) + 1630 le32_to_cpu(err_table->offset); 1631 1632 range->internal_base_addr = cpu_to_le32(addr); 1633 range->range_data_size = err_table->size; 1634 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1635 le32_to_cpu(err_table->size)); 1636 1637 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1638 } 1639 1640 static int 1641 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1642 struct iwl_dump_ini_region_data *reg_data, 1643 void *range_ptr, u32 range_len, int idx) 1644 { 1645 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1646 struct iwl_fw_ini_region_special_device_memory *special_mem = 1647 ®->special_mem; 1648 1649 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1650 u32 addr = le32_to_cpu(special_mem->base_addr) + 1651 le32_to_cpu(special_mem->offset); 1652 1653 range->internal_base_addr = cpu_to_le32(addr); 1654 range->range_data_size = special_mem->size; 1655 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1656 le32_to_cpu(special_mem->size)); 1657 1658 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1659 } 1660 1661 static int 1662 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1663 struct iwl_dump_ini_region_data *reg_data, 1664 void *range_ptr, u32 range_len, int idx) 1665 { 1666 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1667 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1668 __le32 *val = range->data; 1669 u32 prph_data; 1670 int i; 1671 1672 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1673 return -EBUSY; 1674 1675 range->range_data_size = reg->dev_addr.size; 1676 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1677 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1678 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1679 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1680 if (iwl_trans_is_hw_error_value(prph_data)) { 1681 iwl_trans_release_nic_access(fwrt->trans); 1682 return -EBUSY; 1683 } 1684 *val++ = cpu_to_le32(prph_data); 1685 } 1686 iwl_trans_release_nic_access(fwrt->trans); 1687 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1688 } 1689 1690 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1691 struct iwl_dump_ini_region_data *reg_data, 1692 void *range_ptr, u32 range_len, int idx) 1693 { 1694 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1695 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1696 u32 pkt_len; 1697 1698 if (!pkt) 1699 return -EIO; 1700 1701 pkt_len = iwl_rx_packet_payload_len(pkt); 1702 1703 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1704 range->range_data_size = cpu_to_le32(pkt_len); 1705 1706 memcpy(range->data, pkt->data, pkt_len); 1707 1708 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1709 } 1710 1711 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1712 struct iwl_dump_ini_region_data *reg_data, 1713 void *range_ptr, u32 range_len, int idx) 1714 { 1715 /* read the IMR memory and DMA it to SRAM */ 1716 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1717 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1718 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1719 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1720 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1721 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1722 1723 range->range_data_size = cpu_to_le32(size_to_dump); 1724 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1725 imr_curr_addr, size_to_dump)) { 1726 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1727 return -1; 1728 } 1729 1730 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1731 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1732 1733 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1734 size_to_dump); 1735 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1736 } 1737 1738 static void * 1739 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1740 struct iwl_dump_ini_region_data *reg_data, 1741 void *data, u32 data_len) 1742 { 1743 struct iwl_fw_ini_error_dump *dump = data; 1744 1745 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1746 1747 return dump->data; 1748 } 1749 1750 /** 1751 * mask_apply_and_normalize - applies mask on val and normalize the result 1752 * 1753 * @val: value 1754 * @mask: mask to apply and to normalize with 1755 * 1756 * The normalization is based on the first set bit in the mask 1757 * 1758 * Returns: the extracted value 1759 */ 1760 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1761 { 1762 return (val & mask) >> (ffs(mask) - 1); 1763 } 1764 1765 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1766 const struct iwl_fw_mon_reg *reg_info) 1767 { 1768 u32 val, offs; 1769 1770 /* The header addresses of DBGCi is calculate as follows: 1771 * DBGC1 address + (0x100 * i) 1772 */ 1773 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1774 1775 if (!reg_info || !reg_info->addr || !reg_info->mask) 1776 return 0; 1777 1778 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1779 1780 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1781 } 1782 1783 static void * 1784 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1785 struct iwl_fw_ini_monitor_dump *data, 1786 const struct iwl_fw_mon_regs *addrs) 1787 { 1788 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1789 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1790 return NULL; 1791 } 1792 1793 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1794 &addrs->write_ptr); 1795 if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1796 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1797 1798 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1799 } 1800 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1801 &addrs->cycle_cnt); 1802 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1803 &addrs->cur_frag); 1804 1805 iwl_trans_release_nic_access(fwrt->trans); 1806 1807 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1808 1809 return data->data; 1810 } 1811 1812 static void * 1813 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1814 struct iwl_dump_ini_region_data *reg_data, 1815 void *data, u32 data_len) 1816 { 1817 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1818 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1819 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1820 1821 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1822 &fwrt->trans->mac_cfg->base->mon_dram_regs); 1823 } 1824 1825 static void * 1826 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1827 struct iwl_dump_ini_region_data *reg_data, 1828 void *data, u32 data_len) 1829 { 1830 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1831 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1832 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1833 1834 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1835 &fwrt->trans->mac_cfg->base->mon_smem_regs); 1836 } 1837 1838 static void * 1839 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1840 struct iwl_dump_ini_region_data *reg_data, 1841 void *data, u32 data_len) 1842 { 1843 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1844 1845 return iwl_dump_ini_mon_fill_header(fwrt, 1846 /* no offset calculation later */ 1847 IWL_FW_INI_ALLOCATION_ID_DBGC1, 1848 mon_dump, 1849 &fwrt->trans->mac_cfg->base->mon_dbgi_regs); 1850 } 1851 1852 static void * 1853 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1854 struct iwl_dump_ini_region_data *reg_data, 1855 void *data, u32 data_len) 1856 { 1857 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1858 struct iwl_fw_ini_err_table_dump *dump = data; 1859 1860 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1861 dump->version = reg->err_table.version; 1862 1863 return dump->data; 1864 } 1865 1866 static void * 1867 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1868 struct iwl_dump_ini_region_data *reg_data, 1869 void *data, u32 data_len) 1870 { 1871 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1872 struct iwl_fw_ini_special_device_memory *dump = data; 1873 1874 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1875 dump->type = reg->special_mem.type; 1876 dump->version = reg->special_mem.version; 1877 1878 return dump->data; 1879 } 1880 1881 static void * 1882 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1883 struct iwl_dump_ini_region_data *reg_data, 1884 void *data, u32 data_len) 1885 { 1886 struct iwl_fw_ini_error_dump *dump = data; 1887 1888 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1889 1890 return dump->data; 1891 } 1892 1893 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1894 struct iwl_dump_ini_region_data *reg_data) 1895 { 1896 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1897 1898 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1899 } 1900 1901 static u32 1902 iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime *fwrt, 1903 struct iwl_dump_ini_region_data *reg_data) 1904 { 1905 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1906 size_t size = sizeof(struct iwl_fw_ini_addr_size); 1907 1908 return iwl_tlv_array_len_with_size(reg_data->reg_tlv, reg, size); 1909 } 1910 1911 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1912 struct iwl_dump_ini_region_data *reg_data) 1913 { 1914 if (fwrt->trans->mac_cfg->gen2) { 1915 if (fwrt->trans->init_dram.paging_cnt) 1916 return fwrt->trans->init_dram.paging_cnt - 1; 1917 else 1918 return 0; 1919 } 1920 1921 return fwrt->num_of_paging_blk; 1922 } 1923 1924 static u32 1925 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1926 struct iwl_dump_ini_region_data *reg_data) 1927 { 1928 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1929 struct iwl_fw_mon *fw_mon; 1930 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1931 int i; 1932 1933 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1934 1935 for (i = 0; i < fw_mon->num_frags; i++) { 1936 if (!fw_mon->frags[i].size) 1937 break; 1938 1939 ranges++; 1940 } 1941 1942 return ranges; 1943 } 1944 1945 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1946 struct iwl_dump_ini_region_data *reg_data) 1947 { 1948 u32 num_of_fifos = 0; 1949 1950 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1951 num_of_fifos++; 1952 1953 return num_of_fifos; 1954 } 1955 1956 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1957 struct iwl_dump_ini_region_data *reg_data) 1958 { 1959 return 1; 1960 } 1961 1962 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1963 struct iwl_dump_ini_region_data *reg_data) 1964 { 1965 /* range is total number of pages need to copied from 1966 *IMR memory to SRAM and later from SRAM to DRAM 1967 */ 1968 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1969 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1970 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1971 1972 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1973 IWL_DEBUG_INFO(fwrt, 1974 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1975 imr_enable, imr_size, sram_size); 1976 return 0; 1977 } 1978 1979 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1980 } 1981 1982 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1983 struct iwl_dump_ini_region_data *reg_data) 1984 { 1985 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1986 u32 size = le32_to_cpu(reg->dev_addr.size); 1987 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1988 1989 if (!size || !ranges) 1990 return 0; 1991 1992 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1993 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1994 } 1995 1996 static u32 1997 iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime *fwrt, 1998 struct iwl_dump_ini_region_data *reg_data) 1999 { 2000 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2001 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 2002 u32 ranges = iwl_dump_ini_mem_block_ranges(fwrt, reg_data); 2003 u32 size = sizeof(struct iwl_fw_ini_error_dump); 2004 int range; 2005 2006 if (!ranges) 2007 return 0; 2008 2009 for (range = 0; range < ranges; range++) 2010 size += le32_to_cpu(pairs[range].size); 2011 2012 return size + ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2013 } 2014 2015 static u32 2016 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 2017 struct iwl_dump_ini_region_data *reg_data) 2018 { 2019 int i; 2020 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 2021 u32 size = sizeof(struct iwl_fw_ini_error_dump); 2022 2023 /* start from 1 to skip CSS section */ 2024 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 2025 size += range_header_len; 2026 if (fwrt->trans->mac_cfg->gen2) 2027 size += fwrt->trans->init_dram.paging[i].size; 2028 else 2029 size += fwrt->fw_paging_db[i].fw_paging_size; 2030 } 2031 2032 return size; 2033 } 2034 2035 static u32 2036 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 2037 struct iwl_dump_ini_region_data *reg_data) 2038 { 2039 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2040 struct iwl_fw_mon *fw_mon; 2041 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 2042 int i; 2043 2044 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 2045 2046 for (i = 0; i < fw_mon->num_frags; i++) { 2047 struct iwl_dram_data *frag = &fw_mon->frags[i]; 2048 2049 if (!frag->size) 2050 break; 2051 2052 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 2053 } 2054 2055 if (size) 2056 size += sizeof(struct iwl_fw_ini_monitor_dump); 2057 2058 return size; 2059 } 2060 2061 static u32 2062 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 2063 struct iwl_dump_ini_region_data *reg_data) 2064 { 2065 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2066 u32 size; 2067 2068 size = le32_to_cpu(reg->internal_buffer.size); 2069 if (!size) 2070 return 0; 2071 2072 size += sizeof(struct iwl_fw_ini_monitor_dump) + 2073 sizeof(struct iwl_fw_ini_error_dump_range); 2074 2075 return size; 2076 } 2077 2078 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 2079 struct iwl_dump_ini_region_data *reg_data) 2080 { 2081 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2082 u32 size = le32_to_cpu(reg->dev_addr.size); 2083 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 2084 2085 if (!size || !ranges) 2086 return 0; 2087 2088 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 2089 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 2090 } 2091 2092 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 2093 struct iwl_dump_ini_region_data *reg_data) 2094 { 2095 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2096 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 2097 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2098 u32 size = 0; 2099 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 2100 registers_num * 2101 sizeof(struct iwl_fw_ini_error_dump_register); 2102 2103 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 2104 size += fifo_hdr; 2105 if (!reg->fifos.hdr_only) 2106 size += iter->fifo_size; 2107 } 2108 2109 if (!size) 2110 return 0; 2111 2112 return size + sizeof(struct iwl_fw_ini_error_dump); 2113 } 2114 2115 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 2116 struct iwl_dump_ini_region_data *reg_data) 2117 { 2118 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2119 struct iwl_ini_rxf_data rx_data; 2120 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2121 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 2122 sizeof(struct iwl_fw_ini_error_dump_range) + 2123 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 2124 2125 if (reg->fifos.hdr_only) 2126 return size; 2127 2128 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 2129 size += rx_data.size; 2130 2131 return size; 2132 } 2133 2134 static u32 2135 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 2136 struct iwl_dump_ini_region_data *reg_data) 2137 { 2138 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2139 u32 size = le32_to_cpu(reg->err_table.size); 2140 2141 if (size) 2142 size += sizeof(struct iwl_fw_ini_err_table_dump) + 2143 sizeof(struct iwl_fw_ini_error_dump_range); 2144 2145 return size; 2146 } 2147 2148 static u32 2149 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2150 struct iwl_dump_ini_region_data *reg_data) 2151 { 2152 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2153 u32 size = le32_to_cpu(reg->special_mem.size); 2154 2155 if (size) 2156 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2157 sizeof(struct iwl_fw_ini_error_dump_range); 2158 2159 return size; 2160 } 2161 2162 static u32 2163 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2164 struct iwl_dump_ini_region_data *reg_data) 2165 { 2166 u32 size = 0; 2167 2168 if (!reg_data->dump_data->fw_pkt) 2169 return 0; 2170 2171 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2172 if (size) 2173 size += sizeof(struct iwl_fw_ini_error_dump) + 2174 sizeof(struct iwl_fw_ini_error_dump_range); 2175 2176 return size; 2177 } 2178 2179 static u32 2180 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2181 struct iwl_dump_ini_region_data *reg_data) 2182 { 2183 u32 ranges = 0; 2184 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2185 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2186 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2187 2188 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2189 IWL_DEBUG_INFO(fwrt, 2190 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2191 imr_enable, imr_size, sram_size); 2192 return 0; 2193 } 2194 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2195 if (!ranges) { 2196 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges); 2197 return 0; 2198 } 2199 imr_size += sizeof(struct iwl_fw_ini_error_dump) + 2200 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2201 return imr_size; 2202 } 2203 2204 /** 2205 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2206 * @get_num_of_ranges: returns the number of memory ranges in the region. 2207 * @get_size: returns the total size of the region. 2208 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2209 * the first range or NULL if failed to fill headers. 2210 * @fill_range: copies a given memory range into the dump. 2211 * Returns the size of the range or negative error value otherwise. 2212 */ 2213 struct iwl_dump_ini_mem_ops { 2214 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2215 struct iwl_dump_ini_region_data *reg_data); 2216 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2217 struct iwl_dump_ini_region_data *reg_data); 2218 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2219 struct iwl_dump_ini_region_data *reg_data, 2220 void *data, u32 data_len); 2221 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2222 struct iwl_dump_ini_region_data *reg_data, 2223 void *range, u32 range_len, int idx); 2224 }; 2225 2226 /** 2227 * iwl_dump_ini_mem - dump memory region 2228 * 2229 * @fwrt: fw runtime struct 2230 * @list: list to add the dump tlv to 2231 * @reg_data: memory region 2232 * @ops: memory dump operations 2233 * 2234 * Creates a dump tlv and copy a memory region into it. 2235 * 2236 * Returns: the size of the current dump tlv or 0 if failed 2237 */ 2238 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2239 struct iwl_dump_ini_region_data *reg_data, 2240 const struct iwl_dump_ini_mem_ops *ops) 2241 { 2242 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2243 struct iwl_fw_ini_dump_entry *entry; 2244 struct iwl_fw_ini_error_dump_data *tlv; 2245 struct iwl_fw_ini_error_dump_header *header; 2246 u32 type = reg->type; 2247 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK); 2248 u32 num_of_ranges, i, size; 2249 u8 *range; 2250 u32 free_size; 2251 u64 header_size; 2252 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE; 2253 2254 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n", 2255 dump_policy, id, type); 2256 2257 if (le32_to_cpu(reg->hdr.version) >= 2) { 2258 u32 dp = le32_get_bits(reg->id, 2259 IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2260 2261 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE && 2262 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) { 2263 IWL_DEBUG_FW(fwrt, 2264 "WRT: no dump - type %d and policy mismatch=%d\n", 2265 dump_policy, dp); 2266 return 0; 2267 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM && 2268 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) { 2269 IWL_DEBUG_FW(fwrt, 2270 "WRT: no dump - type %d and policy mismatch=%d\n", 2271 dump_policy, dp); 2272 return 0; 2273 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF && 2274 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) { 2275 IWL_DEBUG_FW(fwrt, 2276 "WRT: no dump - type %d and policy mismatch=%d\n", 2277 dump_policy, dp); 2278 return 0; 2279 } 2280 } 2281 2282 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2283 !ops->fill_range) { 2284 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2285 return 0; 2286 } 2287 2288 size = ops->get_size(fwrt, reg_data); 2289 2290 if (size < sizeof(*header)) { 2291 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2292 return 0; 2293 } 2294 2295 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2296 if (!entry) 2297 return 0; 2298 2299 entry->size = sizeof(*tlv) + size; 2300 2301 tlv = (void *)entry->data; 2302 tlv->type = reg->type; 2303 tlv->sub_type = reg->sub_type; 2304 tlv->sub_type_ver = reg->sub_type_ver; 2305 tlv->reserved = reg->reserved; 2306 tlv->len = cpu_to_le32(size); 2307 2308 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2309 2310 header = (void *)tlv->data; 2311 header->region_id = cpu_to_le32(id); 2312 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2313 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2314 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2315 2316 free_size = size; 2317 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2318 if (!range) { 2319 IWL_ERR(fwrt, 2320 "WRT: Failed to fill region header: id=%d, type=%d\n", 2321 id, type); 2322 goto out_err; 2323 } 2324 2325 header_size = range - (u8 *)header; 2326 2327 if (WARN(header_size > free_size, 2328 "header size %llu > free_size %d", 2329 header_size, free_size)) { 2330 IWL_ERR(fwrt, 2331 "WRT: fill_mem_hdr used more than given free_size\n"); 2332 goto out_err; 2333 } 2334 2335 free_size -= header_size; 2336 2337 for (i = 0; i < num_of_ranges; i++) { 2338 int range_size = ops->fill_range(fwrt, reg_data, range, 2339 free_size, i); 2340 2341 if (range_size < 0) { 2342 IWL_ERR(fwrt, 2343 "WRT: Failed to dump region: id=%d, type=%d\n", 2344 id, type); 2345 goto out_err; 2346 } 2347 2348 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2349 range_size, free_size)) { 2350 IWL_ERR(fwrt, 2351 "WRT: fill_raged used more than given free_size\n"); 2352 goto out_err; 2353 } 2354 2355 free_size -= range_size; 2356 range = range + range_size; 2357 } 2358 2359 list_add_tail(&entry->list, list); 2360 2361 return entry->size; 2362 2363 out_err: 2364 vfree(entry); 2365 2366 return 0; 2367 } 2368 2369 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2370 struct iwl_fw_ini_trigger_tlv *trigger, 2371 struct list_head *list) 2372 { 2373 struct iwl_fw_ini_dump_entry *entry; 2374 struct iwl_fw_error_dump_data *tlv; 2375 struct iwl_fw_ini_dump_info *dump; 2376 struct iwl_dbg_tlv_node *node; 2377 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2378 u32 size = sizeof(*tlv) + sizeof(*dump); 2379 u32 num_of_cfg_names = 0; 2380 u32 hw_type, is_cdb, is_jacket; 2381 2382 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2383 size += sizeof(*cfg_name); 2384 num_of_cfg_names++; 2385 } 2386 2387 entry = vzalloc(sizeof(*entry) + size); 2388 if (!entry) 2389 return 0; 2390 2391 entry->size = size; 2392 2393 tlv = (void *)entry->data; 2394 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2395 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2396 2397 dump = (void *)tlv->data; 2398 2399 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2400 dump->time_point = trigger->time_point; 2401 dump->trigger_reason = trigger->trigger_reason; 2402 dump->external_cfg_state = 2403 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2404 2405 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2406 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2407 2408 dump->hw_step = cpu_to_le32(fwrt->trans->info.hw_rev_step); 2409 2410 hw_type = CSR_HW_REV_TYPE(fwrt->trans->info.hw_rev); 2411 2412 is_cdb = CSR_HW_RFID_IS_CDB(fwrt->trans->info.hw_rf_id); 2413 is_jacket = !!(iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR) & 2414 WFPM_OTP_CFG1_IS_JACKET_BIT); 2415 2416 /* Use bits 12 and 13 to indicate jacket/CDB, respectively */ 2417 hw_type |= (is_jacket | (is_cdb << 1)) << IWL_JACKET_CDB_SHIFT; 2418 2419 dump->hw_type = cpu_to_le32(hw_type); 2420 2421 dump->rf_id_flavor = 2422 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->info.hw_rf_id)); 2423 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->info.hw_rf_id)); 2424 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->info.hw_rf_id)); 2425 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->info.hw_rf_id)); 2426 2427 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2428 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2429 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2430 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2431 2432 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2433 dump->regions_mask = trigger->regions_mask & 2434 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2435 2436 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2437 memcpy(dump->build_tag, fwrt->fw->human_readable, 2438 sizeof(dump->build_tag)); 2439 2440 cfg_name = dump->cfg_names; 2441 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2442 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2443 struct iwl_fw_ini_debug_info_tlv *debug_info = 2444 (void *)node->tlv.data; 2445 2446 BUILD_BUG_ON(sizeof(cfg_name->cfg_name) != 2447 sizeof(debug_info->debug_cfg_name)); 2448 2449 cfg_name->image_type = debug_info->image_type; 2450 cfg_name->cfg_name_len = 2451 cpu_to_le32(sizeof(cfg_name->cfg_name)); 2452 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2453 sizeof(cfg_name->cfg_name)); 2454 cfg_name++; 2455 } 2456 2457 /* add dump info TLV to the beginning of the list since it needs to be 2458 * the first TLV in the dump 2459 */ 2460 list_add(&entry->list, list); 2461 2462 return entry->size; 2463 } 2464 2465 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt, 2466 struct list_head *list) 2467 { 2468 struct iwl_fw_ini_dump_entry *entry; 2469 struct iwl_dump_file_name_info *tlv; 2470 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext, 2471 IWL_FW_INI_MAX_NAME); 2472 2473 if (!fwrt->trans->dbg.dump_file_name_ext_valid) 2474 return 0; 2475 2476 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len); 2477 if (!entry) 2478 return 0; 2479 2480 entry->size = sizeof(*tlv) + len; 2481 2482 tlv = (void *)entry->data; 2483 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE); 2484 tlv->len = cpu_to_le32(len); 2485 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len); 2486 2487 /* add the dump file name extension tlv to the list */ 2488 list_add_tail(&entry->list, list); 2489 2490 fwrt->trans->dbg.dump_file_name_ext_valid = false; 2491 2492 return entry->size; 2493 } 2494 2495 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2496 [IWL_FW_INI_REGION_INVALID] = {}, 2497 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2498 .get_num_of_ranges = iwl_dump_ini_single_range, 2499 .get_size = iwl_dump_ini_mon_smem_get_size, 2500 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2501 .fill_range = iwl_dump_ini_mon_smem_iter, 2502 }, 2503 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2504 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2505 .get_size = iwl_dump_ini_mon_dram_get_size, 2506 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2507 .fill_range = iwl_dump_ini_mon_dram_iter, 2508 }, 2509 [IWL_FW_INI_REGION_TXF] = { 2510 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2511 .get_size = iwl_dump_ini_txf_get_size, 2512 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2513 .fill_range = iwl_dump_ini_txf_iter, 2514 }, 2515 [IWL_FW_INI_REGION_RXF] = { 2516 .get_num_of_ranges = iwl_dump_ini_single_range, 2517 .get_size = iwl_dump_ini_rxf_get_size, 2518 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2519 .fill_range = iwl_dump_ini_rxf_iter, 2520 }, 2521 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2522 .get_num_of_ranges = iwl_dump_ini_single_range, 2523 .get_size = iwl_dump_ini_err_table_get_size, 2524 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2525 .fill_range = iwl_dump_ini_err_table_iter, 2526 }, 2527 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2528 .get_num_of_ranges = iwl_dump_ini_single_range, 2529 .get_size = iwl_dump_ini_err_table_get_size, 2530 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2531 .fill_range = iwl_dump_ini_err_table_iter, 2532 }, 2533 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2534 .get_num_of_ranges = iwl_dump_ini_single_range, 2535 .get_size = iwl_dump_ini_fw_pkt_get_size, 2536 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2537 .fill_range = iwl_dump_ini_fw_pkt_iter, 2538 }, 2539 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2540 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2541 .get_size = iwl_dump_ini_mem_get_size, 2542 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2543 .fill_range = iwl_dump_ini_dev_mem_iter, 2544 }, 2545 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2546 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2547 .get_size = iwl_dump_ini_mem_get_size, 2548 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2549 .fill_range = iwl_dump_ini_prph_mac_iter, 2550 }, 2551 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2552 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2553 .get_size = iwl_dump_ini_mem_get_size, 2554 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2555 .fill_range = iwl_dump_ini_prph_phy_iter, 2556 }, 2557 [IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE] = { 2558 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2559 .get_size = iwl_dump_ini_mem_block_get_size, 2560 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2561 .fill_range = iwl_dump_ini_prph_mac_block_iter, 2562 }, 2563 [IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE] = { 2564 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2565 .get_size = iwl_dump_ini_mem_block_get_size, 2566 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2567 .fill_range = iwl_dump_ini_prph_phy_block_iter, 2568 }, 2569 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2570 [IWL_FW_INI_REGION_PAGING] = { 2571 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2572 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2573 .get_size = iwl_dump_ini_paging_get_size, 2574 .fill_range = iwl_dump_ini_paging_iter, 2575 }, 2576 [IWL_FW_INI_REGION_CSR] = { 2577 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2578 .get_size = iwl_dump_ini_mem_get_size, 2579 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2580 .fill_range = iwl_dump_ini_csr_iter, 2581 }, 2582 [IWL_FW_INI_REGION_DRAM_IMR] = { 2583 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2584 .get_size = iwl_dump_ini_imr_get_size, 2585 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2586 .fill_range = iwl_dump_ini_imr_iter, 2587 }, 2588 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2589 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2590 .get_size = iwl_dump_ini_mem_get_size, 2591 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2592 .fill_range = iwl_dump_ini_config_iter, 2593 }, 2594 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2595 .get_num_of_ranges = iwl_dump_ini_single_range, 2596 .get_size = iwl_dump_ini_special_mem_get_size, 2597 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2598 .fill_range = iwl_dump_ini_special_mem_iter, 2599 }, 2600 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2601 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2602 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2603 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2604 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2605 }, 2606 [IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = { 2607 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2608 .get_size = iwl_dump_ini_mem_get_size, 2609 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2610 .fill_range = iwl_dump_ini_prph_snps_dphyip_iter, 2611 }, 2612 }; 2613 2614 enum iwl_dump_ini_region_selector { 2615 IWL_INI_DUMP_ALL_REGIONS, 2616 IWL_INI_DUMP_EARLY_REGIONS, 2617 IWL_INI_DUMP_LATE_REGIONS, 2618 }; 2619 2620 static bool iwl_dump_due_to_error(enum iwl_fw_ini_time_point tp_id) 2621 { 2622 return tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT || 2623 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR; 2624 } 2625 2626 static u32 2627 iwl_dump_ini_dump_regions(struct iwl_fw_runtime *fwrt, 2628 struct iwl_fwrt_dump_data *dump_data, 2629 struct list_head *list, 2630 enum iwl_fw_ini_time_point tp_id, 2631 u64 regions_mask, 2632 struct iwl_dump_ini_region_data *imr_reg_data, 2633 enum iwl_dump_ini_region_selector which) 2634 { 2635 u32 size = 0; 2636 2637 for (int i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2638 struct iwl_dump_ini_region_data reg_data = { 2639 .dump_data = dump_data, 2640 }; 2641 u32 reg_type, dp; 2642 struct iwl_fw_ini_region_tlv *reg; 2643 2644 if (!(BIT_ULL(i) & regions_mask)) 2645 continue; 2646 2647 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2648 if (!reg_data.reg_tlv) { 2649 IWL_WARN(fwrt, 2650 "WRT: Unassigned region id %d, skipping\n", i); 2651 continue; 2652 } 2653 2654 reg = (void *)reg_data.reg_tlv->data; 2655 reg_type = reg->type; 2656 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2657 continue; 2658 2659 dp = le32_get_bits(reg->id, IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2660 2661 if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2662 reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE || 2663 reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) && 2664 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2665 IWL_WARN(fwrt, 2666 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2667 tp_id); 2668 continue; 2669 } 2670 2671 switch (which) { 2672 case IWL_INI_DUMP_ALL_REGIONS: 2673 break; 2674 case IWL_INI_DUMP_EARLY_REGIONS: 2675 if (!(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_BEFORE_RESET)) 2676 continue; 2677 break; 2678 case IWL_INI_DUMP_LATE_REGIONS: 2679 if (dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_BEFORE_RESET) 2680 continue; 2681 break; 2682 } 2683 2684 /* 2685 * DRAM_IMR can be collected only for FW/HW error timepoint 2686 * when fw is not alive. In addition, it must be collected 2687 * lastly as it overwrites SRAM that can possibly contain 2688 * debug data which also need to be collected. 2689 */ 2690 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { 2691 if (iwl_dump_due_to_error(tp_id)) 2692 imr_reg_data->reg_tlv = 2693 fwrt->trans->dbg.active_regions[i]; 2694 else 2695 IWL_INFO(fwrt, 2696 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n", 2697 tp_id); 2698 /* continue to next region */ 2699 continue; 2700 } 2701 2702 2703 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2704 &iwl_dump_ini_region_ops[reg_type]); 2705 } 2706 2707 return size; 2708 } 2709 2710 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2711 struct iwl_fwrt_dump_data *dump_data, 2712 struct list_head *list) 2713 { 2714 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2715 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2716 struct iwl_dump_ini_region_data imr_reg_data = { 2717 .dump_data = dump_data, 2718 }; 2719 u32 size = 0; 2720 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2721 ~(fwrt->trans->dbg.unsupported_region_msk); 2722 2723 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2724 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2725 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2726 2727 if (trigger->apply_policy & 2728 cpu_to_le32(IWL_FW_INI_APPLY_POLICY_SPLIT_DUMP_RESET)) { 2729 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id, 2730 regions_mask, &imr_reg_data, 2731 IWL_INI_DUMP_EARLY_REGIONS); 2732 iwl_trans_pcie_fw_reset_handshake(fwrt->trans); 2733 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id, 2734 regions_mask, &imr_reg_data, 2735 IWL_INI_DUMP_LATE_REGIONS); 2736 } else { 2737 if (fw_has_capa(&fwrt->fw->ucode_capa, 2738 IWL_UCODE_TLV_CAPA_RESET_DURING_ASSERT) && 2739 iwl_dump_due_to_error(tp_id)) 2740 iwl_trans_pcie_fw_reset_handshake(fwrt->trans); 2741 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id, 2742 regions_mask, &imr_reg_data, 2743 IWL_INI_DUMP_ALL_REGIONS); 2744 } 2745 /* collect DRAM_IMR region in the last */ 2746 if (imr_reg_data.reg_tlv) 2747 size += iwl_dump_ini_mem(fwrt, list, &imr_reg_data, 2748 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]); 2749 2750 if (size) { 2751 size += iwl_dump_ini_file_name_info(fwrt, list); 2752 size += iwl_dump_ini_info(fwrt, trigger, list); 2753 } 2754 2755 return size; 2756 } 2757 2758 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2759 struct iwl_fw_ini_trigger_tlv *trig) 2760 { 2761 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2762 u32 usec = le32_to_cpu(trig->ignore_consec); 2763 2764 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2765 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2766 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2767 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2768 return false; 2769 2770 return true; 2771 } 2772 2773 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2774 struct iwl_fwrt_dump_data *dump_data, 2775 struct list_head *list) 2776 { 2777 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2778 struct iwl_fw_ini_dump_entry *entry; 2779 struct iwl_fw_ini_dump_file_hdr *hdr; 2780 u32 size; 2781 2782 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2783 !le64_to_cpu(trigger->regions_mask)) 2784 return 0; 2785 2786 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2787 if (!entry) 2788 return 0; 2789 2790 entry->size = sizeof(*hdr); 2791 2792 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2793 if (!size) { 2794 vfree(entry); 2795 return 0; 2796 } 2797 2798 hdr = (void *)entry->data; 2799 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2800 hdr->file_len = cpu_to_le32(size + entry->size); 2801 2802 list_add(&entry->list, list); 2803 2804 return le32_to_cpu(hdr->file_len); 2805 } 2806 2807 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2808 const struct iwl_fw_dump_desc *desc) 2809 { 2810 if (desc && desc != &iwl_dump_desc_assert) 2811 kfree(desc); 2812 2813 fwrt->dump.lmac_err_id[0] = 0; 2814 if (fwrt->smem_cfg.num_lmacs > 1) 2815 fwrt->dump.lmac_err_id[1] = 0; 2816 fwrt->dump.umac_err_id = 0; 2817 } 2818 2819 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2820 struct iwl_fwrt_dump_data *dump_data) 2821 { 2822 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2823 struct iwl_fw_error_dump_file *dump_file; 2824 struct scatterlist *sg_dump_data; 2825 u32 file_len; 2826 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2827 2828 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2829 if (!dump_file) 2830 return; 2831 2832 if (dump_data->monitor_only) 2833 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2834 2835 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2836 fwrt->sanitize_ops, 2837 fwrt->sanitize_ctx); 2838 file_len = le32_to_cpu(dump_file->file_len); 2839 fw_error_dump.fwrt_len = file_len; 2840 2841 if (fw_error_dump.trans_ptr) { 2842 file_len += fw_error_dump.trans_ptr->len; 2843 dump_file->file_len = cpu_to_le32(file_len); 2844 } 2845 2846 sg_dump_data = alloc_sgtable(file_len); 2847 if (sg_dump_data) { 2848 sg_pcopy_from_buffer(sg_dump_data, 2849 sg_nents(sg_dump_data), 2850 fw_error_dump.fwrt_ptr, 2851 fw_error_dump.fwrt_len, 0); 2852 if (fw_error_dump.trans_ptr) 2853 sg_pcopy_from_buffer(sg_dump_data, 2854 sg_nents(sg_dump_data), 2855 fw_error_dump.trans_ptr->data, 2856 fw_error_dump.trans_ptr->len, 2857 fw_error_dump.fwrt_len); 2858 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2859 GFP_KERNEL); 2860 } 2861 vfree(fw_error_dump.fwrt_ptr); 2862 vfree(fw_error_dump.trans_ptr); 2863 } 2864 2865 static void iwl_dump_ini_list_free(struct list_head *list) 2866 { 2867 while (!list_empty(list)) { 2868 struct iwl_fw_ini_dump_entry *entry = 2869 list_entry(list->next, typeof(*entry), list); 2870 2871 list_del(&entry->list); 2872 vfree(entry); 2873 } 2874 } 2875 2876 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2877 { 2878 dump_data->trig = NULL; 2879 kfree(dump_data->fw_pkt); 2880 dump_data->fw_pkt = NULL; 2881 } 2882 2883 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2884 struct iwl_fwrt_dump_data *dump_data) 2885 { 2886 LIST_HEAD(dump_list); 2887 struct scatterlist *sg_dump_data; 2888 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2889 2890 if (!file_len) 2891 return; 2892 2893 sg_dump_data = alloc_sgtable(file_len); 2894 if (sg_dump_data) { 2895 struct iwl_fw_ini_dump_entry *entry; 2896 int sg_entries = sg_nents(sg_dump_data); 2897 u32 offs = 0; 2898 2899 list_for_each_entry(entry, &dump_list, list) { 2900 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2901 entry->data, entry->size, offs); 2902 offs += entry->size; 2903 } 2904 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2905 GFP_KERNEL); 2906 } 2907 iwl_dump_ini_list_free(&dump_list); 2908 } 2909 2910 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2911 .trig_desc = { 2912 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2913 }, 2914 }; 2915 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2916 2917 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2918 const struct iwl_fw_dump_desc *desc, 2919 bool monitor_only, 2920 unsigned int delay) 2921 { 2922 struct iwl_fwrt_wk_data *wk_data; 2923 unsigned long idx; 2924 2925 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2926 iwl_fw_free_dump_desc(fwrt, desc); 2927 return 0; 2928 } 2929 2930 /* 2931 * Check there is an available worker. 2932 * ffz return value is undefined if no zero exists, 2933 * so check against ~0UL first. 2934 */ 2935 if (fwrt->dump.active_wks == ~0UL) 2936 return -EBUSY; 2937 2938 idx = ffz(fwrt->dump.active_wks); 2939 2940 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2941 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2942 return -EBUSY; 2943 2944 wk_data = &fwrt->dump.wks[idx]; 2945 2946 if (WARN_ON(wk_data->dump_data.desc)) 2947 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2948 2949 wk_data->dump_data.desc = desc; 2950 wk_data->dump_data.monitor_only = monitor_only; 2951 2952 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2953 le32_to_cpu(desc->trig_desc.type)); 2954 2955 queue_delayed_work(system_unbound_wq, &wk_data->wk, 2956 usecs_to_jiffies(delay)); 2957 2958 return 0; 2959 } 2960 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2961 2962 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2963 enum iwl_fw_dbg_trigger trig_type) 2964 { 2965 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2966 return -EIO; 2967 2968 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2969 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2970 trig_type != FW_DBG_TRIGGER_DRIVER) 2971 return -EIO; 2972 2973 iwl_dbg_tlv_time_point(fwrt, 2974 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2975 NULL); 2976 } else { 2977 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2978 int ret; 2979 2980 iwl_dump_error_desc = 2981 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2982 2983 if (!iwl_dump_error_desc) 2984 return -ENOMEM; 2985 2986 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2987 iwl_dump_error_desc->len = 0; 2988 2989 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2990 false, 0); 2991 if (ret) { 2992 kfree(iwl_dump_error_desc); 2993 return ret; 2994 } 2995 } 2996 2997 iwl_trans_sync_nmi(fwrt->trans); 2998 2999 return 0; 3000 } 3001 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 3002 3003 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 3004 enum iwl_fw_dbg_trigger trig, 3005 const char *str, size_t len, 3006 struct iwl_fw_dbg_trigger_tlv *trigger) 3007 { 3008 struct iwl_fw_dump_desc *desc; 3009 unsigned int delay = 0; 3010 bool monitor_only = false; 3011 3012 if (trigger) { 3013 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 3014 3015 if (!le16_to_cpu(trigger->occurrences)) 3016 return 0; 3017 3018 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 3019 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 3020 trig); 3021 iwl_force_nmi(fwrt->trans); 3022 return 0; 3023 } 3024 3025 trigger->occurrences = cpu_to_le16(occurrences); 3026 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 3027 3028 /* convert msec to usec */ 3029 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 3030 } 3031 3032 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC); 3033 if (!desc) 3034 return -ENOMEM; 3035 3036 3037 desc->len = len; 3038 desc->trig_desc.type = cpu_to_le32(trig); 3039 memcpy(desc->trig_desc.data, str, len); 3040 3041 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 3042 } 3043 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 3044 3045 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 3046 struct iwl_fw_dbg_trigger_tlv *trigger, 3047 const char *fmt, ...) 3048 { 3049 int ret, len = 0; 3050 char buf[64]; 3051 3052 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 3053 return 0; 3054 3055 if (fmt) { 3056 va_list ap; 3057 3058 buf[sizeof(buf) - 1] = '\0'; 3059 3060 va_start(ap, fmt); 3061 vsnprintf(buf, sizeof(buf), fmt, ap); 3062 va_end(ap); 3063 3064 /* check for truncation */ 3065 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 3066 buf[sizeof(buf) - 1] = '\0'; 3067 3068 len = strlen(buf) + 1; 3069 } 3070 3071 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 3072 trigger); 3073 3074 if (ret) 3075 return ret; 3076 3077 return 0; 3078 } 3079 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 3080 3081 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 3082 { 3083 u8 *ptr; 3084 int ret; 3085 int i; 3086 3087 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 3088 "Invalid configuration %d\n", conf_id)) 3089 return -EINVAL; 3090 3091 /* EARLY START - firmware's configuration is hard coded */ 3092 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 3093 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 3094 conf_id == FW_DBG_START_FROM_ALIVE) 3095 return 0; 3096 3097 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 3098 return -EINVAL; 3099 3100 if (fwrt->dump.conf != FW_DBG_INVALID) 3101 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 3102 fwrt->dump.conf); 3103 3104 /* Send all HCMDs for configuring the FW debug */ 3105 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 3106 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 3107 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 3108 struct iwl_host_cmd hcmd = { 3109 .id = cmd->id, 3110 .len = { le16_to_cpu(cmd->len), }, 3111 .data = { cmd->data, }, 3112 }; 3113 3114 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3115 if (ret) 3116 return ret; 3117 3118 ptr += sizeof(*cmd); 3119 ptr += le16_to_cpu(cmd->len); 3120 } 3121 3122 fwrt->dump.conf = conf_id; 3123 3124 return 0; 3125 } 3126 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 3127 3128 static void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt, 3129 u32 timepoint, u32 timepoint_data) 3130 { 3131 struct iwl_dbg_dump_complete_cmd hcmd_data; 3132 struct iwl_host_cmd hcmd = { 3133 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD), 3134 .data[0] = &hcmd_data, 3135 .len[0] = sizeof(hcmd_data), 3136 }; 3137 3138 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3139 return; 3140 3141 if (fw_has_capa(&fwrt->fw->ucode_capa, 3142 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) { 3143 hcmd_data.tp = cpu_to_le32(timepoint); 3144 hcmd_data.tp_data = cpu_to_le32(timepoint_data); 3145 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3146 } 3147 } 3148 3149 /* this function assumes dump_start was called beforehand and dump_end will be 3150 * called afterwards 3151 */ 3152 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 3153 { 3154 struct iwl_fw_dbg_params params = {0}; 3155 struct iwl_fwrt_dump_data *dump_data = 3156 &fwrt->dump.wks[wk_idx].dump_data; 3157 3158 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 3159 return; 3160 3161 /* also checks 'desc' for pre-ini mode, since that shadows in union */ 3162 if (!dump_data->trig) { 3163 IWL_ERR(fwrt, "dump trigger data is not set\n"); 3164 goto out; 3165 } 3166 3167 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 3168 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 3169 goto out; 3170 } 3171 3172 /* there's no point in fw dump if the bus is dead */ 3173 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 3174 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 3175 goto out; 3176 } 3177 3178 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 3179 3180 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 3181 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 3182 iwl_fw_error_ini_dump(fwrt, dump_data); 3183 else 3184 iwl_fw_error_dump(fwrt, dump_data); 3185 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 3186 3187 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3188 3189 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3190 u32 policy = le32_to_cpu(dump_data->trig->apply_policy); 3191 u32 time_point = le32_to_cpu(dump_data->trig->time_point); 3192 3193 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) { 3194 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n"); 3195 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0); 3196 } 3197 } 3198 3199 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 3200 iwl_force_nmi(fwrt->trans); 3201 out: 3202 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3203 iwl_fw_error_dump_data_free(dump_data); 3204 } else { 3205 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 3206 dump_data->desc = NULL; 3207 } 3208 3209 clear_bit(wk_idx, &fwrt->dump.active_wks); 3210 } 3211 3212 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 3213 struct iwl_fwrt_dump_data *dump_data, 3214 bool sync) 3215 { 3216 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 3217 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 3218 u32 occur, delay; 3219 unsigned long idx; 3220 3221 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 3222 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 3223 tp_id); 3224 return -EINVAL; 3225 } 3226 3227 delay = le32_to_cpu(trig->dump_delay); 3228 occur = le32_to_cpu(trig->occurrences); 3229 if (!occur) 3230 return 0; 3231 3232 trig->occurrences = cpu_to_le32(--occur); 3233 3234 /* Check there is an available worker. 3235 * ffz return value is undefined if no zero exists, 3236 * so check against ~0UL first. 3237 */ 3238 if (fwrt->dump.active_wks == ~0UL) 3239 return -EBUSY; 3240 3241 idx = ffz(fwrt->dump.active_wks); 3242 3243 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 3244 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 3245 return -EBUSY; 3246 3247 fwrt->dump.wks[idx].dump_data = *dump_data; 3248 3249 if (sync) 3250 delay = 0; 3251 3252 IWL_WARN(fwrt, 3253 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 3254 tp_id, (u32)(delay / USEC_PER_MSEC)); 3255 3256 if (sync) 3257 iwl_fw_dbg_collect_sync(fwrt, idx); 3258 else 3259 queue_delayed_work(system_unbound_wq, 3260 &fwrt->dump.wks[idx].wk, 3261 usecs_to_jiffies(delay)); 3262 3263 return 0; 3264 } 3265 3266 void iwl_fw_error_dump_wk(struct work_struct *work) 3267 { 3268 struct iwl_fwrt_wk_data *wks = 3269 container_of(work, typeof(*wks), wk.work); 3270 struct iwl_fw_runtime *fwrt = 3271 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 3272 3273 /* assumes the op mode mutex is locked in dump_start since 3274 * iwl_fw_dbg_collect_sync can't run in parallel 3275 */ 3276 if (fwrt->ops && fwrt->ops->dump_start) 3277 fwrt->ops->dump_start(fwrt->ops_ctx); 3278 3279 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 3280 3281 if (fwrt->ops && fwrt->ops->dump_end) 3282 fwrt->ops->dump_end(fwrt->ops_ctx); 3283 } 3284 3285 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 3286 { 3287 const struct iwl_mac_cfg *mac_cfg = fwrt->trans->mac_cfg; 3288 3289 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 3290 return; 3291 3292 if (!fwrt->dump.d3_debug_data) { 3293 fwrt->dump.d3_debug_data = kmalloc(mac_cfg->base->d3_debug_data_length, 3294 GFP_KERNEL); 3295 if (!fwrt->dump.d3_debug_data) { 3296 IWL_ERR(fwrt, 3297 "failed to allocate memory for D3 debug data\n"); 3298 return; 3299 } 3300 } 3301 3302 /* if the buffer holds previous debug data it is overwritten */ 3303 iwl_trans_read_mem_bytes(fwrt->trans, mac_cfg->base->d3_debug_data_base_addr, 3304 fwrt->dump.d3_debug_data, 3305 mac_cfg->base->d3_debug_data_length); 3306 3307 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 3308 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 3309 mac_cfg->base->d3_debug_data_base_addr, 3310 fwrt->dump.d3_debug_data, 3311 mac_cfg->base->d3_debug_data_length); 3312 } 3313 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 3314 3315 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 3316 { 3317 int i; 3318 3319 iwl_dbg_tlv_del_timers(fwrt->trans); 3320 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 3321 iwl_fw_dbg_collect_sync(fwrt, i); 3322 3323 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 3324 } 3325 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 3326 3327 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 3328 { 3329 struct iwl_dbg_suspend_resume_cmd cmd = { 3330 .operation = suspend ? 3331 cpu_to_le32(DBGC_SUSPEND_CMD) : 3332 cpu_to_le32(DBGC_RESUME_CMD), 3333 }; 3334 struct iwl_host_cmd hcmd = { 3335 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3336 .data[0] = &cmd, 3337 .len[0] = sizeof(cmd), 3338 }; 3339 3340 return iwl_trans_send_cmd(trans, &hcmd); 3341 } 3342 3343 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3344 struct iwl_fw_dbg_params *params) 3345 { 3346 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3347 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3348 return; 3349 } 3350 3351 if (params) { 3352 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3353 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3354 } 3355 3356 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3357 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3358 * avoid halting the HW while writing 3359 */ 3360 usleep_range(700, 1000); 3361 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3362 } 3363 3364 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3365 struct iwl_fw_dbg_params *params) 3366 { 3367 if (!params) 3368 return -EIO; 3369 3370 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3371 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3372 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3373 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3374 } else { 3375 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3376 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3377 } 3378 3379 return 0; 3380 } 3381 3382 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt) 3383 { 3384 struct iwl_mvm_marker marker = { 3385 .dw_len = sizeof(struct iwl_mvm_marker) / 4, 3386 .marker_id = MARKER_ID_SYNC_CLOCK, 3387 }; 3388 struct iwl_host_cmd hcmd = { 3389 .flags = CMD_ASYNC, 3390 .id = WIDE_ID(LONG_GROUP, MARKER_CMD), 3391 .dataflags = {}, 3392 }; 3393 struct iwl_mvm_marker_rsp *resp; 3394 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw, 3395 WIDE_ID(LONG_GROUP, MARKER_CMD), 3396 IWL_FW_CMD_VER_UNKNOWN); 3397 int ret; 3398 3399 if (cmd_ver == 1) { 3400 /* the real timestamp is taken from the ftrace clock 3401 * this is for finding the match between fw and kernel logs 3402 */ 3403 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++); 3404 } else if (cmd_ver == 2) { 3405 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns()); 3406 } else { 3407 IWL_DEBUG_INFO(fwrt, 3408 "Invalid version of Marker CMD. Ver = %d\n", 3409 cmd_ver); 3410 return -EINVAL; 3411 } 3412 3413 hcmd.data[0] = ▮ 3414 hcmd.len[0] = sizeof(marker); 3415 3416 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3417 3418 if (cmd_ver > 1 && hcmd.resp_pkt) { 3419 resp = (void *)hcmd.resp_pkt->data; 3420 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n", 3421 le32_to_cpu(resp->gp2)); 3422 } 3423 3424 return ret; 3425 } 3426 3427 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3428 struct iwl_fw_dbg_params *params, 3429 bool stop) 3430 { 3431 int ret __maybe_unused = 0; 3432 3433 if (!iwl_trans_fw_running(fwrt->trans)) 3434 return; 3435 3436 if (fw_has_capa(&fwrt->fw->ucode_capa, 3437 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) { 3438 if (stop) 3439 iwl_fw_send_timestamp_marker_cmd(fwrt); 3440 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3441 } else if (stop) { 3442 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3443 } else { 3444 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3445 } 3446 #ifdef CONFIG_IWLWIFI_DEBUGFS 3447 if (!ret) { 3448 if (stop) 3449 fwrt->trans->dbg.rec_on = false; 3450 else 3451 iwl_fw_set_dbg_rec_on(fwrt); 3452 } 3453 #endif 3454 } 3455 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3456 3457 void iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime *fwrt) 3458 { 3459 struct iwl_fw_dbg_config_cmd cmd = { 3460 .type = cpu_to_le32(DEBUG_TOKEN_CONFIG_TYPE), 3461 .conf = cpu_to_le32(IWL_FW_DBG_CONFIG_TOKEN), 3462 }; 3463 struct iwl_host_cmd hcmd = { 3464 .id = WIDE_ID(LONG_GROUP, LDBG_CONFIG_CMD), 3465 .data[0] = &cmd, 3466 .len[0] = sizeof(cmd), 3467 }; 3468 u32 preset = u32_get_bits(fwrt->trans->dbg.domains_bitmap, 3469 GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1)); 3470 3471 /* supported starting from 9000 devices */ 3472 if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_9000) 3473 return; 3474 3475 if (fwrt->trans->dbg.yoyo_bin_loaded || (preset && preset != 1)) 3476 return; 3477 3478 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3479 } 3480 IWL_EXPORT_SYMBOL(iwl_fw_disable_dbg_asserts); 3481 3482 void iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime *fwrt) 3483 { 3484 struct iwl_fw_dbg_params params = {0}; 3485 3486 iwl_fw_dbg_stop_sync(fwrt); 3487 3488 if (fw_has_api(&fwrt->fw->ucode_capa, 3489 IWL_UCODE_TLV_API_INT_DBG_BUF_CLEAR)) { 3490 struct iwl_host_cmd hcmd = { 3491 .id = WIDE_ID(DEBUG_GROUP, FW_CLEAR_BUFFER), 3492 }; 3493 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3494 } 3495 3496 iwl_dbg_tlv_init_cfg(fwrt); 3497 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3498 } 3499 IWL_EXPORT_SYMBOL(iwl_fw_dbg_clear_monitor_buf); 3500