1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "iwl-fh.h" 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @fwrt_len: length of the valid data in fwrt_ptr 23 */ 24 struct iwl_fw_dump_ptrs { 25 struct iwl_trans_dump_data *trans_ptr; 26 void *fwrt_ptr; 27 u32 fwrt_len; 28 }; 29 30 #define RADIO_REG_MAX_READ 0x2ad 31 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 32 struct iwl_fw_error_dump_data **dump_data) 33 { 34 u8 *pos = (void *)(*dump_data)->data; 35 int i; 36 37 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 38 39 if (!iwl_trans_grab_nic_access(fwrt->trans)) 40 return; 41 42 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 43 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 44 45 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 46 u32 rd_cmd = RADIO_RSP_RD_CMD; 47 48 rd_cmd |= i << RADIO_RSP_ADDR_POS; 49 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 50 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 51 52 pos++; 53 } 54 55 *dump_data = iwl_fw_error_next_data(*dump_data); 56 57 iwl_trans_release_nic_access(fwrt->trans); 58 } 59 60 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 61 struct iwl_fw_error_dump_data **dump_data, 62 int size, u32 offset, int fifo_num) 63 { 64 struct iwl_fw_error_dump_fifo *fifo_hdr; 65 u32 *fifo_data; 66 u32 fifo_len; 67 int i; 68 69 fifo_hdr = (void *)(*dump_data)->data; 70 fifo_data = (void *)fifo_hdr->data; 71 fifo_len = size; 72 73 /* No need to try to read the data if the length is 0 */ 74 if (fifo_len == 0) 75 return; 76 77 /* Add a TLV for the RXF */ 78 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 79 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 80 81 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 82 fifo_hdr->available_bytes = 83 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 84 RXF_RD_D_SPACE + offset)); 85 fifo_hdr->wr_ptr = 86 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 87 RXF_RD_WR_PTR + offset)); 88 fifo_hdr->rd_ptr = 89 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 90 RXF_RD_RD_PTR + offset)); 91 fifo_hdr->fence_ptr = 92 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 93 RXF_RD_FENCE_PTR + offset)); 94 fifo_hdr->fence_mode = 95 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 96 RXF_SET_FENCE_MODE + offset)); 97 98 /* Lock fence */ 99 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 100 /* Set fence pointer to the same place like WR pointer */ 101 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 102 /* Set fence offset */ 103 iwl_trans_write_prph(fwrt->trans, 104 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 105 106 /* Read FIFO */ 107 fifo_len /= sizeof(u32); /* Size in DWORDS */ 108 for (i = 0; i < fifo_len; i++) 109 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 110 RXF_FIFO_RD_FENCE_INC + 111 offset); 112 *dump_data = iwl_fw_error_next_data(*dump_data); 113 } 114 115 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 116 struct iwl_fw_error_dump_data **dump_data, 117 int size, u32 offset, int fifo_num) 118 { 119 struct iwl_fw_error_dump_fifo *fifo_hdr; 120 u32 *fifo_data; 121 u32 fifo_len; 122 int i; 123 124 fifo_hdr = (void *)(*dump_data)->data; 125 fifo_data = (void *)fifo_hdr->data; 126 fifo_len = size; 127 128 /* No need to try to read the data if the length is 0 */ 129 if (fifo_len == 0) 130 return; 131 132 /* Add a TLV for the FIFO */ 133 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 134 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 135 136 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 137 fifo_hdr->available_bytes = 138 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 139 TXF_FIFO_ITEM_CNT + offset)); 140 fifo_hdr->wr_ptr = 141 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 142 TXF_WR_PTR + offset)); 143 fifo_hdr->rd_ptr = 144 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 145 TXF_RD_PTR + offset)); 146 fifo_hdr->fence_ptr = 147 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 148 TXF_FENCE_PTR + offset)); 149 fifo_hdr->fence_mode = 150 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 151 TXF_LOCK_FENCE + offset)); 152 153 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 154 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 155 TXF_WR_PTR + offset); 156 157 /* Dummy-read to advance the read pointer to the head */ 158 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 159 160 /* Read FIFO */ 161 for (i = 0; i < fifo_len / sizeof(u32); i++) 162 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 163 TXF_READ_MODIFY_DATA + 164 offset); 165 166 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 167 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 168 fifo_data, fifo_len); 169 170 *dump_data = iwl_fw_error_next_data(*dump_data); 171 } 172 173 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 174 struct iwl_fw_error_dump_data **dump_data) 175 { 176 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 177 178 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 179 180 if (!iwl_trans_grab_nic_access(fwrt->trans)) 181 return; 182 183 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 184 /* Pull RXF1 */ 185 iwl_fwrt_dump_rxf(fwrt, dump_data, 186 cfg->lmac[0].rxfifo1_size, 0, 0); 187 /* Pull RXF2 */ 188 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 189 RXF_DIFF_FROM_PREV + 190 fwrt->trans->mac_cfg->umac_prph_offset, 1); 191 /* Pull LMAC2 RXF1 */ 192 if (fwrt->smem_cfg.num_lmacs > 1) 193 iwl_fwrt_dump_rxf(fwrt, dump_data, 194 cfg->lmac[1].rxfifo1_size, 195 LMAC2_PRPH_OFFSET, 2); 196 } 197 198 iwl_trans_release_nic_access(fwrt->trans); 199 } 200 201 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 202 struct iwl_fw_error_dump_data **dump_data) 203 { 204 struct iwl_fw_error_dump_fifo *fifo_hdr; 205 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 206 u32 *fifo_data; 207 u32 fifo_len; 208 int i, j; 209 210 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 211 212 if (!iwl_trans_grab_nic_access(fwrt->trans)) 213 return; 214 215 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 216 /* Pull TXF data from LMAC1 */ 217 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 218 /* Mark the number of TXF we're pulling now */ 219 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 220 iwl_fwrt_dump_txf(fwrt, dump_data, 221 cfg->lmac[0].txfifo_size[i], 0, i); 222 } 223 224 /* Pull TXF data from LMAC2 */ 225 if (fwrt->smem_cfg.num_lmacs > 1) { 226 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 227 i++) { 228 /* Mark the number of TXF we're pulling now */ 229 iwl_trans_write_prph(fwrt->trans, 230 TXF_LARC_NUM + 231 LMAC2_PRPH_OFFSET, i); 232 iwl_fwrt_dump_txf(fwrt, dump_data, 233 cfg->lmac[1].txfifo_size[i], 234 LMAC2_PRPH_OFFSET, 235 i + cfg->num_txfifo_entries); 236 } 237 } 238 } 239 240 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 241 fw_has_capa(&fwrt->fw->ucode_capa, 242 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 243 /* Pull UMAC internal TXF data from all TXFs */ 244 for (i = 0; 245 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 246 i++) { 247 fifo_hdr = (void *)(*dump_data)->data; 248 fifo_data = (void *)fifo_hdr->data; 249 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 250 251 /* No need to try to read the data if the length is 0 */ 252 if (fifo_len == 0) 253 continue; 254 255 /* Add a TLV for the internal FIFOs */ 256 (*dump_data)->type = 257 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 258 (*dump_data)->len = 259 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 260 261 fifo_hdr->fifo_num = cpu_to_le32(i); 262 263 /* Mark the number of TXF we're pulling now */ 264 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 265 fwrt->smem_cfg.num_txfifo_entries); 266 267 fifo_hdr->available_bytes = 268 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 269 TXF_CPU2_FIFO_ITEM_CNT)); 270 fifo_hdr->wr_ptr = 271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 272 TXF_CPU2_WR_PTR)); 273 fifo_hdr->rd_ptr = 274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 275 TXF_CPU2_RD_PTR)); 276 fifo_hdr->fence_ptr = 277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 278 TXF_CPU2_FENCE_PTR)); 279 fifo_hdr->fence_mode = 280 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 281 TXF_CPU2_LOCK_FENCE)); 282 283 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 284 iwl_trans_write_prph(fwrt->trans, 285 TXF_CPU2_READ_MODIFY_ADDR, 286 TXF_CPU2_WR_PTR); 287 288 /* Dummy-read to advance the read pointer to head */ 289 iwl_trans_read_prph(fwrt->trans, 290 TXF_CPU2_READ_MODIFY_DATA); 291 292 /* Read FIFO */ 293 fifo_len /= sizeof(u32); /* Size in DWORDS */ 294 for (j = 0; j < fifo_len; j++) 295 fifo_data[j] = 296 iwl_trans_read_prph(fwrt->trans, 297 TXF_CPU2_READ_MODIFY_DATA); 298 *dump_data = iwl_fw_error_next_data(*dump_data); 299 } 300 } 301 302 iwl_trans_release_nic_access(fwrt->trans); 303 } 304 305 struct iwl_prph_range { 306 u32 start, end; 307 }; 308 309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 310 { .start = 0x00a00000, .end = 0x00a00000 }, 311 { .start = 0x00a0000c, .end = 0x00a00024 }, 312 { .start = 0x00a0002c, .end = 0x00a0003c }, 313 { .start = 0x00a00410, .end = 0x00a00418 }, 314 { .start = 0x00a00420, .end = 0x00a00420 }, 315 { .start = 0x00a00428, .end = 0x00a00428 }, 316 { .start = 0x00a00430, .end = 0x00a0043c }, 317 { .start = 0x00a00444, .end = 0x00a00444 }, 318 { .start = 0x00a004c0, .end = 0x00a004cc }, 319 { .start = 0x00a004d8, .end = 0x00a004d8 }, 320 { .start = 0x00a004e0, .end = 0x00a004f0 }, 321 { .start = 0x00a00840, .end = 0x00a00840 }, 322 { .start = 0x00a00850, .end = 0x00a00858 }, 323 { .start = 0x00a01004, .end = 0x00a01008 }, 324 { .start = 0x00a01010, .end = 0x00a01010 }, 325 { .start = 0x00a01018, .end = 0x00a01018 }, 326 { .start = 0x00a01024, .end = 0x00a01024 }, 327 { .start = 0x00a0102c, .end = 0x00a01034 }, 328 { .start = 0x00a0103c, .end = 0x00a01040 }, 329 { .start = 0x00a01048, .end = 0x00a01094 }, 330 { .start = 0x00a01c00, .end = 0x00a01c20 }, 331 { .start = 0x00a01c58, .end = 0x00a01c58 }, 332 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 333 { .start = 0x00a01c28, .end = 0x00a01c54 }, 334 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 335 { .start = 0x00a01c60, .end = 0x00a01cdc }, 336 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 337 { .start = 0x00a01d18, .end = 0x00a01d20 }, 338 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 339 { .start = 0x00a01d40, .end = 0x00a01d5c }, 340 { .start = 0x00a01d80, .end = 0x00a01d80 }, 341 { .start = 0x00a01d98, .end = 0x00a01d9c }, 342 { .start = 0x00a01da8, .end = 0x00a01da8 }, 343 { .start = 0x00a01db8, .end = 0x00a01df4 }, 344 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 345 { .start = 0x00a01e00, .end = 0x00a01e2c }, 346 { .start = 0x00a01e40, .end = 0x00a01e60 }, 347 { .start = 0x00a01e68, .end = 0x00a01e6c }, 348 { .start = 0x00a01e74, .end = 0x00a01e74 }, 349 { .start = 0x00a01e84, .end = 0x00a01e90 }, 350 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 351 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 352 { .start = 0x00a01f00, .end = 0x00a01f1c }, 353 { .start = 0x00a01f44, .end = 0x00a01ffc }, 354 { .start = 0x00a02000, .end = 0x00a02048 }, 355 { .start = 0x00a02068, .end = 0x00a020f0 }, 356 { .start = 0x00a02100, .end = 0x00a02118 }, 357 { .start = 0x00a02140, .end = 0x00a0214c }, 358 { .start = 0x00a02168, .end = 0x00a0218c }, 359 { .start = 0x00a021c0, .end = 0x00a021c0 }, 360 { .start = 0x00a02400, .end = 0x00a02410 }, 361 { .start = 0x00a02418, .end = 0x00a02420 }, 362 { .start = 0x00a02428, .end = 0x00a0242c }, 363 { .start = 0x00a02434, .end = 0x00a02434 }, 364 { .start = 0x00a02440, .end = 0x00a02460 }, 365 { .start = 0x00a02468, .end = 0x00a024b0 }, 366 { .start = 0x00a024c8, .end = 0x00a024cc }, 367 { .start = 0x00a02500, .end = 0x00a02504 }, 368 { .start = 0x00a0250c, .end = 0x00a02510 }, 369 { .start = 0x00a02540, .end = 0x00a02554 }, 370 { .start = 0x00a02580, .end = 0x00a025f4 }, 371 { .start = 0x00a02600, .end = 0x00a0260c }, 372 { .start = 0x00a02648, .end = 0x00a02650 }, 373 { .start = 0x00a02680, .end = 0x00a02680 }, 374 { .start = 0x00a026c0, .end = 0x00a026d0 }, 375 { .start = 0x00a02700, .end = 0x00a0270c }, 376 { .start = 0x00a02804, .end = 0x00a02804 }, 377 { .start = 0x00a02818, .end = 0x00a0281c }, 378 { .start = 0x00a02c00, .end = 0x00a02db4 }, 379 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 380 { .start = 0x00a03000, .end = 0x00a03014 }, 381 { .start = 0x00a0301c, .end = 0x00a0302c }, 382 { .start = 0x00a03034, .end = 0x00a03038 }, 383 { .start = 0x00a03040, .end = 0x00a03048 }, 384 { .start = 0x00a03060, .end = 0x00a03068 }, 385 { .start = 0x00a03070, .end = 0x00a03074 }, 386 { .start = 0x00a0307c, .end = 0x00a0307c }, 387 { .start = 0x00a03080, .end = 0x00a03084 }, 388 { .start = 0x00a0308c, .end = 0x00a03090 }, 389 { .start = 0x00a03098, .end = 0x00a03098 }, 390 { .start = 0x00a030a0, .end = 0x00a030a0 }, 391 { .start = 0x00a030a8, .end = 0x00a030b4 }, 392 { .start = 0x00a030bc, .end = 0x00a030bc }, 393 { .start = 0x00a030c0, .end = 0x00a0312c }, 394 { .start = 0x00a03c00, .end = 0x00a03c5c }, 395 { .start = 0x00a04400, .end = 0x00a04454 }, 396 { .start = 0x00a04460, .end = 0x00a04474 }, 397 { .start = 0x00a044c0, .end = 0x00a044ec }, 398 { .start = 0x00a04500, .end = 0x00a04504 }, 399 { .start = 0x00a04510, .end = 0x00a04538 }, 400 { .start = 0x00a04540, .end = 0x00a04548 }, 401 { .start = 0x00a04560, .end = 0x00a0457c }, 402 { .start = 0x00a04590, .end = 0x00a04598 }, 403 { .start = 0x00a045c0, .end = 0x00a045f4 }, 404 }; 405 406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 407 { .start = 0x00a05c00, .end = 0x00a05c18 }, 408 { .start = 0x00a05400, .end = 0x00a056e8 }, 409 { .start = 0x00a08000, .end = 0x00a098bc }, 410 { .start = 0x00a02400, .end = 0x00a02758 }, 411 { .start = 0x00a04764, .end = 0x00a0476c }, 412 { .start = 0x00a04770, .end = 0x00a04774 }, 413 { .start = 0x00a04620, .end = 0x00a04624 }, 414 }; 415 416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 417 { .start = 0x00a00000, .end = 0x00a00000 }, 418 { .start = 0x00a0000c, .end = 0x00a00024 }, 419 { .start = 0x00a0002c, .end = 0x00a00034 }, 420 { .start = 0x00a0003c, .end = 0x00a0003c }, 421 { .start = 0x00a00410, .end = 0x00a00418 }, 422 { .start = 0x00a00420, .end = 0x00a00420 }, 423 { .start = 0x00a00428, .end = 0x00a00428 }, 424 { .start = 0x00a00430, .end = 0x00a0043c }, 425 { .start = 0x00a00444, .end = 0x00a00444 }, 426 { .start = 0x00a00840, .end = 0x00a00840 }, 427 { .start = 0x00a00850, .end = 0x00a00858 }, 428 { .start = 0x00a01004, .end = 0x00a01008 }, 429 { .start = 0x00a01010, .end = 0x00a01010 }, 430 { .start = 0x00a01018, .end = 0x00a01018 }, 431 { .start = 0x00a01024, .end = 0x00a01024 }, 432 { .start = 0x00a0102c, .end = 0x00a01034 }, 433 { .start = 0x00a0103c, .end = 0x00a01040 }, 434 { .start = 0x00a01048, .end = 0x00a01050 }, 435 { .start = 0x00a01058, .end = 0x00a01058 }, 436 { .start = 0x00a01060, .end = 0x00a01070 }, 437 { .start = 0x00a0108c, .end = 0x00a0108c }, 438 { .start = 0x00a01c20, .end = 0x00a01c28 }, 439 { .start = 0x00a01d10, .end = 0x00a01d10 }, 440 { .start = 0x00a01e28, .end = 0x00a01e2c }, 441 { .start = 0x00a01e60, .end = 0x00a01e60 }, 442 { .start = 0x00a01e80, .end = 0x00a01e80 }, 443 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 444 { .start = 0x00a02000, .end = 0x00a0201c }, 445 { .start = 0x00a02024, .end = 0x00a02024 }, 446 { .start = 0x00a02040, .end = 0x00a02048 }, 447 { .start = 0x00a020c0, .end = 0x00a020e0 }, 448 { .start = 0x00a02400, .end = 0x00a02404 }, 449 { .start = 0x00a0240c, .end = 0x00a02414 }, 450 { .start = 0x00a0241c, .end = 0x00a0243c }, 451 { .start = 0x00a02448, .end = 0x00a024bc }, 452 { .start = 0x00a024c4, .end = 0x00a024cc }, 453 { .start = 0x00a02508, .end = 0x00a02508 }, 454 { .start = 0x00a02510, .end = 0x00a02514 }, 455 { .start = 0x00a0251c, .end = 0x00a0251c }, 456 { .start = 0x00a0252c, .end = 0x00a0255c }, 457 { .start = 0x00a02564, .end = 0x00a025a0 }, 458 { .start = 0x00a025a8, .end = 0x00a025b4 }, 459 { .start = 0x00a025c0, .end = 0x00a025c0 }, 460 { .start = 0x00a025e8, .end = 0x00a025f4 }, 461 { .start = 0x00a02c08, .end = 0x00a02c18 }, 462 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 463 { .start = 0x00a02c68, .end = 0x00a02c78 }, 464 { .start = 0x00a03000, .end = 0x00a03000 }, 465 { .start = 0x00a03010, .end = 0x00a03014 }, 466 { .start = 0x00a0301c, .end = 0x00a0302c }, 467 { .start = 0x00a03034, .end = 0x00a03038 }, 468 { .start = 0x00a03040, .end = 0x00a03044 }, 469 { .start = 0x00a03060, .end = 0x00a03068 }, 470 { .start = 0x00a03070, .end = 0x00a03070 }, 471 { .start = 0x00a0307c, .end = 0x00a03084 }, 472 { .start = 0x00a0308c, .end = 0x00a03090 }, 473 { .start = 0x00a03098, .end = 0x00a03098 }, 474 { .start = 0x00a030a0, .end = 0x00a030a0 }, 475 { .start = 0x00a030a8, .end = 0x00a030b4 }, 476 { .start = 0x00a030bc, .end = 0x00a030c0 }, 477 { .start = 0x00a030c8, .end = 0x00a030f4 }, 478 { .start = 0x00a03100, .end = 0x00a0312c }, 479 { .start = 0x00a03c00, .end = 0x00a03c5c }, 480 { .start = 0x00a04400, .end = 0x00a04454 }, 481 { .start = 0x00a04460, .end = 0x00a04474 }, 482 { .start = 0x00a044c0, .end = 0x00a044ec }, 483 { .start = 0x00a04500, .end = 0x00a04504 }, 484 { .start = 0x00a04510, .end = 0x00a04538 }, 485 { .start = 0x00a04540, .end = 0x00a04548 }, 486 { .start = 0x00a04560, .end = 0x00a04560 }, 487 { .start = 0x00a04570, .end = 0x00a0457c }, 488 { .start = 0x00a04590, .end = 0x00a04590 }, 489 { .start = 0x00a04598, .end = 0x00a04598 }, 490 { .start = 0x00a045c0, .end = 0x00a045f4 }, 491 { .start = 0x00a05c18, .end = 0x00a05c1c }, 492 { .start = 0x00a0c000, .end = 0x00a0c018 }, 493 { .start = 0x00a0c020, .end = 0x00a0c028 }, 494 { .start = 0x00a0c038, .end = 0x00a0c094 }, 495 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 496 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 497 { .start = 0x00a0c150, .end = 0x00a0c174 }, 498 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 499 { .start = 0x00a0c190, .end = 0x00a0c198 }, 500 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 501 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 502 }; 503 504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 505 { .start = 0x00d03c00, .end = 0x00d03c64 }, 506 { .start = 0x00d05c18, .end = 0x00d05c1c }, 507 { .start = 0x00d0c000, .end = 0x00d0c174 }, 508 }; 509 510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 511 u32 len_bytes, __le32 *data) 512 { 513 u32 i; 514 515 for (i = 0; i < len_bytes; i += 4) 516 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 517 } 518 519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 520 const struct iwl_prph_range *iwl_prph_dump_addr, 521 u32 range_len, void *ptr) 522 { 523 struct iwl_fw_error_dump_prph *prph; 524 struct iwl_trans *trans = fwrt->trans; 525 struct iwl_fw_error_dump_data **data = 526 (struct iwl_fw_error_dump_data **)ptr; 527 u32 i; 528 529 if (!data) 530 return; 531 532 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 533 534 if (!iwl_trans_grab_nic_access(trans)) 535 return; 536 537 for (i = 0; i < range_len; i++) { 538 /* The range includes both boundaries */ 539 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 540 iwl_prph_dump_addr[i].start + 4; 541 542 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 543 (*data)->len = cpu_to_le32(sizeof(*prph) + 544 num_bytes_in_chunk); 545 prph = (void *)(*data)->data; 546 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 547 548 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 549 /* our range is inclusive, hence + 4 */ 550 iwl_prph_dump_addr[i].end - 551 iwl_prph_dump_addr[i].start + 4, 552 (void *)prph->data); 553 554 *data = iwl_fw_error_next_data(*data); 555 } 556 557 iwl_trans_release_nic_access(trans); 558 } 559 560 /* 561 * alloc_sgtable - allocates (chained) scatterlist in the given size, 562 * fills it with pages and returns it 563 * @size: the size (in bytes) of the table 564 */ 565 static struct scatterlist *alloc_sgtable(ssize_t size) 566 { 567 struct scatterlist *result = NULL, *prev; 568 int nents, i, n_prev; 569 570 nents = DIV_ROUND_UP(size, PAGE_SIZE); 571 572 #define N_ENTRIES_PER_PAGE (PAGE_SIZE / sizeof(*result)) 573 /* 574 * We need an additional entry for table chaining, 575 * this ensures the loop can finish i.e. we can 576 * fit at least two entries per page (obviously, 577 * many more really fit.) 578 */ 579 BUILD_BUG_ON(N_ENTRIES_PER_PAGE < 2); 580 581 while (nents > 0) { 582 struct scatterlist *new, *iter; 583 int n_fill, n_alloc; 584 585 if (nents <= N_ENTRIES_PER_PAGE) { 586 /* last needed table */ 587 n_fill = nents; 588 n_alloc = nents; 589 nents = 0; 590 } else { 591 /* fill a page with entries */ 592 n_alloc = N_ENTRIES_PER_PAGE; 593 /* reserve one for chaining */ 594 n_fill = n_alloc - 1; 595 nents -= n_fill; 596 } 597 598 new = kcalloc(n_alloc, sizeof(*new), GFP_KERNEL); 599 if (!new) { 600 if (result) 601 _devcd_free_sgtable(result); 602 return NULL; 603 } 604 sg_init_table(new, n_alloc); 605 606 if (!result) 607 result = new; 608 else 609 sg_chain(prev, n_prev, new); 610 prev = new; 611 n_prev = n_alloc; 612 613 for_each_sg(new, iter, n_fill, i) { 614 struct page *new_page = alloc_page(GFP_KERNEL); 615 616 if (!new_page) { 617 _devcd_free_sgtable(result); 618 return NULL; 619 } 620 621 sg_set_page(iter, new_page, PAGE_SIZE, 0); 622 } 623 } 624 625 return result; 626 } 627 628 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 629 const struct iwl_prph_range *iwl_prph_dump_addr, 630 u32 range_len, void *ptr) 631 { 632 u32 *prph_len = (u32 *)ptr; 633 int i, num_bytes_in_chunk; 634 635 if (!prph_len) 636 return; 637 638 for (i = 0; i < range_len; i++) { 639 /* The range includes both boundaries */ 640 num_bytes_in_chunk = 641 iwl_prph_dump_addr[i].end - 642 iwl_prph_dump_addr[i].start + 4; 643 644 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 645 sizeof(struct iwl_fw_error_dump_prph) + 646 num_bytes_in_chunk; 647 } 648 } 649 650 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 651 void (*handler)(struct iwl_fw_runtime *, 652 const struct iwl_prph_range *, 653 u32, void *)) 654 { 655 u32 range_len; 656 657 if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 658 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 659 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 660 } else if (fwrt->trans->mac_cfg->device_family >= 661 IWL_DEVICE_FAMILY_22000) { 662 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 663 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 664 } else { 665 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 666 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 667 668 if (fwrt->trans->mac_cfg->mq_rx_supported) { 669 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 670 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 671 } 672 } 673 } 674 675 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 676 struct iwl_fw_error_dump_data **dump_data, 677 u32 len, u32 ofs, u32 type) 678 { 679 struct iwl_fw_error_dump_mem *dump_mem; 680 681 if (!len) 682 return; 683 684 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 685 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 686 dump_mem = (void *)(*dump_data)->data; 687 dump_mem->type = cpu_to_le32(type); 688 dump_mem->offset = cpu_to_le32(ofs); 689 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 690 *dump_data = iwl_fw_error_next_data(*dump_data); 691 692 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 693 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 694 dump_mem->data, len); 695 696 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 697 } 698 699 #define ADD_LEN(len, item_len, const_len) \ 700 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 701 while (0) 702 703 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 704 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 705 { 706 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 707 sizeof(struct iwl_fw_error_dump_fifo); 708 u32 fifo_len = 0; 709 int i; 710 711 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 712 return 0; 713 714 /* Count RXF2 size */ 715 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 716 717 /* Count RXF1 sizes */ 718 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 719 mem_cfg->num_lmacs = MAX_NUM_LMAC; 720 721 for (i = 0; i < mem_cfg->num_lmacs; i++) 722 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 723 724 return fifo_len; 725 } 726 727 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 728 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 729 { 730 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 731 sizeof(struct iwl_fw_error_dump_fifo); 732 u32 fifo_len = 0; 733 int i; 734 735 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 736 goto dump_internal_txf; 737 738 /* Count TXF sizes */ 739 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 740 mem_cfg->num_lmacs = MAX_NUM_LMAC; 741 742 for (i = 0; i < mem_cfg->num_lmacs; i++) { 743 int j; 744 745 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 746 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 747 hdr_len); 748 } 749 750 dump_internal_txf: 751 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 752 fw_has_capa(&fwrt->fw->ucode_capa, 753 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 754 goto out; 755 756 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 757 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 758 759 out: 760 return fifo_len; 761 } 762 763 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 764 struct iwl_fw_error_dump_data **data) 765 { 766 int i; 767 768 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 769 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 770 struct iwl_fw_error_dump_paging *paging; 771 struct page *pages = 772 fwrt->fw_paging_db[i].fw_paging_block; 773 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 774 775 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 776 (*data)->len = cpu_to_le32(sizeof(*paging) + 777 PAGING_BLOCK_SIZE); 778 paging = (void *)(*data)->data; 779 paging->index = cpu_to_le32(i); 780 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 781 PAGING_BLOCK_SIZE, 782 DMA_BIDIRECTIONAL); 783 memcpy(paging->data, page_address(pages), 784 PAGING_BLOCK_SIZE); 785 dma_sync_single_for_device(fwrt->trans->dev, addr, 786 PAGING_BLOCK_SIZE, 787 DMA_BIDIRECTIONAL); 788 (*data) = iwl_fw_error_next_data(*data); 789 790 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 791 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 792 fwrt->fw_paging_db[i].fw_offs, 793 paging->data, 794 PAGING_BLOCK_SIZE); 795 } 796 } 797 798 static struct iwl_fw_error_dump_file * 799 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 800 struct iwl_fw_dump_ptrs *fw_error_dump, 801 struct iwl_fwrt_dump_data *data) 802 { 803 struct iwl_fw_error_dump_file *dump_file; 804 struct iwl_fw_error_dump_data *dump_data; 805 struct iwl_fw_error_dump_info *dump_info; 806 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 807 struct iwl_fw_error_dump_trigger_desc *dump_trig; 808 u32 sram_len, sram_ofs; 809 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 810 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 811 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 812 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->mac_cfg->base->smem_len; 813 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 814 0 : fwrt->trans->cfg->dccm2_len; 815 int i; 816 817 /* SRAM - include stack CCM if driver knows the values for it */ 818 if (!fwrt->trans->cfg->dccm_offset || 819 !fwrt->trans->cfg->dccm_len) { 820 const struct fw_img *img; 821 822 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 823 return NULL; 824 img = &fwrt->fw->img[fwrt->cur_fw_img]; 825 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 826 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 827 } else { 828 sram_ofs = fwrt->trans->cfg->dccm_offset; 829 sram_len = fwrt->trans->cfg->dccm_len; 830 } 831 832 /* reading RXF/TXF sizes */ 833 if (iwl_trans_is_fw_error(fwrt->trans)) { 834 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 835 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 836 837 /* Make room for PRPH registers */ 838 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 839 iwl_fw_prph_handler(fwrt, &prph_len, 840 iwl_fw_get_prph_len); 841 842 if (fwrt->trans->mac_cfg->device_family == 843 IWL_DEVICE_FAMILY_7000 && 844 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 845 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 846 } 847 848 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 849 850 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 851 file_len += sizeof(*dump_data) + sizeof(*dump_info); 852 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 853 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 854 855 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 856 size_t hdr_len = sizeof(*dump_data) + 857 sizeof(struct iwl_fw_error_dump_mem); 858 859 /* Dump SRAM only if no mem_tlvs */ 860 if (!fwrt->fw->dbg.n_mem_tlv) 861 ADD_LEN(file_len, sram_len, hdr_len); 862 863 /* Make room for all mem types that exist */ 864 ADD_LEN(file_len, smem_len, hdr_len); 865 ADD_LEN(file_len, sram2_len, hdr_len); 866 867 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 868 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 869 } 870 871 /* Make room for fw's virtual image pages, if it exists */ 872 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 873 file_len += fwrt->num_of_paging_blk * 874 (sizeof(*dump_data) + 875 sizeof(struct iwl_fw_error_dump_paging) + 876 PAGING_BLOCK_SIZE); 877 878 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 879 file_len += sizeof(*dump_data) + 880 fwrt->trans->mac_cfg->base->d3_debug_data_length * 2; 881 } 882 883 /* If we only want a monitor dump, reset the file length */ 884 if (data->monitor_only) { 885 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 886 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 887 } 888 889 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 890 data->desc) 891 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 892 data->desc->len; 893 894 dump_file = vzalloc(file_len); 895 if (!dump_file) 896 return NULL; 897 898 fw_error_dump->fwrt_ptr = dump_file; 899 900 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 901 dump_data = (void *)dump_file->data; 902 903 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 904 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 905 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 906 dump_info = (void *)dump_data->data; 907 dump_info->hw_type = 908 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->info.hw_rev)); 909 dump_info->hw_step = 910 cpu_to_le32(fwrt->trans->info.hw_rev_step); 911 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 912 sizeof(dump_info->fw_human_readable)); 913 strscpy_pad(dump_info->dev_human_readable, 914 fwrt->trans->info.name, 915 sizeof(dump_info->dev_human_readable)); 916 strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name, 917 sizeof(dump_info->bus_human_readable)); 918 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 919 dump_info->lmac_err_id[0] = 920 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 921 if (fwrt->smem_cfg.num_lmacs > 1) 922 dump_info->lmac_err_id[1] = 923 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 924 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 925 926 dump_data = iwl_fw_error_next_data(dump_data); 927 } 928 929 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 930 /* Dump shared memory configuration */ 931 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 932 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 933 dump_smem_cfg = (void *)dump_data->data; 934 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 935 dump_smem_cfg->num_txfifo_entries = 936 cpu_to_le32(mem_cfg->num_txfifo_entries); 937 for (i = 0; i < MAX_NUM_LMAC; i++) { 938 int j; 939 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 940 941 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 942 dump_smem_cfg->lmac[i].txfifo_size[j] = 943 cpu_to_le32(txf_size[j]); 944 dump_smem_cfg->lmac[i].rxfifo1_size = 945 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 946 } 947 dump_smem_cfg->rxfifo2_size = 948 cpu_to_le32(mem_cfg->rxfifo2_size); 949 dump_smem_cfg->internal_txfifo_addr = 950 cpu_to_le32(mem_cfg->internal_txfifo_addr); 951 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 952 dump_smem_cfg->internal_txfifo_size[i] = 953 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 954 } 955 956 dump_data = iwl_fw_error_next_data(dump_data); 957 } 958 959 /* We only dump the FIFOs if the FW is in error state */ 960 if (fifo_len) { 961 iwl_fw_dump_rxf(fwrt, &dump_data); 962 iwl_fw_dump_txf(fwrt, &dump_data); 963 } 964 965 if (radio_len) 966 iwl_read_radio_regs(fwrt, &dump_data); 967 968 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 969 data->desc) { 970 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 971 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 972 data->desc->len); 973 dump_trig = (void *)dump_data->data; 974 memcpy(dump_trig, &data->desc->trig_desc, 975 sizeof(*dump_trig) + data->desc->len); 976 977 dump_data = iwl_fw_error_next_data(dump_data); 978 } 979 980 /* In case we only want monitor dump, skip to dump trasport data */ 981 if (data->monitor_only) 982 goto out; 983 984 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 985 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 986 fwrt->fw->dbg.mem_tlv; 987 988 if (!fwrt->fw->dbg.n_mem_tlv) 989 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 990 IWL_FW_ERROR_DUMP_MEM_SRAM); 991 992 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 993 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 994 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 995 996 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 997 le32_to_cpu(fw_dbg_mem[i].data_type)); 998 } 999 1000 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1001 fwrt->trans->mac_cfg->base->smem_offset, 1002 IWL_FW_ERROR_DUMP_MEM_SMEM); 1003 1004 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1005 fwrt->trans->cfg->dccm2_offset, 1006 IWL_FW_ERROR_DUMP_MEM_SRAM); 1007 } 1008 1009 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1010 u32 addr = fwrt->trans->mac_cfg->base->d3_debug_data_base_addr; 1011 size_t data_size = fwrt->trans->mac_cfg->base->d3_debug_data_length; 1012 1013 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1014 dump_data->len = cpu_to_le32(data_size * 2); 1015 1016 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1017 1018 kfree(fwrt->dump.d3_debug_data); 1019 fwrt->dump.d3_debug_data = NULL; 1020 1021 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1022 dump_data->data + data_size, 1023 data_size); 1024 1025 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 1026 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 1027 dump_data->data + data_size, 1028 data_size); 1029 1030 dump_data = iwl_fw_error_next_data(dump_data); 1031 } 1032 1033 /* Dump fw's virtual image */ 1034 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1035 iwl_dump_paging(fwrt, &dump_data); 1036 1037 if (prph_len) 1038 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1039 1040 out: 1041 dump_file->file_len = cpu_to_le32(file_len); 1042 return dump_file; 1043 } 1044 1045 /** 1046 * struct iwl_dump_ini_region_data - region data 1047 * @reg_tlv: region TLV 1048 * @dump_data: dump data 1049 */ 1050 struct iwl_dump_ini_region_data { 1051 struct iwl_ucode_tlv *reg_tlv; 1052 struct iwl_fwrt_dump_data *dump_data; 1053 }; 1054 1055 static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt, 1056 void *range_ptr, u32 addr, 1057 __le32 size) 1058 { 1059 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1060 __le32 *val = range->data; 1061 int i; 1062 1063 range->internal_base_addr = cpu_to_le32(addr); 1064 range->range_data_size = size; 1065 for (i = 0; i < le32_to_cpu(size); i += 4) 1066 *val++ = cpu_to_le32(iwl_read_prph(fwrt->trans, addr + i)); 1067 1068 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1069 } 1070 1071 static int 1072 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1073 struct iwl_dump_ini_region_data *reg_data, 1074 void *range_ptr, u32 range_len, int idx) 1075 { 1076 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1077 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1078 le32_to_cpu(reg->dev_addr.offset); 1079 1080 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1081 reg->dev_addr.size); 1082 } 1083 1084 static int 1085 iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime *fwrt, 1086 struct iwl_dump_ini_region_data *reg_data, 1087 void *range_ptr, u32 range_len, int idx) 1088 { 1089 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1090 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1091 u32 addr = le32_to_cpu(reg->dev_addr_range.offset) + 1092 le32_to_cpu(pairs[idx].addr); 1093 1094 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1095 pairs[idx].size); 1096 } 1097 1098 static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt, 1099 void *range_ptr, u32 addr, 1100 __le32 size, __le32 offset) 1101 { 1102 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1103 __le32 *val = range->data; 1104 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1105 u32 indirect_rd_addr = WMAL_MRSPF_1; 1106 u32 prph_val; 1107 u32 dphy_state; 1108 u32 dphy_addr; 1109 u32 prph_stts; 1110 int i; 1111 1112 range->internal_base_addr = cpu_to_le32(addr); 1113 range->range_data_size = size; 1114 1115 if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1116 indirect_wr_addr = WMAL_INDRCT_CMD1; 1117 1118 indirect_wr_addr += le32_to_cpu(offset); 1119 indirect_rd_addr += le32_to_cpu(offset); 1120 1121 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1122 return -EBUSY; 1123 1124 dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1125 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1126 1127 for (i = 0; i < le32_to_cpu(size); i += 4) { 1128 if (dphy_state == HBUS_TIMEOUT || 1129 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1130 WFPM_PHYRF_STATE_ON) { 1131 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1132 continue; 1133 } 1134 1135 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1136 WMAL_INDRCT_CMD(addr + i)); 1137 1138 if (fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_JF1 && 1139 fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_JF2 && 1140 fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_HR1 && 1141 fwrt->trans->info.hw_rf_id != IWL_CFG_RF_TYPE_HR2) { 1142 udelay(2); 1143 prph_stts = iwl_read_prph_no_grab(fwrt->trans, 1144 WMAL_MRSPF_STTS); 1145 1146 /* Abort dump if status is 0xA5A5A5A2 or FIFO1 empty */ 1147 if (prph_stts == WMAL_TIMEOUT_VAL || 1148 !WMAL_MRSPF_STTS_IS_FIFO1_NOT_EMPTY(prph_stts)) 1149 break; 1150 } 1151 1152 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1153 indirect_rd_addr); 1154 *val++ = cpu_to_le32(prph_val); 1155 } 1156 1157 iwl_trans_release_nic_access(fwrt->trans); 1158 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1159 } 1160 1161 static int 1162 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1163 struct iwl_dump_ini_region_data *reg_data, 1164 void *range_ptr, u32 range_len, int idx) 1165 { 1166 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1167 u32 addr = le32_to_cpu(reg->addrs[idx]); 1168 1169 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1170 reg->dev_addr.size, 1171 reg->dev_addr.offset); 1172 } 1173 1174 static int 1175 iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime *fwrt, 1176 struct iwl_dump_ini_region_data *reg_data, 1177 void *range_ptr, u32 range_len, int idx) 1178 { 1179 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1180 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1181 u32 addr = le32_to_cpu(pairs[idx].addr); 1182 1183 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1184 pairs[idx].size, 1185 reg->dev_addr_range.offset); 1186 } 1187 1188 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1189 struct iwl_dump_ini_region_data *reg_data, 1190 void *range_ptr, u32 range_len, int idx) 1191 { 1192 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1193 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1194 __le32 *val = range->data; 1195 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1196 le32_to_cpu(reg->dev_addr.offset); 1197 int i; 1198 1199 range->internal_base_addr = cpu_to_le32(addr); 1200 range->range_data_size = reg->dev_addr.size; 1201 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1202 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1203 1204 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1205 } 1206 1207 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1208 struct iwl_dump_ini_region_data *reg_data, 1209 void *range_ptr, u32 range_len, int idx) 1210 { 1211 struct iwl_trans *trans = fwrt->trans; 1212 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1213 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1214 __le32 *val = range->data; 1215 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1216 le32_to_cpu(reg->dev_addr.offset); 1217 int i; 1218 1219 range->internal_base_addr = cpu_to_le32(addr); 1220 range->range_data_size = reg->dev_addr.size; 1221 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1222 int ret; 1223 u32 tmp; 1224 1225 ret = iwl_trans_read_config32(trans, addr + i, &tmp); 1226 if (ret < 0) 1227 return ret; 1228 1229 *val++ = cpu_to_le32(tmp); 1230 } 1231 1232 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1233 } 1234 1235 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1236 struct iwl_dump_ini_region_data *reg_data, 1237 void *range_ptr, u32 range_len, int idx) 1238 { 1239 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1240 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1241 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1242 le32_to_cpu(reg->dev_addr.offset); 1243 1244 range->internal_base_addr = cpu_to_le32(addr); 1245 range->range_data_size = reg->dev_addr.size; 1246 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1247 le32_to_cpu(reg->dev_addr.size)); 1248 1249 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1250 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1251 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1252 range->data, 1253 le32_to_cpu(reg->dev_addr.size)); 1254 1255 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1256 } 1257 1258 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1259 void *range_ptr, u32 range_len, int idx) 1260 { 1261 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1262 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1263 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1264 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1265 1266 range->page_num = cpu_to_le32(idx); 1267 range->range_data_size = cpu_to_le32(page_size); 1268 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1269 DMA_BIDIRECTIONAL); 1270 memcpy(range->data, page_address(page), page_size); 1271 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1272 DMA_BIDIRECTIONAL); 1273 1274 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1275 } 1276 1277 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1278 struct iwl_dump_ini_region_data *reg_data, 1279 void *range_ptr, u32 range_len, int idx) 1280 { 1281 struct iwl_fw_ini_error_dump_range *range; 1282 u32 page_size; 1283 1284 /* all paged index start from 1 to skip CSS section */ 1285 idx++; 1286 1287 if (!fwrt->trans->mac_cfg->gen2) 1288 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1289 1290 range = range_ptr; 1291 page_size = fwrt->trans->init_dram.paging[idx].size; 1292 1293 range->page_num = cpu_to_le32(idx); 1294 range->range_data_size = cpu_to_le32(page_size); 1295 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1296 page_size); 1297 1298 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1299 } 1300 1301 static int 1302 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1303 struct iwl_dump_ini_region_data *reg_data, 1304 void *range_ptr, u32 range_len, int idx) 1305 { 1306 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1307 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1308 struct iwl_dram_data *frag; 1309 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1310 1311 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1312 1313 range->dram_base_addr = cpu_to_le64(frag->physical); 1314 range->range_data_size = cpu_to_le32(frag->size); 1315 1316 memcpy(range->data, frag->block, frag->size); 1317 1318 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1319 } 1320 1321 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1322 struct iwl_dump_ini_region_data *reg_data, 1323 void *range_ptr, u32 range_len, int idx) 1324 { 1325 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1326 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1327 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1328 1329 range->internal_base_addr = cpu_to_le32(addr); 1330 range->range_data_size = reg->internal_buffer.size; 1331 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1332 le32_to_cpu(reg->internal_buffer.size)); 1333 1334 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1335 } 1336 1337 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1338 struct iwl_dump_ini_region_data *reg_data, int idx) 1339 { 1340 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1341 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1342 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1343 int txf_num = cfg->num_txfifo_entries; 1344 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1345 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1346 1347 if (!idx) { 1348 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1349 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1350 le32_to_cpu(reg->fifos.offset)); 1351 return false; 1352 } 1353 1354 iter->internal_txf = 0; 1355 iter->fifo_size = 0; 1356 iter->fifo = -1; 1357 if (le32_to_cpu(reg->fifos.offset)) 1358 iter->lmac = 1; 1359 else 1360 iter->lmac = 0; 1361 } 1362 1363 if (!iter->internal_txf) { 1364 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1365 iter->fifo_size = 1366 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1367 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1368 return true; 1369 } 1370 iter->fifo--; 1371 } 1372 1373 iter->internal_txf = 1; 1374 1375 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1376 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1377 return false; 1378 1379 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1380 iter->fifo_size = 1381 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1382 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1383 return true; 1384 } 1385 1386 return false; 1387 } 1388 1389 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1390 struct iwl_dump_ini_region_data *reg_data, 1391 void *range_ptr, u32 range_len, int idx) 1392 { 1393 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1394 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1395 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1396 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1397 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1398 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1399 u32 registers_size = registers_num * sizeof(*reg_dump); 1400 __le32 *data; 1401 int i; 1402 1403 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1404 return -EIO; 1405 1406 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1407 return -EBUSY; 1408 1409 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1410 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1411 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1412 1413 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1414 1415 /* 1416 * read txf registers. for each register, write to the dump the 1417 * register address and its value 1418 */ 1419 for (i = 0; i < registers_num; i++) { 1420 addr = le32_to_cpu(reg->addrs[i]) + offs; 1421 1422 reg_dump->addr = cpu_to_le32(addr); 1423 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1424 addr)); 1425 1426 reg_dump++; 1427 } 1428 1429 if (reg->fifos.hdr_only) { 1430 range->range_data_size = cpu_to_le32(registers_size); 1431 goto out; 1432 } 1433 1434 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1435 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1436 TXF_WR_PTR + offs); 1437 1438 /* Dummy-read to advance the read pointer to the head */ 1439 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1440 1441 /* Read FIFO */ 1442 addr = TXF_READ_MODIFY_DATA + offs; 1443 data = (void *)reg_dump; 1444 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1445 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1446 1447 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1448 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1449 reg_dump, iter->fifo_size); 1450 1451 out: 1452 iwl_trans_release_nic_access(fwrt->trans); 1453 1454 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1455 } 1456 1457 static int 1458 iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt, 1459 struct iwl_dump_ini_region_data *reg_data, 1460 void *range_ptr, u32 range_len, int idx) 1461 { 1462 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1463 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1464 __le32 *val = range->data; 1465 __le32 offset = reg->dev_addr.offset; 1466 u32 indirect_rd_wr_addr = DPHYIP_INDIRECT; 1467 u32 addr = le32_to_cpu(reg->addrs[idx]); 1468 u32 dphy_state, dphy_addr, prph_val; 1469 int i; 1470 1471 range->internal_base_addr = cpu_to_le32(addr); 1472 range->range_data_size = reg->dev_addr.size; 1473 1474 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1475 return -EBUSY; 1476 1477 indirect_rd_wr_addr += le32_to_cpu(offset); 1478 1479 dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1480 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1481 1482 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1483 if (dphy_state == HBUS_TIMEOUT || 1484 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1485 WFPM_PHYRF_STATE_ON) { 1486 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1487 continue; 1488 } 1489 1490 iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr, 1491 addr + i); 1492 /* wait a bit for value to be ready in register */ 1493 udelay(1); 1494 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1495 indirect_rd_wr_addr); 1496 *val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >> 1497 DPHYIP_INDIRECT_RD_SHIFT); 1498 } 1499 1500 iwl_trans_release_nic_access(fwrt->trans); 1501 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1502 } 1503 1504 struct iwl_ini_rxf_data { 1505 u32 fifo_num; 1506 u32 size; 1507 u32 offset; 1508 }; 1509 1510 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1511 struct iwl_dump_ini_region_data *reg_data, 1512 struct iwl_ini_rxf_data *data) 1513 { 1514 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1515 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1516 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1517 u8 fifo_idx; 1518 1519 if (!data) 1520 return; 1521 1522 memset(data, 0, sizeof(*data)); 1523 1524 /* make sure only one bit is set in only one fid */ 1525 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1526 "fid1=%x, fid2=%x\n", fid1, fid2)) 1527 return; 1528 1529 if (fid1) { 1530 fifo_idx = ffs(fid1) - 1; 1531 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1532 fifo_idx)) 1533 return; 1534 1535 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1536 data->fifo_num = fifo_idx; 1537 } else { 1538 u8 max_idx; 1539 1540 fifo_idx = ffs(fid2) - 1; 1541 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1542 SHARED_MEM_CFG_CMD, 0) <= 3) 1543 max_idx = 0; 1544 else 1545 max_idx = 1; 1546 1547 if (WARN_ONCE(fifo_idx > max_idx, 1548 "invalid umac fifo idx %d", fifo_idx)) 1549 return; 1550 1551 /* use bit 31 to distinguish between umac and lmac rxf while 1552 * parsing the dump 1553 */ 1554 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1555 1556 switch (fifo_idx) { 1557 case 0: 1558 data->size = fwrt->smem_cfg.rxfifo2_size; 1559 data->offset = iwl_umac_prph(fwrt->trans, 1560 RXF_DIFF_FROM_PREV); 1561 break; 1562 case 1: 1563 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1564 data->offset = iwl_umac_prph(fwrt->trans, 1565 RXF2C_DIFF_FROM_PREV); 1566 break; 1567 } 1568 } 1569 } 1570 1571 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1572 struct iwl_dump_ini_region_data *reg_data, 1573 void *range_ptr, u32 range_len, int idx) 1574 { 1575 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1576 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1577 struct iwl_ini_rxf_data rxf_data; 1578 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1579 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1580 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1581 u32 registers_size = registers_num * sizeof(*reg_dump); 1582 __le32 *data; 1583 int i; 1584 1585 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1586 if (!rxf_data.size) 1587 return -EIO; 1588 1589 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1590 return -EBUSY; 1591 1592 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1593 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1594 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1595 1596 /* 1597 * read rxf registers. for each register, write to the dump the 1598 * register address and its value 1599 */ 1600 for (i = 0; i < registers_num; i++) { 1601 addr = le32_to_cpu(reg->addrs[i]) + offs; 1602 1603 reg_dump->addr = cpu_to_le32(addr); 1604 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1605 addr)); 1606 1607 reg_dump++; 1608 } 1609 1610 if (reg->fifos.hdr_only) { 1611 range->range_data_size = cpu_to_le32(registers_size); 1612 goto out; 1613 } 1614 1615 offs = rxf_data.offset; 1616 1617 /* Lock fence */ 1618 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1619 /* Set fence pointer to the same place like WR pointer */ 1620 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1621 /* Set fence offset */ 1622 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1623 0x0); 1624 1625 /* Read FIFO */ 1626 addr = RXF_FIFO_RD_FENCE_INC + offs; 1627 data = (void *)reg_dump; 1628 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1629 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1630 1631 out: 1632 iwl_trans_release_nic_access(fwrt->trans); 1633 1634 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1635 } 1636 1637 static int 1638 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1639 struct iwl_dump_ini_region_data *reg_data, 1640 void *range_ptr, u32 range_len, int idx) 1641 { 1642 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1643 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1644 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1645 u32 addr = le32_to_cpu(err_table->base_addr) + 1646 le32_to_cpu(err_table->offset); 1647 1648 range->internal_base_addr = cpu_to_le32(addr); 1649 range->range_data_size = err_table->size; 1650 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1651 le32_to_cpu(err_table->size)); 1652 1653 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1654 } 1655 1656 static int 1657 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1658 struct iwl_dump_ini_region_data *reg_data, 1659 void *range_ptr, u32 range_len, int idx) 1660 { 1661 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1662 struct iwl_fw_ini_region_special_device_memory *special_mem = 1663 ®->special_mem; 1664 1665 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1666 u32 addr = le32_to_cpu(special_mem->base_addr) + 1667 le32_to_cpu(special_mem->offset); 1668 1669 range->internal_base_addr = cpu_to_le32(addr); 1670 range->range_data_size = special_mem->size; 1671 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1672 le32_to_cpu(special_mem->size)); 1673 1674 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1675 } 1676 1677 static int 1678 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1679 struct iwl_dump_ini_region_data *reg_data, 1680 void *range_ptr, u32 range_len, int idx) 1681 { 1682 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1683 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1684 __le32 *val = range->data; 1685 u32 prph_data; 1686 int i; 1687 1688 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1689 return -EBUSY; 1690 1691 range->range_data_size = reg->dev_addr.size; 1692 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1693 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1694 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1695 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1696 if (iwl_trans_is_hw_error_value(prph_data)) { 1697 iwl_trans_release_nic_access(fwrt->trans); 1698 return -EBUSY; 1699 } 1700 *val++ = cpu_to_le32(prph_data); 1701 } 1702 iwl_trans_release_nic_access(fwrt->trans); 1703 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1704 } 1705 1706 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1707 struct iwl_dump_ini_region_data *reg_data, 1708 void *range_ptr, u32 range_len, int idx) 1709 { 1710 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1711 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1712 u32 pkt_len; 1713 1714 if (!pkt) 1715 return -EIO; 1716 1717 pkt_len = iwl_rx_packet_payload_len(pkt); 1718 1719 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1720 range->range_data_size = cpu_to_le32(pkt_len); 1721 1722 memcpy(range->data, pkt->data, pkt_len); 1723 1724 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1725 } 1726 1727 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1728 struct iwl_dump_ini_region_data *reg_data, 1729 void *range_ptr, u32 range_len, int idx) 1730 { 1731 /* read the IMR memory and DMA it to SRAM */ 1732 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1733 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1734 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1735 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1736 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1737 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1738 1739 range->range_data_size = cpu_to_le32(size_to_dump); 1740 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1741 imr_curr_addr, size_to_dump)) { 1742 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1743 return -1; 1744 } 1745 1746 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1747 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1748 1749 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1750 size_to_dump); 1751 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1752 } 1753 1754 static void * 1755 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1756 struct iwl_dump_ini_region_data *reg_data, 1757 void *data, u32 data_len) 1758 { 1759 struct iwl_fw_ini_error_dump *dump = data; 1760 1761 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1762 1763 return dump->data; 1764 } 1765 1766 /** 1767 * mask_apply_and_normalize - applies mask on val and normalize the result 1768 * 1769 * @val: value 1770 * @mask: mask to apply and to normalize with 1771 * 1772 * The normalization is based on the first set bit in the mask 1773 * 1774 * Returns: the extracted value 1775 */ 1776 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1777 { 1778 return (val & mask) >> (ffs(mask) - 1); 1779 } 1780 1781 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1782 const struct iwl_fw_mon_reg *reg_info) 1783 { 1784 u32 val, offs; 1785 1786 /* The header addresses of DBGCi is calculate as follows: 1787 * DBGC1 address + (0x100 * i) 1788 */ 1789 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1790 1791 if (!reg_info || !reg_info->addr || !reg_info->mask) 1792 return 0; 1793 1794 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1795 1796 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1797 } 1798 1799 static void * 1800 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1801 struct iwl_fw_ini_monitor_dump *data, 1802 const struct iwl_fw_mon_regs *addrs) 1803 { 1804 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1805 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1806 return NULL; 1807 } 1808 1809 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1810 &addrs->write_ptr); 1811 if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1812 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1813 1814 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1815 } 1816 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1817 &addrs->cycle_cnt); 1818 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1819 &addrs->cur_frag); 1820 1821 iwl_trans_release_nic_access(fwrt->trans); 1822 1823 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1824 1825 return data->data; 1826 } 1827 1828 static void * 1829 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1830 struct iwl_dump_ini_region_data *reg_data, 1831 void *data, u32 data_len) 1832 { 1833 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1834 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1835 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1836 1837 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1838 &fwrt->trans->mac_cfg->base->mon_dram_regs); 1839 } 1840 1841 static void * 1842 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1843 struct iwl_dump_ini_region_data *reg_data, 1844 void *data, u32 data_len) 1845 { 1846 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1847 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1848 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1849 1850 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1851 &fwrt->trans->mac_cfg->base->mon_smem_regs); 1852 } 1853 1854 static void * 1855 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1856 struct iwl_dump_ini_region_data *reg_data, 1857 void *data, u32 data_len) 1858 { 1859 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1860 1861 return iwl_dump_ini_mon_fill_header(fwrt, 1862 /* no offset calculation later */ 1863 IWL_FW_INI_ALLOCATION_ID_DBGC1, 1864 mon_dump, 1865 &fwrt->trans->mac_cfg->base->mon_dbgi_regs); 1866 } 1867 1868 static void * 1869 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1870 struct iwl_dump_ini_region_data *reg_data, 1871 void *data, u32 data_len) 1872 { 1873 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1874 struct iwl_fw_ini_err_table_dump *dump = data; 1875 1876 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1877 dump->version = reg->err_table.version; 1878 1879 return dump->data; 1880 } 1881 1882 static void * 1883 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1884 struct iwl_dump_ini_region_data *reg_data, 1885 void *data, u32 data_len) 1886 { 1887 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1888 struct iwl_fw_ini_special_device_memory *dump = data; 1889 1890 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1891 dump->type = reg->special_mem.type; 1892 dump->version = reg->special_mem.version; 1893 1894 return dump->data; 1895 } 1896 1897 static void * 1898 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1899 struct iwl_dump_ini_region_data *reg_data, 1900 void *data, u32 data_len) 1901 { 1902 struct iwl_fw_ini_error_dump *dump = data; 1903 1904 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1905 1906 return dump->data; 1907 } 1908 1909 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1910 struct iwl_dump_ini_region_data *reg_data) 1911 { 1912 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1913 1914 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1915 } 1916 1917 static u32 1918 iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime *fwrt, 1919 struct iwl_dump_ini_region_data *reg_data) 1920 { 1921 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1922 size_t size = sizeof(struct iwl_fw_ini_addr_size); 1923 1924 return iwl_tlv_array_len_with_size(reg_data->reg_tlv, reg, size); 1925 } 1926 1927 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1928 struct iwl_dump_ini_region_data *reg_data) 1929 { 1930 if (fwrt->trans->mac_cfg->gen2) { 1931 if (fwrt->trans->init_dram.paging_cnt) 1932 return fwrt->trans->init_dram.paging_cnt - 1; 1933 else 1934 return 0; 1935 } 1936 1937 return fwrt->num_of_paging_blk; 1938 } 1939 1940 static u32 1941 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1942 struct iwl_dump_ini_region_data *reg_data) 1943 { 1944 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1945 struct iwl_fw_mon *fw_mon; 1946 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1947 int i; 1948 1949 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1950 1951 for (i = 0; i < fw_mon->num_frags; i++) { 1952 if (!fw_mon->frags[i].size) 1953 break; 1954 1955 ranges++; 1956 } 1957 1958 return ranges; 1959 } 1960 1961 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1962 struct iwl_dump_ini_region_data *reg_data) 1963 { 1964 u32 num_of_fifos = 0; 1965 1966 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1967 num_of_fifos++; 1968 1969 return num_of_fifos; 1970 } 1971 1972 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1973 struct iwl_dump_ini_region_data *reg_data) 1974 { 1975 return 1; 1976 } 1977 1978 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1979 struct iwl_dump_ini_region_data *reg_data) 1980 { 1981 /* range is total number of pages need to copied from 1982 *IMR memory to SRAM and later from SRAM to DRAM 1983 */ 1984 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1985 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1986 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1987 1988 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1989 IWL_DEBUG_INFO(fwrt, 1990 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1991 imr_enable, imr_size, sram_size); 1992 return 0; 1993 } 1994 1995 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1996 } 1997 1998 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1999 struct iwl_dump_ini_region_data *reg_data) 2000 { 2001 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2002 u32 size = le32_to_cpu(reg->dev_addr.size); 2003 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 2004 2005 if (!size || !ranges) 2006 return 0; 2007 2008 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 2009 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 2010 } 2011 2012 static u32 2013 iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime *fwrt, 2014 struct iwl_dump_ini_region_data *reg_data) 2015 { 2016 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2017 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 2018 u32 ranges = iwl_dump_ini_mem_block_ranges(fwrt, reg_data); 2019 u32 size = sizeof(struct iwl_fw_ini_error_dump); 2020 int range; 2021 2022 if (!ranges) 2023 return 0; 2024 2025 for (range = 0; range < ranges; range++) 2026 size += le32_to_cpu(pairs[range].size); 2027 2028 return size + ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2029 } 2030 2031 static u32 2032 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 2033 struct iwl_dump_ini_region_data *reg_data) 2034 { 2035 int i; 2036 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 2037 u32 size = sizeof(struct iwl_fw_ini_error_dump); 2038 2039 /* start from 1 to skip CSS section */ 2040 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 2041 size += range_header_len; 2042 if (fwrt->trans->mac_cfg->gen2) 2043 size += fwrt->trans->init_dram.paging[i].size; 2044 else 2045 size += fwrt->fw_paging_db[i].fw_paging_size; 2046 } 2047 2048 return size; 2049 } 2050 2051 static u32 2052 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 2053 struct iwl_dump_ini_region_data *reg_data) 2054 { 2055 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2056 struct iwl_fw_mon *fw_mon; 2057 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 2058 int i; 2059 2060 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 2061 2062 for (i = 0; i < fw_mon->num_frags; i++) { 2063 struct iwl_dram_data *frag = &fw_mon->frags[i]; 2064 2065 if (!frag->size) 2066 break; 2067 2068 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 2069 } 2070 2071 if (size) 2072 size += sizeof(struct iwl_fw_ini_monitor_dump); 2073 2074 return size; 2075 } 2076 2077 static u32 2078 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 2079 struct iwl_dump_ini_region_data *reg_data) 2080 { 2081 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2082 u32 size; 2083 2084 size = le32_to_cpu(reg->internal_buffer.size); 2085 if (!size) 2086 return 0; 2087 2088 size += sizeof(struct iwl_fw_ini_monitor_dump) + 2089 sizeof(struct iwl_fw_ini_error_dump_range); 2090 2091 return size; 2092 } 2093 2094 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 2095 struct iwl_dump_ini_region_data *reg_data) 2096 { 2097 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2098 u32 size = le32_to_cpu(reg->dev_addr.size); 2099 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 2100 2101 if (!size || !ranges) 2102 return 0; 2103 2104 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 2105 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 2106 } 2107 2108 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 2109 struct iwl_dump_ini_region_data *reg_data) 2110 { 2111 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2112 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 2113 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2114 u32 size = 0; 2115 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 2116 registers_num * 2117 sizeof(struct iwl_fw_ini_error_dump_register); 2118 2119 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 2120 size += fifo_hdr; 2121 if (!reg->fifos.hdr_only) 2122 size += iter->fifo_size; 2123 } 2124 2125 if (!size) 2126 return 0; 2127 2128 return size + sizeof(struct iwl_fw_ini_error_dump); 2129 } 2130 2131 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 2132 struct iwl_dump_ini_region_data *reg_data) 2133 { 2134 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2135 struct iwl_ini_rxf_data rx_data; 2136 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2137 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 2138 sizeof(struct iwl_fw_ini_error_dump_range) + 2139 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 2140 2141 if (reg->fifos.hdr_only) 2142 return size; 2143 2144 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 2145 size += rx_data.size; 2146 2147 return size; 2148 } 2149 2150 static u32 2151 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 2152 struct iwl_dump_ini_region_data *reg_data) 2153 { 2154 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2155 u32 size = le32_to_cpu(reg->err_table.size); 2156 2157 if (size) 2158 size += sizeof(struct iwl_fw_ini_err_table_dump) + 2159 sizeof(struct iwl_fw_ini_error_dump_range); 2160 2161 return size; 2162 } 2163 2164 static u32 2165 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2166 struct iwl_dump_ini_region_data *reg_data) 2167 { 2168 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2169 u32 size = le32_to_cpu(reg->special_mem.size); 2170 2171 if (size) 2172 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2173 sizeof(struct iwl_fw_ini_error_dump_range); 2174 2175 return size; 2176 } 2177 2178 static u32 2179 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2180 struct iwl_dump_ini_region_data *reg_data) 2181 { 2182 u32 size = 0; 2183 2184 if (!reg_data->dump_data->fw_pkt) 2185 return 0; 2186 2187 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2188 if (size) 2189 size += sizeof(struct iwl_fw_ini_error_dump) + 2190 sizeof(struct iwl_fw_ini_error_dump_range); 2191 2192 return size; 2193 } 2194 2195 static u32 2196 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2197 struct iwl_dump_ini_region_data *reg_data) 2198 { 2199 u32 ranges = 0; 2200 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2201 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2202 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2203 2204 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2205 IWL_DEBUG_INFO(fwrt, 2206 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2207 imr_enable, imr_size, sram_size); 2208 return 0; 2209 } 2210 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2211 if (!ranges) { 2212 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges); 2213 return 0; 2214 } 2215 imr_size += sizeof(struct iwl_fw_ini_error_dump) + 2216 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2217 return imr_size; 2218 } 2219 2220 /** 2221 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2222 * @get_num_of_ranges: returns the number of memory ranges in the region. 2223 * @get_size: returns the total size of the region. 2224 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2225 * the first range or NULL if failed to fill headers. 2226 * @fill_range: copies a given memory range into the dump. 2227 * Returns the size of the range or negative error value otherwise. 2228 */ 2229 struct iwl_dump_ini_mem_ops { 2230 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2231 struct iwl_dump_ini_region_data *reg_data); 2232 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2233 struct iwl_dump_ini_region_data *reg_data); 2234 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2235 struct iwl_dump_ini_region_data *reg_data, 2236 void *data, u32 data_len); 2237 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2238 struct iwl_dump_ini_region_data *reg_data, 2239 void *range, u32 range_len, int idx); 2240 }; 2241 2242 /** 2243 * iwl_dump_ini_mem - dump memory region 2244 * 2245 * @fwrt: fw runtime struct 2246 * @list: list to add the dump tlv to 2247 * @reg_data: memory region 2248 * @ops: memory dump operations 2249 * 2250 * Creates a dump tlv and copy a memory region into it. 2251 * 2252 * Returns: the size of the current dump tlv or 0 if failed 2253 */ 2254 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2255 struct iwl_dump_ini_region_data *reg_data, 2256 const struct iwl_dump_ini_mem_ops *ops) 2257 { 2258 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2259 struct iwl_fw_ini_dump_entry *entry; 2260 struct iwl_fw_ini_error_dump_data *tlv; 2261 struct iwl_fw_ini_error_dump_header *header; 2262 u32 type = reg->type; 2263 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK); 2264 u32 num_of_ranges, i, size; 2265 u8 *range; 2266 u32 free_size; 2267 u64 header_size; 2268 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE; 2269 2270 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n", 2271 dump_policy, id, type); 2272 2273 if (le32_to_cpu(reg->hdr.version) >= 2) { 2274 u32 dp = le32_get_bits(reg->id, 2275 IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2276 2277 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE && 2278 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) { 2279 IWL_DEBUG_FW(fwrt, 2280 "WRT: no dump - type %d and policy mismatch=%d\n", 2281 dump_policy, dp); 2282 return 0; 2283 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM && 2284 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) { 2285 IWL_DEBUG_FW(fwrt, 2286 "WRT: no dump - type %d and policy mismatch=%d\n", 2287 dump_policy, dp); 2288 return 0; 2289 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF && 2290 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) { 2291 IWL_DEBUG_FW(fwrt, 2292 "WRT: no dump - type %d and policy mismatch=%d\n", 2293 dump_policy, dp); 2294 return 0; 2295 } 2296 } 2297 2298 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2299 !ops->fill_range) { 2300 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2301 return 0; 2302 } 2303 2304 size = ops->get_size(fwrt, reg_data); 2305 2306 if (size < sizeof(*header)) { 2307 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2308 return 0; 2309 } 2310 2311 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2312 if (!entry) 2313 return 0; 2314 2315 entry->size = sizeof(*tlv) + size; 2316 2317 tlv = (void *)entry->data; 2318 tlv->type = reg->type; 2319 tlv->sub_type = reg->sub_type; 2320 tlv->sub_type_ver = reg->sub_type_ver; 2321 tlv->reserved = reg->reserved; 2322 tlv->len = cpu_to_le32(size); 2323 2324 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2325 2326 header = (void *)tlv->data; 2327 header->region_id = cpu_to_le32(id); 2328 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2329 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2330 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2331 2332 free_size = size; 2333 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2334 if (!range) { 2335 IWL_ERR(fwrt, 2336 "WRT: Failed to fill region header: id=%d, type=%d\n", 2337 id, type); 2338 goto out_err; 2339 } 2340 2341 header_size = range - (u8 *)header; 2342 2343 if (WARN(header_size > free_size, 2344 "header size %llu > free_size %d", 2345 header_size, free_size)) { 2346 IWL_ERR(fwrt, 2347 "WRT: fill_mem_hdr used more than given free_size\n"); 2348 goto out_err; 2349 } 2350 2351 free_size -= header_size; 2352 2353 for (i = 0; i < num_of_ranges; i++) { 2354 int range_size = ops->fill_range(fwrt, reg_data, range, 2355 free_size, i); 2356 2357 if (range_size < 0) { 2358 IWL_ERR(fwrt, 2359 "WRT: Failed to dump region: id=%d, type=%d\n", 2360 id, type); 2361 goto out_err; 2362 } 2363 2364 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2365 range_size, free_size)) { 2366 IWL_ERR(fwrt, 2367 "WRT: fill_raged used more than given free_size\n"); 2368 goto out_err; 2369 } 2370 2371 free_size -= range_size; 2372 range = range + range_size; 2373 } 2374 2375 list_add_tail(&entry->list, list); 2376 2377 return entry->size; 2378 2379 out_err: 2380 vfree(entry); 2381 2382 return 0; 2383 } 2384 2385 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2386 struct iwl_fw_ini_trigger_tlv *trigger, 2387 struct list_head *list) 2388 { 2389 struct iwl_fw_ini_dump_entry *entry; 2390 struct iwl_fw_error_dump_data *tlv; 2391 struct iwl_fw_ini_dump_info *dump; 2392 struct iwl_dbg_tlv_node *node; 2393 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2394 u32 size = sizeof(*tlv) + sizeof(*dump); 2395 u32 num_of_cfg_names = 0; 2396 u32 hw_type, is_cdb; 2397 2398 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2399 size += sizeof(*cfg_name); 2400 num_of_cfg_names++; 2401 } 2402 2403 entry = vzalloc(sizeof(*entry) + size); 2404 if (!entry) 2405 return 0; 2406 2407 entry->size = size; 2408 2409 tlv = (void *)entry->data; 2410 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2411 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2412 2413 dump = (void *)tlv->data; 2414 2415 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2416 dump->time_point = trigger->time_point; 2417 dump->trigger_reason = trigger->trigger_reason; 2418 dump->external_cfg_state = 2419 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2420 2421 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2422 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2423 2424 dump->hw_step = cpu_to_le32(fwrt->trans->info.hw_rev_step); 2425 2426 hw_type = CSR_HW_REV_TYPE(fwrt->trans->info.hw_rev); 2427 2428 is_cdb = CSR_HW_RFID_IS_CDB(fwrt->trans->info.hw_rf_id); 2429 hw_type |= IWL_CDB_MASK(is_cdb); 2430 2431 dump->hw_type = cpu_to_le32(hw_type); 2432 2433 dump->rf_id_flavor = 2434 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->info.hw_rf_id)); 2435 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->info.hw_rf_id)); 2436 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->info.hw_rf_id)); 2437 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->info.hw_rf_id)); 2438 2439 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2440 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2441 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2442 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2443 2444 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2445 dump->regions_mask = trigger->regions_mask & 2446 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2447 2448 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2449 memcpy(dump->build_tag, fwrt->fw->human_readable, 2450 sizeof(dump->build_tag)); 2451 2452 cfg_name = dump->cfg_names; 2453 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2454 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2455 struct iwl_fw_ini_debug_info_tlv *debug_info = 2456 (void *)node->tlv.data; 2457 2458 BUILD_BUG_ON(sizeof(cfg_name->cfg_name) != 2459 sizeof(debug_info->debug_cfg_name)); 2460 2461 cfg_name->image_type = debug_info->image_type; 2462 cfg_name->cfg_name_len = 2463 cpu_to_le32(sizeof(cfg_name->cfg_name)); 2464 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2465 sizeof(cfg_name->cfg_name)); 2466 cfg_name++; 2467 } 2468 2469 /* add dump info TLV to the beginning of the list since it needs to be 2470 * the first TLV in the dump 2471 */ 2472 list_add(&entry->list, list); 2473 2474 return entry->size; 2475 } 2476 2477 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2478 [IWL_FW_INI_REGION_INVALID] = {}, 2479 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2480 .get_num_of_ranges = iwl_dump_ini_single_range, 2481 .get_size = iwl_dump_ini_mon_smem_get_size, 2482 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2483 .fill_range = iwl_dump_ini_mon_smem_iter, 2484 }, 2485 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2486 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2487 .get_size = iwl_dump_ini_mon_dram_get_size, 2488 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2489 .fill_range = iwl_dump_ini_mon_dram_iter, 2490 }, 2491 [IWL_FW_INI_REGION_TXF] = { 2492 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2493 .get_size = iwl_dump_ini_txf_get_size, 2494 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2495 .fill_range = iwl_dump_ini_txf_iter, 2496 }, 2497 [IWL_FW_INI_REGION_RXF] = { 2498 .get_num_of_ranges = iwl_dump_ini_single_range, 2499 .get_size = iwl_dump_ini_rxf_get_size, 2500 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2501 .fill_range = iwl_dump_ini_rxf_iter, 2502 }, 2503 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2504 .get_num_of_ranges = iwl_dump_ini_single_range, 2505 .get_size = iwl_dump_ini_err_table_get_size, 2506 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2507 .fill_range = iwl_dump_ini_err_table_iter, 2508 }, 2509 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2510 .get_num_of_ranges = iwl_dump_ini_single_range, 2511 .get_size = iwl_dump_ini_err_table_get_size, 2512 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2513 .fill_range = iwl_dump_ini_err_table_iter, 2514 }, 2515 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2516 .get_num_of_ranges = iwl_dump_ini_single_range, 2517 .get_size = iwl_dump_ini_fw_pkt_get_size, 2518 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2519 .fill_range = iwl_dump_ini_fw_pkt_iter, 2520 }, 2521 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2522 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2523 .get_size = iwl_dump_ini_mem_get_size, 2524 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2525 .fill_range = iwl_dump_ini_dev_mem_iter, 2526 }, 2527 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2528 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2529 .get_size = iwl_dump_ini_mem_get_size, 2530 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2531 .fill_range = iwl_dump_ini_prph_mac_iter, 2532 }, 2533 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2534 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2535 .get_size = iwl_dump_ini_mem_get_size, 2536 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2537 .fill_range = iwl_dump_ini_prph_phy_iter, 2538 }, 2539 [IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE] = { 2540 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2541 .get_size = iwl_dump_ini_mem_block_get_size, 2542 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2543 .fill_range = iwl_dump_ini_prph_mac_block_iter, 2544 }, 2545 [IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE] = { 2546 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2547 .get_size = iwl_dump_ini_mem_block_get_size, 2548 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2549 .fill_range = iwl_dump_ini_prph_phy_block_iter, 2550 }, 2551 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2552 [IWL_FW_INI_REGION_PAGING] = { 2553 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2554 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2555 .get_size = iwl_dump_ini_paging_get_size, 2556 .fill_range = iwl_dump_ini_paging_iter, 2557 }, 2558 [IWL_FW_INI_REGION_CSR] = { 2559 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2560 .get_size = iwl_dump_ini_mem_get_size, 2561 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2562 .fill_range = iwl_dump_ini_csr_iter, 2563 }, 2564 [IWL_FW_INI_REGION_DRAM_IMR] = { 2565 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2566 .get_size = iwl_dump_ini_imr_get_size, 2567 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2568 .fill_range = iwl_dump_ini_imr_iter, 2569 }, 2570 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2571 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2572 .get_size = iwl_dump_ini_mem_get_size, 2573 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2574 .fill_range = iwl_dump_ini_config_iter, 2575 }, 2576 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2577 .get_num_of_ranges = iwl_dump_ini_single_range, 2578 .get_size = iwl_dump_ini_special_mem_get_size, 2579 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2580 .fill_range = iwl_dump_ini_special_mem_iter, 2581 }, 2582 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2583 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2584 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2585 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2586 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2587 }, 2588 [IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = { 2589 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2590 .get_size = iwl_dump_ini_mem_get_size, 2591 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2592 .fill_range = iwl_dump_ini_prph_snps_dphyip_iter, 2593 }, 2594 }; 2595 2596 enum iwl_dump_ini_region_selector { 2597 IWL_INI_DUMP_ALL_REGIONS, 2598 IWL_INI_DUMP_EARLY_REGIONS, 2599 IWL_INI_DUMP_LATE_REGIONS, 2600 }; 2601 2602 static bool iwl_dump_due_to_error(enum iwl_fw_ini_time_point tp_id) 2603 { 2604 return tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT || 2605 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR; 2606 } 2607 2608 static u32 2609 iwl_dump_ini_dump_regions(struct iwl_fw_runtime *fwrt, 2610 struct iwl_fwrt_dump_data *dump_data, 2611 struct list_head *list, 2612 enum iwl_fw_ini_time_point tp_id, 2613 u64 regions_mask, 2614 struct iwl_dump_ini_region_data *imr_reg_data, 2615 enum iwl_dump_ini_region_selector which) 2616 { 2617 u32 size = 0; 2618 2619 for (int i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2620 struct iwl_dump_ini_region_data reg_data = { 2621 .dump_data = dump_data, 2622 }; 2623 u32 reg_type, dp; 2624 struct iwl_fw_ini_region_tlv *reg; 2625 2626 if (!(BIT_ULL(i) & regions_mask)) 2627 continue; 2628 2629 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2630 if (!reg_data.reg_tlv) { 2631 IWL_WARN(fwrt, 2632 "WRT: Unassigned region id %d, skipping\n", i); 2633 continue; 2634 } 2635 2636 reg = (void *)reg_data.reg_tlv->data; 2637 reg_type = reg->type; 2638 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2639 continue; 2640 2641 dp = le32_get_bits(reg->id, IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2642 2643 if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2644 reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE || 2645 reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) && 2646 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2647 IWL_WARN(fwrt, 2648 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2649 tp_id); 2650 continue; 2651 } 2652 2653 switch (which) { 2654 case IWL_INI_DUMP_ALL_REGIONS: 2655 break; 2656 case IWL_INI_DUMP_EARLY_REGIONS: 2657 if (!(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_BEFORE_RESET)) 2658 continue; 2659 break; 2660 case IWL_INI_DUMP_LATE_REGIONS: 2661 if (dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_BEFORE_RESET) 2662 continue; 2663 break; 2664 } 2665 2666 /* 2667 * DRAM_IMR can be collected only for FW/HW error timepoint 2668 * when fw is not alive. In addition, it must be collected 2669 * lastly as it overwrites SRAM that can possibly contain 2670 * debug data which also need to be collected. 2671 */ 2672 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { 2673 if (iwl_dump_due_to_error(tp_id)) 2674 imr_reg_data->reg_tlv = 2675 fwrt->trans->dbg.active_regions[i]; 2676 else 2677 IWL_INFO(fwrt, 2678 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n", 2679 tp_id); 2680 /* continue to next region */ 2681 continue; 2682 } 2683 2684 2685 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2686 &iwl_dump_ini_region_ops[reg_type]); 2687 } 2688 2689 return size; 2690 } 2691 2692 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2693 struct iwl_fwrt_dump_data *dump_data, 2694 struct list_head *list) 2695 { 2696 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2697 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2698 struct iwl_dump_ini_region_data imr_reg_data = { 2699 .dump_data = dump_data, 2700 }; 2701 u32 size = 0; 2702 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2703 ~(fwrt->trans->dbg.unsupported_region_msk); 2704 2705 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2706 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2707 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2708 2709 if (trigger->apply_policy & 2710 cpu_to_le32(IWL_FW_INI_APPLY_POLICY_SPLIT_DUMP_RESET)) { 2711 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id, 2712 regions_mask, &imr_reg_data, 2713 IWL_INI_DUMP_EARLY_REGIONS); 2714 iwl_trans_pcie_fw_reset_handshake(fwrt->trans); 2715 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id, 2716 regions_mask, &imr_reg_data, 2717 IWL_INI_DUMP_LATE_REGIONS); 2718 } else { 2719 if (fw_has_capa(&fwrt->fw->ucode_capa, 2720 IWL_UCODE_TLV_CAPA_RESET_DURING_ASSERT) && 2721 iwl_dump_due_to_error(tp_id)) 2722 iwl_trans_pcie_fw_reset_handshake(fwrt->trans); 2723 size += iwl_dump_ini_dump_regions(fwrt, dump_data, list, tp_id, 2724 regions_mask, &imr_reg_data, 2725 IWL_INI_DUMP_ALL_REGIONS); 2726 } 2727 /* collect DRAM_IMR region in the last */ 2728 if (imr_reg_data.reg_tlv) 2729 size += iwl_dump_ini_mem(fwrt, list, &imr_reg_data, 2730 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]); 2731 2732 if (size) { 2733 size += iwl_dump_ini_info(fwrt, trigger, list); 2734 } 2735 2736 return size; 2737 } 2738 2739 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2740 struct iwl_fw_ini_trigger_tlv *trig) 2741 { 2742 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2743 u32 usec = le32_to_cpu(trig->ignore_consec); 2744 2745 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2746 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2747 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2748 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2749 return false; 2750 2751 return true; 2752 } 2753 2754 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2755 struct iwl_fwrt_dump_data *dump_data, 2756 struct list_head *list) 2757 { 2758 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2759 struct iwl_fw_ini_dump_entry *entry; 2760 struct iwl_fw_ini_dump_file_hdr *hdr; 2761 u32 size; 2762 2763 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2764 !le64_to_cpu(trigger->regions_mask)) 2765 return 0; 2766 2767 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2768 if (!entry) 2769 return 0; 2770 2771 entry->size = sizeof(*hdr); 2772 2773 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2774 if (!size) { 2775 vfree(entry); 2776 return 0; 2777 } 2778 2779 hdr = (void *)entry->data; 2780 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2781 hdr->file_len = cpu_to_le32(size + entry->size); 2782 2783 list_add(&entry->list, list); 2784 2785 return le32_to_cpu(hdr->file_len); 2786 } 2787 2788 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2789 const struct iwl_fw_dump_desc *desc) 2790 { 2791 if (desc && desc != &iwl_dump_desc_assert) 2792 kfree(desc); 2793 2794 fwrt->dump.lmac_err_id[0] = 0; 2795 if (fwrt->smem_cfg.num_lmacs > 1) 2796 fwrt->dump.lmac_err_id[1] = 0; 2797 fwrt->dump.umac_err_id = 0; 2798 } 2799 2800 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2801 struct iwl_fwrt_dump_data *dump_data) 2802 { 2803 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2804 struct iwl_fw_error_dump_file *dump_file; 2805 struct scatterlist *sg_dump_data; 2806 u32 file_len; 2807 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2808 2809 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2810 if (!dump_file) 2811 return; 2812 2813 if (dump_data->monitor_only) 2814 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2815 2816 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2817 fwrt->sanitize_ops, 2818 fwrt->sanitize_ctx); 2819 file_len = le32_to_cpu(dump_file->file_len); 2820 fw_error_dump.fwrt_len = file_len; 2821 2822 if (fw_error_dump.trans_ptr) { 2823 file_len += fw_error_dump.trans_ptr->len; 2824 dump_file->file_len = cpu_to_le32(file_len); 2825 } 2826 2827 sg_dump_data = alloc_sgtable(file_len); 2828 if (sg_dump_data) { 2829 sg_pcopy_from_buffer(sg_dump_data, 2830 sg_nents(sg_dump_data), 2831 fw_error_dump.fwrt_ptr, 2832 fw_error_dump.fwrt_len, 0); 2833 if (fw_error_dump.trans_ptr) 2834 sg_pcopy_from_buffer(sg_dump_data, 2835 sg_nents(sg_dump_data), 2836 fw_error_dump.trans_ptr->data, 2837 fw_error_dump.trans_ptr->len, 2838 fw_error_dump.fwrt_len); 2839 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2840 GFP_KERNEL); 2841 } 2842 vfree(fw_error_dump.fwrt_ptr); 2843 vfree(fw_error_dump.trans_ptr); 2844 } 2845 2846 static void iwl_dump_ini_list_free(struct list_head *list) 2847 { 2848 while (!list_empty(list)) { 2849 struct iwl_fw_ini_dump_entry *entry = 2850 list_entry(list->next, typeof(*entry), list); 2851 2852 list_del(&entry->list); 2853 vfree(entry); 2854 } 2855 } 2856 2857 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2858 { 2859 dump_data->trig = NULL; 2860 kfree(dump_data->fw_pkt); 2861 dump_data->fw_pkt = NULL; 2862 } 2863 2864 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2865 struct iwl_fwrt_dump_data *dump_data) 2866 { 2867 LIST_HEAD(dump_list); 2868 struct scatterlist *sg_dump_data; 2869 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2870 2871 if (!file_len) 2872 return; 2873 2874 sg_dump_data = alloc_sgtable(file_len); 2875 if (sg_dump_data) { 2876 struct iwl_fw_ini_dump_entry *entry; 2877 int sg_entries = sg_nents(sg_dump_data); 2878 u32 offs = 0; 2879 2880 list_for_each_entry(entry, &dump_list, list) { 2881 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2882 entry->data, entry->size, offs); 2883 offs += entry->size; 2884 } 2885 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2886 GFP_KERNEL); 2887 } 2888 iwl_dump_ini_list_free(&dump_list); 2889 } 2890 2891 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2892 .trig_desc = { 2893 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2894 }, 2895 }; 2896 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2897 2898 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2899 const struct iwl_fw_dump_desc *desc, 2900 bool monitor_only, 2901 unsigned int delay) 2902 { 2903 struct iwl_fwrt_wk_data *wk_data; 2904 unsigned long idx; 2905 2906 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2907 iwl_fw_free_dump_desc(fwrt, desc); 2908 return 0; 2909 } 2910 2911 /* 2912 * Check there is an available worker. 2913 * ffz return value is undefined if no zero exists, 2914 * so check against ~0UL first. 2915 */ 2916 if (fwrt->dump.active_wks == ~0UL) 2917 return -EBUSY; 2918 2919 idx = ffz(fwrt->dump.active_wks); 2920 2921 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2922 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2923 return -EBUSY; 2924 2925 wk_data = &fwrt->dump.wks[idx]; 2926 2927 if (WARN_ON(wk_data->dump_data.desc)) 2928 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2929 2930 wk_data->dump_data.desc = desc; 2931 wk_data->dump_data.monitor_only = monitor_only; 2932 2933 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2934 le32_to_cpu(desc->trig_desc.type)); 2935 2936 queue_delayed_work(system_unbound_wq, &wk_data->wk, 2937 usecs_to_jiffies(delay)); 2938 2939 return 0; 2940 } 2941 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2942 2943 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2944 enum iwl_fw_dbg_trigger trig_type) 2945 { 2946 if (!iwl_trans_device_enabled(fwrt->trans)) 2947 return -EIO; 2948 2949 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2950 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2951 trig_type != FW_DBG_TRIGGER_DRIVER) 2952 return -EIO; 2953 2954 iwl_dbg_tlv_time_point(fwrt, 2955 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2956 NULL); 2957 } else { 2958 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2959 int ret; 2960 2961 iwl_dump_error_desc = 2962 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2963 2964 if (!iwl_dump_error_desc) 2965 return -ENOMEM; 2966 2967 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2968 iwl_dump_error_desc->len = 0; 2969 2970 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2971 false, 0); 2972 if (ret) { 2973 kfree(iwl_dump_error_desc); 2974 return ret; 2975 } 2976 } 2977 2978 iwl_trans_sync_nmi(fwrt->trans); 2979 2980 return 0; 2981 } 2982 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2983 2984 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2985 enum iwl_fw_dbg_trigger trig, 2986 const char *str, size_t len, 2987 struct iwl_fw_dbg_trigger_tlv *trigger) 2988 { 2989 struct iwl_fw_dump_desc *desc; 2990 unsigned int delay = 0; 2991 bool monitor_only = false; 2992 int ret; 2993 2994 if (trigger) { 2995 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2996 2997 if (!le16_to_cpu(trigger->occurrences)) 2998 return 0; 2999 3000 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 3001 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 3002 trig); 3003 iwl_force_nmi(fwrt->trans); 3004 return 0; 3005 } 3006 3007 trigger->occurrences = cpu_to_le16(occurrences); 3008 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 3009 3010 /* convert msec to usec */ 3011 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 3012 } 3013 3014 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC); 3015 if (!desc) 3016 return -ENOMEM; 3017 3018 3019 desc->len = len; 3020 desc->trig_desc.type = cpu_to_le32(trig); 3021 memcpy(desc->trig_desc.data, str, len); 3022 3023 ret = iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 3024 if (ret) 3025 kfree(desc); 3026 3027 return ret; 3028 } 3029 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 3030 3031 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 3032 struct iwl_fw_dbg_trigger_tlv *trigger, 3033 const char *fmt, ...) 3034 { 3035 int len = 0; 3036 char buf[64]; 3037 3038 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 3039 return 0; 3040 3041 if (fmt) { 3042 va_list ap; 3043 3044 buf[sizeof(buf) - 1] = '\0'; 3045 3046 va_start(ap, fmt); 3047 vsnprintf(buf, sizeof(buf), fmt, ap); 3048 va_end(ap); 3049 3050 /* check for truncation */ 3051 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 3052 buf[sizeof(buf) - 1] = '\0'; 3053 3054 len = strlen(buf) + 1; 3055 } 3056 3057 return iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 3058 trigger); 3059 } 3060 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 3061 3062 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 3063 { 3064 u8 *ptr; 3065 int ret; 3066 int i; 3067 3068 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 3069 "Invalid configuration %d\n", conf_id)) 3070 return -EINVAL; 3071 3072 /* EARLY START - firmware's configuration is hard coded */ 3073 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 3074 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 3075 conf_id == FW_DBG_START_FROM_ALIVE) 3076 return 0; 3077 3078 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 3079 return -EINVAL; 3080 3081 if (fwrt->dump.conf != FW_DBG_INVALID) 3082 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 3083 fwrt->dump.conf); 3084 3085 /* Send all HCMDs for configuring the FW debug */ 3086 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 3087 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 3088 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 3089 struct iwl_host_cmd hcmd = { 3090 .id = cmd->id, 3091 .len = { le16_to_cpu(cmd->len), }, 3092 .data = { cmd->data, }, 3093 }; 3094 3095 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3096 if (ret) 3097 return ret; 3098 3099 ptr += sizeof(*cmd); 3100 ptr += le16_to_cpu(cmd->len); 3101 } 3102 3103 fwrt->dump.conf = conf_id; 3104 3105 return 0; 3106 } 3107 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 3108 3109 static void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt, 3110 u32 timepoint, u32 timepoint_data) 3111 { 3112 struct iwl_dbg_dump_complete_cmd hcmd_data; 3113 struct iwl_host_cmd hcmd = { 3114 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD), 3115 .data[0] = &hcmd_data, 3116 .len[0] = sizeof(hcmd_data), 3117 }; 3118 3119 if (iwl_trans_is_fw_error(fwrt->trans)) 3120 return; 3121 3122 if (fw_has_capa(&fwrt->fw->ucode_capa, 3123 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) { 3124 hcmd_data.tp = cpu_to_le32(timepoint); 3125 hcmd_data.tp_data = cpu_to_le32(timepoint_data); 3126 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3127 } 3128 } 3129 3130 /* this function assumes dump_start was called beforehand and dump_end will be 3131 * called afterwards 3132 */ 3133 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 3134 { 3135 struct iwl_fw_dbg_params params = {0}; 3136 struct iwl_fwrt_dump_data *dump_data = 3137 &fwrt->dump.wks[wk_idx].dump_data; 3138 3139 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 3140 return; 3141 3142 /* also checks 'desc' for pre-ini mode, since that shadows in union */ 3143 if (!dump_data->trig) { 3144 IWL_ERR(fwrt, "dump trigger data is not set\n"); 3145 goto out; 3146 } 3147 3148 if (!iwl_trans_device_enabled(fwrt->trans)) { 3149 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 3150 goto out; 3151 } 3152 3153 /* there's no point in fw dump if the bus is dead */ 3154 if (iwl_trans_is_dead(fwrt->trans)) { 3155 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 3156 goto out; 3157 } 3158 3159 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 3160 3161 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 3162 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 3163 iwl_fw_error_ini_dump(fwrt, dump_data); 3164 else 3165 iwl_fw_error_dump(fwrt, dump_data); 3166 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 3167 3168 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3169 3170 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3171 u32 policy = le32_to_cpu(dump_data->trig->apply_policy); 3172 u32 time_point = le32_to_cpu(dump_data->trig->time_point); 3173 3174 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) { 3175 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n"); 3176 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0); 3177 } 3178 } 3179 3180 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 3181 iwl_force_nmi(fwrt->trans); 3182 out: 3183 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3184 iwl_fw_error_dump_data_free(dump_data); 3185 } else { 3186 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 3187 dump_data->desc = NULL; 3188 } 3189 3190 clear_bit(wk_idx, &fwrt->dump.active_wks); 3191 } 3192 3193 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 3194 struct iwl_fwrt_dump_data *dump_data, 3195 bool sync) 3196 { 3197 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 3198 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 3199 u32 occur, delay; 3200 unsigned long idx; 3201 3202 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 3203 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 3204 tp_id); 3205 return -EINVAL; 3206 } 3207 3208 delay = le32_to_cpu(trig->dump_delay); 3209 occur = le32_to_cpu(trig->occurrences); 3210 if (!occur) 3211 return 0; 3212 3213 trig->occurrences = cpu_to_le32(--occur); 3214 3215 /* Check there is an available worker. 3216 * ffz return value is undefined if no zero exists, 3217 * so check against ~0UL first. 3218 */ 3219 if (fwrt->dump.active_wks == ~0UL) 3220 return -EBUSY; 3221 3222 idx = ffz(fwrt->dump.active_wks); 3223 3224 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 3225 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 3226 return -EBUSY; 3227 3228 fwrt->dump.wks[idx].dump_data = *dump_data; 3229 3230 if (sync) 3231 delay = 0; 3232 3233 IWL_WARN(fwrt, 3234 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 3235 tp_id, (u32)(delay / USEC_PER_MSEC)); 3236 3237 if (sync) 3238 iwl_fw_dbg_collect_sync(fwrt, idx); 3239 else 3240 queue_delayed_work(system_unbound_wq, 3241 &fwrt->dump.wks[idx].wk, 3242 usecs_to_jiffies(delay)); 3243 3244 return 0; 3245 } 3246 3247 void iwl_fw_error_dump_wk(struct work_struct *work) 3248 { 3249 struct iwl_fwrt_wk_data *wks = 3250 container_of(work, typeof(*wks), wk.work); 3251 struct iwl_fw_runtime *fwrt = 3252 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 3253 3254 /* assumes the op mode mutex is locked in dump_start since 3255 * iwl_fw_dbg_collect_sync can't run in parallel 3256 */ 3257 if (fwrt->ops && fwrt->ops->dump_start) 3258 fwrt->ops->dump_start(fwrt->ops_ctx); 3259 3260 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 3261 3262 if (fwrt->ops && fwrt->ops->dump_end) 3263 fwrt->ops->dump_end(fwrt->ops_ctx); 3264 } 3265 3266 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 3267 { 3268 const struct iwl_mac_cfg *mac_cfg = fwrt->trans->mac_cfg; 3269 3270 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 3271 return; 3272 3273 if (!fwrt->dump.d3_debug_data) { 3274 fwrt->dump.d3_debug_data = kmalloc(mac_cfg->base->d3_debug_data_length, 3275 GFP_KERNEL); 3276 if (!fwrt->dump.d3_debug_data) { 3277 IWL_ERR(fwrt, 3278 "failed to allocate memory for D3 debug data\n"); 3279 return; 3280 } 3281 } 3282 3283 /* if the buffer holds previous debug data it is overwritten */ 3284 iwl_trans_read_mem_bytes(fwrt->trans, mac_cfg->base->d3_debug_data_base_addr, 3285 fwrt->dump.d3_debug_data, 3286 mac_cfg->base->d3_debug_data_length); 3287 3288 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 3289 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 3290 mac_cfg->base->d3_debug_data_base_addr, 3291 fwrt->dump.d3_debug_data, 3292 mac_cfg->base->d3_debug_data_length); 3293 } 3294 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 3295 3296 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 3297 { 3298 int i; 3299 3300 iwl_dbg_tlv_del_timers(fwrt->trans); 3301 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 3302 iwl_fw_dbg_collect_sync(fwrt, i); 3303 3304 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 3305 } 3306 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 3307 3308 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 3309 { 3310 struct iwl_dbg_suspend_resume_cmd cmd = { 3311 .operation = suspend ? 3312 cpu_to_le32(DBGC_SUSPEND_CMD) : 3313 cpu_to_le32(DBGC_RESUME_CMD), 3314 }; 3315 struct iwl_host_cmd hcmd = { 3316 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3317 .data[0] = &cmd, 3318 .len[0] = sizeof(cmd), 3319 }; 3320 3321 return iwl_trans_send_cmd(trans, &hcmd); 3322 } 3323 3324 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3325 struct iwl_fw_dbg_params *params) 3326 { 3327 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3328 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3329 return; 3330 } 3331 3332 if (params) { 3333 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3334 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3335 } 3336 3337 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3338 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3339 * avoid halting the HW while writing 3340 */ 3341 usleep_range(700, 1000); 3342 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3343 } 3344 3345 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3346 struct iwl_fw_dbg_params *params) 3347 { 3348 if (!params) 3349 return -EIO; 3350 3351 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3352 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3353 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3354 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3355 } else { 3356 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3357 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3358 } 3359 3360 return 0; 3361 } 3362 3363 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt) 3364 { 3365 struct iwl_mvm_marker marker = { 3366 .dw_len = sizeof(struct iwl_mvm_marker) / 4, 3367 .marker_id = MARKER_ID_SYNC_CLOCK, 3368 }; 3369 struct iwl_host_cmd hcmd = { 3370 .flags = CMD_ASYNC, 3371 .id = WIDE_ID(LONG_GROUP, MARKER_CMD), 3372 .dataflags = {}, 3373 }; 3374 struct iwl_mvm_marker_rsp *resp; 3375 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw, 3376 WIDE_ID(LONG_GROUP, MARKER_CMD), 3377 IWL_FW_CMD_VER_UNKNOWN); 3378 int ret; 3379 3380 if (cmd_ver == 1) { 3381 /* the real timestamp is taken from the ftrace clock 3382 * this is for finding the match between fw and kernel logs 3383 */ 3384 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++); 3385 } else if (cmd_ver == 2) { 3386 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns()); 3387 } else { 3388 IWL_DEBUG_INFO(fwrt, 3389 "Invalid version of Marker CMD. Ver = %d\n", 3390 cmd_ver); 3391 return -EINVAL; 3392 } 3393 3394 hcmd.data[0] = ▮ 3395 hcmd.len[0] = sizeof(marker); 3396 3397 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3398 3399 if (cmd_ver > 1 && hcmd.resp_pkt) { 3400 resp = (void *)hcmd.resp_pkt->data; 3401 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n", 3402 le32_to_cpu(resp->gp2)); 3403 } 3404 3405 return ret; 3406 } 3407 3408 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3409 struct iwl_fw_dbg_params *params, 3410 bool stop) 3411 { 3412 int ret __maybe_unused = 0; 3413 3414 if (!iwl_trans_fw_running(fwrt->trans)) 3415 return; 3416 3417 if (fw_has_capa(&fwrt->fw->ucode_capa, 3418 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) { 3419 if (stop) 3420 iwl_fw_send_timestamp_marker_cmd(fwrt); 3421 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3422 } else if (stop) { 3423 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3424 } else { 3425 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3426 } 3427 #ifdef CONFIG_IWLWIFI_DEBUGFS 3428 if (!ret) { 3429 if (stop) 3430 fwrt->trans->dbg.rec_on = false; 3431 else 3432 iwl_fw_set_dbg_rec_on(fwrt); 3433 } 3434 #endif 3435 } 3436 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3437 3438 void iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime *fwrt) 3439 { 3440 struct iwl_fw_dbg_config_cmd cmd = { 3441 .type = cpu_to_le32(DEBUG_TOKEN_CONFIG_TYPE), 3442 .conf = cpu_to_le32(IWL_FW_DBG_CONFIG_TOKEN), 3443 }; 3444 struct iwl_host_cmd hcmd = { 3445 .id = WIDE_ID(LONG_GROUP, LDBG_CONFIG_CMD), 3446 .data[0] = &cmd, 3447 .len[0] = sizeof(cmd), 3448 }; 3449 u32 preset = u32_get_bits(fwrt->trans->dbg.domains_bitmap, 3450 GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1)); 3451 3452 /* supported starting from 9000 devices */ 3453 if (fwrt->trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_9000) 3454 return; 3455 3456 if (fwrt->trans->dbg.yoyo_bin_loaded || (preset && preset != 1)) 3457 return; 3458 3459 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3460 } 3461 IWL_EXPORT_SYMBOL(iwl_fw_disable_dbg_asserts); 3462 3463 void iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime *fwrt) 3464 { 3465 struct iwl_fw_dbg_params params = {0}; 3466 3467 iwl_fw_dbg_stop_sync(fwrt); 3468 3469 if (fw_has_api(&fwrt->fw->ucode_capa, 3470 IWL_UCODE_TLV_API_INT_DBG_BUF_CLEAR)) { 3471 struct iwl_host_cmd hcmd = { 3472 .id = WIDE_ID(DEBUG_GROUP, FW_CLEAR_BUFFER), 3473 }; 3474 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3475 } 3476 3477 iwl_dbg_tlv_init_cfg(fwrt); 3478 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3479 } 3480 IWL_EXPORT_SYMBOL(iwl_fw_dbg_clear_monitor_buf); 3481