1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/devcoredump.h> 65 #include "iwl-drv.h" 66 #include "runtime.h" 67 #include "dbg.h" 68 #include "debugfs.h" 69 #include "iwl-io.h" 70 #include "iwl-prph.h" 71 #include "iwl-csr.h" 72 73 /** 74 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 75 * 76 * @fwrt_ptr: pointer to the buffer coming from fwrt 77 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 78 * transport's data. 79 * @trans_len: length of the valid data in trans_ptr 80 * @fwrt_len: length of the valid data in fwrt_ptr 81 */ 82 struct iwl_fw_dump_ptrs { 83 struct iwl_trans_dump_data *trans_ptr; 84 void *fwrt_ptr; 85 u32 fwrt_len; 86 }; 87 88 #define RADIO_REG_MAX_READ 0x2ad 89 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 90 struct iwl_fw_error_dump_data **dump_data) 91 { 92 u8 *pos = (void *)(*dump_data)->data; 93 unsigned long flags; 94 int i; 95 96 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 97 98 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 99 return; 100 101 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 102 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 103 104 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 105 u32 rd_cmd = RADIO_RSP_RD_CMD; 106 107 rd_cmd |= i << RADIO_RSP_ADDR_POS; 108 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 109 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 110 111 pos++; 112 } 113 114 *dump_data = iwl_fw_error_next_data(*dump_data); 115 116 iwl_trans_release_nic_access(fwrt->trans, &flags); 117 } 118 119 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122 { 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the RXF */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 RXF_RD_D_SPACE + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 RXF_RD_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 RXF_RD_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 RXF_RD_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 RXF_SET_FENCE_MODE + offset)); 156 157 /* Lock fence */ 158 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 159 /* Set fence pointer to the same place like WR pointer */ 160 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 161 /* Set fence offset */ 162 iwl_trans_write_prph(fwrt->trans, 163 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 164 165 /* Read FIFO */ 166 fifo_len /= sizeof(u32); /* Size in DWORDS */ 167 for (i = 0; i < fifo_len; i++) 168 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 169 RXF_FIFO_RD_FENCE_INC + 170 offset); 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data, 176 int size, u32 offset, int fifo_num) 177 { 178 struct iwl_fw_error_dump_fifo *fifo_hdr; 179 u32 *fifo_data; 180 u32 fifo_len; 181 int i; 182 183 fifo_hdr = (void *)(*dump_data)->data; 184 fifo_data = (void *)fifo_hdr->data; 185 fifo_len = size; 186 187 /* No need to try to read the data if the length is 0 */ 188 if (fifo_len == 0) 189 return; 190 191 /* Add a TLV for the FIFO */ 192 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 193 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 194 195 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 196 fifo_hdr->available_bytes = 197 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 198 TXF_FIFO_ITEM_CNT + offset)); 199 fifo_hdr->wr_ptr = 200 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 201 TXF_WR_PTR + offset)); 202 fifo_hdr->rd_ptr = 203 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 204 TXF_RD_PTR + offset)); 205 fifo_hdr->fence_ptr = 206 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 207 TXF_FENCE_PTR + offset)); 208 fifo_hdr->fence_mode = 209 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 210 TXF_LOCK_FENCE + offset)); 211 212 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 213 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 214 TXF_WR_PTR + offset); 215 216 /* Dummy-read to advance the read pointer to the head */ 217 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 218 219 /* Read FIFO */ 220 fifo_len /= sizeof(u32); /* Size in DWORDS */ 221 for (i = 0; i < fifo_len; i++) 222 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 223 TXF_READ_MODIFY_DATA + 224 offset); 225 *dump_data = iwl_fw_error_next_data(*dump_data); 226 } 227 228 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 229 struct iwl_fw_error_dump_data **dump_data) 230 { 231 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 232 unsigned long flags; 233 234 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 235 236 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 237 return; 238 239 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 240 /* Pull RXF1 */ 241 iwl_fwrt_dump_rxf(fwrt, dump_data, 242 cfg->lmac[0].rxfifo1_size, 0, 0); 243 /* Pull RXF2 */ 244 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 245 RXF_DIFF_FROM_PREV + 246 fwrt->trans->cfg->umac_prph_offset, 1); 247 /* Pull LMAC2 RXF1 */ 248 if (fwrt->smem_cfg.num_lmacs > 1) 249 iwl_fwrt_dump_rxf(fwrt, dump_data, 250 cfg->lmac[1].rxfifo1_size, 251 LMAC2_PRPH_OFFSET, 2); 252 } 253 254 iwl_trans_release_nic_access(fwrt->trans, &flags); 255 } 256 257 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 258 struct iwl_fw_error_dump_data **dump_data) 259 { 260 struct iwl_fw_error_dump_fifo *fifo_hdr; 261 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 262 u32 *fifo_data; 263 u32 fifo_len; 264 unsigned long flags; 265 int i, j; 266 267 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 268 269 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 270 return; 271 272 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 273 /* Pull TXF data from LMAC1 */ 274 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 275 /* Mark the number of TXF we're pulling now */ 276 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 277 iwl_fwrt_dump_txf(fwrt, dump_data, 278 cfg->lmac[0].txfifo_size[i], 0, i); 279 } 280 281 /* Pull TXF data from LMAC2 */ 282 if (fwrt->smem_cfg.num_lmacs > 1) { 283 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 284 i++) { 285 /* Mark the number of TXF we're pulling now */ 286 iwl_trans_write_prph(fwrt->trans, 287 TXF_LARC_NUM + 288 LMAC2_PRPH_OFFSET, i); 289 iwl_fwrt_dump_txf(fwrt, dump_data, 290 cfg->lmac[1].txfifo_size[i], 291 LMAC2_PRPH_OFFSET, 292 i + cfg->num_txfifo_entries); 293 } 294 } 295 } 296 297 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 298 fw_has_capa(&fwrt->fw->ucode_capa, 299 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 300 /* Pull UMAC internal TXF data from all TXFs */ 301 for (i = 0; 302 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 303 i++) { 304 fifo_hdr = (void *)(*dump_data)->data; 305 fifo_data = (void *)fifo_hdr->data; 306 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 307 308 /* No need to try to read the data if the length is 0 */ 309 if (fifo_len == 0) 310 continue; 311 312 /* Add a TLV for the internal FIFOs */ 313 (*dump_data)->type = 314 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 315 (*dump_data)->len = 316 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 317 318 fifo_hdr->fifo_num = cpu_to_le32(i); 319 320 /* Mark the number of TXF we're pulling now */ 321 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 322 fwrt->smem_cfg.num_txfifo_entries); 323 324 fifo_hdr->available_bytes = 325 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_FIFO_ITEM_CNT)); 327 fifo_hdr->wr_ptr = 328 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 329 TXF_CPU2_WR_PTR)); 330 fifo_hdr->rd_ptr = 331 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 332 TXF_CPU2_RD_PTR)); 333 fifo_hdr->fence_ptr = 334 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 335 TXF_CPU2_FENCE_PTR)); 336 fifo_hdr->fence_mode = 337 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 338 TXF_CPU2_LOCK_FENCE)); 339 340 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 341 iwl_trans_write_prph(fwrt->trans, 342 TXF_CPU2_READ_MODIFY_ADDR, 343 TXF_CPU2_WR_PTR); 344 345 /* Dummy-read to advance the read pointer to head */ 346 iwl_trans_read_prph(fwrt->trans, 347 TXF_CPU2_READ_MODIFY_DATA); 348 349 /* Read FIFO */ 350 fifo_len /= sizeof(u32); /* Size in DWORDS */ 351 for (j = 0; j < fifo_len; j++) 352 fifo_data[j] = 353 iwl_trans_read_prph(fwrt->trans, 354 TXF_CPU2_READ_MODIFY_DATA); 355 *dump_data = iwl_fw_error_next_data(*dump_data); 356 } 357 } 358 359 iwl_trans_release_nic_access(fwrt->trans, &flags); 360 } 361 362 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 363 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 364 365 struct iwl_prph_range { 366 u32 start, end; 367 }; 368 369 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 370 { .start = 0x00a00000, .end = 0x00a00000 }, 371 { .start = 0x00a0000c, .end = 0x00a00024 }, 372 { .start = 0x00a0002c, .end = 0x00a0003c }, 373 { .start = 0x00a00410, .end = 0x00a00418 }, 374 { .start = 0x00a00420, .end = 0x00a00420 }, 375 { .start = 0x00a00428, .end = 0x00a00428 }, 376 { .start = 0x00a00430, .end = 0x00a0043c }, 377 { .start = 0x00a00444, .end = 0x00a00444 }, 378 { .start = 0x00a004c0, .end = 0x00a004cc }, 379 { .start = 0x00a004d8, .end = 0x00a004d8 }, 380 { .start = 0x00a004e0, .end = 0x00a004f0 }, 381 { .start = 0x00a00840, .end = 0x00a00840 }, 382 { .start = 0x00a00850, .end = 0x00a00858 }, 383 { .start = 0x00a01004, .end = 0x00a01008 }, 384 { .start = 0x00a01010, .end = 0x00a01010 }, 385 { .start = 0x00a01018, .end = 0x00a01018 }, 386 { .start = 0x00a01024, .end = 0x00a01024 }, 387 { .start = 0x00a0102c, .end = 0x00a01034 }, 388 { .start = 0x00a0103c, .end = 0x00a01040 }, 389 { .start = 0x00a01048, .end = 0x00a01094 }, 390 { .start = 0x00a01c00, .end = 0x00a01c20 }, 391 { .start = 0x00a01c58, .end = 0x00a01c58 }, 392 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 393 { .start = 0x00a01c28, .end = 0x00a01c54 }, 394 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 395 { .start = 0x00a01c60, .end = 0x00a01cdc }, 396 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 397 { .start = 0x00a01d18, .end = 0x00a01d20 }, 398 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 399 { .start = 0x00a01d40, .end = 0x00a01d5c }, 400 { .start = 0x00a01d80, .end = 0x00a01d80 }, 401 { .start = 0x00a01d98, .end = 0x00a01d9c }, 402 { .start = 0x00a01da8, .end = 0x00a01da8 }, 403 { .start = 0x00a01db8, .end = 0x00a01df4 }, 404 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 405 { .start = 0x00a01e00, .end = 0x00a01e2c }, 406 { .start = 0x00a01e40, .end = 0x00a01e60 }, 407 { .start = 0x00a01e68, .end = 0x00a01e6c }, 408 { .start = 0x00a01e74, .end = 0x00a01e74 }, 409 { .start = 0x00a01e84, .end = 0x00a01e90 }, 410 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 411 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 412 { .start = 0x00a01f00, .end = 0x00a01f1c }, 413 { .start = 0x00a01f44, .end = 0x00a01ffc }, 414 { .start = 0x00a02000, .end = 0x00a02048 }, 415 { .start = 0x00a02068, .end = 0x00a020f0 }, 416 { .start = 0x00a02100, .end = 0x00a02118 }, 417 { .start = 0x00a02140, .end = 0x00a0214c }, 418 { .start = 0x00a02168, .end = 0x00a0218c }, 419 { .start = 0x00a021c0, .end = 0x00a021c0 }, 420 { .start = 0x00a02400, .end = 0x00a02410 }, 421 { .start = 0x00a02418, .end = 0x00a02420 }, 422 { .start = 0x00a02428, .end = 0x00a0242c }, 423 { .start = 0x00a02434, .end = 0x00a02434 }, 424 { .start = 0x00a02440, .end = 0x00a02460 }, 425 { .start = 0x00a02468, .end = 0x00a024b0 }, 426 { .start = 0x00a024c8, .end = 0x00a024cc }, 427 { .start = 0x00a02500, .end = 0x00a02504 }, 428 { .start = 0x00a0250c, .end = 0x00a02510 }, 429 { .start = 0x00a02540, .end = 0x00a02554 }, 430 { .start = 0x00a02580, .end = 0x00a025f4 }, 431 { .start = 0x00a02600, .end = 0x00a0260c }, 432 { .start = 0x00a02648, .end = 0x00a02650 }, 433 { .start = 0x00a02680, .end = 0x00a02680 }, 434 { .start = 0x00a026c0, .end = 0x00a026d0 }, 435 { .start = 0x00a02700, .end = 0x00a0270c }, 436 { .start = 0x00a02804, .end = 0x00a02804 }, 437 { .start = 0x00a02818, .end = 0x00a0281c }, 438 { .start = 0x00a02c00, .end = 0x00a02db4 }, 439 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 440 { .start = 0x00a03000, .end = 0x00a03014 }, 441 { .start = 0x00a0301c, .end = 0x00a0302c }, 442 { .start = 0x00a03034, .end = 0x00a03038 }, 443 { .start = 0x00a03040, .end = 0x00a03048 }, 444 { .start = 0x00a03060, .end = 0x00a03068 }, 445 { .start = 0x00a03070, .end = 0x00a03074 }, 446 { .start = 0x00a0307c, .end = 0x00a0307c }, 447 { .start = 0x00a03080, .end = 0x00a03084 }, 448 { .start = 0x00a0308c, .end = 0x00a03090 }, 449 { .start = 0x00a03098, .end = 0x00a03098 }, 450 { .start = 0x00a030a0, .end = 0x00a030a0 }, 451 { .start = 0x00a030a8, .end = 0x00a030b4 }, 452 { .start = 0x00a030bc, .end = 0x00a030bc }, 453 { .start = 0x00a030c0, .end = 0x00a0312c }, 454 { .start = 0x00a03c00, .end = 0x00a03c5c }, 455 { .start = 0x00a04400, .end = 0x00a04454 }, 456 { .start = 0x00a04460, .end = 0x00a04474 }, 457 { .start = 0x00a044c0, .end = 0x00a044ec }, 458 { .start = 0x00a04500, .end = 0x00a04504 }, 459 { .start = 0x00a04510, .end = 0x00a04538 }, 460 { .start = 0x00a04540, .end = 0x00a04548 }, 461 { .start = 0x00a04560, .end = 0x00a0457c }, 462 { .start = 0x00a04590, .end = 0x00a04598 }, 463 { .start = 0x00a045c0, .end = 0x00a045f4 }, 464 }; 465 466 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 467 { .start = 0x00a05c00, .end = 0x00a05c18 }, 468 { .start = 0x00a05400, .end = 0x00a056e8 }, 469 { .start = 0x00a08000, .end = 0x00a098bc }, 470 { .start = 0x00a02400, .end = 0x00a02758 }, 471 { .start = 0x00a04764, .end = 0x00a0476c }, 472 { .start = 0x00a04770, .end = 0x00a04774 }, 473 { .start = 0x00a04620, .end = 0x00a04624 }, 474 }; 475 476 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 477 { .start = 0x00a00000, .end = 0x00a00000 }, 478 { .start = 0x00a0000c, .end = 0x00a00024 }, 479 { .start = 0x00a0002c, .end = 0x00a00034 }, 480 { .start = 0x00a0003c, .end = 0x00a0003c }, 481 { .start = 0x00a00410, .end = 0x00a00418 }, 482 { .start = 0x00a00420, .end = 0x00a00420 }, 483 { .start = 0x00a00428, .end = 0x00a00428 }, 484 { .start = 0x00a00430, .end = 0x00a0043c }, 485 { .start = 0x00a00444, .end = 0x00a00444 }, 486 { .start = 0x00a00840, .end = 0x00a00840 }, 487 { .start = 0x00a00850, .end = 0x00a00858 }, 488 { .start = 0x00a01004, .end = 0x00a01008 }, 489 { .start = 0x00a01010, .end = 0x00a01010 }, 490 { .start = 0x00a01018, .end = 0x00a01018 }, 491 { .start = 0x00a01024, .end = 0x00a01024 }, 492 { .start = 0x00a0102c, .end = 0x00a01034 }, 493 { .start = 0x00a0103c, .end = 0x00a01040 }, 494 { .start = 0x00a01048, .end = 0x00a01050 }, 495 { .start = 0x00a01058, .end = 0x00a01058 }, 496 { .start = 0x00a01060, .end = 0x00a01070 }, 497 { .start = 0x00a0108c, .end = 0x00a0108c }, 498 { .start = 0x00a01c20, .end = 0x00a01c28 }, 499 { .start = 0x00a01d10, .end = 0x00a01d10 }, 500 { .start = 0x00a01e28, .end = 0x00a01e2c }, 501 { .start = 0x00a01e60, .end = 0x00a01e60 }, 502 { .start = 0x00a01e80, .end = 0x00a01e80 }, 503 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 504 { .start = 0x00a02000, .end = 0x00a0201c }, 505 { .start = 0x00a02024, .end = 0x00a02024 }, 506 { .start = 0x00a02040, .end = 0x00a02048 }, 507 { .start = 0x00a020c0, .end = 0x00a020e0 }, 508 { .start = 0x00a02400, .end = 0x00a02404 }, 509 { .start = 0x00a0240c, .end = 0x00a02414 }, 510 { .start = 0x00a0241c, .end = 0x00a0243c }, 511 { .start = 0x00a02448, .end = 0x00a024bc }, 512 { .start = 0x00a024c4, .end = 0x00a024cc }, 513 { .start = 0x00a02508, .end = 0x00a02508 }, 514 { .start = 0x00a02510, .end = 0x00a02514 }, 515 { .start = 0x00a0251c, .end = 0x00a0251c }, 516 { .start = 0x00a0252c, .end = 0x00a0255c }, 517 { .start = 0x00a02564, .end = 0x00a025a0 }, 518 { .start = 0x00a025a8, .end = 0x00a025b4 }, 519 { .start = 0x00a025c0, .end = 0x00a025c0 }, 520 { .start = 0x00a025e8, .end = 0x00a025f4 }, 521 { .start = 0x00a02c08, .end = 0x00a02c18 }, 522 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 523 { .start = 0x00a02c68, .end = 0x00a02c78 }, 524 { .start = 0x00a03000, .end = 0x00a03000 }, 525 { .start = 0x00a03010, .end = 0x00a03014 }, 526 { .start = 0x00a0301c, .end = 0x00a0302c }, 527 { .start = 0x00a03034, .end = 0x00a03038 }, 528 { .start = 0x00a03040, .end = 0x00a03044 }, 529 { .start = 0x00a03060, .end = 0x00a03068 }, 530 { .start = 0x00a03070, .end = 0x00a03070 }, 531 { .start = 0x00a0307c, .end = 0x00a03084 }, 532 { .start = 0x00a0308c, .end = 0x00a03090 }, 533 { .start = 0x00a03098, .end = 0x00a03098 }, 534 { .start = 0x00a030a0, .end = 0x00a030a0 }, 535 { .start = 0x00a030a8, .end = 0x00a030b4 }, 536 { .start = 0x00a030bc, .end = 0x00a030c0 }, 537 { .start = 0x00a030c8, .end = 0x00a030f4 }, 538 { .start = 0x00a03100, .end = 0x00a0312c }, 539 { .start = 0x00a03c00, .end = 0x00a03c5c }, 540 { .start = 0x00a04400, .end = 0x00a04454 }, 541 { .start = 0x00a04460, .end = 0x00a04474 }, 542 { .start = 0x00a044c0, .end = 0x00a044ec }, 543 { .start = 0x00a04500, .end = 0x00a04504 }, 544 { .start = 0x00a04510, .end = 0x00a04538 }, 545 { .start = 0x00a04540, .end = 0x00a04548 }, 546 { .start = 0x00a04560, .end = 0x00a04560 }, 547 { .start = 0x00a04570, .end = 0x00a0457c }, 548 { .start = 0x00a04590, .end = 0x00a04590 }, 549 { .start = 0x00a04598, .end = 0x00a04598 }, 550 { .start = 0x00a045c0, .end = 0x00a045f4 }, 551 { .start = 0x00a05c18, .end = 0x00a05c1c }, 552 { .start = 0x00a0c000, .end = 0x00a0c018 }, 553 { .start = 0x00a0c020, .end = 0x00a0c028 }, 554 { .start = 0x00a0c038, .end = 0x00a0c094 }, 555 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 556 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 557 { .start = 0x00a0c150, .end = 0x00a0c174 }, 558 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 559 { .start = 0x00a0c190, .end = 0x00a0c198 }, 560 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 561 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 562 }; 563 564 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 565 { .start = 0x00d03c00, .end = 0x00d03c64 }, 566 { .start = 0x00d05c18, .end = 0x00d05c1c }, 567 { .start = 0x00d0c000, .end = 0x00d0c174 }, 568 }; 569 570 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 571 u32 len_bytes, __le32 *data) 572 { 573 u32 i; 574 575 for (i = 0; i < len_bytes; i += 4) 576 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 577 } 578 579 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 580 const struct iwl_prph_range *iwl_prph_dump_addr, 581 u32 range_len, void *ptr) 582 { 583 struct iwl_fw_error_dump_prph *prph; 584 struct iwl_trans *trans = fwrt->trans; 585 struct iwl_fw_error_dump_data **data = 586 (struct iwl_fw_error_dump_data **)ptr; 587 unsigned long flags; 588 u32 i; 589 590 if (!data) 591 return; 592 593 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 594 595 if (!iwl_trans_grab_nic_access(trans, &flags)) 596 return; 597 598 for (i = 0; i < range_len; i++) { 599 /* The range includes both boundaries */ 600 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 601 iwl_prph_dump_addr[i].start + 4; 602 603 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 604 (*data)->len = cpu_to_le32(sizeof(*prph) + 605 num_bytes_in_chunk); 606 prph = (void *)(*data)->data; 607 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 608 609 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 610 /* our range is inclusive, hence + 4 */ 611 iwl_prph_dump_addr[i].end - 612 iwl_prph_dump_addr[i].start + 4, 613 (void *)prph->data); 614 615 *data = iwl_fw_error_next_data(*data); 616 } 617 618 iwl_trans_release_nic_access(trans, &flags); 619 } 620 621 /* 622 * alloc_sgtable - allocates scallerlist table in the given size, 623 * fills it with pages and returns it 624 * @size: the size (in bytes) of the table 625 */ 626 static struct scatterlist *alloc_sgtable(int size) 627 { 628 int alloc_size, nents, i; 629 struct page *new_page; 630 struct scatterlist *iter; 631 struct scatterlist *table; 632 633 nents = DIV_ROUND_UP(size, PAGE_SIZE); 634 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 635 if (!table) 636 return NULL; 637 sg_init_table(table, nents); 638 iter = table; 639 for_each_sg(table, iter, sg_nents(table), i) { 640 new_page = alloc_page(GFP_KERNEL); 641 if (!new_page) { 642 /* release all previous allocated pages in the table */ 643 iter = table; 644 for_each_sg(table, iter, sg_nents(table), i) { 645 new_page = sg_page(iter); 646 if (new_page) 647 __free_page(new_page); 648 } 649 return NULL; 650 } 651 alloc_size = min_t(int, size, PAGE_SIZE); 652 size -= PAGE_SIZE; 653 sg_set_page(iter, new_page, alloc_size, 0); 654 } 655 return table; 656 } 657 658 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 659 const struct iwl_prph_range *iwl_prph_dump_addr, 660 u32 range_len, void *ptr) 661 { 662 u32 *prph_len = (u32 *)ptr; 663 int i, num_bytes_in_chunk; 664 665 if (!prph_len) 666 return; 667 668 for (i = 0; i < range_len; i++) { 669 /* The range includes both boundaries */ 670 num_bytes_in_chunk = 671 iwl_prph_dump_addr[i].end - 672 iwl_prph_dump_addr[i].start + 4; 673 674 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 675 sizeof(struct iwl_fw_error_dump_prph) + 676 num_bytes_in_chunk; 677 } 678 } 679 680 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 681 void (*handler)(struct iwl_fw_runtime *, 682 const struct iwl_prph_range *, 683 u32, void *)) 684 { 685 u32 range_len; 686 687 if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 688 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 689 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 690 } else if (fwrt->trans->cfg->device_family >= IWL_DEVICE_FAMILY_22000) { 691 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 692 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 693 } else { 694 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 695 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 696 697 if (fwrt->trans->cfg->mq_rx_supported) { 698 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 699 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 700 } 701 } 702 } 703 704 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 705 struct iwl_fw_error_dump_data **dump_data, 706 u32 len, u32 ofs, u32 type) 707 { 708 struct iwl_fw_error_dump_mem *dump_mem; 709 710 if (!len) 711 return; 712 713 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 714 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 715 dump_mem = (void *)(*dump_data)->data; 716 dump_mem->type = cpu_to_le32(type); 717 dump_mem->offset = cpu_to_le32(ofs); 718 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 719 *dump_data = iwl_fw_error_next_data(*dump_data); 720 721 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 722 } 723 724 #define ADD_LEN(len, item_len, const_len) \ 725 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 726 while (0) 727 728 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 729 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 730 { 731 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 732 sizeof(struct iwl_fw_error_dump_fifo); 733 u32 fifo_len = 0; 734 int i; 735 736 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 737 return 0; 738 739 /* Count RXF2 size */ 740 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 741 742 /* Count RXF1 sizes */ 743 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 744 mem_cfg->num_lmacs = MAX_NUM_LMAC; 745 746 for (i = 0; i < mem_cfg->num_lmacs; i++) 747 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 748 749 return fifo_len; 750 } 751 752 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 753 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 754 { 755 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 756 sizeof(struct iwl_fw_error_dump_fifo); 757 u32 fifo_len = 0; 758 int i; 759 760 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 761 goto dump_internal_txf; 762 763 /* Count TXF sizes */ 764 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 765 mem_cfg->num_lmacs = MAX_NUM_LMAC; 766 767 for (i = 0; i < mem_cfg->num_lmacs; i++) { 768 int j; 769 770 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 771 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 772 hdr_len); 773 } 774 775 dump_internal_txf: 776 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 777 fw_has_capa(&fwrt->fw->ucode_capa, 778 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 779 goto out; 780 781 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 782 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 783 784 out: 785 return fifo_len; 786 } 787 788 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 789 struct iwl_fw_error_dump_data **data) 790 { 791 int i; 792 793 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 794 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 795 struct iwl_fw_error_dump_paging *paging; 796 struct page *pages = 797 fwrt->fw_paging_db[i].fw_paging_block; 798 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 799 800 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 801 (*data)->len = cpu_to_le32(sizeof(*paging) + 802 PAGING_BLOCK_SIZE); 803 paging = (void *)(*data)->data; 804 paging->index = cpu_to_le32(i); 805 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 806 PAGING_BLOCK_SIZE, 807 DMA_BIDIRECTIONAL); 808 memcpy(paging->data, page_address(pages), 809 PAGING_BLOCK_SIZE); 810 dma_sync_single_for_device(fwrt->trans->dev, addr, 811 PAGING_BLOCK_SIZE, 812 DMA_BIDIRECTIONAL); 813 (*data) = iwl_fw_error_next_data(*data); 814 } 815 } 816 817 static struct iwl_fw_error_dump_file * 818 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 819 struct iwl_fw_dump_ptrs *fw_error_dump) 820 { 821 struct iwl_fw_error_dump_file *dump_file; 822 struct iwl_fw_error_dump_data *dump_data; 823 struct iwl_fw_error_dump_info *dump_info; 824 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 825 struct iwl_fw_error_dump_trigger_desc *dump_trig; 826 u32 sram_len, sram_ofs; 827 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 828 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 829 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 830 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 831 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 832 0 : fwrt->trans->cfg->dccm2_len; 833 int i; 834 835 /* SRAM - include stack CCM if driver knows the values for it */ 836 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 837 const struct fw_img *img; 838 839 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 840 return NULL; 841 img = &fwrt->fw->img[fwrt->cur_fw_img]; 842 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 843 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 844 } else { 845 sram_ofs = fwrt->trans->cfg->dccm_offset; 846 sram_len = fwrt->trans->cfg->dccm_len; 847 } 848 849 /* reading RXF/TXF sizes */ 850 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 851 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 852 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 853 854 /* Make room for PRPH registers */ 855 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 856 iwl_fw_prph_handler(fwrt, &prph_len, 857 iwl_fw_get_prph_len); 858 859 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 && 860 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 861 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 862 } 863 864 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 865 866 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 867 file_len += sizeof(*dump_data) + sizeof(*dump_info); 868 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 869 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 870 871 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 872 size_t hdr_len = sizeof(*dump_data) + 873 sizeof(struct iwl_fw_error_dump_mem); 874 875 /* Dump SRAM only if no mem_tlvs */ 876 if (!fwrt->fw->dbg.n_mem_tlv) 877 ADD_LEN(file_len, sram_len, hdr_len); 878 879 /* Make room for all mem types that exist */ 880 ADD_LEN(file_len, smem_len, hdr_len); 881 ADD_LEN(file_len, sram2_len, hdr_len); 882 883 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 884 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 885 } 886 887 /* Make room for fw's virtual image pages, if it exists */ 888 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 889 file_len += fwrt->num_of_paging_blk * 890 (sizeof(*dump_data) + 891 sizeof(struct iwl_fw_error_dump_paging) + 892 PAGING_BLOCK_SIZE); 893 894 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 895 file_len += sizeof(*dump_data) + 896 fwrt->trans->cfg->d3_debug_data_length * 2; 897 } 898 899 /* If we only want a monitor dump, reset the file length */ 900 if (fwrt->dump.monitor_only) { 901 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 902 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 903 } 904 905 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 906 fwrt->dump.desc) 907 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 908 fwrt->dump.desc->len; 909 910 dump_file = vzalloc(file_len); 911 if (!dump_file) 912 return NULL; 913 914 fw_error_dump->fwrt_ptr = dump_file; 915 916 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 917 dump_data = (void *)dump_file->data; 918 919 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 920 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 921 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 922 dump_info = (void *)dump_data->data; 923 dump_info->hw_type = 924 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 925 dump_info->hw_step = 926 cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 927 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 928 sizeof(dump_info->fw_human_readable)); 929 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 930 sizeof(dump_info->dev_human_readable) - 1); 931 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 932 sizeof(dump_info->bus_human_readable) - 1); 933 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 934 dump_info->lmac_err_id[0] = 935 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 936 if (fwrt->smem_cfg.num_lmacs > 1) 937 dump_info->lmac_err_id[1] = 938 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 939 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 940 941 dump_data = iwl_fw_error_next_data(dump_data); 942 } 943 944 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 945 /* Dump shared memory configuration */ 946 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 947 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 948 dump_smem_cfg = (void *)dump_data->data; 949 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 950 dump_smem_cfg->num_txfifo_entries = 951 cpu_to_le32(mem_cfg->num_txfifo_entries); 952 for (i = 0; i < MAX_NUM_LMAC; i++) { 953 int j; 954 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 955 956 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 957 dump_smem_cfg->lmac[i].txfifo_size[j] = 958 cpu_to_le32(txf_size[j]); 959 dump_smem_cfg->lmac[i].rxfifo1_size = 960 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 961 } 962 dump_smem_cfg->rxfifo2_size = 963 cpu_to_le32(mem_cfg->rxfifo2_size); 964 dump_smem_cfg->internal_txfifo_addr = 965 cpu_to_le32(mem_cfg->internal_txfifo_addr); 966 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 967 dump_smem_cfg->internal_txfifo_size[i] = 968 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 969 } 970 971 dump_data = iwl_fw_error_next_data(dump_data); 972 } 973 974 /* We only dump the FIFOs if the FW is in error state */ 975 if (fifo_len) { 976 iwl_fw_dump_rxf(fwrt, &dump_data); 977 iwl_fw_dump_txf(fwrt, &dump_data); 978 } 979 980 if (radio_len) 981 iwl_read_radio_regs(fwrt, &dump_data); 982 983 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 984 fwrt->dump.desc) { 985 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 986 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 987 fwrt->dump.desc->len); 988 dump_trig = (void *)dump_data->data; 989 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 990 sizeof(*dump_trig) + fwrt->dump.desc->len); 991 992 dump_data = iwl_fw_error_next_data(dump_data); 993 } 994 995 /* In case we only want monitor dump, skip to dump trasport data */ 996 if (fwrt->dump.monitor_only) 997 goto out; 998 999 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 1000 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 1001 fwrt->fw->dbg.mem_tlv; 1002 1003 if (!fwrt->fw->dbg.n_mem_tlv) 1004 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 1005 IWL_FW_ERROR_DUMP_MEM_SRAM); 1006 1007 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 1008 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 1009 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 1010 1011 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 1012 le32_to_cpu(fw_dbg_mem[i].data_type)); 1013 } 1014 1015 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 1016 fwrt->trans->cfg->smem_offset, 1017 IWL_FW_ERROR_DUMP_MEM_SMEM); 1018 1019 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 1020 fwrt->trans->cfg->dccm2_offset, 1021 IWL_FW_ERROR_DUMP_MEM_SRAM); 1022 } 1023 1024 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 1025 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 1026 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 1027 1028 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 1029 dump_data->len = cpu_to_le32(data_size * 2); 1030 1031 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 1032 1033 kfree(fwrt->dump.d3_debug_data); 1034 fwrt->dump.d3_debug_data = NULL; 1035 1036 iwl_trans_read_mem_bytes(fwrt->trans, addr, 1037 dump_data->data + data_size, 1038 data_size); 1039 1040 dump_data = iwl_fw_error_next_data(dump_data); 1041 } 1042 1043 /* Dump fw's virtual image */ 1044 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1045 iwl_dump_paging(fwrt, &dump_data); 1046 1047 if (prph_len) 1048 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1049 1050 out: 1051 dump_file->file_len = cpu_to_le32(file_len); 1052 return dump_file; 1053 } 1054 1055 static int iwl_dump_ini_prph_iter(struct iwl_fw_runtime *fwrt, 1056 struct iwl_fw_ini_region_cfg *reg, 1057 void *range_ptr, int idx) 1058 { 1059 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1060 __le32 *val = range->data; 1061 u32 prph_val; 1062 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1063 int i; 1064 1065 range->internal_base_addr = cpu_to_le32(addr); 1066 range->range_data_size = reg->internal.range_data_size; 1067 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { 1068 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1069 if (prph_val == 0x5a5a5a5a) 1070 return -EBUSY; 1071 *val++ = cpu_to_le32(prph_val); 1072 } 1073 1074 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1075 } 1076 1077 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1078 struct iwl_fw_ini_region_cfg *reg, 1079 void *range_ptr, int idx) 1080 { 1081 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1082 __le32 *val = range->data; 1083 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1084 int i; 1085 1086 range->internal_base_addr = cpu_to_le32(addr); 1087 range->range_data_size = reg->internal.range_data_size; 1088 for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) 1089 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1090 1091 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1092 } 1093 1094 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1095 struct iwl_fw_ini_region_cfg *reg, 1096 void *range_ptr, int idx) 1097 { 1098 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1099 u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); 1100 1101 range->internal_base_addr = cpu_to_le32(addr); 1102 range->range_data_size = reg->internal.range_data_size; 1103 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1104 le32_to_cpu(reg->internal.range_data_size)); 1105 1106 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1107 } 1108 1109 static int 1110 iwl_dump_ini_paging_gen2_iter(struct iwl_fw_runtime *fwrt, 1111 struct iwl_fw_ini_region_cfg *reg, 1112 void *range_ptr, int idx) 1113 { 1114 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1115 u32 page_size = fwrt->trans->init_dram.paging[idx].size; 1116 1117 range->page_num = cpu_to_le32(idx); 1118 range->range_data_size = cpu_to_le32(page_size); 1119 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1120 page_size); 1121 1122 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1123 } 1124 1125 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1126 struct iwl_fw_ini_region_cfg *reg, 1127 void *range_ptr, int idx) 1128 { 1129 /* increase idx by 1 since the pages are from 1 to 1130 * fwrt->num_of_paging_blk + 1 1131 */ 1132 struct page *page = fwrt->fw_paging_db[++idx].fw_paging_block; 1133 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1134 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1135 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1136 1137 range->page_num = cpu_to_le32(idx); 1138 range->range_data_size = cpu_to_le32(page_size); 1139 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1140 DMA_BIDIRECTIONAL); 1141 memcpy(range->data, page_address(page), page_size); 1142 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1143 DMA_BIDIRECTIONAL); 1144 1145 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1146 } 1147 1148 static int 1149 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1150 struct iwl_fw_ini_region_cfg *reg, void *range_ptr, 1151 int idx) 1152 { 1153 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1154 u32 start_addr = iwl_read_umac_prph(fwrt->trans, 1155 MON_BUFF_BASE_ADDR_VER2); 1156 1157 if (start_addr == 0x5a5a5a5a) 1158 return -EBUSY; 1159 1160 range->dram_base_addr = cpu_to_le64(start_addr); 1161 range->range_data_size = cpu_to_le32(fwrt->trans->dbg.fw_mon[idx].size); 1162 1163 memcpy(range->data, fwrt->trans->dbg.fw_mon[idx].block, 1164 fwrt->trans->dbg.fw_mon[idx].size); 1165 1166 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1167 } 1168 1169 struct iwl_ini_txf_iter_data { 1170 int fifo; 1171 int lmac; 1172 u32 fifo_size; 1173 bool internal_txf; 1174 bool init; 1175 }; 1176 1177 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1178 struct iwl_fw_ini_region_cfg *reg) 1179 { 1180 struct iwl_ini_txf_iter_data *iter = fwrt->dump.fifo_iter; 1181 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1182 int txf_num = cfg->num_txfifo_entries; 1183 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1184 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1); 1185 1186 if (!iter) 1187 return false; 1188 1189 if (iter->init) { 1190 if (le32_to_cpu(reg->offset) && 1191 WARN_ONCE(cfg->num_lmacs == 1, 1192 "Invalid lmac offset: 0x%x\n", 1193 le32_to_cpu(reg->offset))) 1194 return false; 1195 1196 iter->init = false; 1197 iter->internal_txf = false; 1198 iter->fifo_size = 0; 1199 iter->fifo = -1; 1200 if (le32_to_cpu(reg->offset)) 1201 iter->lmac = 1; 1202 else 1203 iter->lmac = 0; 1204 } 1205 1206 if (!iter->internal_txf) 1207 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1208 iter->fifo_size = 1209 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1210 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1211 return true; 1212 } 1213 1214 iter->internal_txf = true; 1215 1216 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1217 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1218 return false; 1219 1220 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1221 iter->fifo_size = 1222 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1223 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1224 return true; 1225 } 1226 1227 return false; 1228 } 1229 1230 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1231 struct iwl_fw_ini_region_cfg *reg, 1232 void *range_ptr, int idx) 1233 { 1234 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1235 struct iwl_ini_txf_iter_data *iter; 1236 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1237 u32 offs = le32_to_cpu(reg->offset), addr; 1238 u32 registers_size = 1239 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1240 __le32 *data; 1241 unsigned long flags; 1242 int i; 1243 1244 if (!iwl_ini_txf_iter(fwrt, reg)) 1245 return -EIO; 1246 1247 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1248 return -EBUSY; 1249 1250 iter = fwrt->dump.fifo_iter; 1251 1252 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1253 range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers; 1254 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1255 1256 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1257 1258 /* 1259 * read txf registers. for each register, write to the dump the 1260 * register address and its value 1261 */ 1262 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1263 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1264 1265 reg_dump->addr = cpu_to_le32(addr); 1266 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1267 addr)); 1268 1269 reg_dump++; 1270 } 1271 1272 if (reg->fifos.header_only) { 1273 range->range_data_size = cpu_to_le32(registers_size); 1274 goto out; 1275 } 1276 1277 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1278 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1279 TXF_WR_PTR + offs); 1280 1281 /* Dummy-read to advance the read pointer to the head */ 1282 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1283 1284 /* Read FIFO */ 1285 addr = TXF_READ_MODIFY_DATA + offs; 1286 data = (void *)reg_dump; 1287 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1288 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1289 1290 out: 1291 iwl_trans_release_nic_access(fwrt->trans, &flags); 1292 1293 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1294 } 1295 1296 struct iwl_ini_rxf_data { 1297 u32 fifo_num; 1298 u32 size; 1299 u32 offset; 1300 }; 1301 1302 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1303 struct iwl_fw_ini_region_cfg *reg, 1304 struct iwl_ini_rxf_data *data) 1305 { 1306 u32 fid1 = le32_to_cpu(reg->fifos.fid1); 1307 u32 fid2 = le32_to_cpu(reg->fifos.fid2); 1308 u32 fifo_idx; 1309 1310 if (!data) 1311 return; 1312 1313 memset(data, 0, sizeof(*data)); 1314 1315 if (WARN_ON_ONCE((fid1 && fid2) || (!fid1 && !fid2))) 1316 return; 1317 1318 fifo_idx = ffs(fid1) - 1; 1319 if (fid1 && !WARN_ON_ONCE((~BIT(fifo_idx) & fid1) || 1320 fifo_idx >= MAX_NUM_LMAC)) { 1321 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1322 data->fifo_num = fifo_idx; 1323 return; 1324 } 1325 1326 fifo_idx = ffs(fid2) - 1; 1327 if (fid2 && !WARN_ON_ONCE(fifo_idx != 0)) { 1328 data->size = fwrt->smem_cfg.rxfifo2_size; 1329 data->offset = RXF_DIFF_FROM_PREV; 1330 /* use bit 31 to distinguish between umac and lmac rxf while 1331 * parsing the dump 1332 */ 1333 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1334 return; 1335 } 1336 } 1337 1338 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1339 struct iwl_fw_ini_region_cfg *reg, 1340 void *range_ptr, int idx) 1341 { 1342 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1343 struct iwl_ini_rxf_data rxf_data; 1344 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1345 u32 offs = le32_to_cpu(reg->offset), addr; 1346 u32 registers_size = 1347 le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); 1348 __le32 *data; 1349 unsigned long flags; 1350 int i; 1351 1352 iwl_ini_get_rxf_data(fwrt, reg, &rxf_data); 1353 if (!rxf_data.size) 1354 return -EIO; 1355 1356 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 1357 return -EBUSY; 1358 1359 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1360 range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers; 1361 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1362 1363 /* 1364 * read rxf registers. for each register, write to the dump the 1365 * register address and its value 1366 */ 1367 for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { 1368 addr = le32_to_cpu(reg->start_addr[i]) + offs; 1369 1370 reg_dump->addr = cpu_to_le32(addr); 1371 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1372 addr)); 1373 1374 reg_dump++; 1375 } 1376 1377 if (reg->fifos.header_only) { 1378 range->range_data_size = cpu_to_le32(registers_size); 1379 goto out; 1380 } 1381 1382 /* 1383 * region register have absolute value so apply rxf offset after 1384 * reading the registers 1385 */ 1386 offs += rxf_data.offset; 1387 1388 /* Lock fence */ 1389 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1390 /* Set fence pointer to the same place like WR pointer */ 1391 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1392 /* Set fence offset */ 1393 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1394 0x0); 1395 1396 /* Read FIFO */ 1397 addr = RXF_FIFO_RD_FENCE_INC + offs; 1398 data = (void *)reg_dump; 1399 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1400 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1401 1402 out: 1403 iwl_trans_release_nic_access(fwrt->trans, &flags); 1404 1405 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1406 } 1407 1408 static void *iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1409 struct iwl_fw_ini_region_cfg *reg, 1410 void *data) 1411 { 1412 struct iwl_fw_ini_error_dump *dump = data; 1413 1414 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1415 1416 return dump->ranges; 1417 } 1418 1419 static void 1420 *iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, 1421 struct iwl_fw_ini_region_cfg *reg, 1422 struct iwl_fw_ini_monitor_dump *data, 1423 u32 write_ptr_addr, u32 write_ptr_msk, 1424 u32 cycle_cnt_addr, u32 cycle_cnt_msk) 1425 { 1426 u32 write_ptr, cycle_cnt; 1427 unsigned long flags; 1428 1429 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) { 1430 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1431 return NULL; 1432 } 1433 1434 write_ptr = iwl_read_prph_no_grab(fwrt->trans, write_ptr_addr); 1435 cycle_cnt = iwl_read_prph_no_grab(fwrt->trans, cycle_cnt_addr); 1436 1437 iwl_trans_release_nic_access(fwrt->trans, &flags); 1438 1439 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1440 data->write_ptr = cpu_to_le32(write_ptr & write_ptr_msk); 1441 data->cycle_cnt = cpu_to_le32(cycle_cnt & cycle_cnt_msk); 1442 1443 return data->ranges; 1444 } 1445 1446 static void 1447 *iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1448 struct iwl_fw_ini_region_cfg *reg, 1449 void *data) 1450 { 1451 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1452 u32 write_ptr_addr, write_ptr_msk, cycle_cnt_addr, cycle_cnt_msk; 1453 1454 switch (fwrt->trans->cfg->device_family) { 1455 case IWL_DEVICE_FAMILY_9000: 1456 case IWL_DEVICE_FAMILY_22000: 1457 write_ptr_addr = MON_BUFF_WRPTR_VER2; 1458 write_ptr_msk = -1; 1459 cycle_cnt_addr = MON_BUFF_CYCLE_CNT_VER2; 1460 cycle_cnt_msk = -1; 1461 break; 1462 default: 1463 IWL_ERR(fwrt, "Unsupported device family %d\n", 1464 fwrt->trans->cfg->device_family); 1465 return NULL; 1466 } 1467 1468 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, write_ptr_addr, 1469 write_ptr_msk, cycle_cnt_addr, 1470 cycle_cnt_msk); 1471 } 1472 1473 static void 1474 *iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1475 struct iwl_fw_ini_region_cfg *reg, 1476 void *data) 1477 { 1478 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1479 const struct iwl_cfg *cfg = fwrt->trans->cfg; 1480 1481 if (fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_9000 && 1482 fwrt->trans->cfg->device_family != IWL_DEVICE_FAMILY_22000) { 1483 IWL_ERR(fwrt, "Unsupported device family %d\n", 1484 fwrt->trans->cfg->device_family); 1485 return NULL; 1486 } 1487 1488 return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, 1489 cfg->fw_mon_smem_write_ptr_addr, 1490 cfg->fw_mon_smem_write_ptr_msk, 1491 cfg->fw_mon_smem_cycle_cnt_ptr_addr, 1492 cfg->fw_mon_smem_cycle_cnt_ptr_msk); 1493 1494 } 1495 1496 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1497 struct iwl_fw_ini_region_cfg *reg) 1498 { 1499 return le32_to_cpu(reg->internal.num_of_ranges); 1500 } 1501 1502 static u32 iwl_dump_ini_paging_gen2_ranges(struct iwl_fw_runtime *fwrt, 1503 struct iwl_fw_ini_region_cfg *reg) 1504 { 1505 return fwrt->trans->init_dram.paging_cnt; 1506 } 1507 1508 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1509 struct iwl_fw_ini_region_cfg *reg) 1510 { 1511 return fwrt->num_of_paging_blk; 1512 } 1513 1514 static u32 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1515 struct iwl_fw_ini_region_cfg *reg) 1516 { 1517 return 1; 1518 } 1519 1520 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1521 struct iwl_fw_ini_region_cfg *reg) 1522 { 1523 struct iwl_ini_txf_iter_data iter = { .init = true }; 1524 void *fifo_iter = fwrt->dump.fifo_iter; 1525 u32 num_of_fifos = 0; 1526 1527 fwrt->dump.fifo_iter = &iter; 1528 while (iwl_ini_txf_iter(fwrt, reg)) 1529 num_of_fifos++; 1530 1531 fwrt->dump.fifo_iter = fifo_iter; 1532 1533 return num_of_fifos; 1534 } 1535 1536 static u32 iwl_dump_ini_rxf_ranges(struct iwl_fw_runtime *fwrt, 1537 struct iwl_fw_ini_region_cfg *reg) 1538 { 1539 /* Each Rx fifo needs a different offset and therefore, it's 1540 * region can contain only one fifo, i.e. 1 memory range. 1541 */ 1542 return 1; 1543 } 1544 1545 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1546 struct iwl_fw_ini_region_cfg *reg) 1547 { 1548 return sizeof(struct iwl_fw_ini_error_dump) + 1549 iwl_dump_ini_mem_ranges(fwrt, reg) * 1550 (sizeof(struct iwl_fw_ini_error_dump_range) + 1551 le32_to_cpu(reg->internal.range_data_size)); 1552 } 1553 1554 static u32 iwl_dump_ini_paging_gen2_get_size(struct iwl_fw_runtime *fwrt, 1555 struct iwl_fw_ini_region_cfg *reg) 1556 { 1557 int i; 1558 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1559 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1560 1561 for (i = 0; i < iwl_dump_ini_paging_gen2_ranges(fwrt, reg); i++) 1562 size += range_header_len + 1563 fwrt->trans->init_dram.paging[i].size; 1564 1565 return size; 1566 } 1567 1568 static u32 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1569 struct iwl_fw_ini_region_cfg *reg) 1570 { 1571 int i; 1572 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1573 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1574 1575 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++) 1576 size += range_header_len + fwrt->fw_paging_db[i].fw_paging_size; 1577 1578 return size; 1579 } 1580 1581 static u32 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1582 struct iwl_fw_ini_region_cfg *reg) 1583 { 1584 u32 size = sizeof(struct iwl_fw_ini_monitor_dump) + 1585 sizeof(struct iwl_fw_ini_error_dump_range); 1586 1587 if (fwrt->trans->dbg.num_blocks) 1588 size += fwrt->trans->dbg.fw_mon[0].size; 1589 1590 return size; 1591 } 1592 1593 static u32 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1594 struct iwl_fw_ini_region_cfg *reg) 1595 { 1596 return sizeof(struct iwl_fw_ini_monitor_dump) + 1597 iwl_dump_ini_mem_ranges(fwrt, reg) * 1598 (sizeof(struct iwl_fw_ini_error_dump_range) + 1599 le32_to_cpu(reg->internal.range_data_size)); 1600 } 1601 1602 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1603 struct iwl_fw_ini_region_cfg *reg) 1604 { 1605 struct iwl_ini_txf_iter_data iter = { .init = true }; 1606 void *fifo_iter = fwrt->dump.fifo_iter; 1607 u32 size = 0; 1608 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1609 le32_to_cpu(reg->fifos.num_of_registers) * 1610 sizeof(struct iwl_fw_ini_error_dump_register); 1611 1612 fwrt->dump.fifo_iter = &iter; 1613 while (iwl_ini_txf_iter(fwrt, reg)) { 1614 size += fifo_hdr; 1615 if (!reg->fifos.header_only) 1616 size += iter.fifo_size; 1617 } 1618 1619 if (size) 1620 size += sizeof(struct iwl_fw_ini_error_dump); 1621 1622 fwrt->dump.fifo_iter = fifo_iter; 1623 1624 return size; 1625 } 1626 1627 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1628 struct iwl_fw_ini_region_cfg *reg) 1629 { 1630 struct iwl_ini_rxf_data rx_data; 1631 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1632 sizeof(struct iwl_fw_ini_error_dump_range) + 1633 le32_to_cpu(reg->fifos.num_of_registers) * 1634 sizeof(struct iwl_fw_ini_error_dump_register); 1635 1636 if (reg->fifos.header_only) 1637 return size; 1638 1639 iwl_ini_get_rxf_data(fwrt, reg, &rx_data); 1640 size += rx_data.size; 1641 1642 return size; 1643 } 1644 1645 /** 1646 * struct iwl_dump_ini_mem_ops - ini memory dump operations 1647 * @get_num_of_ranges: returns the number of memory ranges in the region. 1648 * @get_size: returns the total size of the region. 1649 * @fill_mem_hdr: fills region type specific headers and returns pointer to 1650 * the first range or NULL if failed to fill headers. 1651 * @fill_range: copies a given memory range into the dump. 1652 * Returns the size of the range or negative error value otherwise. 1653 */ 1654 struct iwl_dump_ini_mem_ops { 1655 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 1656 struct iwl_fw_ini_region_cfg *reg); 1657 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 1658 struct iwl_fw_ini_region_cfg *reg); 1659 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 1660 struct iwl_fw_ini_region_cfg *reg, void *data); 1661 int (*fill_range)(struct iwl_fw_runtime *fwrt, 1662 struct iwl_fw_ini_region_cfg *reg, void *range, 1663 int idx); 1664 }; 1665 1666 /** 1667 * iwl_dump_ini_mem - copy a memory region into the dump 1668 * @fwrt: fw runtime struct. 1669 * @data: dump memory data. 1670 * @reg: region to copy to the dump. 1671 * @ops: memory dump operations. 1672 */ 1673 static void 1674 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, 1675 struct iwl_fw_error_dump_data **data, 1676 struct iwl_fw_ini_region_cfg *reg, 1677 struct iwl_dump_ini_mem_ops *ops) 1678 { 1679 struct iwl_fw_ini_error_dump_header *header = (void *)(*data)->data; 1680 u32 num_of_ranges, i, type = le32_to_cpu(reg->region_type), size; 1681 void *range; 1682 1683 if (WARN_ON(!ops || !ops->get_num_of_ranges || !ops->get_size || 1684 !ops->fill_mem_hdr || !ops->fill_range)) 1685 return; 1686 1687 size = ops->get_size(fwrt, reg); 1688 if (!size) 1689 return; 1690 1691 IWL_DEBUG_FW(fwrt, "WRT: collecting region: id=%d, type=%d\n", 1692 le32_to_cpu(reg->region_id), type); 1693 1694 num_of_ranges = ops->get_num_of_ranges(fwrt, reg); 1695 1696 (*data)->type = cpu_to_le32(type); 1697 (*data)->len = cpu_to_le32(size); 1698 1699 header->region_id = reg->region_id; 1700 header->num_of_ranges = cpu_to_le32(num_of_ranges); 1701 header->name_len = cpu_to_le32(min_t(int, IWL_FW_INI_MAX_NAME, 1702 le32_to_cpu(reg->name_len))); 1703 memcpy(header->name, reg->name, le32_to_cpu(header->name_len)); 1704 1705 range = ops->fill_mem_hdr(fwrt, reg, header); 1706 if (!range) { 1707 IWL_ERR(fwrt, 1708 "WRT: failed to fill region header: id=%d, type=%d\n", 1709 le32_to_cpu(reg->region_id), type); 1710 memset(*data, 0, size); 1711 return; 1712 } 1713 1714 for (i = 0; i < num_of_ranges; i++) { 1715 int range_size = ops->fill_range(fwrt, reg, range, i); 1716 1717 if (range_size < 0) { 1718 IWL_ERR(fwrt, 1719 "WRT: failed to dump region: id=%d, type=%d\n", 1720 le32_to_cpu(reg->region_id), type); 1721 memset(*data, 0, size); 1722 return; 1723 } 1724 range = range + range_size; 1725 } 1726 *data = iwl_fw_error_next_data(*data); 1727 } 1728 1729 static void iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 1730 struct iwl_fw_ini_trigger *trigger, 1731 struct iwl_fw_error_dump_data **data) 1732 { 1733 struct iwl_fw_ini_dump_info *dump = (void *)(*data)->data; 1734 u32 reg_ids_size = le32_to_cpu(trigger->num_regions) * sizeof(__le32); 1735 1736 (*data)->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 1737 (*data)->len = cpu_to_le32(sizeof(*dump) + reg_ids_size); 1738 1739 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 1740 dump->trigger_id = trigger->trigger_id; 1741 dump->is_external_cfg = 1742 cpu_to_le32(fwrt->trans->dbg.external_ini_loaded); 1743 1744 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 1745 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 1746 1747 dump->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 1748 dump->hw_type = cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 1749 1750 dump->rf_id_flavor = 1751 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 1752 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 1753 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 1754 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 1755 1756 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 1757 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 1758 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 1759 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 1760 1761 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 1762 memcpy(dump->build_tag, fwrt->fw->human_readable, 1763 sizeof(dump->build_tag)); 1764 1765 dump->img_name_len = cpu_to_le32(sizeof(dump->img_name)); 1766 memcpy(dump->img_name, fwrt->dump.img_name, sizeof(dump->img_name)); 1767 1768 dump->internal_dbg_cfg_name_len = 1769 cpu_to_le32(sizeof(dump->internal_dbg_cfg_name)); 1770 memcpy(dump->internal_dbg_cfg_name, fwrt->dump.internal_dbg_cfg_name, 1771 sizeof(dump->internal_dbg_cfg_name)); 1772 1773 dump->external_dbg_cfg_name_len = 1774 cpu_to_le32(sizeof(dump->external_dbg_cfg_name)); 1775 1776 /* dump info size is allocated in iwl_fw_ini_get_trigger_len. 1777 * The driver allocates (sizeof(*dump) + reg_ids_size) so it is safe to 1778 * use reg_ids_size 1779 */ 1780 memcpy(dump->external_dbg_cfg_name, fwrt->dump.external_dbg_cfg_name, 1781 sizeof(dump->external_dbg_cfg_name)); 1782 1783 dump->regions_num = trigger->num_regions; 1784 memcpy(dump->region_ids, trigger->data, reg_ids_size); 1785 1786 *data = iwl_fw_error_next_data(*data); 1787 } 1788 1789 static int iwl_fw_ini_get_trigger_len(struct iwl_fw_runtime *fwrt, 1790 struct iwl_fw_ini_trigger *trigger) 1791 { 1792 int i, ret_size = 0, hdr_len = sizeof(struct iwl_fw_error_dump_data); 1793 u32 size; 1794 1795 if (!trigger || !trigger->num_regions) 1796 return 0; 1797 1798 for (i = 0; i < le32_to_cpu(trigger->num_regions); i++) { 1799 u32 reg_id = le32_to_cpu(trigger->data[i]); 1800 struct iwl_fw_ini_region_cfg *reg; 1801 1802 if (WARN_ON(reg_id >= ARRAY_SIZE(fwrt->dump.active_regs))) 1803 continue; 1804 1805 reg = fwrt->dump.active_regs[reg_id]; 1806 if (!reg) { 1807 IWL_WARN(fwrt, 1808 "WRT: unassigned region id %d, skipping\n", 1809 reg_id); 1810 continue; 1811 } 1812 1813 /* currently the driver supports always on domain only */ 1814 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 1815 continue; 1816 1817 switch (le32_to_cpu(reg->region_type)) { 1818 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1819 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1820 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1821 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1822 case IWL_FW_INI_REGION_CSR: 1823 case IWL_FW_INI_REGION_LMAC_ERROR_TABLE: 1824 case IWL_FW_INI_REGION_UMAC_ERROR_TABLE: 1825 size = iwl_dump_ini_mem_get_size(fwrt, reg); 1826 if (size) 1827 ret_size += hdr_len + size; 1828 break; 1829 case IWL_FW_INI_REGION_TXF: 1830 size = iwl_dump_ini_txf_get_size(fwrt, reg); 1831 if (size) 1832 ret_size += hdr_len + size; 1833 break; 1834 case IWL_FW_INI_REGION_RXF: 1835 size = iwl_dump_ini_rxf_get_size(fwrt, reg); 1836 if (size) 1837 ret_size += hdr_len + size; 1838 break; 1839 case IWL_FW_INI_REGION_PAGING: 1840 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1841 size = iwl_dump_ini_paging_get_size(fwrt, reg); 1842 else 1843 size = iwl_dump_ini_paging_gen2_get_size(fwrt, 1844 reg); 1845 if (size) 1846 ret_size += hdr_len + size; 1847 break; 1848 case IWL_FW_INI_REGION_DRAM_BUFFER: 1849 if (!fwrt->trans->dbg.num_blocks) 1850 break; 1851 size = iwl_dump_ini_mon_dram_get_size(fwrt, reg); 1852 if (size) 1853 ret_size += hdr_len + size; 1854 break; 1855 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1856 size = iwl_dump_ini_mon_smem_get_size(fwrt, reg); 1857 if (size) 1858 ret_size += hdr_len + size; 1859 break; 1860 case IWL_FW_INI_REGION_DRAM_IMR: 1861 /* Undefined yet */ 1862 default: 1863 break; 1864 } 1865 } 1866 1867 /* add dump info size */ 1868 if (ret_size) 1869 ret_size += hdr_len + sizeof(struct iwl_fw_ini_dump_info) + 1870 (le32_to_cpu(trigger->num_regions) * sizeof(__le32)); 1871 1872 return ret_size; 1873 } 1874 1875 static void iwl_fw_ini_dump_trigger(struct iwl_fw_runtime *fwrt, 1876 struct iwl_fw_ini_trigger *trigger, 1877 struct iwl_fw_error_dump_data **data) 1878 { 1879 int i, num = le32_to_cpu(trigger->num_regions); 1880 1881 iwl_dump_ini_info(fwrt, trigger, data); 1882 1883 for (i = 0; i < num; i++) { 1884 u32 reg_id = le32_to_cpu(trigger->data[i]); 1885 struct iwl_fw_ini_region_cfg *reg; 1886 struct iwl_dump_ini_mem_ops ops; 1887 1888 if (reg_id >= ARRAY_SIZE(fwrt->dump.active_regs)) 1889 continue; 1890 1891 reg = fwrt->dump.active_regs[reg_id]; 1892 /* Don't warn, get_trigger_len already warned */ 1893 if (!reg) 1894 continue; 1895 1896 /* currently the driver supports always on domain only */ 1897 if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 1898 continue; 1899 1900 switch (le32_to_cpu(reg->region_type)) { 1901 case IWL_FW_INI_REGION_DEVICE_MEMORY: 1902 case IWL_FW_INI_REGION_LMAC_ERROR_TABLE: 1903 case IWL_FW_INI_REGION_UMAC_ERROR_TABLE: 1904 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1905 ops.get_size = iwl_dump_ini_mem_get_size; 1906 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1907 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1908 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1909 break; 1910 case IWL_FW_INI_REGION_PERIPHERY_MAC: 1911 case IWL_FW_INI_REGION_PERIPHERY_PHY: 1912 case IWL_FW_INI_REGION_PERIPHERY_AUX: 1913 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1914 ops.get_size = iwl_dump_ini_mem_get_size; 1915 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1916 ops.fill_range = iwl_dump_ini_prph_iter; 1917 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1918 break; 1919 case IWL_FW_INI_REGION_DRAM_BUFFER: 1920 ops.get_num_of_ranges = iwl_dump_ini_mon_dram_ranges; 1921 ops.get_size = iwl_dump_ini_mon_dram_get_size; 1922 ops.fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header; 1923 ops.fill_range = iwl_dump_ini_mon_dram_iter; 1924 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1925 break; 1926 case IWL_FW_INI_REGION_INTERNAL_BUFFER: 1927 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1928 ops.get_size = iwl_dump_ini_mon_smem_get_size; 1929 ops.fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header; 1930 ops.fill_range = iwl_dump_ini_dev_mem_iter; 1931 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1932 break; 1933 case IWL_FW_INI_REGION_PAGING: 1934 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1935 if (iwl_fw_dbg_is_paging_enabled(fwrt)) { 1936 ops.get_num_of_ranges = 1937 iwl_dump_ini_paging_ranges; 1938 ops.get_size = iwl_dump_ini_paging_get_size; 1939 ops.fill_range = iwl_dump_ini_paging_iter; 1940 } else { 1941 ops.get_num_of_ranges = 1942 iwl_dump_ini_paging_gen2_ranges; 1943 ops.get_size = 1944 iwl_dump_ini_paging_gen2_get_size; 1945 ops.fill_range = iwl_dump_ini_paging_gen2_iter; 1946 } 1947 1948 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1949 break; 1950 case IWL_FW_INI_REGION_TXF: { 1951 struct iwl_ini_txf_iter_data iter = { .init = true }; 1952 void *fifo_iter = fwrt->dump.fifo_iter; 1953 1954 fwrt->dump.fifo_iter = &iter; 1955 ops.get_num_of_ranges = iwl_dump_ini_txf_ranges; 1956 ops.get_size = iwl_dump_ini_txf_get_size; 1957 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1958 ops.fill_range = iwl_dump_ini_txf_iter; 1959 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1960 fwrt->dump.fifo_iter = fifo_iter; 1961 break; 1962 } 1963 case IWL_FW_INI_REGION_RXF: 1964 ops.get_num_of_ranges = iwl_dump_ini_rxf_ranges; 1965 ops.get_size = iwl_dump_ini_rxf_get_size; 1966 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1967 ops.fill_range = iwl_dump_ini_rxf_iter; 1968 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1969 break; 1970 case IWL_FW_INI_REGION_CSR: 1971 ops.get_num_of_ranges = iwl_dump_ini_mem_ranges; 1972 ops.get_size = iwl_dump_ini_mem_get_size; 1973 ops.fill_mem_hdr = iwl_dump_ini_mem_fill_header; 1974 ops.fill_range = iwl_dump_ini_csr_iter; 1975 iwl_dump_ini_mem(fwrt, data, reg, &ops); 1976 break; 1977 case IWL_FW_INI_REGION_DRAM_IMR: 1978 /* This is undefined yet */ 1979 default: 1980 break; 1981 } 1982 } 1983 } 1984 1985 static struct iwl_fw_error_dump_file * 1986 iwl_fw_error_ini_dump_file(struct iwl_fw_runtime *fwrt, 1987 enum iwl_fw_ini_trigger_id trig_id) 1988 { 1989 int size; 1990 struct iwl_fw_error_dump_data *dump_data; 1991 struct iwl_fw_error_dump_file *dump_file; 1992 struct iwl_fw_ini_trigger *trigger; 1993 1994 if (!iwl_fw_ini_trigger_on(fwrt, trig_id)) 1995 return NULL; 1996 1997 trigger = fwrt->dump.active_trigs[trig_id].trig; 1998 1999 size = iwl_fw_ini_get_trigger_len(fwrt, trigger); 2000 if (!size) 2001 return NULL; 2002 2003 size += sizeof(*dump_file); 2004 2005 dump_file = vzalloc(size); 2006 if (!dump_file) 2007 return NULL; 2008 2009 dump_file->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2010 dump_data = (void *)dump_file->data; 2011 dump_file->file_len = cpu_to_le32(size); 2012 2013 iwl_fw_ini_dump_trigger(fwrt, trigger, &dump_data); 2014 2015 return dump_file; 2016 } 2017 2018 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 2019 { 2020 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2021 struct iwl_fw_error_dump_file *dump_file; 2022 struct scatterlist *sg_dump_data; 2023 u32 file_len; 2024 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2025 2026 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump); 2027 if (!dump_file) 2028 goto out; 2029 2030 if (fwrt->dump.monitor_only) 2031 dump_mask &= IWL_FW_ERROR_DUMP_FW_MONITOR; 2032 2033 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask); 2034 file_len = le32_to_cpu(dump_file->file_len); 2035 fw_error_dump.fwrt_len = file_len; 2036 2037 if (fw_error_dump.trans_ptr) { 2038 file_len += fw_error_dump.trans_ptr->len; 2039 dump_file->file_len = cpu_to_le32(file_len); 2040 } 2041 2042 sg_dump_data = alloc_sgtable(file_len); 2043 if (sg_dump_data) { 2044 sg_pcopy_from_buffer(sg_dump_data, 2045 sg_nents(sg_dump_data), 2046 fw_error_dump.fwrt_ptr, 2047 fw_error_dump.fwrt_len, 0); 2048 if (fw_error_dump.trans_ptr) 2049 sg_pcopy_from_buffer(sg_dump_data, 2050 sg_nents(sg_dump_data), 2051 fw_error_dump.trans_ptr->data, 2052 fw_error_dump.trans_ptr->len, 2053 fw_error_dump.fwrt_len); 2054 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2055 GFP_KERNEL); 2056 } 2057 vfree(fw_error_dump.fwrt_ptr); 2058 vfree(fw_error_dump.trans_ptr); 2059 2060 out: 2061 iwl_fw_free_dump_desc(fwrt); 2062 } 2063 2064 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2065 { 2066 enum iwl_fw_ini_trigger_id trig_id = fwrt->dump.wks[wk_idx].ini_trig_id; 2067 struct iwl_fw_error_dump_file *dump_file; 2068 struct scatterlist *sg_dump_data; 2069 u32 file_len; 2070 2071 dump_file = iwl_fw_error_ini_dump_file(fwrt, trig_id); 2072 if (!dump_file) 2073 goto out; 2074 2075 file_len = le32_to_cpu(dump_file->file_len); 2076 2077 sg_dump_data = alloc_sgtable(file_len); 2078 if (sg_dump_data) { 2079 sg_pcopy_from_buffer(sg_dump_data, sg_nents(sg_dump_data), 2080 dump_file, file_len, 0); 2081 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2082 GFP_KERNEL); 2083 } 2084 vfree(dump_file); 2085 out: 2086 fwrt->dump.wks[wk_idx].ini_trig_id = IWL_FW_TRIGGER_ID_INVALID; 2087 } 2088 2089 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2090 .trig_desc = { 2091 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2092 }, 2093 }; 2094 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2095 2096 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2097 const struct iwl_fw_dump_desc *desc, 2098 bool monitor_only, 2099 unsigned int delay) 2100 { 2101 u32 trig_type = le32_to_cpu(desc->trig_desc.type); 2102 int ret; 2103 2104 if (fwrt->trans->dbg.ini_valid) { 2105 ret = iwl_fw_dbg_ini_collect(fwrt, trig_type); 2106 if (!ret) 2107 iwl_fw_free_dump_desc(fwrt); 2108 2109 return ret; 2110 } 2111 2112 /* use wks[0] since dump flow prior to ini does not need to support 2113 * consecutive triggers collection 2114 */ 2115 if (test_and_set_bit(fwrt->dump.wks[0].idx, &fwrt->dump.active_wks)) 2116 return -EBUSY; 2117 2118 if (WARN_ON(fwrt->dump.desc)) 2119 iwl_fw_free_dump_desc(fwrt); 2120 2121 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2122 le32_to_cpu(desc->trig_desc.type)); 2123 2124 fwrt->dump.desc = desc; 2125 fwrt->dump.monitor_only = monitor_only; 2126 2127 schedule_delayed_work(&fwrt->dump.wks[0].wk, usecs_to_jiffies(delay)); 2128 2129 return 0; 2130 } 2131 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2132 2133 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2134 enum iwl_fw_dbg_trigger trig_type) 2135 { 2136 int ret; 2137 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2138 2139 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2140 return -EIO; 2141 2142 iwl_dump_error_desc = kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2143 if (!iwl_dump_error_desc) 2144 return -ENOMEM; 2145 2146 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2147 iwl_dump_error_desc->len = 0; 2148 2149 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, false, 0); 2150 if (ret) 2151 kfree(iwl_dump_error_desc); 2152 else 2153 iwl_trans_sync_nmi(fwrt->trans); 2154 2155 return ret; 2156 } 2157 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2158 2159 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2160 enum iwl_fw_dbg_trigger trig, 2161 const char *str, size_t len, 2162 struct iwl_fw_dbg_trigger_tlv *trigger) 2163 { 2164 struct iwl_fw_dump_desc *desc; 2165 unsigned int delay = 0; 2166 bool monitor_only = false; 2167 2168 if (trigger) { 2169 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2170 2171 if (!le16_to_cpu(trigger->occurrences)) 2172 return 0; 2173 2174 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2175 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2176 trig); 2177 iwl_force_nmi(fwrt->trans); 2178 return 0; 2179 } 2180 2181 trigger->occurrences = cpu_to_le16(occurrences); 2182 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2183 2184 /* convert msec to usec */ 2185 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2186 } 2187 2188 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 2189 if (!desc) 2190 return -ENOMEM; 2191 2192 2193 desc->len = len; 2194 desc->trig_desc.type = cpu_to_le32(trig); 2195 memcpy(desc->trig_desc.data, str, len); 2196 2197 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2198 } 2199 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2200 2201 int _iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 2202 enum iwl_fw_ini_trigger_id id) 2203 { 2204 struct iwl_fw_ini_active_triggers *active; 2205 u32 occur, delay; 2206 unsigned long idx; 2207 2208 if (WARN_ON(!iwl_fw_ini_trigger_on(fwrt, id))) 2209 return -EINVAL; 2210 2211 if (!iwl_fw_ini_trigger_on(fwrt, id)) { 2212 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 2213 id); 2214 return -EINVAL; 2215 } 2216 2217 active = &fwrt->dump.active_trigs[id]; 2218 delay = le32_to_cpu(active->trig->dump_delay); 2219 occur = le32_to_cpu(active->trig->occurrences); 2220 if (!occur) 2221 return 0; 2222 2223 active->trig->occurrences = cpu_to_le32(--occur); 2224 2225 if (le32_to_cpu(active->trig->force_restart)) { 2226 IWL_WARN(fwrt, "WRT: force restart: trigger %d fired.\n", id); 2227 iwl_force_nmi(fwrt->trans); 2228 return 0; 2229 } 2230 2231 /* Check there is an available worker. 2232 * ffz return value is undefined if no zero exists, 2233 * so check against ~0UL first. 2234 */ 2235 if (fwrt->dump.active_wks == ~0UL) 2236 return -EBUSY; 2237 2238 idx = ffz(fwrt->dump.active_wks); 2239 2240 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2241 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2242 return -EBUSY; 2243 2244 fwrt->dump.wks[idx].ini_trig_id = id; 2245 2246 IWL_WARN(fwrt, "WRT: collecting data: ini trigger %d fired.\n", id); 2247 2248 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 2249 2250 return 0; 2251 } 2252 IWL_EXPORT_SYMBOL(_iwl_fw_dbg_ini_collect); 2253 2254 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, u32 legacy_trigger_id) 2255 { 2256 int id; 2257 2258 switch (legacy_trigger_id) { 2259 case FW_DBG_TRIGGER_FW_ASSERT: 2260 case FW_DBG_TRIGGER_ALIVE_TIMEOUT: 2261 case FW_DBG_TRIGGER_DRIVER: 2262 id = IWL_FW_TRIGGER_ID_FW_ASSERT; 2263 break; 2264 case FW_DBG_TRIGGER_USER: 2265 id = IWL_FW_TRIGGER_ID_USER_TRIGGER; 2266 break; 2267 default: 2268 return -EIO; 2269 } 2270 2271 return _iwl_fw_dbg_ini_collect(fwrt, id); 2272 } 2273 IWL_EXPORT_SYMBOL(iwl_fw_dbg_ini_collect); 2274 2275 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2276 struct iwl_fw_dbg_trigger_tlv *trigger, 2277 const char *fmt, ...) 2278 { 2279 int ret, len = 0; 2280 char buf[64]; 2281 2282 if (fmt) { 2283 va_list ap; 2284 2285 buf[sizeof(buf) - 1] = '\0'; 2286 2287 va_start(ap, fmt); 2288 vsnprintf(buf, sizeof(buf), fmt, ap); 2289 va_end(ap); 2290 2291 /* check for truncation */ 2292 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2293 buf[sizeof(buf) - 1] = '\0'; 2294 2295 len = strlen(buf) + 1; 2296 } 2297 2298 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2299 trigger); 2300 2301 if (ret) 2302 return ret; 2303 2304 return 0; 2305 } 2306 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2307 2308 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2309 { 2310 u8 *ptr; 2311 int ret; 2312 int i; 2313 2314 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2315 "Invalid configuration %d\n", conf_id)) 2316 return -EINVAL; 2317 2318 /* EARLY START - firmware's configuration is hard coded */ 2319 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2320 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2321 conf_id == FW_DBG_START_FROM_ALIVE) 2322 return 0; 2323 2324 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2325 return -EINVAL; 2326 2327 if (fwrt->dump.conf != FW_DBG_INVALID) 2328 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 2329 fwrt->dump.conf); 2330 2331 /* Send all HCMDs for configuring the FW debug */ 2332 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2333 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2334 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2335 struct iwl_host_cmd hcmd = { 2336 .id = cmd->id, 2337 .len = { le16_to_cpu(cmd->len), }, 2338 .data = { cmd->data, }, 2339 }; 2340 2341 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2342 if (ret) 2343 return ret; 2344 2345 ptr += sizeof(*cmd); 2346 ptr += le16_to_cpu(cmd->len); 2347 } 2348 2349 fwrt->dump.conf = conf_id; 2350 2351 return 0; 2352 } 2353 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2354 2355 /* this function assumes dump_start was called beforehand and dump_end will be 2356 * called afterwards 2357 */ 2358 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2359 { 2360 struct iwl_fw_dbg_params params = {0}; 2361 2362 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2363 return; 2364 2365 if (fwrt->ops && fwrt->ops->fw_running && 2366 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 2367 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 2368 iwl_fw_free_dump_desc(fwrt); 2369 goto out; 2370 } 2371 2372 /* there's no point in fw dump if the bus is dead */ 2373 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2374 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2375 goto out; 2376 } 2377 2378 if (iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true)) { 2379 IWL_ERR(fwrt, "Failed to stop DBGC recording, aborting dump\n"); 2380 goto out; 2381 } 2382 2383 IWL_DEBUG_FW_INFO(fwrt, "WRT: data collection start\n"); 2384 if (fwrt->trans->dbg.ini_valid) 2385 iwl_fw_error_ini_dump(fwrt, wk_idx); 2386 else 2387 iwl_fw_error_dump(fwrt); 2388 IWL_DEBUG_FW_INFO(fwrt, "WRT: data collection done\n"); 2389 2390 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2391 2392 out: 2393 clear_bit(wk_idx, &fwrt->dump.active_wks); 2394 } 2395 2396 void iwl_fw_error_dump_wk(struct work_struct *work) 2397 { 2398 struct iwl_fw_runtime *fwrt; 2399 typeof(fwrt->dump.wks[0]) *wks; 2400 2401 wks = container_of(work, typeof(fwrt->dump.wks[0]), wk.work); 2402 fwrt = container_of(wks, struct iwl_fw_runtime, dump.wks[wks->idx]); 2403 2404 /* assumes the op mode mutex is locked in dump_start since 2405 * iwl_fw_dbg_collect_sync can't run in parallel 2406 */ 2407 if (fwrt->ops && fwrt->ops->dump_start && 2408 fwrt->ops->dump_start(fwrt->ops_ctx)) 2409 return; 2410 2411 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 2412 2413 if (fwrt->ops && fwrt->ops->dump_end) 2414 fwrt->ops->dump_end(fwrt->ops_ctx); 2415 } 2416 2417 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 2418 { 2419 const struct iwl_cfg *cfg = fwrt->trans->cfg; 2420 2421 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 2422 return; 2423 2424 if (!fwrt->dump.d3_debug_data) { 2425 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 2426 GFP_KERNEL); 2427 if (!fwrt->dump.d3_debug_data) { 2428 IWL_ERR(fwrt, 2429 "failed to allocate memory for D3 debug data\n"); 2430 return; 2431 } 2432 } 2433 2434 /* if the buffer holds previous debug data it is overwritten */ 2435 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 2436 fwrt->dump.d3_debug_data, 2437 cfg->d3_debug_data_length); 2438 } 2439 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 2440 2441 static void iwl_fw_dbg_info_apply(struct iwl_fw_runtime *fwrt, 2442 struct iwl_fw_ini_debug_info_tlv *dbg_info, 2443 bool ext, enum iwl_fw_ini_apply_point pnt) 2444 { 2445 u32 img_name_len = le32_to_cpu(dbg_info->img_name_len); 2446 u32 dbg_cfg_name_len = le32_to_cpu(dbg_info->dbg_cfg_name_len); 2447 2448 if (img_name_len != IWL_FW_INI_MAX_IMG_NAME_LEN) { 2449 IWL_WARN(fwrt, 2450 "WRT: ext=%d. Invalid image name length %d, expected %d\n", 2451 ext, img_name_len, 2452 IWL_FW_INI_MAX_IMG_NAME_LEN); 2453 return; 2454 } 2455 2456 if (dbg_cfg_name_len != IWL_FW_INI_MAX_DBG_CFG_NAME_LEN) { 2457 IWL_WARN(fwrt, 2458 "WRT: ext=%d. Invalid debug cfg name length %d, expected %d\n", 2459 ext, dbg_cfg_name_len, 2460 IWL_FW_INI_MAX_DBG_CFG_NAME_LEN); 2461 return; 2462 } 2463 2464 if (ext) { 2465 memcpy(fwrt->dump.external_dbg_cfg_name, dbg_info->dbg_cfg_name, 2466 sizeof(fwrt->dump.external_dbg_cfg_name)); 2467 } else { 2468 memcpy(fwrt->dump.img_name, dbg_info->img_name, 2469 sizeof(fwrt->dump.img_name)); 2470 memcpy(fwrt->dump.internal_dbg_cfg_name, dbg_info->dbg_cfg_name, 2471 sizeof(fwrt->dump.internal_dbg_cfg_name)); 2472 } 2473 } 2474 2475 static void 2476 iwl_fw_dbg_buffer_allocation(struct iwl_fw_runtime *fwrt, u32 size) 2477 { 2478 struct iwl_trans *trans = fwrt->trans; 2479 void *virtual_addr = NULL; 2480 dma_addr_t phys_addr; 2481 2482 if (WARN_ON_ONCE(trans->dbg.num_blocks == 2483 ARRAY_SIZE(trans->dbg.fw_mon))) 2484 return; 2485 2486 virtual_addr = 2487 dma_alloc_coherent(fwrt->trans->dev, size, &phys_addr, 2488 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO | 2489 __GFP_COMP); 2490 2491 /* TODO: alloc fragments if needed */ 2492 if (!virtual_addr) 2493 IWL_ERR(fwrt, "Failed to allocate debug memory\n"); 2494 2495 IWL_DEBUG_FW(trans, 2496 "Allocated DRAM buffer[%d], size=0x%x\n", 2497 trans->dbg.num_blocks, size); 2498 2499 trans->dbg.fw_mon[trans->dbg.num_blocks].block = virtual_addr; 2500 trans->dbg.fw_mon[trans->dbg.num_blocks].physical = phys_addr; 2501 trans->dbg.fw_mon[trans->dbg.num_blocks].size = size; 2502 trans->dbg.num_blocks++; 2503 } 2504 2505 static void iwl_fw_dbg_buffer_apply(struct iwl_fw_runtime *fwrt, 2506 struct iwl_fw_ini_allocation_tlv *alloc, 2507 enum iwl_fw_ini_apply_point pnt) 2508 { 2509 struct iwl_trans *trans = fwrt->trans; 2510 struct iwl_ldbg_config_cmd ldbg_cmd = { 2511 .type = cpu_to_le32(BUFFER_ALLOCATION), 2512 }; 2513 struct iwl_buffer_allocation_cmd *cmd = &ldbg_cmd.buffer_allocation; 2514 struct iwl_host_cmd hcmd = { 2515 .id = LDBG_CONFIG_CMD, 2516 .flags = CMD_ASYNC, 2517 .data[0] = &ldbg_cmd, 2518 .len[0] = sizeof(ldbg_cmd), 2519 }; 2520 int block_idx = trans->dbg.num_blocks; 2521 u32 buf_location = le32_to_cpu(alloc->buffer_location); 2522 u32 alloc_id = le32_to_cpu(alloc->allocation_id); 2523 2524 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 2525 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) { 2526 IWL_ERR(fwrt, "WRT: Invalid allocation id %d\n", alloc_id); 2527 return; 2528 } 2529 2530 if (fwrt->trans->dbg.ini_dest == IWL_FW_INI_LOCATION_INVALID) 2531 fwrt->trans->dbg.ini_dest = buf_location; 2532 2533 if (buf_location != fwrt->trans->dbg.ini_dest) { 2534 WARN(fwrt, 2535 "WRT: attempt to override buffer location on apply point %d\n", 2536 pnt); 2537 2538 return; 2539 } 2540 2541 if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH) { 2542 IWL_DEBUG_FW(trans, "WRT: applying SMEM buffer destination\n"); 2543 /* set sram monitor by enabling bit 7 */ 2544 iwl_set_bit(fwrt->trans, CSR_HW_IF_CONFIG_REG, 2545 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 2546 2547 return; 2548 } 2549 2550 if (buf_location != IWL_FW_INI_LOCATION_DRAM_PATH) 2551 return; 2552 2553 if (!(BIT(alloc_id) & fwrt->trans->dbg.is_alloc)) { 2554 iwl_fw_dbg_buffer_allocation(fwrt, le32_to_cpu(alloc->size)); 2555 if (block_idx == trans->dbg.num_blocks) 2556 return; 2557 fwrt->trans->dbg.is_alloc |= BIT(alloc_id); 2558 } 2559 2560 /* First block is assigned via registers / context info */ 2561 if (trans->dbg.num_blocks == 1) 2562 return; 2563 2564 IWL_DEBUG_FW(trans, 2565 "WRT: applying DRAM buffer[%d] destination\n", block_idx); 2566 2567 cmd->num_frags = cpu_to_le32(1); 2568 cmd->fragments[0].address = 2569 cpu_to_le64(trans->dbg.fw_mon[block_idx].physical); 2570 cmd->fragments[0].size = alloc->size; 2571 cmd->allocation_id = alloc->allocation_id; 2572 cmd->buffer_location = alloc->buffer_location; 2573 2574 iwl_trans_send_cmd(trans, &hcmd); 2575 } 2576 2577 static void iwl_fw_dbg_send_hcmd(struct iwl_fw_runtime *fwrt, 2578 struct iwl_ucode_tlv *tlv, 2579 bool ext) 2580 { 2581 struct iwl_fw_ini_hcmd_tlv *hcmd_tlv = (void *)&tlv->data[0]; 2582 struct iwl_fw_ini_hcmd *data = &hcmd_tlv->hcmd; 2583 u16 len = le32_to_cpu(tlv->length) - sizeof(*hcmd_tlv); 2584 2585 struct iwl_host_cmd hcmd = { 2586 .id = WIDE_ID(data->group, data->id), 2587 .len = { len, }, 2588 .data = { data->data, }, 2589 }; 2590 2591 /* currently the driver supports always on domain only */ 2592 if (le32_to_cpu(hcmd_tlv->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) 2593 return; 2594 2595 IWL_DEBUG_FW(fwrt, 2596 "WRT: ext=%d. Sending host command id=0x%x, group=0x%x\n", 2597 ext, data->id, data->group); 2598 2599 iwl_trans_send_cmd(fwrt->trans, &hcmd); 2600 } 2601 2602 static void iwl_fw_dbg_update_regions(struct iwl_fw_runtime *fwrt, 2603 struct iwl_fw_ini_region_tlv *tlv, 2604 bool ext, enum iwl_fw_ini_apply_point pnt) 2605 { 2606 void *iter = (void *)tlv->region_config; 2607 int i, size = le32_to_cpu(tlv->num_regions); 2608 const char *err_st = 2609 "WRT: ext=%d. Invalid region %s %d for apply point %d\n"; 2610 2611 for (i = 0; i < size; i++) { 2612 struct iwl_fw_ini_region_cfg *reg = iter, **active; 2613 int id = le32_to_cpu(reg->region_id); 2614 u32 type = le32_to_cpu(reg->region_type); 2615 2616 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_regs), err_st, ext, 2617 "id", id, pnt)) 2618 break; 2619 2620 if (WARN(type == 0 || type >= IWL_FW_INI_REGION_NUM, err_st, 2621 ext, "type", type, pnt)) 2622 break; 2623 2624 active = &fwrt->dump.active_regs[id]; 2625 2626 if (*active) 2627 IWL_WARN(fwrt->trans, 2628 "WRT: ext=%d. Region id %d override\n", 2629 ext, id); 2630 2631 IWL_DEBUG_FW(fwrt, 2632 "WRT: ext=%d. Activating region id %d\n", 2633 ext, id); 2634 2635 *active = reg; 2636 2637 if (type == IWL_FW_INI_REGION_TXF || 2638 type == IWL_FW_INI_REGION_RXF) 2639 iter += le32_to_cpu(reg->fifos.num_of_registers) * 2640 sizeof(__le32); 2641 else if (type == IWL_FW_INI_REGION_DEVICE_MEMORY || 2642 type == IWL_FW_INI_REGION_PERIPHERY_MAC || 2643 type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2644 type == IWL_FW_INI_REGION_PERIPHERY_AUX || 2645 type == IWL_FW_INI_REGION_INTERNAL_BUFFER || 2646 type == IWL_FW_INI_REGION_PAGING || 2647 type == IWL_FW_INI_REGION_CSR || 2648 type == IWL_FW_INI_REGION_LMAC_ERROR_TABLE || 2649 type == IWL_FW_INI_REGION_UMAC_ERROR_TABLE) 2650 iter += le32_to_cpu(reg->internal.num_of_ranges) * 2651 sizeof(__le32); 2652 2653 iter += sizeof(*reg); 2654 } 2655 } 2656 2657 static int iwl_fw_dbg_trig_realloc(struct iwl_fw_runtime *fwrt, 2658 struct iwl_fw_ini_active_triggers *active, 2659 u32 id, int size) 2660 { 2661 void *ptr; 2662 2663 if (size <= active->size) 2664 return 0; 2665 2666 ptr = krealloc(active->trig, size, GFP_KERNEL); 2667 if (!ptr) { 2668 IWL_ERR(fwrt, "WRT: Failed to allocate memory for trigger %d\n", 2669 id); 2670 return -ENOMEM; 2671 } 2672 active->trig = ptr; 2673 active->size = size; 2674 2675 return 0; 2676 } 2677 2678 static void iwl_fw_dbg_update_triggers(struct iwl_fw_runtime *fwrt, 2679 struct iwl_fw_ini_trigger_tlv *tlv, 2680 bool ext, 2681 enum iwl_fw_ini_apply_point apply_point) 2682 { 2683 int i, size = le32_to_cpu(tlv->num_triggers); 2684 void *iter = (void *)tlv->trigger_config; 2685 2686 for (i = 0; i < size; i++) { 2687 struct iwl_fw_ini_trigger *trig = iter; 2688 struct iwl_fw_ini_active_triggers *active; 2689 int id = le32_to_cpu(trig->trigger_id); 2690 u32 trig_regs_size = le32_to_cpu(trig->num_regions) * 2691 sizeof(__le32); 2692 2693 if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_trigs), 2694 "WRT: ext=%d. Invalid trigger id %d for apply point %d\n", 2695 ext, id, apply_point)) 2696 break; 2697 2698 active = &fwrt->dump.active_trigs[id]; 2699 2700 if (!active->active) { 2701 size_t trig_size = sizeof(*trig) + trig_regs_size; 2702 2703 IWL_DEBUG_FW(fwrt, 2704 "WRT: ext=%d. Activating trigger %d\n", 2705 ext, id); 2706 2707 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2708 trig_size)) 2709 goto next; 2710 2711 memcpy(active->trig, trig, trig_size); 2712 2713 } else { 2714 u32 conf_override = 2715 !(le32_to_cpu(trig->override_trig) & 0xff); 2716 u32 region_override = 2717 !(le32_to_cpu(trig->override_trig) & 0xff00); 2718 u32 offset = 0; 2719 u32 active_regs = 2720 le32_to_cpu(active->trig->num_regions); 2721 u32 new_regs = le32_to_cpu(trig->num_regions); 2722 int mem_to_add = trig_regs_size; 2723 2724 if (region_override) { 2725 IWL_DEBUG_FW(fwrt, 2726 "WRT: ext=%d. Trigger %d regions override\n", 2727 ext, id); 2728 2729 mem_to_add -= active_regs * sizeof(__le32); 2730 } else { 2731 IWL_DEBUG_FW(fwrt, 2732 "WRT: ext=%d. Trigger %d regions appending\n", 2733 ext, id); 2734 2735 offset += active_regs; 2736 new_regs += active_regs; 2737 } 2738 2739 if (iwl_fw_dbg_trig_realloc(fwrt, active, id, 2740 active->size + mem_to_add)) 2741 goto next; 2742 2743 if (conf_override) { 2744 IWL_DEBUG_FW(fwrt, 2745 "WRT: ext=%d. Trigger %d configuration override\n", 2746 ext, id); 2747 2748 memcpy(active->trig, trig, sizeof(*trig)); 2749 } 2750 2751 memcpy(active->trig->data + offset, trig->data, 2752 trig_regs_size); 2753 active->trig->num_regions = cpu_to_le32(new_regs); 2754 } 2755 2756 /* Since zero means infinity - just set to -1 */ 2757 if (!le32_to_cpu(active->trig->occurrences)) 2758 active->trig->occurrences = cpu_to_le32(-1); 2759 2760 active->active = true; 2761 2762 if (id == IWL_FW_TRIGGER_ID_PERIODIC_TRIGGER) { 2763 u32 collect_interval = le32_to_cpu(trig->trigger_data); 2764 2765 /* the minimum allowed interval is 50ms */ 2766 if (collect_interval < 50) { 2767 collect_interval = 50; 2768 trig->trigger_data = 2769 cpu_to_le32(collect_interval); 2770 } 2771 2772 mod_timer(&fwrt->dump.periodic_trig, 2773 jiffies + msecs_to_jiffies(collect_interval)); 2774 } 2775 next: 2776 iter += sizeof(*trig) + trig_regs_size; 2777 2778 } 2779 } 2780 2781 static void _iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2782 struct iwl_apply_point_data *data, 2783 enum iwl_fw_ini_apply_point pnt, 2784 bool ext) 2785 { 2786 void *iter = data->data; 2787 2788 while (iter && iter < data->data + data->size) { 2789 struct iwl_ucode_tlv *tlv = iter; 2790 void *ini_tlv = (void *)tlv->data; 2791 u32 type = le32_to_cpu(tlv->type); 2792 2793 switch (type) { 2794 case IWL_UCODE_TLV_TYPE_DEBUG_INFO: 2795 iwl_fw_dbg_info_apply(fwrt, ini_tlv, ext, pnt); 2796 break; 2797 case IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION: 2798 if (pnt != IWL_FW_INI_APPLY_EARLY) { 2799 IWL_ERR(fwrt, 2800 "WRT: ext=%d. Invalid apply point %d for buffer allocation\n", 2801 ext, pnt); 2802 goto next; 2803 } 2804 iwl_fw_dbg_buffer_apply(fwrt, ini_tlv, pnt); 2805 break; 2806 case IWL_UCODE_TLV_TYPE_HCMD: 2807 if (pnt < IWL_FW_INI_APPLY_AFTER_ALIVE) { 2808 IWL_ERR(fwrt, 2809 "WRT: ext=%d. Invalid apply point %d for host command\n", 2810 ext, pnt); 2811 goto next; 2812 } 2813 iwl_fw_dbg_send_hcmd(fwrt, tlv, ext); 2814 break; 2815 case IWL_UCODE_TLV_TYPE_REGIONS: 2816 iwl_fw_dbg_update_regions(fwrt, ini_tlv, ext, pnt); 2817 break; 2818 case IWL_UCODE_TLV_TYPE_TRIGGERS: 2819 iwl_fw_dbg_update_triggers(fwrt, ini_tlv, ext, pnt); 2820 break; 2821 case IWL_UCODE_TLV_TYPE_DEBUG_FLOW: 2822 break; 2823 default: 2824 WARN_ONCE(1, 2825 "WRT: ext=%d. Invalid TLV 0x%x for apply point\n", 2826 ext, type); 2827 break; 2828 } 2829 next: 2830 iter += sizeof(*tlv) + le32_to_cpu(tlv->length); 2831 } 2832 } 2833 2834 static void iwl_fw_dbg_ini_reset_cfg(struct iwl_fw_runtime *fwrt) 2835 { 2836 int i; 2837 2838 for (i = 0; i < IWL_FW_INI_MAX_REGION_ID; i++) 2839 fwrt->dump.active_regs[i] = NULL; 2840 2841 /* disable the triggers, used in recovery flow */ 2842 for (i = 0; i < IWL_FW_TRIGGER_ID_NUM; i++) 2843 fwrt->dump.active_trigs[i].active = false; 2844 2845 memset(fwrt->dump.img_name, 0, 2846 sizeof(fwrt->dump.img_name)); 2847 memset(fwrt->dump.internal_dbg_cfg_name, 0, 2848 sizeof(fwrt->dump.internal_dbg_cfg_name)); 2849 memset(fwrt->dump.external_dbg_cfg_name, 0, 2850 sizeof(fwrt->dump.external_dbg_cfg_name)); 2851 2852 fwrt->trans->dbg.ini_dest = IWL_FW_INI_LOCATION_INVALID; 2853 } 2854 2855 void iwl_fw_dbg_apply_point(struct iwl_fw_runtime *fwrt, 2856 enum iwl_fw_ini_apply_point apply_point) 2857 { 2858 void *data = &fwrt->trans->dbg.apply_points[apply_point]; 2859 2860 IWL_DEBUG_FW(fwrt, "WRT: enabling apply point %d\n", apply_point); 2861 2862 if (apply_point == IWL_FW_INI_APPLY_EARLY) 2863 iwl_fw_dbg_ini_reset_cfg(fwrt); 2864 2865 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, false); 2866 2867 data = &fwrt->trans->dbg.apply_points_ext[apply_point]; 2868 _iwl_fw_dbg_apply_point(fwrt, data, apply_point, true); 2869 } 2870 IWL_EXPORT_SYMBOL(iwl_fw_dbg_apply_point); 2871 2872 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 2873 { 2874 int i; 2875 2876 del_timer(&fwrt->dump.periodic_trig); 2877 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 2878 iwl_fw_dbg_collect_sync(fwrt, i); 2879 2880 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 2881 } 2882 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 2883 2884 void iwl_fw_dbg_periodic_trig_handler(struct timer_list *t) 2885 { 2886 struct iwl_fw_runtime *fwrt; 2887 enum iwl_fw_ini_trigger_id id = IWL_FW_TRIGGER_ID_PERIODIC_TRIGGER; 2888 int ret; 2889 typeof(fwrt->dump) *dump_ptr = container_of(t, typeof(fwrt->dump), 2890 periodic_trig); 2891 2892 fwrt = container_of(dump_ptr, typeof(*fwrt), dump); 2893 2894 ret = _iwl_fw_dbg_ini_collect(fwrt, id); 2895 if (!ret || ret == -EBUSY) { 2896 struct iwl_fw_ini_trigger *trig = 2897 fwrt->dump.active_trigs[id].trig; 2898 u32 occur = le32_to_cpu(trig->occurrences); 2899 u32 collect_interval = le32_to_cpu(trig->trigger_data); 2900 2901 if (!occur) 2902 return; 2903 2904 mod_timer(&fwrt->dump.periodic_trig, 2905 jiffies + msecs_to_jiffies(collect_interval)); 2906 } 2907 } 2908 2909 #define FSEQ_REG(x) { .addr = (x), .str = #x, } 2910 2911 void iwl_fw_error_print_fseq_regs(struct iwl_fw_runtime *fwrt) 2912 { 2913 struct iwl_trans *trans = fwrt->trans; 2914 unsigned long flags; 2915 int i; 2916 struct { 2917 u32 addr; 2918 const char *str; 2919 } fseq_regs[] = { 2920 FSEQ_REG(FSEQ_ERROR_CODE), 2921 FSEQ_REG(FSEQ_TOP_INIT_VERSION), 2922 FSEQ_REG(FSEQ_CNVIO_INIT_VERSION), 2923 FSEQ_REG(FSEQ_OTP_VERSION), 2924 FSEQ_REG(FSEQ_TOP_CONTENT_VERSION), 2925 FSEQ_REG(FSEQ_ALIVE_TOKEN), 2926 FSEQ_REG(FSEQ_CNVI_ID), 2927 FSEQ_REG(FSEQ_CNVR_ID), 2928 FSEQ_REG(CNVI_AUX_MISC_CHIP), 2929 FSEQ_REG(CNVR_AUX_MISC_CHIP), 2930 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM), 2931 FSEQ_REG(CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR), 2932 }; 2933 2934 if (!iwl_trans_grab_nic_access(trans, &flags)) 2935 return; 2936 2937 IWL_ERR(fwrt, "Fseq Registers:\n"); 2938 2939 for (i = 0; i < ARRAY_SIZE(fseq_regs); i++) 2940 IWL_ERR(fwrt, "0x%08X | %s\n", 2941 iwl_read_prph_no_grab(trans, fseq_regs[i].addr), 2942 fseq_regs[i].str); 2943 2944 iwl_trans_release_nic_access(trans, &flags); 2945 } 2946 IWL_EXPORT_SYMBOL(iwl_fw_error_print_fseq_regs); 2947 2948 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 2949 { 2950 struct iwl_dbg_suspend_resume_cmd cmd = { 2951 .operation = suspend ? 2952 cpu_to_le32(DBGC_SUSPEND_CMD) : 2953 cpu_to_le32(DBGC_RESUME_CMD), 2954 }; 2955 struct iwl_host_cmd hcmd = { 2956 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 2957 .data[0] = &cmd, 2958 .len[0] = sizeof(cmd), 2959 }; 2960 2961 return iwl_trans_send_cmd(trans, &hcmd); 2962 } 2963 2964 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 2965 struct iwl_fw_dbg_params *params) 2966 { 2967 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2968 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2969 return; 2970 } 2971 2972 if (params) { 2973 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 2974 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 2975 } 2976 2977 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 2978 /* wait for the DBGC to finish writing the internal buffer to DRAM to 2979 * avoid halting the HW while writing 2980 */ 2981 usleep_range(700, 1000); 2982 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 2983 } 2984 2985 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 2986 struct iwl_fw_dbg_params *params) 2987 { 2988 if (!params) 2989 return -EIO; 2990 2991 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 2992 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 2993 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2994 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 2995 } else { 2996 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 2997 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 2998 } 2999 3000 return 0; 3001 } 3002 3003 int iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3004 struct iwl_fw_dbg_params *params, 3005 bool stop) 3006 { 3007 int ret = 0; 3008 3009 /* if the FW crashed or not debug monitor cfg was given, there is 3010 * no point in changing the recording state 3011 */ 3012 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status) || 3013 (!fwrt->trans->dbg.dest_tlv && 3014 fwrt->trans->dbg.ini_dest == IWL_FW_INI_LOCATION_INVALID)) 3015 return 0; 3016 3017 if (fw_has_capa(&fwrt->fw->ucode_capa, 3018 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) 3019 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3020 else if (stop) 3021 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3022 else 3023 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3024 #ifdef CONFIG_IWLWIFI_DEBUGFS 3025 if (!ret) { 3026 if (stop) 3027 fwrt->trans->dbg.rec_on = false; 3028 else 3029 iwl_fw_set_dbg_rec_on(fwrt); 3030 } 3031 #endif 3032 3033 return ret; 3034 } 3035 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3036