1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "iwl-fh.h" 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @fwrt_len: length of the valid data in fwrt_ptr 23 */ 24 struct iwl_fw_dump_ptrs { 25 struct iwl_trans_dump_data *trans_ptr; 26 void *fwrt_ptr; 27 u32 fwrt_len; 28 }; 29 30 #define RADIO_REG_MAX_READ 0x2ad 31 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 32 struct iwl_fw_error_dump_data **dump_data) 33 { 34 u8 *pos = (void *)(*dump_data)->data; 35 int i; 36 37 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 38 39 if (!iwl_trans_grab_nic_access(fwrt->trans)) 40 return; 41 42 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 43 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 44 45 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 46 u32 rd_cmd = RADIO_RSP_RD_CMD; 47 48 rd_cmd |= i << RADIO_RSP_ADDR_POS; 49 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 50 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 51 52 pos++; 53 } 54 55 *dump_data = iwl_fw_error_next_data(*dump_data); 56 57 iwl_trans_release_nic_access(fwrt->trans); 58 } 59 60 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 61 struct iwl_fw_error_dump_data **dump_data, 62 int size, u32 offset, int fifo_num) 63 { 64 struct iwl_fw_error_dump_fifo *fifo_hdr; 65 u32 *fifo_data; 66 u32 fifo_len; 67 int i; 68 69 fifo_hdr = (void *)(*dump_data)->data; 70 fifo_data = (void *)fifo_hdr->data; 71 fifo_len = size; 72 73 /* No need to try to read the data if the length is 0 */ 74 if (fifo_len == 0) 75 return; 76 77 /* Add a TLV for the RXF */ 78 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 79 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 80 81 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 82 fifo_hdr->available_bytes = 83 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 84 RXF_RD_D_SPACE + offset)); 85 fifo_hdr->wr_ptr = 86 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 87 RXF_RD_WR_PTR + offset)); 88 fifo_hdr->rd_ptr = 89 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 90 RXF_RD_RD_PTR + offset)); 91 fifo_hdr->fence_ptr = 92 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 93 RXF_RD_FENCE_PTR + offset)); 94 fifo_hdr->fence_mode = 95 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 96 RXF_SET_FENCE_MODE + offset)); 97 98 /* Lock fence */ 99 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 100 /* Set fence pointer to the same place like WR pointer */ 101 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 102 /* Set fence offset */ 103 iwl_trans_write_prph(fwrt->trans, 104 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 105 106 /* Read FIFO */ 107 fifo_len /= sizeof(u32); /* Size in DWORDS */ 108 for (i = 0; i < fifo_len; i++) 109 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 110 RXF_FIFO_RD_FENCE_INC + 111 offset); 112 *dump_data = iwl_fw_error_next_data(*dump_data); 113 } 114 115 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 116 struct iwl_fw_error_dump_data **dump_data, 117 int size, u32 offset, int fifo_num) 118 { 119 struct iwl_fw_error_dump_fifo *fifo_hdr; 120 u32 *fifo_data; 121 u32 fifo_len; 122 int i; 123 124 fifo_hdr = (void *)(*dump_data)->data; 125 fifo_data = (void *)fifo_hdr->data; 126 fifo_len = size; 127 128 /* No need to try to read the data if the length is 0 */ 129 if (fifo_len == 0) 130 return; 131 132 /* Add a TLV for the FIFO */ 133 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 134 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 135 136 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 137 fifo_hdr->available_bytes = 138 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 139 TXF_FIFO_ITEM_CNT + offset)); 140 fifo_hdr->wr_ptr = 141 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 142 TXF_WR_PTR + offset)); 143 fifo_hdr->rd_ptr = 144 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 145 TXF_RD_PTR + offset)); 146 fifo_hdr->fence_ptr = 147 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 148 TXF_FENCE_PTR + offset)); 149 fifo_hdr->fence_mode = 150 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 151 TXF_LOCK_FENCE + offset)); 152 153 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 154 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 155 TXF_WR_PTR + offset); 156 157 /* Dummy-read to advance the read pointer to the head */ 158 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 159 160 /* Read FIFO */ 161 for (i = 0; i < fifo_len / sizeof(u32); i++) 162 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 163 TXF_READ_MODIFY_DATA + 164 offset); 165 166 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 167 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 168 fifo_data, fifo_len); 169 170 *dump_data = iwl_fw_error_next_data(*dump_data); 171 } 172 173 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 174 struct iwl_fw_error_dump_data **dump_data) 175 { 176 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 177 178 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 179 180 if (!iwl_trans_grab_nic_access(fwrt->trans)) 181 return; 182 183 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 184 /* Pull RXF1 */ 185 iwl_fwrt_dump_rxf(fwrt, dump_data, 186 cfg->lmac[0].rxfifo1_size, 0, 0); 187 /* Pull RXF2 */ 188 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 189 RXF_DIFF_FROM_PREV + 190 fwrt->trans->trans_cfg->umac_prph_offset, 1); 191 /* Pull LMAC2 RXF1 */ 192 if (fwrt->smem_cfg.num_lmacs > 1) 193 iwl_fwrt_dump_rxf(fwrt, dump_data, 194 cfg->lmac[1].rxfifo1_size, 195 LMAC2_PRPH_OFFSET, 2); 196 } 197 198 iwl_trans_release_nic_access(fwrt->trans); 199 } 200 201 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 202 struct iwl_fw_error_dump_data **dump_data) 203 { 204 struct iwl_fw_error_dump_fifo *fifo_hdr; 205 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 206 u32 *fifo_data; 207 u32 fifo_len; 208 int i, j; 209 210 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 211 212 if (!iwl_trans_grab_nic_access(fwrt->trans)) 213 return; 214 215 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 216 /* Pull TXF data from LMAC1 */ 217 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 218 /* Mark the number of TXF we're pulling now */ 219 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 220 iwl_fwrt_dump_txf(fwrt, dump_data, 221 cfg->lmac[0].txfifo_size[i], 0, i); 222 } 223 224 /* Pull TXF data from LMAC2 */ 225 if (fwrt->smem_cfg.num_lmacs > 1) { 226 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 227 i++) { 228 /* Mark the number of TXF we're pulling now */ 229 iwl_trans_write_prph(fwrt->trans, 230 TXF_LARC_NUM + 231 LMAC2_PRPH_OFFSET, i); 232 iwl_fwrt_dump_txf(fwrt, dump_data, 233 cfg->lmac[1].txfifo_size[i], 234 LMAC2_PRPH_OFFSET, 235 i + cfg->num_txfifo_entries); 236 } 237 } 238 } 239 240 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 241 fw_has_capa(&fwrt->fw->ucode_capa, 242 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 243 /* Pull UMAC internal TXF data from all TXFs */ 244 for (i = 0; 245 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 246 i++) { 247 fifo_hdr = (void *)(*dump_data)->data; 248 fifo_data = (void *)fifo_hdr->data; 249 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 250 251 /* No need to try to read the data if the length is 0 */ 252 if (fifo_len == 0) 253 continue; 254 255 /* Add a TLV for the internal FIFOs */ 256 (*dump_data)->type = 257 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 258 (*dump_data)->len = 259 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 260 261 fifo_hdr->fifo_num = cpu_to_le32(i); 262 263 /* Mark the number of TXF we're pulling now */ 264 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 265 fwrt->smem_cfg.num_txfifo_entries); 266 267 fifo_hdr->available_bytes = 268 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 269 TXF_CPU2_FIFO_ITEM_CNT)); 270 fifo_hdr->wr_ptr = 271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 272 TXF_CPU2_WR_PTR)); 273 fifo_hdr->rd_ptr = 274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 275 TXF_CPU2_RD_PTR)); 276 fifo_hdr->fence_ptr = 277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 278 TXF_CPU2_FENCE_PTR)); 279 fifo_hdr->fence_mode = 280 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 281 TXF_CPU2_LOCK_FENCE)); 282 283 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 284 iwl_trans_write_prph(fwrt->trans, 285 TXF_CPU2_READ_MODIFY_ADDR, 286 TXF_CPU2_WR_PTR); 287 288 /* Dummy-read to advance the read pointer to head */ 289 iwl_trans_read_prph(fwrt->trans, 290 TXF_CPU2_READ_MODIFY_DATA); 291 292 /* Read FIFO */ 293 fifo_len /= sizeof(u32); /* Size in DWORDS */ 294 for (j = 0; j < fifo_len; j++) 295 fifo_data[j] = 296 iwl_trans_read_prph(fwrt->trans, 297 TXF_CPU2_READ_MODIFY_DATA); 298 *dump_data = iwl_fw_error_next_data(*dump_data); 299 } 300 } 301 302 iwl_trans_release_nic_access(fwrt->trans); 303 } 304 305 struct iwl_prph_range { 306 u32 start, end; 307 }; 308 309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 310 { .start = 0x00a00000, .end = 0x00a00000 }, 311 { .start = 0x00a0000c, .end = 0x00a00024 }, 312 { .start = 0x00a0002c, .end = 0x00a0003c }, 313 { .start = 0x00a00410, .end = 0x00a00418 }, 314 { .start = 0x00a00420, .end = 0x00a00420 }, 315 { .start = 0x00a00428, .end = 0x00a00428 }, 316 { .start = 0x00a00430, .end = 0x00a0043c }, 317 { .start = 0x00a00444, .end = 0x00a00444 }, 318 { .start = 0x00a004c0, .end = 0x00a004cc }, 319 { .start = 0x00a004d8, .end = 0x00a004d8 }, 320 { .start = 0x00a004e0, .end = 0x00a004f0 }, 321 { .start = 0x00a00840, .end = 0x00a00840 }, 322 { .start = 0x00a00850, .end = 0x00a00858 }, 323 { .start = 0x00a01004, .end = 0x00a01008 }, 324 { .start = 0x00a01010, .end = 0x00a01010 }, 325 { .start = 0x00a01018, .end = 0x00a01018 }, 326 { .start = 0x00a01024, .end = 0x00a01024 }, 327 { .start = 0x00a0102c, .end = 0x00a01034 }, 328 { .start = 0x00a0103c, .end = 0x00a01040 }, 329 { .start = 0x00a01048, .end = 0x00a01094 }, 330 { .start = 0x00a01c00, .end = 0x00a01c20 }, 331 { .start = 0x00a01c58, .end = 0x00a01c58 }, 332 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 333 { .start = 0x00a01c28, .end = 0x00a01c54 }, 334 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 335 { .start = 0x00a01c60, .end = 0x00a01cdc }, 336 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 337 { .start = 0x00a01d18, .end = 0x00a01d20 }, 338 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 339 { .start = 0x00a01d40, .end = 0x00a01d5c }, 340 { .start = 0x00a01d80, .end = 0x00a01d80 }, 341 { .start = 0x00a01d98, .end = 0x00a01d9c }, 342 { .start = 0x00a01da8, .end = 0x00a01da8 }, 343 { .start = 0x00a01db8, .end = 0x00a01df4 }, 344 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 345 { .start = 0x00a01e00, .end = 0x00a01e2c }, 346 { .start = 0x00a01e40, .end = 0x00a01e60 }, 347 { .start = 0x00a01e68, .end = 0x00a01e6c }, 348 { .start = 0x00a01e74, .end = 0x00a01e74 }, 349 { .start = 0x00a01e84, .end = 0x00a01e90 }, 350 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 351 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 352 { .start = 0x00a01f00, .end = 0x00a01f1c }, 353 { .start = 0x00a01f44, .end = 0x00a01ffc }, 354 { .start = 0x00a02000, .end = 0x00a02048 }, 355 { .start = 0x00a02068, .end = 0x00a020f0 }, 356 { .start = 0x00a02100, .end = 0x00a02118 }, 357 { .start = 0x00a02140, .end = 0x00a0214c }, 358 { .start = 0x00a02168, .end = 0x00a0218c }, 359 { .start = 0x00a021c0, .end = 0x00a021c0 }, 360 { .start = 0x00a02400, .end = 0x00a02410 }, 361 { .start = 0x00a02418, .end = 0x00a02420 }, 362 { .start = 0x00a02428, .end = 0x00a0242c }, 363 { .start = 0x00a02434, .end = 0x00a02434 }, 364 { .start = 0x00a02440, .end = 0x00a02460 }, 365 { .start = 0x00a02468, .end = 0x00a024b0 }, 366 { .start = 0x00a024c8, .end = 0x00a024cc }, 367 { .start = 0x00a02500, .end = 0x00a02504 }, 368 { .start = 0x00a0250c, .end = 0x00a02510 }, 369 { .start = 0x00a02540, .end = 0x00a02554 }, 370 { .start = 0x00a02580, .end = 0x00a025f4 }, 371 { .start = 0x00a02600, .end = 0x00a0260c }, 372 { .start = 0x00a02648, .end = 0x00a02650 }, 373 { .start = 0x00a02680, .end = 0x00a02680 }, 374 { .start = 0x00a026c0, .end = 0x00a026d0 }, 375 { .start = 0x00a02700, .end = 0x00a0270c }, 376 { .start = 0x00a02804, .end = 0x00a02804 }, 377 { .start = 0x00a02818, .end = 0x00a0281c }, 378 { .start = 0x00a02c00, .end = 0x00a02db4 }, 379 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 380 { .start = 0x00a03000, .end = 0x00a03014 }, 381 { .start = 0x00a0301c, .end = 0x00a0302c }, 382 { .start = 0x00a03034, .end = 0x00a03038 }, 383 { .start = 0x00a03040, .end = 0x00a03048 }, 384 { .start = 0x00a03060, .end = 0x00a03068 }, 385 { .start = 0x00a03070, .end = 0x00a03074 }, 386 { .start = 0x00a0307c, .end = 0x00a0307c }, 387 { .start = 0x00a03080, .end = 0x00a03084 }, 388 { .start = 0x00a0308c, .end = 0x00a03090 }, 389 { .start = 0x00a03098, .end = 0x00a03098 }, 390 { .start = 0x00a030a0, .end = 0x00a030a0 }, 391 { .start = 0x00a030a8, .end = 0x00a030b4 }, 392 { .start = 0x00a030bc, .end = 0x00a030bc }, 393 { .start = 0x00a030c0, .end = 0x00a0312c }, 394 { .start = 0x00a03c00, .end = 0x00a03c5c }, 395 { .start = 0x00a04400, .end = 0x00a04454 }, 396 { .start = 0x00a04460, .end = 0x00a04474 }, 397 { .start = 0x00a044c0, .end = 0x00a044ec }, 398 { .start = 0x00a04500, .end = 0x00a04504 }, 399 { .start = 0x00a04510, .end = 0x00a04538 }, 400 { .start = 0x00a04540, .end = 0x00a04548 }, 401 { .start = 0x00a04560, .end = 0x00a0457c }, 402 { .start = 0x00a04590, .end = 0x00a04598 }, 403 { .start = 0x00a045c0, .end = 0x00a045f4 }, 404 }; 405 406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 407 { .start = 0x00a05c00, .end = 0x00a05c18 }, 408 { .start = 0x00a05400, .end = 0x00a056e8 }, 409 { .start = 0x00a08000, .end = 0x00a098bc }, 410 { .start = 0x00a02400, .end = 0x00a02758 }, 411 { .start = 0x00a04764, .end = 0x00a0476c }, 412 { .start = 0x00a04770, .end = 0x00a04774 }, 413 { .start = 0x00a04620, .end = 0x00a04624 }, 414 }; 415 416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 417 { .start = 0x00a00000, .end = 0x00a00000 }, 418 { .start = 0x00a0000c, .end = 0x00a00024 }, 419 { .start = 0x00a0002c, .end = 0x00a00034 }, 420 { .start = 0x00a0003c, .end = 0x00a0003c }, 421 { .start = 0x00a00410, .end = 0x00a00418 }, 422 { .start = 0x00a00420, .end = 0x00a00420 }, 423 { .start = 0x00a00428, .end = 0x00a00428 }, 424 { .start = 0x00a00430, .end = 0x00a0043c }, 425 { .start = 0x00a00444, .end = 0x00a00444 }, 426 { .start = 0x00a00840, .end = 0x00a00840 }, 427 { .start = 0x00a00850, .end = 0x00a00858 }, 428 { .start = 0x00a01004, .end = 0x00a01008 }, 429 { .start = 0x00a01010, .end = 0x00a01010 }, 430 { .start = 0x00a01018, .end = 0x00a01018 }, 431 { .start = 0x00a01024, .end = 0x00a01024 }, 432 { .start = 0x00a0102c, .end = 0x00a01034 }, 433 { .start = 0x00a0103c, .end = 0x00a01040 }, 434 { .start = 0x00a01048, .end = 0x00a01050 }, 435 { .start = 0x00a01058, .end = 0x00a01058 }, 436 { .start = 0x00a01060, .end = 0x00a01070 }, 437 { .start = 0x00a0108c, .end = 0x00a0108c }, 438 { .start = 0x00a01c20, .end = 0x00a01c28 }, 439 { .start = 0x00a01d10, .end = 0x00a01d10 }, 440 { .start = 0x00a01e28, .end = 0x00a01e2c }, 441 { .start = 0x00a01e60, .end = 0x00a01e60 }, 442 { .start = 0x00a01e80, .end = 0x00a01e80 }, 443 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 444 { .start = 0x00a02000, .end = 0x00a0201c }, 445 { .start = 0x00a02024, .end = 0x00a02024 }, 446 { .start = 0x00a02040, .end = 0x00a02048 }, 447 { .start = 0x00a020c0, .end = 0x00a020e0 }, 448 { .start = 0x00a02400, .end = 0x00a02404 }, 449 { .start = 0x00a0240c, .end = 0x00a02414 }, 450 { .start = 0x00a0241c, .end = 0x00a0243c }, 451 { .start = 0x00a02448, .end = 0x00a024bc }, 452 { .start = 0x00a024c4, .end = 0x00a024cc }, 453 { .start = 0x00a02508, .end = 0x00a02508 }, 454 { .start = 0x00a02510, .end = 0x00a02514 }, 455 { .start = 0x00a0251c, .end = 0x00a0251c }, 456 { .start = 0x00a0252c, .end = 0x00a0255c }, 457 { .start = 0x00a02564, .end = 0x00a025a0 }, 458 { .start = 0x00a025a8, .end = 0x00a025b4 }, 459 { .start = 0x00a025c0, .end = 0x00a025c0 }, 460 { .start = 0x00a025e8, .end = 0x00a025f4 }, 461 { .start = 0x00a02c08, .end = 0x00a02c18 }, 462 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 463 { .start = 0x00a02c68, .end = 0x00a02c78 }, 464 { .start = 0x00a03000, .end = 0x00a03000 }, 465 { .start = 0x00a03010, .end = 0x00a03014 }, 466 { .start = 0x00a0301c, .end = 0x00a0302c }, 467 { .start = 0x00a03034, .end = 0x00a03038 }, 468 { .start = 0x00a03040, .end = 0x00a03044 }, 469 { .start = 0x00a03060, .end = 0x00a03068 }, 470 { .start = 0x00a03070, .end = 0x00a03070 }, 471 { .start = 0x00a0307c, .end = 0x00a03084 }, 472 { .start = 0x00a0308c, .end = 0x00a03090 }, 473 { .start = 0x00a03098, .end = 0x00a03098 }, 474 { .start = 0x00a030a0, .end = 0x00a030a0 }, 475 { .start = 0x00a030a8, .end = 0x00a030b4 }, 476 { .start = 0x00a030bc, .end = 0x00a030c0 }, 477 { .start = 0x00a030c8, .end = 0x00a030f4 }, 478 { .start = 0x00a03100, .end = 0x00a0312c }, 479 { .start = 0x00a03c00, .end = 0x00a03c5c }, 480 { .start = 0x00a04400, .end = 0x00a04454 }, 481 { .start = 0x00a04460, .end = 0x00a04474 }, 482 { .start = 0x00a044c0, .end = 0x00a044ec }, 483 { .start = 0x00a04500, .end = 0x00a04504 }, 484 { .start = 0x00a04510, .end = 0x00a04538 }, 485 { .start = 0x00a04540, .end = 0x00a04548 }, 486 { .start = 0x00a04560, .end = 0x00a04560 }, 487 { .start = 0x00a04570, .end = 0x00a0457c }, 488 { .start = 0x00a04590, .end = 0x00a04590 }, 489 { .start = 0x00a04598, .end = 0x00a04598 }, 490 { .start = 0x00a045c0, .end = 0x00a045f4 }, 491 { .start = 0x00a05c18, .end = 0x00a05c1c }, 492 { .start = 0x00a0c000, .end = 0x00a0c018 }, 493 { .start = 0x00a0c020, .end = 0x00a0c028 }, 494 { .start = 0x00a0c038, .end = 0x00a0c094 }, 495 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 496 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 497 { .start = 0x00a0c150, .end = 0x00a0c174 }, 498 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 499 { .start = 0x00a0c190, .end = 0x00a0c198 }, 500 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 501 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 502 }; 503 504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 505 { .start = 0x00d03c00, .end = 0x00d03c64 }, 506 { .start = 0x00d05c18, .end = 0x00d05c1c }, 507 { .start = 0x00d0c000, .end = 0x00d0c174 }, 508 }; 509 510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 511 u32 len_bytes, __le32 *data) 512 { 513 u32 i; 514 515 for (i = 0; i < len_bytes; i += 4) 516 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 517 } 518 519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 520 const struct iwl_prph_range *iwl_prph_dump_addr, 521 u32 range_len, void *ptr) 522 { 523 struct iwl_fw_error_dump_prph *prph; 524 struct iwl_trans *trans = fwrt->trans; 525 struct iwl_fw_error_dump_data **data = 526 (struct iwl_fw_error_dump_data **)ptr; 527 u32 i; 528 529 if (!data) 530 return; 531 532 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 533 534 if (!iwl_trans_grab_nic_access(trans)) 535 return; 536 537 for (i = 0; i < range_len; i++) { 538 /* The range includes both boundaries */ 539 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 540 iwl_prph_dump_addr[i].start + 4; 541 542 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 543 (*data)->len = cpu_to_le32(sizeof(*prph) + 544 num_bytes_in_chunk); 545 prph = (void *)(*data)->data; 546 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 547 548 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 549 /* our range is inclusive, hence + 4 */ 550 iwl_prph_dump_addr[i].end - 551 iwl_prph_dump_addr[i].start + 4, 552 (void *)prph->data); 553 554 *data = iwl_fw_error_next_data(*data); 555 } 556 557 iwl_trans_release_nic_access(trans); 558 } 559 560 /* 561 * alloc_sgtable - allocates scallerlist table in the given size, 562 * fills it with pages and returns it 563 * @size: the size (in bytes) of the table 564 */ 565 static struct scatterlist *alloc_sgtable(int size) 566 { 567 int alloc_size, nents, i; 568 struct page *new_page; 569 struct scatterlist *iter; 570 struct scatterlist *table; 571 572 nents = DIV_ROUND_UP(size, PAGE_SIZE); 573 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 574 if (!table) 575 return NULL; 576 sg_init_table(table, nents); 577 iter = table; 578 for_each_sg(table, iter, sg_nents(table), i) { 579 new_page = alloc_page(GFP_KERNEL); 580 if (!new_page) { 581 /* release all previous allocated pages in the table */ 582 iter = table; 583 for_each_sg(table, iter, sg_nents(table), i) { 584 new_page = sg_page(iter); 585 if (new_page) 586 __free_page(new_page); 587 } 588 kfree(table); 589 return NULL; 590 } 591 alloc_size = min_t(int, size, PAGE_SIZE); 592 size -= PAGE_SIZE; 593 sg_set_page(iter, new_page, alloc_size, 0); 594 } 595 return table; 596 } 597 598 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 599 const struct iwl_prph_range *iwl_prph_dump_addr, 600 u32 range_len, void *ptr) 601 { 602 u32 *prph_len = (u32 *)ptr; 603 int i, num_bytes_in_chunk; 604 605 if (!prph_len) 606 return; 607 608 for (i = 0; i < range_len; i++) { 609 /* The range includes both boundaries */ 610 num_bytes_in_chunk = 611 iwl_prph_dump_addr[i].end - 612 iwl_prph_dump_addr[i].start + 4; 613 614 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 615 sizeof(struct iwl_fw_error_dump_prph) + 616 num_bytes_in_chunk; 617 } 618 } 619 620 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 621 void (*handler)(struct iwl_fw_runtime *, 622 const struct iwl_prph_range *, 623 u32, void *)) 624 { 625 u32 range_len; 626 627 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 628 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 629 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 630 } else if (fwrt->trans->trans_cfg->device_family >= 631 IWL_DEVICE_FAMILY_22000) { 632 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 633 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 634 } else { 635 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 636 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 637 638 if (fwrt->trans->trans_cfg->mq_rx_supported) { 639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 640 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 641 } 642 } 643 } 644 645 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 646 struct iwl_fw_error_dump_data **dump_data, 647 u32 len, u32 ofs, u32 type) 648 { 649 struct iwl_fw_error_dump_mem *dump_mem; 650 651 if (!len) 652 return; 653 654 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 655 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 656 dump_mem = (void *)(*dump_data)->data; 657 dump_mem->type = cpu_to_le32(type); 658 dump_mem->offset = cpu_to_le32(ofs); 659 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 660 *dump_data = iwl_fw_error_next_data(*dump_data); 661 662 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 663 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 664 dump_mem->data, len); 665 666 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 667 } 668 669 #define ADD_LEN(len, item_len, const_len) \ 670 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 671 while (0) 672 673 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 674 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 675 { 676 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 677 sizeof(struct iwl_fw_error_dump_fifo); 678 u32 fifo_len = 0; 679 int i; 680 681 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 682 return 0; 683 684 /* Count RXF2 size */ 685 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 686 687 /* Count RXF1 sizes */ 688 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 689 mem_cfg->num_lmacs = MAX_NUM_LMAC; 690 691 for (i = 0; i < mem_cfg->num_lmacs; i++) 692 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 693 694 return fifo_len; 695 } 696 697 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 698 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 699 { 700 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 701 sizeof(struct iwl_fw_error_dump_fifo); 702 u32 fifo_len = 0; 703 int i; 704 705 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 706 goto dump_internal_txf; 707 708 /* Count TXF sizes */ 709 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 710 mem_cfg->num_lmacs = MAX_NUM_LMAC; 711 712 for (i = 0; i < mem_cfg->num_lmacs; i++) { 713 int j; 714 715 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 716 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 717 hdr_len); 718 } 719 720 dump_internal_txf: 721 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 722 fw_has_capa(&fwrt->fw->ucode_capa, 723 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 724 goto out; 725 726 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 727 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 728 729 out: 730 return fifo_len; 731 } 732 733 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 734 struct iwl_fw_error_dump_data **data) 735 { 736 int i; 737 738 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 739 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 740 struct iwl_fw_error_dump_paging *paging; 741 struct page *pages = 742 fwrt->fw_paging_db[i].fw_paging_block; 743 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 744 745 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 746 (*data)->len = cpu_to_le32(sizeof(*paging) + 747 PAGING_BLOCK_SIZE); 748 paging = (void *)(*data)->data; 749 paging->index = cpu_to_le32(i); 750 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 751 PAGING_BLOCK_SIZE, 752 DMA_BIDIRECTIONAL); 753 memcpy(paging->data, page_address(pages), 754 PAGING_BLOCK_SIZE); 755 dma_sync_single_for_device(fwrt->trans->dev, addr, 756 PAGING_BLOCK_SIZE, 757 DMA_BIDIRECTIONAL); 758 (*data) = iwl_fw_error_next_data(*data); 759 760 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 761 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 762 fwrt->fw_paging_db[i].fw_offs, 763 paging->data, 764 PAGING_BLOCK_SIZE); 765 } 766 } 767 768 static struct iwl_fw_error_dump_file * 769 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 770 struct iwl_fw_dump_ptrs *fw_error_dump, 771 struct iwl_fwrt_dump_data *data) 772 { 773 struct iwl_fw_error_dump_file *dump_file; 774 struct iwl_fw_error_dump_data *dump_data; 775 struct iwl_fw_error_dump_info *dump_info; 776 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 777 struct iwl_fw_error_dump_trigger_desc *dump_trig; 778 u32 sram_len, sram_ofs; 779 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 780 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 781 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 782 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 783 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 784 0 : fwrt->trans->cfg->dccm2_len; 785 int i; 786 787 /* SRAM - include stack CCM if driver knows the values for it */ 788 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 789 const struct fw_img *img; 790 791 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 792 return NULL; 793 img = &fwrt->fw->img[fwrt->cur_fw_img]; 794 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 795 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 796 } else { 797 sram_ofs = fwrt->trans->cfg->dccm_offset; 798 sram_len = fwrt->trans->cfg->dccm_len; 799 } 800 801 /* reading RXF/TXF sizes */ 802 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 803 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 804 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 805 806 /* Make room for PRPH registers */ 807 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 808 iwl_fw_prph_handler(fwrt, &prph_len, 809 iwl_fw_get_prph_len); 810 811 if (fwrt->trans->trans_cfg->device_family == 812 IWL_DEVICE_FAMILY_7000 && 813 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 814 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 815 } 816 817 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 818 819 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 820 file_len += sizeof(*dump_data) + sizeof(*dump_info); 821 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 822 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 823 824 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 825 size_t hdr_len = sizeof(*dump_data) + 826 sizeof(struct iwl_fw_error_dump_mem); 827 828 /* Dump SRAM only if no mem_tlvs */ 829 if (!fwrt->fw->dbg.n_mem_tlv) 830 ADD_LEN(file_len, sram_len, hdr_len); 831 832 /* Make room for all mem types that exist */ 833 ADD_LEN(file_len, smem_len, hdr_len); 834 ADD_LEN(file_len, sram2_len, hdr_len); 835 836 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 837 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 838 } 839 840 /* Make room for fw's virtual image pages, if it exists */ 841 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 842 file_len += fwrt->num_of_paging_blk * 843 (sizeof(*dump_data) + 844 sizeof(struct iwl_fw_error_dump_paging) + 845 PAGING_BLOCK_SIZE); 846 847 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 848 file_len += sizeof(*dump_data) + 849 fwrt->trans->cfg->d3_debug_data_length * 2; 850 } 851 852 /* If we only want a monitor dump, reset the file length */ 853 if (data->monitor_only) { 854 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 855 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 856 } 857 858 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 859 data->desc) 860 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 861 data->desc->len; 862 863 dump_file = vzalloc(file_len); 864 if (!dump_file) 865 return NULL; 866 867 fw_error_dump->fwrt_ptr = dump_file; 868 869 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 870 dump_data = (void *)dump_file->data; 871 872 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 873 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 874 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 875 dump_info = (void *)dump_data->data; 876 dump_info->hw_type = 877 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 878 dump_info->hw_step = 879 cpu_to_le32(fwrt->trans->hw_rev_step); 880 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 881 sizeof(dump_info->fw_human_readable)); 882 strscpy_pad(dump_info->dev_human_readable, fwrt->trans->name, 883 sizeof(dump_info->dev_human_readable)); 884 strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name, 885 sizeof(dump_info->bus_human_readable)); 886 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 887 dump_info->lmac_err_id[0] = 888 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 889 if (fwrt->smem_cfg.num_lmacs > 1) 890 dump_info->lmac_err_id[1] = 891 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 892 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 893 894 dump_data = iwl_fw_error_next_data(dump_data); 895 } 896 897 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 898 /* Dump shared memory configuration */ 899 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 900 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 901 dump_smem_cfg = (void *)dump_data->data; 902 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 903 dump_smem_cfg->num_txfifo_entries = 904 cpu_to_le32(mem_cfg->num_txfifo_entries); 905 for (i = 0; i < MAX_NUM_LMAC; i++) { 906 int j; 907 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 908 909 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 910 dump_smem_cfg->lmac[i].txfifo_size[j] = 911 cpu_to_le32(txf_size[j]); 912 dump_smem_cfg->lmac[i].rxfifo1_size = 913 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 914 } 915 dump_smem_cfg->rxfifo2_size = 916 cpu_to_le32(mem_cfg->rxfifo2_size); 917 dump_smem_cfg->internal_txfifo_addr = 918 cpu_to_le32(mem_cfg->internal_txfifo_addr); 919 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 920 dump_smem_cfg->internal_txfifo_size[i] = 921 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 922 } 923 924 dump_data = iwl_fw_error_next_data(dump_data); 925 } 926 927 /* We only dump the FIFOs if the FW is in error state */ 928 if (fifo_len) { 929 iwl_fw_dump_rxf(fwrt, &dump_data); 930 iwl_fw_dump_txf(fwrt, &dump_data); 931 } 932 933 if (radio_len) 934 iwl_read_radio_regs(fwrt, &dump_data); 935 936 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 937 data->desc) { 938 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 939 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 940 data->desc->len); 941 dump_trig = (void *)dump_data->data; 942 memcpy(dump_trig, &data->desc->trig_desc, 943 sizeof(*dump_trig) + data->desc->len); 944 945 dump_data = iwl_fw_error_next_data(dump_data); 946 } 947 948 /* In case we only want monitor dump, skip to dump trasport data */ 949 if (data->monitor_only) 950 goto out; 951 952 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 953 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 954 fwrt->fw->dbg.mem_tlv; 955 956 if (!fwrt->fw->dbg.n_mem_tlv) 957 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 958 IWL_FW_ERROR_DUMP_MEM_SRAM); 959 960 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 961 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 962 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 963 964 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 965 le32_to_cpu(fw_dbg_mem[i].data_type)); 966 } 967 968 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 969 fwrt->trans->cfg->smem_offset, 970 IWL_FW_ERROR_DUMP_MEM_SMEM); 971 972 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 973 fwrt->trans->cfg->dccm2_offset, 974 IWL_FW_ERROR_DUMP_MEM_SRAM); 975 } 976 977 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 978 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 979 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 980 981 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 982 dump_data->len = cpu_to_le32(data_size * 2); 983 984 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 985 986 kfree(fwrt->dump.d3_debug_data); 987 fwrt->dump.d3_debug_data = NULL; 988 989 iwl_trans_read_mem_bytes(fwrt->trans, addr, 990 dump_data->data + data_size, 991 data_size); 992 993 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 994 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 995 dump_data->data + data_size, 996 data_size); 997 998 dump_data = iwl_fw_error_next_data(dump_data); 999 } 1000 1001 /* Dump fw's virtual image */ 1002 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1003 iwl_dump_paging(fwrt, &dump_data); 1004 1005 if (prph_len) 1006 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1007 1008 out: 1009 dump_file->file_len = cpu_to_le32(file_len); 1010 return dump_file; 1011 } 1012 1013 /** 1014 * struct iwl_dump_ini_region_data - region data 1015 * @reg_tlv: region TLV 1016 * @dump_data: dump data 1017 */ 1018 struct iwl_dump_ini_region_data { 1019 struct iwl_ucode_tlv *reg_tlv; 1020 struct iwl_fwrt_dump_data *dump_data; 1021 }; 1022 1023 static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt, 1024 void *range_ptr, u32 addr, 1025 __le32 size) 1026 { 1027 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1028 __le32 *val = range->data; 1029 int i; 1030 1031 range->internal_base_addr = cpu_to_le32(addr); 1032 range->range_data_size = size; 1033 for (i = 0; i < le32_to_cpu(size); i += 4) 1034 *val++ = cpu_to_le32(iwl_read_prph(fwrt->trans, addr + i)); 1035 1036 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1037 } 1038 1039 static int 1040 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1041 struct iwl_dump_ini_region_data *reg_data, 1042 void *range_ptr, u32 range_len, int idx) 1043 { 1044 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1045 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1046 le32_to_cpu(reg->dev_addr.offset); 1047 1048 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1049 reg->dev_addr.size); 1050 } 1051 1052 static int 1053 iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime *fwrt, 1054 struct iwl_dump_ini_region_data *reg_data, 1055 void *range_ptr, u32 range_len, int idx) 1056 { 1057 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1058 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1059 u32 addr = le32_to_cpu(reg->dev_addr_range.offset) + 1060 le32_to_cpu(pairs[idx].addr); 1061 1062 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1063 pairs[idx].size); 1064 } 1065 1066 static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt, 1067 void *range_ptr, u32 addr, 1068 __le32 size, __le32 offset) 1069 { 1070 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1071 __le32 *val = range->data; 1072 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1073 u32 indirect_rd_addr = WMAL_MRSPF_1; 1074 u32 prph_val; 1075 u32 dphy_state; 1076 u32 dphy_addr; 1077 int i; 1078 1079 range->internal_base_addr = cpu_to_le32(addr); 1080 range->range_data_size = size; 1081 1082 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1083 indirect_wr_addr = WMAL_INDRCT_CMD1; 1084 1085 indirect_wr_addr += le32_to_cpu(offset); 1086 indirect_rd_addr += le32_to_cpu(offset); 1087 1088 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1089 return -EBUSY; 1090 1091 dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1092 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1093 1094 for (i = 0; i < le32_to_cpu(size); i += 4) { 1095 if (dphy_state == HBUS_TIMEOUT || 1096 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1097 WFPM_PHYRF_STATE_ON) { 1098 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1099 continue; 1100 } 1101 1102 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1103 WMAL_INDRCT_CMD(addr + i)); 1104 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1105 indirect_rd_addr); 1106 *val++ = cpu_to_le32(prph_val); 1107 } 1108 1109 iwl_trans_release_nic_access(fwrt->trans); 1110 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1111 } 1112 1113 static int 1114 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1115 struct iwl_dump_ini_region_data *reg_data, 1116 void *range_ptr, u32 range_len, int idx) 1117 { 1118 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1119 u32 addr = le32_to_cpu(reg->addrs[idx]); 1120 1121 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1122 reg->dev_addr.size, 1123 reg->dev_addr.offset); 1124 } 1125 1126 static int 1127 iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime *fwrt, 1128 struct iwl_dump_ini_region_data *reg_data, 1129 void *range_ptr, u32 range_len, int idx) 1130 { 1131 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1132 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1133 u32 addr = le32_to_cpu(pairs[idx].addr); 1134 1135 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1136 pairs[idx].size, 1137 reg->dev_addr_range.offset); 1138 } 1139 1140 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1141 struct iwl_dump_ini_region_data *reg_data, 1142 void *range_ptr, u32 range_len, int idx) 1143 { 1144 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1145 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1146 __le32 *val = range->data; 1147 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1148 le32_to_cpu(reg->dev_addr.offset); 1149 int i; 1150 1151 range->internal_base_addr = cpu_to_le32(addr); 1152 range->range_data_size = reg->dev_addr.size; 1153 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1154 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1155 1156 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1157 } 1158 1159 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1160 struct iwl_dump_ini_region_data *reg_data, 1161 void *range_ptr, u32 range_len, int idx) 1162 { 1163 struct iwl_trans *trans = fwrt->trans; 1164 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1165 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1166 __le32 *val = range->data; 1167 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1168 le32_to_cpu(reg->dev_addr.offset); 1169 int i; 1170 1171 range->internal_base_addr = cpu_to_le32(addr); 1172 range->range_data_size = reg->dev_addr.size; 1173 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1174 int ret; 1175 u32 tmp; 1176 1177 ret = iwl_trans_read_config32(trans, addr + i, &tmp); 1178 if (ret < 0) 1179 return ret; 1180 1181 *val++ = cpu_to_le32(tmp); 1182 } 1183 1184 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1185 } 1186 1187 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1188 struct iwl_dump_ini_region_data *reg_data, 1189 void *range_ptr, u32 range_len, int idx) 1190 { 1191 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1192 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1193 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1194 le32_to_cpu(reg->dev_addr.offset); 1195 1196 range->internal_base_addr = cpu_to_le32(addr); 1197 range->range_data_size = reg->dev_addr.size; 1198 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1199 le32_to_cpu(reg->dev_addr.size)); 1200 1201 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1202 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1203 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1204 range->data, 1205 le32_to_cpu(reg->dev_addr.size)); 1206 1207 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1208 } 1209 1210 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1211 void *range_ptr, u32 range_len, int idx) 1212 { 1213 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1214 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1215 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1216 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1217 1218 range->page_num = cpu_to_le32(idx); 1219 range->range_data_size = cpu_to_le32(page_size); 1220 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1221 DMA_BIDIRECTIONAL); 1222 memcpy(range->data, page_address(page), page_size); 1223 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1224 DMA_BIDIRECTIONAL); 1225 1226 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1227 } 1228 1229 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1230 struct iwl_dump_ini_region_data *reg_data, 1231 void *range_ptr, u32 range_len, int idx) 1232 { 1233 struct iwl_fw_ini_error_dump_range *range; 1234 u32 page_size; 1235 1236 /* all paged index start from 1 to skip CSS section */ 1237 idx++; 1238 1239 if (!fwrt->trans->trans_cfg->gen2) 1240 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1241 1242 range = range_ptr; 1243 page_size = fwrt->trans->init_dram.paging[idx].size; 1244 1245 range->page_num = cpu_to_le32(idx); 1246 range->range_data_size = cpu_to_le32(page_size); 1247 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1248 page_size); 1249 1250 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1251 } 1252 1253 static int 1254 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1255 struct iwl_dump_ini_region_data *reg_data, 1256 void *range_ptr, u32 range_len, int idx) 1257 { 1258 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1259 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1260 struct iwl_dram_data *frag; 1261 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1262 1263 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1264 1265 range->dram_base_addr = cpu_to_le64(frag->physical); 1266 range->range_data_size = cpu_to_le32(frag->size); 1267 1268 memcpy(range->data, frag->block, frag->size); 1269 1270 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1271 } 1272 1273 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1274 struct iwl_dump_ini_region_data *reg_data, 1275 void *range_ptr, u32 range_len, int idx) 1276 { 1277 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1278 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1279 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1280 1281 range->internal_base_addr = cpu_to_le32(addr); 1282 range->range_data_size = reg->internal_buffer.size; 1283 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1284 le32_to_cpu(reg->internal_buffer.size)); 1285 1286 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1287 } 1288 1289 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1290 struct iwl_dump_ini_region_data *reg_data, int idx) 1291 { 1292 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1293 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1294 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1295 int txf_num = cfg->num_txfifo_entries; 1296 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1297 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1298 1299 if (!idx) { 1300 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1301 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1302 le32_to_cpu(reg->fifos.offset)); 1303 return false; 1304 } 1305 1306 iter->internal_txf = 0; 1307 iter->fifo_size = 0; 1308 iter->fifo = -1; 1309 if (le32_to_cpu(reg->fifos.offset)) 1310 iter->lmac = 1; 1311 else 1312 iter->lmac = 0; 1313 } 1314 1315 if (!iter->internal_txf) { 1316 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1317 iter->fifo_size = 1318 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1319 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1320 return true; 1321 } 1322 iter->fifo--; 1323 } 1324 1325 iter->internal_txf = 1; 1326 1327 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1328 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1329 return false; 1330 1331 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1332 iter->fifo_size = 1333 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1334 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1335 return true; 1336 } 1337 1338 return false; 1339 } 1340 1341 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1342 struct iwl_dump_ini_region_data *reg_data, 1343 void *range_ptr, u32 range_len, int idx) 1344 { 1345 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1346 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1347 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1348 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1349 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1350 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1351 u32 registers_size = registers_num * sizeof(*reg_dump); 1352 __le32 *data; 1353 int i; 1354 1355 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1356 return -EIO; 1357 1358 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1359 return -EBUSY; 1360 1361 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1362 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1363 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1364 1365 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1366 1367 /* 1368 * read txf registers. for each register, write to the dump the 1369 * register address and its value 1370 */ 1371 for (i = 0; i < registers_num; i++) { 1372 addr = le32_to_cpu(reg->addrs[i]) + offs; 1373 1374 reg_dump->addr = cpu_to_le32(addr); 1375 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1376 addr)); 1377 1378 reg_dump++; 1379 } 1380 1381 if (reg->fifos.hdr_only) { 1382 range->range_data_size = cpu_to_le32(registers_size); 1383 goto out; 1384 } 1385 1386 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1387 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1388 TXF_WR_PTR + offs); 1389 1390 /* Dummy-read to advance the read pointer to the head */ 1391 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1392 1393 /* Read FIFO */ 1394 addr = TXF_READ_MODIFY_DATA + offs; 1395 data = (void *)reg_dump; 1396 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1397 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1398 1399 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1400 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1401 reg_dump, iter->fifo_size); 1402 1403 out: 1404 iwl_trans_release_nic_access(fwrt->trans); 1405 1406 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1407 } 1408 1409 static int 1410 iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt, 1411 struct iwl_dump_ini_region_data *reg_data, 1412 void *range_ptr, u32 range_len, int idx) 1413 { 1414 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1415 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1416 __le32 *val = range->data; 1417 __le32 offset = reg->dev_addr.offset; 1418 u32 indirect_rd_wr_addr = DPHYIP_INDIRECT; 1419 u32 addr = le32_to_cpu(reg->addrs[idx]); 1420 u32 dphy_state, dphy_addr, prph_val; 1421 int i; 1422 1423 range->internal_base_addr = cpu_to_le32(addr); 1424 range->range_data_size = reg->dev_addr.size; 1425 1426 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1427 return -EBUSY; 1428 1429 indirect_rd_wr_addr += le32_to_cpu(offset); 1430 1431 dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1432 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1433 1434 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1435 if (dphy_state == HBUS_TIMEOUT || 1436 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1437 WFPM_PHYRF_STATE_ON) { 1438 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1439 continue; 1440 } 1441 1442 iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr, 1443 addr + i); 1444 /* wait a bit for value to be ready in register */ 1445 udelay(1); 1446 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1447 indirect_rd_wr_addr); 1448 *val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >> 1449 DPHYIP_INDIRECT_RD_SHIFT); 1450 } 1451 1452 iwl_trans_release_nic_access(fwrt->trans); 1453 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1454 } 1455 1456 struct iwl_ini_rxf_data { 1457 u32 fifo_num; 1458 u32 size; 1459 u32 offset; 1460 }; 1461 1462 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1463 struct iwl_dump_ini_region_data *reg_data, 1464 struct iwl_ini_rxf_data *data) 1465 { 1466 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1467 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1468 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1469 u8 fifo_idx; 1470 1471 if (!data) 1472 return; 1473 1474 memset(data, 0, sizeof(*data)); 1475 1476 /* make sure only one bit is set in only one fid */ 1477 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1478 "fid1=%x, fid2=%x\n", fid1, fid2)) 1479 return; 1480 1481 if (fid1) { 1482 fifo_idx = ffs(fid1) - 1; 1483 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1484 fifo_idx)) 1485 return; 1486 1487 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1488 data->fifo_num = fifo_idx; 1489 } else { 1490 u8 max_idx; 1491 1492 fifo_idx = ffs(fid2) - 1; 1493 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1494 SHARED_MEM_CFG_CMD, 0) <= 3) 1495 max_idx = 0; 1496 else 1497 max_idx = 1; 1498 1499 if (WARN_ONCE(fifo_idx > max_idx, 1500 "invalid umac fifo idx %d", fifo_idx)) 1501 return; 1502 1503 /* use bit 31 to distinguish between umac and lmac rxf while 1504 * parsing the dump 1505 */ 1506 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1507 1508 switch (fifo_idx) { 1509 case 0: 1510 data->size = fwrt->smem_cfg.rxfifo2_size; 1511 data->offset = iwl_umac_prph(fwrt->trans, 1512 RXF_DIFF_FROM_PREV); 1513 break; 1514 case 1: 1515 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1516 data->offset = iwl_umac_prph(fwrt->trans, 1517 RXF2C_DIFF_FROM_PREV); 1518 break; 1519 } 1520 } 1521 } 1522 1523 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1524 struct iwl_dump_ini_region_data *reg_data, 1525 void *range_ptr, u32 range_len, int idx) 1526 { 1527 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1528 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1529 struct iwl_ini_rxf_data rxf_data; 1530 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1531 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1532 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1533 u32 registers_size = registers_num * sizeof(*reg_dump); 1534 __le32 *data; 1535 int i; 1536 1537 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1538 if (!rxf_data.size) 1539 return -EIO; 1540 1541 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1542 return -EBUSY; 1543 1544 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1545 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1546 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1547 1548 /* 1549 * read rxf registers. for each register, write to the dump the 1550 * register address and its value 1551 */ 1552 for (i = 0; i < registers_num; i++) { 1553 addr = le32_to_cpu(reg->addrs[i]) + offs; 1554 1555 reg_dump->addr = cpu_to_le32(addr); 1556 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1557 addr)); 1558 1559 reg_dump++; 1560 } 1561 1562 if (reg->fifos.hdr_only) { 1563 range->range_data_size = cpu_to_le32(registers_size); 1564 goto out; 1565 } 1566 1567 offs = rxf_data.offset; 1568 1569 /* Lock fence */ 1570 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1571 /* Set fence pointer to the same place like WR pointer */ 1572 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1573 /* Set fence offset */ 1574 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1575 0x0); 1576 1577 /* Read FIFO */ 1578 addr = RXF_FIFO_RD_FENCE_INC + offs; 1579 data = (void *)reg_dump; 1580 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1581 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1582 1583 out: 1584 iwl_trans_release_nic_access(fwrt->trans); 1585 1586 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1587 } 1588 1589 static int 1590 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1591 struct iwl_dump_ini_region_data *reg_data, 1592 void *range_ptr, u32 range_len, int idx) 1593 { 1594 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1595 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1596 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1597 u32 addr = le32_to_cpu(err_table->base_addr) + 1598 le32_to_cpu(err_table->offset); 1599 1600 range->internal_base_addr = cpu_to_le32(addr); 1601 range->range_data_size = err_table->size; 1602 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1603 le32_to_cpu(err_table->size)); 1604 1605 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1606 } 1607 1608 static int 1609 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1610 struct iwl_dump_ini_region_data *reg_data, 1611 void *range_ptr, u32 range_len, int idx) 1612 { 1613 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1614 struct iwl_fw_ini_region_special_device_memory *special_mem = 1615 ®->special_mem; 1616 1617 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1618 u32 addr = le32_to_cpu(special_mem->base_addr) + 1619 le32_to_cpu(special_mem->offset); 1620 1621 range->internal_base_addr = cpu_to_le32(addr); 1622 range->range_data_size = special_mem->size; 1623 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1624 le32_to_cpu(special_mem->size)); 1625 1626 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1627 } 1628 1629 static int 1630 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1631 struct iwl_dump_ini_region_data *reg_data, 1632 void *range_ptr, u32 range_len, int idx) 1633 { 1634 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1635 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1636 __le32 *val = range->data; 1637 u32 prph_data; 1638 int i; 1639 1640 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1641 return -EBUSY; 1642 1643 range->range_data_size = reg->dev_addr.size; 1644 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1645 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1646 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1647 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1648 if (iwl_trans_is_hw_error_value(prph_data)) { 1649 iwl_trans_release_nic_access(fwrt->trans); 1650 return -EBUSY; 1651 } 1652 *val++ = cpu_to_le32(prph_data); 1653 } 1654 iwl_trans_release_nic_access(fwrt->trans); 1655 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1656 } 1657 1658 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1659 struct iwl_dump_ini_region_data *reg_data, 1660 void *range_ptr, u32 range_len, int idx) 1661 { 1662 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1663 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1664 u32 pkt_len; 1665 1666 if (!pkt) 1667 return -EIO; 1668 1669 pkt_len = iwl_rx_packet_payload_len(pkt); 1670 1671 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1672 range->range_data_size = cpu_to_le32(pkt_len); 1673 1674 memcpy(range->data, pkt->data, pkt_len); 1675 1676 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1677 } 1678 1679 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1680 struct iwl_dump_ini_region_data *reg_data, 1681 void *range_ptr, u32 range_len, int idx) 1682 { 1683 /* read the IMR memory and DMA it to SRAM */ 1684 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1685 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1686 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1687 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1688 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1689 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1690 1691 range->range_data_size = cpu_to_le32(size_to_dump); 1692 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1693 imr_curr_addr, size_to_dump)) { 1694 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1695 return -1; 1696 } 1697 1698 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1699 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1700 1701 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1702 size_to_dump); 1703 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1704 } 1705 1706 static void * 1707 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1708 struct iwl_dump_ini_region_data *reg_data, 1709 void *data, u32 data_len) 1710 { 1711 struct iwl_fw_ini_error_dump *dump = data; 1712 1713 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1714 1715 return dump->data; 1716 } 1717 1718 /** 1719 * mask_apply_and_normalize - applies mask on val and normalize the result 1720 * 1721 * @val: value 1722 * @mask: mask to apply and to normalize with 1723 * 1724 * The normalization is based on the first set bit in the mask 1725 * 1726 * Returns: the extracted value 1727 */ 1728 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1729 { 1730 return (val & mask) >> (ffs(mask) - 1); 1731 } 1732 1733 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1734 const struct iwl_fw_mon_reg *reg_info) 1735 { 1736 u32 val, offs; 1737 1738 /* The header addresses of DBGCi is calculate as follows: 1739 * DBGC1 address + (0x100 * i) 1740 */ 1741 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1742 1743 if (!reg_info || !reg_info->addr || !reg_info->mask) 1744 return 0; 1745 1746 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1747 1748 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1749 } 1750 1751 static void * 1752 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1753 struct iwl_fw_ini_monitor_dump *data, 1754 const struct iwl_fw_mon_regs *addrs) 1755 { 1756 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1757 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1758 return NULL; 1759 } 1760 1761 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1762 &addrs->write_ptr); 1763 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1764 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1765 1766 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1767 } 1768 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1769 &addrs->cycle_cnt); 1770 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1771 &addrs->cur_frag); 1772 1773 iwl_trans_release_nic_access(fwrt->trans); 1774 1775 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1776 1777 return data->data; 1778 } 1779 1780 static void * 1781 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1782 struct iwl_dump_ini_region_data *reg_data, 1783 void *data, u32 data_len) 1784 { 1785 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1786 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1787 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1788 1789 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1790 &fwrt->trans->cfg->mon_dram_regs); 1791 } 1792 1793 static void * 1794 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1795 struct iwl_dump_ini_region_data *reg_data, 1796 void *data, u32 data_len) 1797 { 1798 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1799 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1800 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1801 1802 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1803 &fwrt->trans->cfg->mon_smem_regs); 1804 } 1805 1806 static void * 1807 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1808 struct iwl_dump_ini_region_data *reg_data, 1809 void *data, u32 data_len) 1810 { 1811 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1812 1813 return iwl_dump_ini_mon_fill_header(fwrt, 1814 /* no offset calculation later */ 1815 IWL_FW_INI_ALLOCATION_ID_DBGC1, 1816 mon_dump, 1817 &fwrt->trans->cfg->mon_dbgi_regs); 1818 } 1819 1820 static void * 1821 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1822 struct iwl_dump_ini_region_data *reg_data, 1823 void *data, u32 data_len) 1824 { 1825 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1826 struct iwl_fw_ini_err_table_dump *dump = data; 1827 1828 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1829 dump->version = reg->err_table.version; 1830 1831 return dump->data; 1832 } 1833 1834 static void * 1835 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1836 struct iwl_dump_ini_region_data *reg_data, 1837 void *data, u32 data_len) 1838 { 1839 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1840 struct iwl_fw_ini_special_device_memory *dump = data; 1841 1842 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1843 dump->type = reg->special_mem.type; 1844 dump->version = reg->special_mem.version; 1845 1846 return dump->data; 1847 } 1848 1849 static void * 1850 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1851 struct iwl_dump_ini_region_data *reg_data, 1852 void *data, u32 data_len) 1853 { 1854 struct iwl_fw_ini_error_dump *dump = data; 1855 1856 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1857 1858 return dump->data; 1859 } 1860 1861 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1862 struct iwl_dump_ini_region_data *reg_data) 1863 { 1864 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1865 1866 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1867 } 1868 1869 static u32 1870 iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime *fwrt, 1871 struct iwl_dump_ini_region_data *reg_data) 1872 { 1873 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1874 size_t size = sizeof(struct iwl_fw_ini_addr_size); 1875 1876 return iwl_tlv_array_len_with_size(reg_data->reg_tlv, reg, size); 1877 } 1878 1879 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1880 struct iwl_dump_ini_region_data *reg_data) 1881 { 1882 if (fwrt->trans->trans_cfg->gen2) { 1883 if (fwrt->trans->init_dram.paging_cnt) 1884 return fwrt->trans->init_dram.paging_cnt - 1; 1885 else 1886 return 0; 1887 } 1888 1889 return fwrt->num_of_paging_blk; 1890 } 1891 1892 static u32 1893 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1894 struct iwl_dump_ini_region_data *reg_data) 1895 { 1896 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1897 struct iwl_fw_mon *fw_mon; 1898 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1899 int i; 1900 1901 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1902 1903 for (i = 0; i < fw_mon->num_frags; i++) { 1904 if (!fw_mon->frags[i].size) 1905 break; 1906 1907 ranges++; 1908 } 1909 1910 return ranges; 1911 } 1912 1913 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1914 struct iwl_dump_ini_region_data *reg_data) 1915 { 1916 u32 num_of_fifos = 0; 1917 1918 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1919 num_of_fifos++; 1920 1921 return num_of_fifos; 1922 } 1923 1924 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1925 struct iwl_dump_ini_region_data *reg_data) 1926 { 1927 return 1; 1928 } 1929 1930 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1931 struct iwl_dump_ini_region_data *reg_data) 1932 { 1933 /* range is total number of pages need to copied from 1934 *IMR memory to SRAM and later from SRAM to DRAM 1935 */ 1936 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1937 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1938 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1939 1940 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1941 IWL_DEBUG_INFO(fwrt, 1942 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1943 imr_enable, imr_size, sram_size); 1944 return 0; 1945 } 1946 1947 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1948 } 1949 1950 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1951 struct iwl_dump_ini_region_data *reg_data) 1952 { 1953 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1954 u32 size = le32_to_cpu(reg->dev_addr.size); 1955 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1956 1957 if (!size || !ranges) 1958 return 0; 1959 1960 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1961 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1962 } 1963 1964 static u32 1965 iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime *fwrt, 1966 struct iwl_dump_ini_region_data *reg_data) 1967 { 1968 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1969 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1970 u32 ranges = iwl_dump_ini_mem_block_ranges(fwrt, reg_data); 1971 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1972 int range; 1973 1974 if (!ranges) 1975 return 0; 1976 1977 for (range = 0; range < ranges; range++) 1978 size += le32_to_cpu(pairs[range].size); 1979 1980 return size + ranges * sizeof(struct iwl_fw_ini_error_dump_range); 1981 } 1982 1983 static u32 1984 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1985 struct iwl_dump_ini_region_data *reg_data) 1986 { 1987 int i; 1988 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1989 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1990 1991 /* start from 1 to skip CSS section */ 1992 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 1993 size += range_header_len; 1994 if (fwrt->trans->trans_cfg->gen2) 1995 size += fwrt->trans->init_dram.paging[i].size; 1996 else 1997 size += fwrt->fw_paging_db[i].fw_paging_size; 1998 } 1999 2000 return size; 2001 } 2002 2003 static u32 2004 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 2005 struct iwl_dump_ini_region_data *reg_data) 2006 { 2007 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2008 struct iwl_fw_mon *fw_mon; 2009 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 2010 int i; 2011 2012 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 2013 2014 for (i = 0; i < fw_mon->num_frags; i++) { 2015 struct iwl_dram_data *frag = &fw_mon->frags[i]; 2016 2017 if (!frag->size) 2018 break; 2019 2020 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 2021 } 2022 2023 if (size) 2024 size += sizeof(struct iwl_fw_ini_monitor_dump); 2025 2026 return size; 2027 } 2028 2029 static u32 2030 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 2031 struct iwl_dump_ini_region_data *reg_data) 2032 { 2033 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2034 u32 size; 2035 2036 size = le32_to_cpu(reg->internal_buffer.size); 2037 if (!size) 2038 return 0; 2039 2040 size += sizeof(struct iwl_fw_ini_monitor_dump) + 2041 sizeof(struct iwl_fw_ini_error_dump_range); 2042 2043 return size; 2044 } 2045 2046 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 2047 struct iwl_dump_ini_region_data *reg_data) 2048 { 2049 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2050 u32 size = le32_to_cpu(reg->dev_addr.size); 2051 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 2052 2053 if (!size || !ranges) 2054 return 0; 2055 2056 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 2057 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 2058 } 2059 2060 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 2061 struct iwl_dump_ini_region_data *reg_data) 2062 { 2063 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2064 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 2065 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2066 u32 size = 0; 2067 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 2068 registers_num * 2069 sizeof(struct iwl_fw_ini_error_dump_register); 2070 2071 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 2072 size += fifo_hdr; 2073 if (!reg->fifos.hdr_only) 2074 size += iter->fifo_size; 2075 } 2076 2077 if (!size) 2078 return 0; 2079 2080 return size + sizeof(struct iwl_fw_ini_error_dump); 2081 } 2082 2083 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 2084 struct iwl_dump_ini_region_data *reg_data) 2085 { 2086 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2087 struct iwl_ini_rxf_data rx_data; 2088 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2089 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 2090 sizeof(struct iwl_fw_ini_error_dump_range) + 2091 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 2092 2093 if (reg->fifos.hdr_only) 2094 return size; 2095 2096 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 2097 size += rx_data.size; 2098 2099 return size; 2100 } 2101 2102 static u32 2103 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 2104 struct iwl_dump_ini_region_data *reg_data) 2105 { 2106 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2107 u32 size = le32_to_cpu(reg->err_table.size); 2108 2109 if (size) 2110 size += sizeof(struct iwl_fw_ini_err_table_dump) + 2111 sizeof(struct iwl_fw_ini_error_dump_range); 2112 2113 return size; 2114 } 2115 2116 static u32 2117 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2118 struct iwl_dump_ini_region_data *reg_data) 2119 { 2120 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2121 u32 size = le32_to_cpu(reg->special_mem.size); 2122 2123 if (size) 2124 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2125 sizeof(struct iwl_fw_ini_error_dump_range); 2126 2127 return size; 2128 } 2129 2130 static u32 2131 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2132 struct iwl_dump_ini_region_data *reg_data) 2133 { 2134 u32 size = 0; 2135 2136 if (!reg_data->dump_data->fw_pkt) 2137 return 0; 2138 2139 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2140 if (size) 2141 size += sizeof(struct iwl_fw_ini_error_dump) + 2142 sizeof(struct iwl_fw_ini_error_dump_range); 2143 2144 return size; 2145 } 2146 2147 static u32 2148 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2149 struct iwl_dump_ini_region_data *reg_data) 2150 { 2151 u32 ranges = 0; 2152 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2153 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2154 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2155 2156 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2157 IWL_DEBUG_INFO(fwrt, 2158 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2159 imr_enable, imr_size, sram_size); 2160 return 0; 2161 } 2162 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2163 if (!ranges) { 2164 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges); 2165 return 0; 2166 } 2167 imr_size += sizeof(struct iwl_fw_ini_error_dump) + 2168 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2169 return imr_size; 2170 } 2171 2172 /** 2173 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2174 * @get_num_of_ranges: returns the number of memory ranges in the region. 2175 * @get_size: returns the total size of the region. 2176 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2177 * the first range or NULL if failed to fill headers. 2178 * @fill_range: copies a given memory range into the dump. 2179 * Returns the size of the range or negative error value otherwise. 2180 */ 2181 struct iwl_dump_ini_mem_ops { 2182 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2183 struct iwl_dump_ini_region_data *reg_data); 2184 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2185 struct iwl_dump_ini_region_data *reg_data); 2186 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2187 struct iwl_dump_ini_region_data *reg_data, 2188 void *data, u32 data_len); 2189 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2190 struct iwl_dump_ini_region_data *reg_data, 2191 void *range, u32 range_len, int idx); 2192 }; 2193 2194 /** 2195 * iwl_dump_ini_mem - dump memory region 2196 * 2197 * @fwrt: fw runtime struct 2198 * @list: list to add the dump tlv to 2199 * @reg_data: memory region 2200 * @ops: memory dump operations 2201 * 2202 * Creates a dump tlv and copy a memory region into it. 2203 * 2204 * Returns: the size of the current dump tlv or 0 if failed 2205 */ 2206 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2207 struct iwl_dump_ini_region_data *reg_data, 2208 const struct iwl_dump_ini_mem_ops *ops) 2209 { 2210 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2211 struct iwl_fw_ini_dump_entry *entry; 2212 struct iwl_fw_ini_error_dump_data *tlv; 2213 struct iwl_fw_ini_error_dump_header *header; 2214 u32 type = reg->type; 2215 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK); 2216 u32 num_of_ranges, i, size; 2217 u8 *range; 2218 u32 free_size; 2219 u64 header_size; 2220 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE; 2221 2222 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n", 2223 dump_policy, id, type); 2224 2225 if (le32_to_cpu(reg->hdr.version) >= 2) { 2226 u32 dp = le32_get_bits(reg->id, 2227 IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2228 2229 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE && 2230 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) { 2231 IWL_DEBUG_FW(fwrt, 2232 "WRT: no dump - type %d and policy mismatch=%d\n", 2233 dump_policy, dp); 2234 return 0; 2235 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM && 2236 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) { 2237 IWL_DEBUG_FW(fwrt, 2238 "WRT: no dump - type %d and policy mismatch=%d\n", 2239 dump_policy, dp); 2240 return 0; 2241 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF && 2242 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) { 2243 IWL_DEBUG_FW(fwrt, 2244 "WRT: no dump - type %d and policy mismatch=%d\n", 2245 dump_policy, dp); 2246 return 0; 2247 } 2248 } 2249 2250 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2251 !ops->fill_range) { 2252 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2253 return 0; 2254 } 2255 2256 size = ops->get_size(fwrt, reg_data); 2257 2258 if (size < sizeof(*header)) { 2259 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2260 return 0; 2261 } 2262 2263 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2264 if (!entry) 2265 return 0; 2266 2267 entry->size = sizeof(*tlv) + size; 2268 2269 tlv = (void *)entry->data; 2270 tlv->type = reg->type; 2271 tlv->sub_type = reg->sub_type; 2272 tlv->sub_type_ver = reg->sub_type_ver; 2273 tlv->reserved = reg->reserved; 2274 tlv->len = cpu_to_le32(size); 2275 2276 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2277 2278 header = (void *)tlv->data; 2279 header->region_id = cpu_to_le32(id); 2280 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2281 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2282 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2283 2284 free_size = size; 2285 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2286 if (!range) { 2287 IWL_ERR(fwrt, 2288 "WRT: Failed to fill region header: id=%d, type=%d\n", 2289 id, type); 2290 goto out_err; 2291 } 2292 2293 header_size = range - (u8 *)header; 2294 2295 if (WARN(header_size > free_size, 2296 "header size %llu > free_size %d", 2297 header_size, free_size)) { 2298 IWL_ERR(fwrt, 2299 "WRT: fill_mem_hdr used more than given free_size\n"); 2300 goto out_err; 2301 } 2302 2303 free_size -= header_size; 2304 2305 for (i = 0; i < num_of_ranges; i++) { 2306 int range_size = ops->fill_range(fwrt, reg_data, range, 2307 free_size, i); 2308 2309 if (range_size < 0) { 2310 IWL_ERR(fwrt, 2311 "WRT: Failed to dump region: id=%d, type=%d\n", 2312 id, type); 2313 goto out_err; 2314 } 2315 2316 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2317 range_size, free_size)) { 2318 IWL_ERR(fwrt, 2319 "WRT: fill_raged used more than given free_size\n"); 2320 goto out_err; 2321 } 2322 2323 free_size -= range_size; 2324 range = range + range_size; 2325 } 2326 2327 list_add_tail(&entry->list, list); 2328 2329 return entry->size; 2330 2331 out_err: 2332 vfree(entry); 2333 2334 return 0; 2335 } 2336 2337 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2338 struct iwl_fw_ini_trigger_tlv *trigger, 2339 struct list_head *list) 2340 { 2341 struct iwl_fw_ini_dump_entry *entry; 2342 struct iwl_fw_error_dump_data *tlv; 2343 struct iwl_fw_ini_dump_info *dump; 2344 struct iwl_dbg_tlv_node *node; 2345 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2346 u32 size = sizeof(*tlv) + sizeof(*dump); 2347 u32 num_of_cfg_names = 0; 2348 u32 hw_type; 2349 2350 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2351 size += sizeof(*cfg_name); 2352 num_of_cfg_names++; 2353 } 2354 2355 entry = vzalloc(sizeof(*entry) + size); 2356 if (!entry) 2357 return 0; 2358 2359 entry->size = size; 2360 2361 tlv = (void *)entry->data; 2362 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2363 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2364 2365 dump = (void *)tlv->data; 2366 2367 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2368 dump->time_point = trigger->time_point; 2369 dump->trigger_reason = trigger->trigger_reason; 2370 dump->external_cfg_state = 2371 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2372 2373 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2374 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2375 2376 dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step); 2377 2378 /* 2379 * Several HWs all have type == 0x42, so we'll override this value 2380 * according to the detected HW 2381 */ 2382 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2383 if (hw_type == IWL_AX210_HW_TYPE) { 2384 u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR); 2385 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2386 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2387 u32 masked_bits = is_jacket | (is_cdb << 1); 2388 2389 /* 2390 * The HW type depends on certain bits in this case, so add 2391 * these bits to the HW type. We won't have collisions since we 2392 * add these bits after the highest possible bit in the mask. 2393 */ 2394 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2395 } 2396 dump->hw_type = cpu_to_le32(hw_type); 2397 2398 dump->rf_id_flavor = 2399 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2400 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2401 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2402 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2403 2404 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2405 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2406 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2407 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2408 2409 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2410 dump->regions_mask = trigger->regions_mask & 2411 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2412 2413 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2414 memcpy(dump->build_tag, fwrt->fw->human_readable, 2415 sizeof(dump->build_tag)); 2416 2417 cfg_name = dump->cfg_names; 2418 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2419 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2420 struct iwl_fw_ini_debug_info_tlv *debug_info = 2421 (void *)node->tlv.data; 2422 2423 BUILD_BUG_ON(sizeof(cfg_name->cfg_name) != 2424 sizeof(debug_info->debug_cfg_name)); 2425 2426 cfg_name->image_type = debug_info->image_type; 2427 cfg_name->cfg_name_len = 2428 cpu_to_le32(sizeof(cfg_name->cfg_name)); 2429 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2430 sizeof(cfg_name->cfg_name)); 2431 cfg_name++; 2432 } 2433 2434 /* add dump info TLV to the beginning of the list since it needs to be 2435 * the first TLV in the dump 2436 */ 2437 list_add(&entry->list, list); 2438 2439 return entry->size; 2440 } 2441 2442 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt, 2443 struct list_head *list) 2444 { 2445 struct iwl_fw_ini_dump_entry *entry; 2446 struct iwl_dump_file_name_info *tlv; 2447 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext, 2448 IWL_FW_INI_MAX_NAME); 2449 2450 if (!fwrt->trans->dbg.dump_file_name_ext_valid) 2451 return 0; 2452 2453 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len); 2454 if (!entry) 2455 return 0; 2456 2457 entry->size = sizeof(*tlv) + len; 2458 2459 tlv = (void *)entry->data; 2460 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE); 2461 tlv->len = cpu_to_le32(len); 2462 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len); 2463 2464 /* add the dump file name extension tlv to the list */ 2465 list_add_tail(&entry->list, list); 2466 2467 fwrt->trans->dbg.dump_file_name_ext_valid = false; 2468 2469 return entry->size; 2470 } 2471 2472 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2473 [IWL_FW_INI_REGION_INVALID] = {}, 2474 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2475 .get_num_of_ranges = iwl_dump_ini_single_range, 2476 .get_size = iwl_dump_ini_mon_smem_get_size, 2477 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2478 .fill_range = iwl_dump_ini_mon_smem_iter, 2479 }, 2480 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2481 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2482 .get_size = iwl_dump_ini_mon_dram_get_size, 2483 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2484 .fill_range = iwl_dump_ini_mon_dram_iter, 2485 }, 2486 [IWL_FW_INI_REGION_TXF] = { 2487 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2488 .get_size = iwl_dump_ini_txf_get_size, 2489 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2490 .fill_range = iwl_dump_ini_txf_iter, 2491 }, 2492 [IWL_FW_INI_REGION_RXF] = { 2493 .get_num_of_ranges = iwl_dump_ini_single_range, 2494 .get_size = iwl_dump_ini_rxf_get_size, 2495 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2496 .fill_range = iwl_dump_ini_rxf_iter, 2497 }, 2498 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2499 .get_num_of_ranges = iwl_dump_ini_single_range, 2500 .get_size = iwl_dump_ini_err_table_get_size, 2501 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2502 .fill_range = iwl_dump_ini_err_table_iter, 2503 }, 2504 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2505 .get_num_of_ranges = iwl_dump_ini_single_range, 2506 .get_size = iwl_dump_ini_err_table_get_size, 2507 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2508 .fill_range = iwl_dump_ini_err_table_iter, 2509 }, 2510 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2511 .get_num_of_ranges = iwl_dump_ini_single_range, 2512 .get_size = iwl_dump_ini_fw_pkt_get_size, 2513 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2514 .fill_range = iwl_dump_ini_fw_pkt_iter, 2515 }, 2516 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2517 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2518 .get_size = iwl_dump_ini_mem_get_size, 2519 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2520 .fill_range = iwl_dump_ini_dev_mem_iter, 2521 }, 2522 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2523 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2524 .get_size = iwl_dump_ini_mem_get_size, 2525 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2526 .fill_range = iwl_dump_ini_prph_mac_iter, 2527 }, 2528 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2529 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2530 .get_size = iwl_dump_ini_mem_get_size, 2531 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2532 .fill_range = iwl_dump_ini_prph_phy_iter, 2533 }, 2534 [IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE] = { 2535 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2536 .get_size = iwl_dump_ini_mem_block_get_size, 2537 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2538 .fill_range = iwl_dump_ini_prph_mac_block_iter, 2539 }, 2540 [IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE] = { 2541 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2542 .get_size = iwl_dump_ini_mem_block_get_size, 2543 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2544 .fill_range = iwl_dump_ini_prph_phy_block_iter, 2545 }, 2546 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2547 [IWL_FW_INI_REGION_PAGING] = { 2548 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2549 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2550 .get_size = iwl_dump_ini_paging_get_size, 2551 .fill_range = iwl_dump_ini_paging_iter, 2552 }, 2553 [IWL_FW_INI_REGION_CSR] = { 2554 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2555 .get_size = iwl_dump_ini_mem_get_size, 2556 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2557 .fill_range = iwl_dump_ini_csr_iter, 2558 }, 2559 [IWL_FW_INI_REGION_DRAM_IMR] = { 2560 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2561 .get_size = iwl_dump_ini_imr_get_size, 2562 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2563 .fill_range = iwl_dump_ini_imr_iter, 2564 }, 2565 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2566 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2567 .get_size = iwl_dump_ini_mem_get_size, 2568 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2569 .fill_range = iwl_dump_ini_config_iter, 2570 }, 2571 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2572 .get_num_of_ranges = iwl_dump_ini_single_range, 2573 .get_size = iwl_dump_ini_special_mem_get_size, 2574 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2575 .fill_range = iwl_dump_ini_special_mem_iter, 2576 }, 2577 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2578 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2579 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2580 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2581 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2582 }, 2583 [IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = { 2584 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2585 .get_size = iwl_dump_ini_mem_get_size, 2586 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2587 .fill_range = iwl_dump_ini_prph_snps_dphyip_iter, 2588 }, 2589 }; 2590 2591 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2592 struct iwl_fwrt_dump_data *dump_data, 2593 struct list_head *list) 2594 { 2595 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2596 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2597 struct iwl_dump_ini_region_data reg_data = { 2598 .dump_data = dump_data, 2599 }; 2600 struct iwl_dump_ini_region_data imr_reg_data = { 2601 .dump_data = dump_data, 2602 }; 2603 int i; 2604 u32 size = 0; 2605 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2606 ~(fwrt->trans->dbg.unsupported_region_msk); 2607 2608 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2609 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2610 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2611 2612 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2613 u32 reg_type; 2614 struct iwl_fw_ini_region_tlv *reg; 2615 2616 if (!(BIT_ULL(i) & regions_mask)) 2617 continue; 2618 2619 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2620 if (!reg_data.reg_tlv) { 2621 IWL_WARN(fwrt, 2622 "WRT: Unassigned region id %d, skipping\n", i); 2623 continue; 2624 } 2625 2626 reg = (void *)reg_data.reg_tlv->data; 2627 reg_type = reg->type; 2628 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2629 continue; 2630 2631 if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2632 reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE || 2633 reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) && 2634 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2635 IWL_WARN(fwrt, 2636 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2637 tp_id); 2638 continue; 2639 } 2640 /* 2641 * DRAM_IMR can be collected only for FW/HW error timepoint 2642 * when fw is not alive. In addition, it must be collected 2643 * lastly as it overwrites SRAM that can possibly contain 2644 * debug data which also need to be collected. 2645 */ 2646 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { 2647 if (tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT || 2648 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR) 2649 imr_reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2650 else 2651 IWL_INFO(fwrt, 2652 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n", 2653 tp_id); 2654 /* continue to next region */ 2655 continue; 2656 } 2657 2658 2659 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2660 &iwl_dump_ini_region_ops[reg_type]); 2661 } 2662 /* collect DRAM_IMR region in the last */ 2663 if (imr_reg_data.reg_tlv) 2664 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2665 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]); 2666 2667 if (size) { 2668 size += iwl_dump_ini_file_name_info(fwrt, list); 2669 size += iwl_dump_ini_info(fwrt, trigger, list); 2670 } 2671 2672 return size; 2673 } 2674 2675 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2676 struct iwl_fw_ini_trigger_tlv *trig) 2677 { 2678 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2679 u32 usec = le32_to_cpu(trig->ignore_consec); 2680 2681 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2682 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2683 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2684 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2685 return false; 2686 2687 return true; 2688 } 2689 2690 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2691 struct iwl_fwrt_dump_data *dump_data, 2692 struct list_head *list) 2693 { 2694 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2695 struct iwl_fw_ini_dump_entry *entry; 2696 struct iwl_fw_ini_dump_file_hdr *hdr; 2697 u32 size; 2698 2699 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2700 !le64_to_cpu(trigger->regions_mask)) 2701 return 0; 2702 2703 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2704 if (!entry) 2705 return 0; 2706 2707 entry->size = sizeof(*hdr); 2708 2709 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2710 if (!size) { 2711 vfree(entry); 2712 return 0; 2713 } 2714 2715 hdr = (void *)entry->data; 2716 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2717 hdr->file_len = cpu_to_le32(size + entry->size); 2718 2719 list_add(&entry->list, list); 2720 2721 return le32_to_cpu(hdr->file_len); 2722 } 2723 2724 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2725 const struct iwl_fw_dump_desc *desc) 2726 { 2727 if (desc && desc != &iwl_dump_desc_assert) 2728 kfree(desc); 2729 2730 fwrt->dump.lmac_err_id[0] = 0; 2731 if (fwrt->smem_cfg.num_lmacs > 1) 2732 fwrt->dump.lmac_err_id[1] = 0; 2733 fwrt->dump.umac_err_id = 0; 2734 } 2735 2736 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2737 struct iwl_fwrt_dump_data *dump_data) 2738 { 2739 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2740 struct iwl_fw_error_dump_file *dump_file; 2741 struct scatterlist *sg_dump_data; 2742 u32 file_len; 2743 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2744 2745 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2746 if (!dump_file) 2747 return; 2748 2749 if (dump_data->monitor_only) 2750 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2751 2752 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2753 fwrt->sanitize_ops, 2754 fwrt->sanitize_ctx); 2755 file_len = le32_to_cpu(dump_file->file_len); 2756 fw_error_dump.fwrt_len = file_len; 2757 2758 if (fw_error_dump.trans_ptr) { 2759 file_len += fw_error_dump.trans_ptr->len; 2760 dump_file->file_len = cpu_to_le32(file_len); 2761 } 2762 2763 sg_dump_data = alloc_sgtable(file_len); 2764 if (sg_dump_data) { 2765 sg_pcopy_from_buffer(sg_dump_data, 2766 sg_nents(sg_dump_data), 2767 fw_error_dump.fwrt_ptr, 2768 fw_error_dump.fwrt_len, 0); 2769 if (fw_error_dump.trans_ptr) 2770 sg_pcopy_from_buffer(sg_dump_data, 2771 sg_nents(sg_dump_data), 2772 fw_error_dump.trans_ptr->data, 2773 fw_error_dump.trans_ptr->len, 2774 fw_error_dump.fwrt_len); 2775 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2776 GFP_KERNEL); 2777 } 2778 vfree(fw_error_dump.fwrt_ptr); 2779 vfree(fw_error_dump.trans_ptr); 2780 } 2781 2782 static void iwl_dump_ini_list_free(struct list_head *list) 2783 { 2784 while (!list_empty(list)) { 2785 struct iwl_fw_ini_dump_entry *entry = 2786 list_entry(list->next, typeof(*entry), list); 2787 2788 list_del(&entry->list); 2789 vfree(entry); 2790 } 2791 } 2792 2793 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2794 { 2795 dump_data->trig = NULL; 2796 kfree(dump_data->fw_pkt); 2797 dump_data->fw_pkt = NULL; 2798 } 2799 2800 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2801 struct iwl_fwrt_dump_data *dump_data) 2802 { 2803 LIST_HEAD(dump_list); 2804 struct scatterlist *sg_dump_data; 2805 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2806 2807 if (!file_len) 2808 return; 2809 2810 sg_dump_data = alloc_sgtable(file_len); 2811 if (sg_dump_data) { 2812 struct iwl_fw_ini_dump_entry *entry; 2813 int sg_entries = sg_nents(sg_dump_data); 2814 u32 offs = 0; 2815 2816 list_for_each_entry(entry, &dump_list, list) { 2817 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2818 entry->data, entry->size, offs); 2819 offs += entry->size; 2820 } 2821 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2822 GFP_KERNEL); 2823 } 2824 iwl_dump_ini_list_free(&dump_list); 2825 } 2826 2827 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2828 .trig_desc = { 2829 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2830 }, 2831 }; 2832 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2833 2834 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2835 const struct iwl_fw_dump_desc *desc, 2836 bool monitor_only, 2837 unsigned int delay) 2838 { 2839 struct iwl_fwrt_wk_data *wk_data; 2840 unsigned long idx; 2841 2842 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2843 iwl_fw_free_dump_desc(fwrt, desc); 2844 return 0; 2845 } 2846 2847 /* 2848 * Check there is an available worker. 2849 * ffz return value is undefined if no zero exists, 2850 * so check against ~0UL first. 2851 */ 2852 if (fwrt->dump.active_wks == ~0UL) 2853 return -EBUSY; 2854 2855 idx = ffz(fwrt->dump.active_wks); 2856 2857 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2858 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2859 return -EBUSY; 2860 2861 wk_data = &fwrt->dump.wks[idx]; 2862 2863 if (WARN_ON(wk_data->dump_data.desc)) 2864 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2865 2866 wk_data->dump_data.desc = desc; 2867 wk_data->dump_data.monitor_only = monitor_only; 2868 2869 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2870 le32_to_cpu(desc->trig_desc.type)); 2871 2872 queue_delayed_work(system_unbound_wq, &wk_data->wk, 2873 usecs_to_jiffies(delay)); 2874 2875 return 0; 2876 } 2877 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2878 2879 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2880 enum iwl_fw_dbg_trigger trig_type) 2881 { 2882 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2883 return -EIO; 2884 2885 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2886 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2887 trig_type != FW_DBG_TRIGGER_DRIVER) 2888 return -EIO; 2889 2890 iwl_dbg_tlv_time_point(fwrt, 2891 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2892 NULL); 2893 } else { 2894 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2895 int ret; 2896 2897 iwl_dump_error_desc = 2898 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2899 2900 if (!iwl_dump_error_desc) 2901 return -ENOMEM; 2902 2903 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2904 iwl_dump_error_desc->len = 0; 2905 2906 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2907 false, 0); 2908 if (ret) { 2909 kfree(iwl_dump_error_desc); 2910 return ret; 2911 } 2912 } 2913 2914 iwl_trans_sync_nmi(fwrt->trans); 2915 2916 return 0; 2917 } 2918 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2919 2920 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2921 enum iwl_fw_dbg_trigger trig, 2922 const char *str, size_t len, 2923 struct iwl_fw_dbg_trigger_tlv *trigger) 2924 { 2925 struct iwl_fw_dump_desc *desc; 2926 unsigned int delay = 0; 2927 bool monitor_only = false; 2928 2929 if (trigger) { 2930 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2931 2932 if (!le16_to_cpu(trigger->occurrences)) 2933 return 0; 2934 2935 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2936 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2937 trig); 2938 iwl_force_nmi(fwrt->trans); 2939 return 0; 2940 } 2941 2942 trigger->occurrences = cpu_to_le16(occurrences); 2943 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2944 2945 /* convert msec to usec */ 2946 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2947 } 2948 2949 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC); 2950 if (!desc) 2951 return -ENOMEM; 2952 2953 2954 desc->len = len; 2955 desc->trig_desc.type = cpu_to_le32(trig); 2956 memcpy(desc->trig_desc.data, str, len); 2957 2958 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2959 } 2960 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2961 2962 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2963 struct iwl_fw_dbg_trigger_tlv *trigger, 2964 const char *fmt, ...) 2965 { 2966 int ret, len = 0; 2967 char buf[64]; 2968 2969 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2970 return 0; 2971 2972 if (fmt) { 2973 va_list ap; 2974 2975 buf[sizeof(buf) - 1] = '\0'; 2976 2977 va_start(ap, fmt); 2978 vsnprintf(buf, sizeof(buf), fmt, ap); 2979 va_end(ap); 2980 2981 /* check for truncation */ 2982 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2983 buf[sizeof(buf) - 1] = '\0'; 2984 2985 len = strlen(buf) + 1; 2986 } 2987 2988 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2989 trigger); 2990 2991 if (ret) 2992 return ret; 2993 2994 return 0; 2995 } 2996 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2997 2998 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2999 { 3000 u8 *ptr; 3001 int ret; 3002 int i; 3003 3004 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 3005 "Invalid configuration %d\n", conf_id)) 3006 return -EINVAL; 3007 3008 /* EARLY START - firmware's configuration is hard coded */ 3009 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 3010 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 3011 conf_id == FW_DBG_START_FROM_ALIVE) 3012 return 0; 3013 3014 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 3015 return -EINVAL; 3016 3017 if (fwrt->dump.conf != FW_DBG_INVALID) 3018 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 3019 fwrt->dump.conf); 3020 3021 /* Send all HCMDs for configuring the FW debug */ 3022 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 3023 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 3024 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 3025 struct iwl_host_cmd hcmd = { 3026 .id = cmd->id, 3027 .len = { le16_to_cpu(cmd->len), }, 3028 .data = { cmd->data, }, 3029 }; 3030 3031 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3032 if (ret) 3033 return ret; 3034 3035 ptr += sizeof(*cmd); 3036 ptr += le16_to_cpu(cmd->len); 3037 } 3038 3039 fwrt->dump.conf = conf_id; 3040 3041 return 0; 3042 } 3043 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 3044 3045 void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt, 3046 u32 timepoint, 3047 u32 timepoint_data) 3048 { 3049 struct iwl_dbg_dump_complete_cmd hcmd_data; 3050 struct iwl_host_cmd hcmd = { 3051 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD), 3052 .data[0] = &hcmd_data, 3053 .len[0] = sizeof(hcmd_data), 3054 }; 3055 3056 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3057 return; 3058 3059 if (fw_has_capa(&fwrt->fw->ucode_capa, 3060 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) { 3061 hcmd_data.tp = cpu_to_le32(timepoint); 3062 hcmd_data.tp_data = cpu_to_le32(timepoint_data); 3063 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3064 } 3065 } 3066 3067 /* this function assumes dump_start was called beforehand and dump_end will be 3068 * called afterwards 3069 */ 3070 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 3071 { 3072 struct iwl_fw_dbg_params params = {0}; 3073 struct iwl_fwrt_dump_data *dump_data = 3074 &fwrt->dump.wks[wk_idx].dump_data; 3075 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 3076 return; 3077 3078 /* also checks 'desc' for pre-ini mode, since that shadows in union */ 3079 if (!dump_data->trig) { 3080 IWL_ERR(fwrt, "dump trigger data is not set\n"); 3081 goto out; 3082 } 3083 3084 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 3085 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 3086 goto out; 3087 } 3088 3089 /* there's no point in fw dump if the bus is dead */ 3090 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 3091 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 3092 goto out; 3093 } 3094 3095 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 3096 3097 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 3098 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 3099 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 3100 else 3101 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 3102 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 3103 3104 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3105 3106 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3107 u32 policy = le32_to_cpu(dump_data->trig->apply_policy); 3108 u32 time_point = le32_to_cpu(dump_data->trig->time_point); 3109 3110 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) { 3111 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n"); 3112 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0); 3113 } 3114 } 3115 3116 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 3117 iwl_force_nmi(fwrt->trans); 3118 3119 out: 3120 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3121 iwl_fw_error_dump_data_free(dump_data); 3122 } else { 3123 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 3124 dump_data->desc = NULL; 3125 } 3126 3127 clear_bit(wk_idx, &fwrt->dump.active_wks); 3128 } 3129 3130 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 3131 struct iwl_fwrt_dump_data *dump_data, 3132 bool sync) 3133 { 3134 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 3135 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 3136 u32 occur, delay; 3137 unsigned long idx; 3138 3139 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 3140 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 3141 tp_id); 3142 return -EINVAL; 3143 } 3144 3145 delay = le32_to_cpu(trig->dump_delay); 3146 occur = le32_to_cpu(trig->occurrences); 3147 if (!occur) 3148 return 0; 3149 3150 trig->occurrences = cpu_to_le32(--occur); 3151 3152 /* Check there is an available worker. 3153 * ffz return value is undefined if no zero exists, 3154 * so check against ~0UL first. 3155 */ 3156 if (fwrt->dump.active_wks == ~0UL) 3157 return -EBUSY; 3158 3159 idx = ffz(fwrt->dump.active_wks); 3160 3161 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 3162 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 3163 return -EBUSY; 3164 3165 fwrt->dump.wks[idx].dump_data = *dump_data; 3166 3167 if (sync) 3168 delay = 0; 3169 3170 IWL_WARN(fwrt, 3171 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 3172 tp_id, (u32)(delay / USEC_PER_MSEC)); 3173 3174 if (sync) 3175 iwl_fw_dbg_collect_sync(fwrt, idx); 3176 else 3177 queue_delayed_work(system_unbound_wq, 3178 &fwrt->dump.wks[idx].wk, 3179 usecs_to_jiffies(delay)); 3180 3181 return 0; 3182 } 3183 3184 void iwl_fw_error_dump_wk(struct work_struct *work) 3185 { 3186 struct iwl_fwrt_wk_data *wks = 3187 container_of(work, typeof(*wks), wk.work); 3188 struct iwl_fw_runtime *fwrt = 3189 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 3190 3191 /* assumes the op mode mutex is locked in dump_start since 3192 * iwl_fw_dbg_collect_sync can't run in parallel 3193 */ 3194 if (fwrt->ops && fwrt->ops->dump_start) 3195 fwrt->ops->dump_start(fwrt->ops_ctx); 3196 3197 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 3198 3199 if (fwrt->ops && fwrt->ops->dump_end) 3200 fwrt->ops->dump_end(fwrt->ops_ctx); 3201 } 3202 3203 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 3204 { 3205 const struct iwl_cfg *cfg = fwrt->trans->cfg; 3206 3207 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 3208 return; 3209 3210 if (!fwrt->dump.d3_debug_data) { 3211 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 3212 GFP_KERNEL); 3213 if (!fwrt->dump.d3_debug_data) { 3214 IWL_ERR(fwrt, 3215 "failed to allocate memory for D3 debug data\n"); 3216 return; 3217 } 3218 } 3219 3220 /* if the buffer holds previous debug data it is overwritten */ 3221 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 3222 fwrt->dump.d3_debug_data, 3223 cfg->d3_debug_data_length); 3224 3225 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 3226 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 3227 cfg->d3_debug_data_base_addr, 3228 fwrt->dump.d3_debug_data, 3229 cfg->d3_debug_data_length); 3230 } 3231 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 3232 3233 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 3234 { 3235 int i; 3236 3237 iwl_dbg_tlv_del_timers(fwrt->trans); 3238 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 3239 iwl_fw_dbg_collect_sync(fwrt, i); 3240 3241 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 3242 } 3243 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 3244 3245 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 3246 { 3247 struct iwl_dbg_suspend_resume_cmd cmd = { 3248 .operation = suspend ? 3249 cpu_to_le32(DBGC_SUSPEND_CMD) : 3250 cpu_to_le32(DBGC_RESUME_CMD), 3251 }; 3252 struct iwl_host_cmd hcmd = { 3253 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3254 .data[0] = &cmd, 3255 .len[0] = sizeof(cmd), 3256 }; 3257 3258 return iwl_trans_send_cmd(trans, &hcmd); 3259 } 3260 3261 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3262 struct iwl_fw_dbg_params *params) 3263 { 3264 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3265 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3266 return; 3267 } 3268 3269 if (params) { 3270 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3271 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3272 } 3273 3274 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3275 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3276 * avoid halting the HW while writing 3277 */ 3278 usleep_range(700, 1000); 3279 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3280 } 3281 3282 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3283 struct iwl_fw_dbg_params *params) 3284 { 3285 if (!params) 3286 return -EIO; 3287 3288 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3289 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3290 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3291 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3292 } else { 3293 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3294 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3295 } 3296 3297 return 0; 3298 } 3299 3300 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt) 3301 { 3302 struct iwl_mvm_marker marker = { 3303 .dw_len = sizeof(struct iwl_mvm_marker) / 4, 3304 .marker_id = MARKER_ID_SYNC_CLOCK, 3305 }; 3306 struct iwl_host_cmd hcmd = { 3307 .flags = CMD_ASYNC, 3308 .id = WIDE_ID(LONG_GROUP, MARKER_CMD), 3309 .dataflags = {}, 3310 }; 3311 struct iwl_mvm_marker_rsp *resp; 3312 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw, 3313 WIDE_ID(LONG_GROUP, MARKER_CMD), 3314 IWL_FW_CMD_VER_UNKNOWN); 3315 int ret; 3316 3317 if (cmd_ver == 1) { 3318 /* the real timestamp is taken from the ftrace clock 3319 * this is for finding the match between fw and kernel logs 3320 */ 3321 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++); 3322 } else if (cmd_ver == 2) { 3323 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns()); 3324 } else { 3325 IWL_DEBUG_INFO(fwrt, 3326 "Invalid version of Marker CMD. Ver = %d\n", 3327 cmd_ver); 3328 return -EINVAL; 3329 } 3330 3331 hcmd.data[0] = ▮ 3332 hcmd.len[0] = sizeof(marker); 3333 3334 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3335 3336 if (cmd_ver > 1 && hcmd.resp_pkt) { 3337 resp = (void *)hcmd.resp_pkt->data; 3338 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n", 3339 le32_to_cpu(resp->gp2)); 3340 } 3341 3342 return ret; 3343 } 3344 3345 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3346 struct iwl_fw_dbg_params *params, 3347 bool stop) 3348 { 3349 int ret __maybe_unused = 0; 3350 3351 if (!iwl_trans_fw_running(fwrt->trans)) 3352 return; 3353 3354 if (fw_has_capa(&fwrt->fw->ucode_capa, 3355 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) { 3356 if (stop) 3357 iwl_fw_send_timestamp_marker_cmd(fwrt); 3358 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3359 } else if (stop) { 3360 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3361 } else { 3362 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3363 } 3364 #ifdef CONFIG_IWLWIFI_DEBUGFS 3365 if (!ret) { 3366 if (stop) 3367 fwrt->trans->dbg.rec_on = false; 3368 else 3369 iwl_fw_set_dbg_rec_on(fwrt); 3370 } 3371 #endif 3372 } 3373 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3374 3375 void iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime *fwrt) 3376 { 3377 struct iwl_fw_dbg_config_cmd cmd = { 3378 .type = cpu_to_le32(DEBUG_TOKEN_CONFIG_TYPE), 3379 .conf = cpu_to_le32(IWL_FW_DBG_CONFIG_TOKEN), 3380 }; 3381 struct iwl_host_cmd hcmd = { 3382 .id = WIDE_ID(LONG_GROUP, LDBG_CONFIG_CMD), 3383 .data[0] = &cmd, 3384 .len[0] = sizeof(cmd), 3385 }; 3386 u32 preset = u32_get_bits(fwrt->trans->dbg.domains_bitmap, 3387 GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1)); 3388 3389 /* supported starting from 9000 devices */ 3390 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000) 3391 return; 3392 3393 if (fwrt->trans->dbg.yoyo_bin_loaded || (preset && preset != 1)) 3394 return; 3395 3396 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3397 } 3398 IWL_EXPORT_SYMBOL(iwl_fw_disable_dbg_asserts); 3399 3400 void iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime *fwrt) 3401 { 3402 struct iwl_fw_dbg_params params = {0}; 3403 3404 iwl_fw_dbg_stop_sync(fwrt); 3405 3406 if (fw_has_api(&fwrt->fw->ucode_capa, 3407 IWL_UCODE_TLV_API_INT_DBG_BUF_CLEAR)) { 3408 struct iwl_host_cmd hcmd = { 3409 .id = WIDE_ID(DEBUG_GROUP, FW_CLEAR_BUFFER), 3410 }; 3411 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3412 } 3413 3414 iwl_dbg_tlv_init_cfg(fwrt); 3415 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3416 } 3417 IWL_EXPORT_SYMBOL(iwl_fw_dbg_clear_monitor_buf); 3418