1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; 24 * 25 * The full GNU General Public License is included in this distribution 26 * in the file called COPYING. 27 * 28 * Contact Information: 29 * Intel Linux Wireless <linuxwifi@intel.com> 30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 31 * 32 * BSD LICENSE 33 * 34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 35 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 36 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 37 * Copyright(c) 2018 Intel Corporation 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/devcoredump.h> 68 #include "iwl-drv.h" 69 #include "runtime.h" 70 #include "dbg.h" 71 #include "iwl-io.h" 72 #include "iwl-prph.h" 73 #include "iwl-csr.h" 74 75 /** 76 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 77 * 78 * @fwrt_ptr: pointer to the buffer coming from fwrt 79 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 80 * transport's data. 81 * @trans_len: length of the valid data in trans_ptr 82 * @fwrt_len: length of the valid data in fwrt_ptr 83 */ 84 struct iwl_fw_dump_ptrs { 85 struct iwl_trans_dump_data *trans_ptr; 86 void *fwrt_ptr; 87 u32 fwrt_len; 88 }; 89 90 #define RADIO_REG_MAX_READ 0x2ad 91 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 92 struct iwl_fw_error_dump_data **dump_data) 93 { 94 u8 *pos = (void *)(*dump_data)->data; 95 unsigned long flags; 96 int i; 97 98 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 99 100 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 101 return; 102 103 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 104 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 105 106 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 107 u32 rd_cmd = RADIO_RSP_RD_CMD; 108 109 rd_cmd |= i << RADIO_RSP_ADDR_POS; 110 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 111 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 112 113 pos++; 114 } 115 116 *dump_data = iwl_fw_error_next_data(*dump_data); 117 118 iwl_trans_release_nic_access(fwrt->trans, &flags); 119 } 120 121 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 122 struct iwl_fw_error_dump_data **dump_data, 123 int size, u32 offset, int fifo_num) 124 { 125 struct iwl_fw_error_dump_fifo *fifo_hdr; 126 u32 *fifo_data; 127 u32 fifo_len; 128 int i; 129 130 fifo_hdr = (void *)(*dump_data)->data; 131 fifo_data = (void *)fifo_hdr->data; 132 fifo_len = size; 133 134 /* No need to try to read the data if the length is 0 */ 135 if (fifo_len == 0) 136 return; 137 138 /* Add a TLV for the RXF */ 139 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 140 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 141 142 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 143 fifo_hdr->available_bytes = 144 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 145 RXF_RD_D_SPACE + offset)); 146 fifo_hdr->wr_ptr = 147 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 148 RXF_RD_WR_PTR + offset)); 149 fifo_hdr->rd_ptr = 150 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 151 RXF_RD_RD_PTR + offset)); 152 fifo_hdr->fence_ptr = 153 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 154 RXF_RD_FENCE_PTR + offset)); 155 fifo_hdr->fence_mode = 156 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 157 RXF_SET_FENCE_MODE + offset)); 158 159 /* Lock fence */ 160 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 161 /* Set fence pointer to the same place like WR pointer */ 162 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 163 /* Set fence offset */ 164 iwl_trans_write_prph(fwrt->trans, 165 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 166 167 /* Read FIFO */ 168 fifo_len /= sizeof(u32); /* Size in DWORDS */ 169 for (i = 0; i < fifo_len; i++) 170 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 171 RXF_FIFO_RD_FENCE_INC + 172 offset); 173 *dump_data = iwl_fw_error_next_data(*dump_data); 174 } 175 176 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 177 struct iwl_fw_error_dump_data **dump_data, 178 int size, u32 offset, int fifo_num) 179 { 180 struct iwl_fw_error_dump_fifo *fifo_hdr; 181 u32 *fifo_data; 182 u32 fifo_len; 183 int i; 184 185 fifo_hdr = (void *)(*dump_data)->data; 186 fifo_data = (void *)fifo_hdr->data; 187 fifo_len = size; 188 189 /* No need to try to read the data if the length is 0 */ 190 if (fifo_len == 0) 191 return; 192 193 /* Add a TLV for the FIFO */ 194 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 195 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 196 197 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 198 fifo_hdr->available_bytes = 199 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 200 TXF_FIFO_ITEM_CNT + offset)); 201 fifo_hdr->wr_ptr = 202 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 203 TXF_WR_PTR + offset)); 204 fifo_hdr->rd_ptr = 205 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 206 TXF_RD_PTR + offset)); 207 fifo_hdr->fence_ptr = 208 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 209 TXF_FENCE_PTR + offset)); 210 fifo_hdr->fence_mode = 211 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 212 TXF_LOCK_FENCE + offset)); 213 214 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 215 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 216 TXF_WR_PTR + offset); 217 218 /* Dummy-read to advance the read pointer to the head */ 219 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 220 221 /* Read FIFO */ 222 fifo_len /= sizeof(u32); /* Size in DWORDS */ 223 for (i = 0; i < fifo_len; i++) 224 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 225 TXF_READ_MODIFY_DATA + 226 offset); 227 *dump_data = iwl_fw_error_next_data(*dump_data); 228 } 229 230 static void iwl_fw_dump_fifos(struct iwl_fw_runtime *fwrt, 231 struct iwl_fw_error_dump_data **dump_data) 232 { 233 struct iwl_fw_error_dump_fifo *fifo_hdr; 234 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 235 u32 *fifo_data; 236 u32 fifo_len; 237 unsigned long flags; 238 int i, j; 239 240 IWL_DEBUG_INFO(fwrt, "WRT FIFO dump\n"); 241 242 if (!iwl_trans_grab_nic_access(fwrt->trans, &flags)) 243 return; 244 245 /* Pull RXF1 */ 246 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->lmac[0].rxfifo1_size, 0, 0); 247 /* Pull RXF2 */ 248 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 249 RXF_DIFF_FROM_PREV, 1); 250 /* Pull LMAC2 RXF1 */ 251 if (fwrt->smem_cfg.num_lmacs > 1) 252 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->lmac[1].rxfifo1_size, 253 LMAC2_PRPH_OFFSET, 2); 254 255 /* Pull TXF data from LMAC1 */ 256 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 257 /* Mark the number of TXF we're pulling now */ 258 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 259 iwl_fwrt_dump_txf(fwrt, dump_data, cfg->lmac[0].txfifo_size[i], 260 0, i); 261 } 262 263 /* Pull TXF data from LMAC2 */ 264 if (fwrt->smem_cfg.num_lmacs > 1) { 265 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 266 /* Mark the number of TXF we're pulling now */ 267 iwl_trans_write_prph(fwrt->trans, 268 TXF_LARC_NUM + LMAC2_PRPH_OFFSET, 269 i); 270 iwl_fwrt_dump_txf(fwrt, dump_data, 271 cfg->lmac[1].txfifo_size[i], 272 LMAC2_PRPH_OFFSET, 273 i + cfg->num_txfifo_entries); 274 } 275 } 276 277 if (fw_has_capa(&fwrt->fw->ucode_capa, 278 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 279 /* Pull UMAC internal TXF data from all TXFs */ 280 for (i = 0; 281 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 282 i++) { 283 fifo_hdr = (void *)(*dump_data)->data; 284 fifo_data = (void *)fifo_hdr->data; 285 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 286 287 /* No need to try to read the data if the length is 0 */ 288 if (fifo_len == 0) 289 continue; 290 291 /* Add a TLV for the internal FIFOs */ 292 (*dump_data)->type = 293 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 294 (*dump_data)->len = 295 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 296 297 fifo_hdr->fifo_num = cpu_to_le32(i); 298 299 /* Mark the number of TXF we're pulling now */ 300 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 301 fwrt->smem_cfg.num_txfifo_entries); 302 303 fifo_hdr->available_bytes = 304 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 305 TXF_CPU2_FIFO_ITEM_CNT)); 306 fifo_hdr->wr_ptr = 307 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 308 TXF_CPU2_WR_PTR)); 309 fifo_hdr->rd_ptr = 310 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 311 TXF_CPU2_RD_PTR)); 312 fifo_hdr->fence_ptr = 313 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 314 TXF_CPU2_FENCE_PTR)); 315 fifo_hdr->fence_mode = 316 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 317 TXF_CPU2_LOCK_FENCE)); 318 319 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 320 iwl_trans_write_prph(fwrt->trans, 321 TXF_CPU2_READ_MODIFY_ADDR, 322 TXF_CPU2_WR_PTR); 323 324 /* Dummy-read to advance the read pointer to head */ 325 iwl_trans_read_prph(fwrt->trans, 326 TXF_CPU2_READ_MODIFY_DATA); 327 328 /* Read FIFO */ 329 fifo_len /= sizeof(u32); /* Size in DWORDS */ 330 for (j = 0; j < fifo_len; j++) 331 fifo_data[j] = 332 iwl_trans_read_prph(fwrt->trans, 333 TXF_CPU2_READ_MODIFY_DATA); 334 *dump_data = iwl_fw_error_next_data(*dump_data); 335 } 336 } 337 338 iwl_trans_release_nic_access(fwrt->trans, &flags); 339 } 340 341 #define IWL8260_ICCM_OFFSET 0x44000 /* Only for B-step */ 342 #define IWL8260_ICCM_LEN 0xC000 /* Only for B-step */ 343 344 struct iwl_prph_range { 345 u32 start, end; 346 }; 347 348 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 349 { .start = 0x00a00000, .end = 0x00a00000 }, 350 { .start = 0x00a0000c, .end = 0x00a00024 }, 351 { .start = 0x00a0002c, .end = 0x00a0003c }, 352 { .start = 0x00a00410, .end = 0x00a00418 }, 353 { .start = 0x00a00420, .end = 0x00a00420 }, 354 { .start = 0x00a00428, .end = 0x00a00428 }, 355 { .start = 0x00a00430, .end = 0x00a0043c }, 356 { .start = 0x00a00444, .end = 0x00a00444 }, 357 { .start = 0x00a004c0, .end = 0x00a004cc }, 358 { .start = 0x00a004d8, .end = 0x00a004d8 }, 359 { .start = 0x00a004e0, .end = 0x00a004f0 }, 360 { .start = 0x00a00840, .end = 0x00a00840 }, 361 { .start = 0x00a00850, .end = 0x00a00858 }, 362 { .start = 0x00a01004, .end = 0x00a01008 }, 363 { .start = 0x00a01010, .end = 0x00a01010 }, 364 { .start = 0x00a01018, .end = 0x00a01018 }, 365 { .start = 0x00a01024, .end = 0x00a01024 }, 366 { .start = 0x00a0102c, .end = 0x00a01034 }, 367 { .start = 0x00a0103c, .end = 0x00a01040 }, 368 { .start = 0x00a01048, .end = 0x00a01094 }, 369 { .start = 0x00a01c00, .end = 0x00a01c20 }, 370 { .start = 0x00a01c58, .end = 0x00a01c58 }, 371 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 372 { .start = 0x00a01c28, .end = 0x00a01c54 }, 373 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 374 { .start = 0x00a01c60, .end = 0x00a01cdc }, 375 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 376 { .start = 0x00a01d18, .end = 0x00a01d20 }, 377 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 378 { .start = 0x00a01d40, .end = 0x00a01d5c }, 379 { .start = 0x00a01d80, .end = 0x00a01d80 }, 380 { .start = 0x00a01d98, .end = 0x00a01d9c }, 381 { .start = 0x00a01da8, .end = 0x00a01da8 }, 382 { .start = 0x00a01db8, .end = 0x00a01df4 }, 383 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 384 { .start = 0x00a01e00, .end = 0x00a01e2c }, 385 { .start = 0x00a01e40, .end = 0x00a01e60 }, 386 { .start = 0x00a01e68, .end = 0x00a01e6c }, 387 { .start = 0x00a01e74, .end = 0x00a01e74 }, 388 { .start = 0x00a01e84, .end = 0x00a01e90 }, 389 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 390 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 391 { .start = 0x00a01f00, .end = 0x00a01f1c }, 392 { .start = 0x00a01f44, .end = 0x00a01ffc }, 393 { .start = 0x00a02000, .end = 0x00a02048 }, 394 { .start = 0x00a02068, .end = 0x00a020f0 }, 395 { .start = 0x00a02100, .end = 0x00a02118 }, 396 { .start = 0x00a02140, .end = 0x00a0214c }, 397 { .start = 0x00a02168, .end = 0x00a0218c }, 398 { .start = 0x00a021c0, .end = 0x00a021c0 }, 399 { .start = 0x00a02400, .end = 0x00a02410 }, 400 { .start = 0x00a02418, .end = 0x00a02420 }, 401 { .start = 0x00a02428, .end = 0x00a0242c }, 402 { .start = 0x00a02434, .end = 0x00a02434 }, 403 { .start = 0x00a02440, .end = 0x00a02460 }, 404 { .start = 0x00a02468, .end = 0x00a024b0 }, 405 { .start = 0x00a024c8, .end = 0x00a024cc }, 406 { .start = 0x00a02500, .end = 0x00a02504 }, 407 { .start = 0x00a0250c, .end = 0x00a02510 }, 408 { .start = 0x00a02540, .end = 0x00a02554 }, 409 { .start = 0x00a02580, .end = 0x00a025f4 }, 410 { .start = 0x00a02600, .end = 0x00a0260c }, 411 { .start = 0x00a02648, .end = 0x00a02650 }, 412 { .start = 0x00a02680, .end = 0x00a02680 }, 413 { .start = 0x00a026c0, .end = 0x00a026d0 }, 414 { .start = 0x00a02700, .end = 0x00a0270c }, 415 { .start = 0x00a02804, .end = 0x00a02804 }, 416 { .start = 0x00a02818, .end = 0x00a0281c }, 417 { .start = 0x00a02c00, .end = 0x00a02db4 }, 418 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 419 { .start = 0x00a03000, .end = 0x00a03014 }, 420 { .start = 0x00a0301c, .end = 0x00a0302c }, 421 { .start = 0x00a03034, .end = 0x00a03038 }, 422 { .start = 0x00a03040, .end = 0x00a03048 }, 423 { .start = 0x00a03060, .end = 0x00a03068 }, 424 { .start = 0x00a03070, .end = 0x00a03074 }, 425 { .start = 0x00a0307c, .end = 0x00a0307c }, 426 { .start = 0x00a03080, .end = 0x00a03084 }, 427 { .start = 0x00a0308c, .end = 0x00a03090 }, 428 { .start = 0x00a03098, .end = 0x00a03098 }, 429 { .start = 0x00a030a0, .end = 0x00a030a0 }, 430 { .start = 0x00a030a8, .end = 0x00a030b4 }, 431 { .start = 0x00a030bc, .end = 0x00a030bc }, 432 { .start = 0x00a030c0, .end = 0x00a0312c }, 433 { .start = 0x00a03c00, .end = 0x00a03c5c }, 434 { .start = 0x00a04400, .end = 0x00a04454 }, 435 { .start = 0x00a04460, .end = 0x00a04474 }, 436 { .start = 0x00a044c0, .end = 0x00a044ec }, 437 { .start = 0x00a04500, .end = 0x00a04504 }, 438 { .start = 0x00a04510, .end = 0x00a04538 }, 439 { .start = 0x00a04540, .end = 0x00a04548 }, 440 { .start = 0x00a04560, .end = 0x00a0457c }, 441 { .start = 0x00a04590, .end = 0x00a04598 }, 442 { .start = 0x00a045c0, .end = 0x00a045f4 }, 443 }; 444 445 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 446 { .start = 0x00a05c00, .end = 0x00a05c18 }, 447 { .start = 0x00a05400, .end = 0x00a056e8 }, 448 { .start = 0x00a08000, .end = 0x00a098bc }, 449 { .start = 0x00a02400, .end = 0x00a02758 }, 450 }; 451 452 static void _iwl_read_prph_block(struct iwl_trans *trans, u32 start, 453 u32 len_bytes, __le32 *data) 454 { 455 u32 i; 456 457 for (i = 0; i < len_bytes; i += 4) 458 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 459 } 460 461 static bool iwl_read_prph_block(struct iwl_trans *trans, u32 start, 462 u32 len_bytes, __le32 *data) 463 { 464 unsigned long flags; 465 bool success = false; 466 467 if (iwl_trans_grab_nic_access(trans, &flags)) { 468 success = true; 469 _iwl_read_prph_block(trans, start, len_bytes, data); 470 iwl_trans_release_nic_access(trans, &flags); 471 } 472 473 return success; 474 } 475 476 static void iwl_dump_prph(struct iwl_trans *trans, 477 struct iwl_fw_error_dump_data **data, 478 const struct iwl_prph_range *iwl_prph_dump_addr, 479 u32 range_len) 480 { 481 struct iwl_fw_error_dump_prph *prph; 482 unsigned long flags; 483 u32 i; 484 485 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 486 487 if (!iwl_trans_grab_nic_access(trans, &flags)) 488 return; 489 490 for (i = 0; i < range_len; i++) { 491 /* The range includes both boundaries */ 492 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 493 iwl_prph_dump_addr[i].start + 4; 494 495 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 496 (*data)->len = cpu_to_le32(sizeof(*prph) + 497 num_bytes_in_chunk); 498 prph = (void *)(*data)->data; 499 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 500 501 _iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 502 /* our range is inclusive, hence + 4 */ 503 iwl_prph_dump_addr[i].end - 504 iwl_prph_dump_addr[i].start + 4, 505 (void *)prph->data); 506 507 *data = iwl_fw_error_next_data(*data); 508 } 509 510 iwl_trans_release_nic_access(trans, &flags); 511 } 512 513 /* 514 * alloc_sgtable - allocates scallerlist table in the given size, 515 * fills it with pages and returns it 516 * @size: the size (in bytes) of the table 517 */ 518 static struct scatterlist *alloc_sgtable(int size) 519 { 520 int alloc_size, nents, i; 521 struct page *new_page; 522 struct scatterlist *iter; 523 struct scatterlist *table; 524 525 nents = DIV_ROUND_UP(size, PAGE_SIZE); 526 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 527 if (!table) 528 return NULL; 529 sg_init_table(table, nents); 530 iter = table; 531 for_each_sg(table, iter, sg_nents(table), i) { 532 new_page = alloc_page(GFP_KERNEL); 533 if (!new_page) { 534 /* release all previous allocated pages in the table */ 535 iter = table; 536 for_each_sg(table, iter, sg_nents(table), i) { 537 new_page = sg_page(iter); 538 if (new_page) 539 __free_page(new_page); 540 } 541 return NULL; 542 } 543 alloc_size = min_t(int, size, PAGE_SIZE); 544 size -= PAGE_SIZE; 545 sg_set_page(iter, new_page, alloc_size, 0); 546 } 547 return table; 548 } 549 550 void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt) 551 { 552 struct iwl_fw_error_dump_file *dump_file; 553 struct iwl_fw_error_dump_data *dump_data; 554 struct iwl_fw_error_dump_info *dump_info; 555 struct iwl_fw_error_dump_mem *dump_mem; 556 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 557 struct iwl_fw_error_dump_trigger_desc *dump_trig; 558 struct iwl_fw_dump_ptrs *fw_error_dump; 559 struct scatterlist *sg_dump_data; 560 u32 sram_len, sram_ofs; 561 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = fwrt->fw->dbg_mem_tlv; 562 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 563 u32 file_len, fifo_data_len = 0, prph_len = 0, radio_len = 0; 564 u32 smem_len = fwrt->fw->n_dbg_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 565 u32 sram2_len = fwrt->fw->n_dbg_mem_tlv ? 566 0 : fwrt->trans->cfg->dccm2_len; 567 bool monitor_dump_only = false; 568 int i; 569 570 IWL_DEBUG_INFO(fwrt, "WRT dump start\n"); 571 572 /* there's no point in fw dump if the bus is dead */ 573 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 574 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 575 goto out; 576 } 577 578 if (fwrt->dump.trig && 579 fwrt->dump.trig->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY) 580 monitor_dump_only = true; 581 582 fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL); 583 if (!fw_error_dump) 584 goto out; 585 586 /* SRAM - include stack CCM if driver knows the values for it */ 587 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 588 const struct fw_img *img; 589 590 img = &fwrt->fw->img[fwrt->cur_fw_img]; 591 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 592 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 593 } else { 594 sram_ofs = fwrt->trans->cfg->dccm_offset; 595 sram_len = fwrt->trans->cfg->dccm_len; 596 } 597 598 /* reading RXF/TXF sizes */ 599 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 600 fifo_data_len = 0; 601 602 /* Count RXF2 size */ 603 if (mem_cfg->rxfifo2_size) { 604 /* Add header info */ 605 fifo_data_len += mem_cfg->rxfifo2_size + 606 sizeof(*dump_data) + 607 sizeof(struct iwl_fw_error_dump_fifo); 608 } 609 610 /* Count RXF1 sizes */ 611 for (i = 0; i < mem_cfg->num_lmacs; i++) { 612 if (!mem_cfg->lmac[i].rxfifo1_size) 613 continue; 614 615 /* Add header info */ 616 fifo_data_len += mem_cfg->lmac[i].rxfifo1_size + 617 sizeof(*dump_data) + 618 sizeof(struct iwl_fw_error_dump_fifo); 619 } 620 621 /* Count TXF sizes */ 622 for (i = 0; i < mem_cfg->num_lmacs; i++) { 623 int j; 624 625 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) { 626 if (!mem_cfg->lmac[i].txfifo_size[j]) 627 continue; 628 629 /* Add header info */ 630 fifo_data_len += 631 mem_cfg->lmac[i].txfifo_size[j] + 632 sizeof(*dump_data) + 633 sizeof(struct iwl_fw_error_dump_fifo); 634 } 635 } 636 637 if (fw_has_capa(&fwrt->fw->ucode_capa, 638 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 639 for (i = 0; 640 i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); 641 i++) { 642 if (!mem_cfg->internal_txfifo_size[i]) 643 continue; 644 645 /* Add header info */ 646 fifo_data_len += 647 mem_cfg->internal_txfifo_size[i] + 648 sizeof(*dump_data) + 649 sizeof(struct iwl_fw_error_dump_fifo); 650 } 651 } 652 653 /* Make room for PRPH registers */ 654 if (!fwrt->trans->cfg->gen2) { 655 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr_comm); 656 i++) { 657 /* The range includes both boundaries */ 658 int num_bytes_in_chunk = 659 iwl_prph_dump_addr_comm[i].end - 660 iwl_prph_dump_addr_comm[i].start + 4; 661 662 prph_len += sizeof(*dump_data) + 663 sizeof(struct iwl_fw_error_dump_prph) + 664 num_bytes_in_chunk; 665 } 666 } 667 668 if (!fwrt->trans->cfg->gen2 && 669 fwrt->trans->cfg->mq_rx_supported) { 670 for (i = 0; i < 671 ARRAY_SIZE(iwl_prph_dump_addr_9000); i++) { 672 /* The range includes both boundaries */ 673 int num_bytes_in_chunk = 674 iwl_prph_dump_addr_9000[i].end - 675 iwl_prph_dump_addr_9000[i].start + 4; 676 677 prph_len += sizeof(*dump_data) + 678 sizeof(struct iwl_fw_error_dump_prph) + 679 num_bytes_in_chunk; 680 } 681 } 682 683 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 684 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 685 } 686 687 file_len = sizeof(*dump_file) + 688 sizeof(*dump_data) * 3 + 689 sizeof(*dump_smem_cfg) + 690 fifo_data_len + 691 prph_len + 692 radio_len + 693 sizeof(*dump_info); 694 695 /* Make room for the SMEM, if it exists */ 696 if (smem_len) 697 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + smem_len; 698 699 /* Make room for the secondary SRAM, if it exists */ 700 if (sram2_len) 701 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + sram2_len; 702 703 /* Make room for MEM segments */ 704 for (i = 0; i < fwrt->fw->n_dbg_mem_tlv; i++) { 705 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + 706 le32_to_cpu(fw_dbg_mem[i].len); 707 } 708 709 /* Make room for fw's virtual image pages, if it exists */ 710 if (!fwrt->trans->cfg->gen2 && 711 fwrt->fw->img[fwrt->cur_fw_img].paging_mem_size && 712 fwrt->fw_paging_db[0].fw_paging_block) 713 file_len += fwrt->num_of_paging_blk * 714 (sizeof(*dump_data) + 715 sizeof(struct iwl_fw_error_dump_paging) + 716 PAGING_BLOCK_SIZE); 717 718 /* If we only want a monitor dump, reset the file length */ 719 if (monitor_dump_only) { 720 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 721 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 722 } 723 724 if (fwrt->dump.desc) 725 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 726 fwrt->dump.desc->len; 727 728 if (!fwrt->fw->n_dbg_mem_tlv) 729 file_len += sram_len + sizeof(*dump_mem); 730 731 dump_file = vzalloc(file_len); 732 if (!dump_file) { 733 kfree(fw_error_dump); 734 goto out; 735 } 736 737 fw_error_dump->fwrt_ptr = dump_file; 738 739 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 740 dump_data = (void *)dump_file->data; 741 742 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 743 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 744 dump_info = (void *)dump_data->data; 745 dump_info->device_family = 746 fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 ? 747 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) : 748 cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8); 749 dump_info->hw_step = cpu_to_le32(CSR_HW_REV_STEP(fwrt->trans->hw_rev)); 750 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 751 sizeof(dump_info->fw_human_readable)); 752 strncpy(dump_info->dev_human_readable, fwrt->trans->cfg->name, 753 sizeof(dump_info->dev_human_readable)); 754 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 755 sizeof(dump_info->bus_human_readable)); 756 757 dump_data = iwl_fw_error_next_data(dump_data); 758 759 /* Dump shared memory configuration */ 760 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 761 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 762 dump_smem_cfg = (void *)dump_data->data; 763 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 764 dump_smem_cfg->num_txfifo_entries = 765 cpu_to_le32(mem_cfg->num_txfifo_entries); 766 for (i = 0; i < MAX_NUM_LMAC; i++) { 767 int j; 768 769 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 770 dump_smem_cfg->lmac[i].txfifo_size[j] = 771 cpu_to_le32(mem_cfg->lmac[i].txfifo_size[j]); 772 dump_smem_cfg->lmac[i].rxfifo1_size = 773 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 774 } 775 dump_smem_cfg->rxfifo2_size = cpu_to_le32(mem_cfg->rxfifo2_size); 776 dump_smem_cfg->internal_txfifo_addr = 777 cpu_to_le32(mem_cfg->internal_txfifo_addr); 778 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 779 dump_smem_cfg->internal_txfifo_size[i] = 780 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 781 } 782 783 dump_data = iwl_fw_error_next_data(dump_data); 784 785 /* We only dump the FIFOs if the FW is in error state */ 786 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 787 iwl_fw_dump_fifos(fwrt, &dump_data); 788 if (radio_len) 789 iwl_read_radio_regs(fwrt, &dump_data); 790 } 791 792 if (fwrt->dump.desc) { 793 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 794 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 795 fwrt->dump.desc->len); 796 dump_trig = (void *)dump_data->data; 797 memcpy(dump_trig, &fwrt->dump.desc->trig_desc, 798 sizeof(*dump_trig) + fwrt->dump.desc->len); 799 800 dump_data = iwl_fw_error_next_data(dump_data); 801 } 802 803 /* In case we only want monitor dump, skip to dump trasport data */ 804 if (monitor_dump_only) 805 goto dump_trans_data; 806 807 if (!fwrt->fw->n_dbg_mem_tlv) { 808 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 809 dump_data->len = cpu_to_le32(sram_len + sizeof(*dump_mem)); 810 dump_mem = (void *)dump_data->data; 811 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM); 812 dump_mem->offset = cpu_to_le32(sram_ofs); 813 iwl_trans_read_mem_bytes(fwrt->trans, sram_ofs, dump_mem->data, 814 sram_len); 815 dump_data = iwl_fw_error_next_data(dump_data); 816 } 817 818 for (i = 0; i < fwrt->fw->n_dbg_mem_tlv; i++) { 819 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 820 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 821 bool success; 822 823 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 824 dump_data->len = cpu_to_le32(len + sizeof(*dump_mem)); 825 dump_mem = (void *)dump_data->data; 826 dump_mem->type = fw_dbg_mem[i].data_type; 827 dump_mem->offset = cpu_to_le32(ofs); 828 829 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", 830 dump_mem->type); 831 832 switch (dump_mem->type & cpu_to_le32(FW_DBG_MEM_TYPE_MASK)) { 833 case cpu_to_le32(FW_DBG_MEM_TYPE_REGULAR): 834 iwl_trans_read_mem_bytes(fwrt->trans, ofs, 835 dump_mem->data, 836 len); 837 success = true; 838 break; 839 case cpu_to_le32(FW_DBG_MEM_TYPE_PRPH): 840 success = iwl_read_prph_block(fwrt->trans, ofs, len, 841 (void *)dump_mem->data); 842 break; 843 default: 844 /* 845 * shouldn't get here, we ignored this kind 846 * of TLV earlier during the TLV parsing?! 847 */ 848 WARN_ON(1); 849 success = false; 850 } 851 852 if (success) 853 dump_data = iwl_fw_error_next_data(dump_data); 854 } 855 856 if (smem_len) { 857 IWL_DEBUG_INFO(fwrt, "WRT SMEM dump\n"); 858 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 859 dump_data->len = cpu_to_le32(smem_len + sizeof(*dump_mem)); 860 dump_mem = (void *)dump_data->data; 861 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SMEM); 862 dump_mem->offset = cpu_to_le32(fwrt->trans->cfg->smem_offset); 863 iwl_trans_read_mem_bytes(fwrt->trans, 864 fwrt->trans->cfg->smem_offset, 865 dump_mem->data, smem_len); 866 dump_data = iwl_fw_error_next_data(dump_data); 867 } 868 869 if (sram2_len) { 870 IWL_DEBUG_INFO(fwrt, "WRT SRAM dump\n"); 871 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 872 dump_data->len = cpu_to_le32(sram2_len + sizeof(*dump_mem)); 873 dump_mem = (void *)dump_data->data; 874 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM); 875 dump_mem->offset = cpu_to_le32(fwrt->trans->cfg->dccm2_offset); 876 iwl_trans_read_mem_bytes(fwrt->trans, 877 fwrt->trans->cfg->dccm2_offset, 878 dump_mem->data, sram2_len); 879 dump_data = iwl_fw_error_next_data(dump_data); 880 } 881 882 /* Dump fw's virtual image */ 883 if (!fwrt->trans->cfg->gen2 && 884 fwrt->fw->img[fwrt->cur_fw_img].paging_mem_size && 885 fwrt->fw_paging_db[0].fw_paging_block) { 886 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 887 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 888 struct iwl_fw_error_dump_paging *paging; 889 struct page *pages = 890 fwrt->fw_paging_db[i].fw_paging_block; 891 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 892 893 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 894 dump_data->len = cpu_to_le32(sizeof(*paging) + 895 PAGING_BLOCK_SIZE); 896 paging = (void *)dump_data->data; 897 paging->index = cpu_to_le32(i); 898 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 899 PAGING_BLOCK_SIZE, 900 DMA_BIDIRECTIONAL); 901 memcpy(paging->data, page_address(pages), 902 PAGING_BLOCK_SIZE); 903 dump_data = iwl_fw_error_next_data(dump_data); 904 } 905 } 906 907 if (prph_len) { 908 iwl_dump_prph(fwrt->trans, &dump_data, 909 iwl_prph_dump_addr_comm, 910 ARRAY_SIZE(iwl_prph_dump_addr_comm)); 911 912 if (fwrt->trans->cfg->mq_rx_supported) 913 iwl_dump_prph(fwrt->trans, &dump_data, 914 iwl_prph_dump_addr_9000, 915 ARRAY_SIZE(iwl_prph_dump_addr_9000)); 916 } 917 918 dump_trans_data: 919 fw_error_dump->trans_ptr = iwl_trans_dump_data(fwrt->trans, 920 fwrt->dump.trig); 921 fw_error_dump->fwrt_len = file_len; 922 if (fw_error_dump->trans_ptr) 923 file_len += fw_error_dump->trans_ptr->len; 924 dump_file->file_len = cpu_to_le32(file_len); 925 926 sg_dump_data = alloc_sgtable(file_len); 927 if (sg_dump_data) { 928 sg_pcopy_from_buffer(sg_dump_data, 929 sg_nents(sg_dump_data), 930 fw_error_dump->fwrt_ptr, 931 fw_error_dump->fwrt_len, 0); 932 if (fw_error_dump->trans_ptr) 933 sg_pcopy_from_buffer(sg_dump_data, 934 sg_nents(sg_dump_data), 935 fw_error_dump->trans_ptr->data, 936 fw_error_dump->trans_ptr->len, 937 fw_error_dump->fwrt_len); 938 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 939 GFP_KERNEL); 940 } 941 vfree(fw_error_dump->fwrt_ptr); 942 vfree(fw_error_dump->trans_ptr); 943 kfree(fw_error_dump); 944 945 out: 946 iwl_fw_free_dump_desc(fwrt); 947 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 948 IWL_DEBUG_INFO(fwrt, "WRT dump done\n"); 949 } 950 IWL_EXPORT_SYMBOL(iwl_fw_error_dump); 951 952 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 953 .trig_desc = { 954 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 955 }, 956 }; 957 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 958 959 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 960 const struct iwl_fw_dump_desc *desc, 961 const struct iwl_fw_dbg_trigger_tlv *trigger) 962 { 963 unsigned int delay = 0; 964 965 if (trigger) 966 delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay)); 967 968 /* 969 * If the loading of the FW completed successfully, the next step is to 970 * get the SMEM config data. Thus, if fwrt->smem_cfg.num_lmacs is non 971 * zero, the FW was already loaded successully. If the state is "NO_FW" 972 * in such a case - WARN and exit, since FW may be dead. Otherwise, we 973 * can try to collect the data, since FW might just not be fully 974 * loaded (no "ALIVE" yet), and the debug data is accessible. 975 * 976 * Corner case: got the FW alive but crashed before getting the SMEM 977 * config. In such a case, due to HW access problems, we might 978 * collect garbage. 979 */ 980 if (WARN((fwrt->trans->state == IWL_TRANS_NO_FW) && 981 fwrt->smem_cfg.num_lmacs, 982 "Can't collect dbg data when FW isn't alive\n")) 983 return -EIO; 984 985 if (test_and_set_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status)) 986 return -EBUSY; 987 988 if (WARN_ON(fwrt->dump.desc)) 989 iwl_fw_free_dump_desc(fwrt); 990 991 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 992 le32_to_cpu(desc->trig_desc.type)); 993 994 fwrt->dump.desc = desc; 995 fwrt->dump.trig = trigger; 996 997 schedule_delayed_work(&fwrt->dump.wk, delay); 998 999 return 0; 1000 } 1001 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 1002 1003 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 1004 enum iwl_fw_dbg_trigger trig, 1005 const char *str, size_t len, 1006 const struct iwl_fw_dbg_trigger_tlv *trigger) 1007 { 1008 struct iwl_fw_dump_desc *desc; 1009 1010 desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC); 1011 if (!desc) 1012 return -ENOMEM; 1013 1014 desc->len = len; 1015 desc->trig_desc.type = cpu_to_le32(trig); 1016 memcpy(desc->trig_desc.data, str, len); 1017 1018 return iwl_fw_dbg_collect_desc(fwrt, desc, trigger); 1019 } 1020 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 1021 1022 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 1023 struct iwl_fw_dbg_trigger_tlv *trigger, 1024 const char *fmt, ...) 1025 { 1026 u16 occurrences = le16_to_cpu(trigger->occurrences); 1027 int ret, len = 0; 1028 char buf[64]; 1029 1030 if (!occurrences) 1031 return 0; 1032 1033 if (fmt) { 1034 va_list ap; 1035 1036 buf[sizeof(buf) - 1] = '\0'; 1037 1038 va_start(ap, fmt); 1039 vsnprintf(buf, sizeof(buf), fmt, ap); 1040 va_end(ap); 1041 1042 /* check for truncation */ 1043 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 1044 buf[sizeof(buf) - 1] = '\0'; 1045 1046 len = strlen(buf) + 1; 1047 } 1048 1049 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 1050 trigger); 1051 1052 if (ret) 1053 return ret; 1054 1055 trigger->occurrences = cpu_to_le16(occurrences - 1); 1056 return 0; 1057 } 1058 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 1059 1060 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 1061 { 1062 u8 *ptr; 1063 int ret; 1064 int i; 1065 1066 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg_conf_tlv), 1067 "Invalid configuration %d\n", conf_id)) 1068 return -EINVAL; 1069 1070 /* EARLY START - firmware's configuration is hard coded */ 1071 if ((!fwrt->fw->dbg_conf_tlv[conf_id] || 1072 !fwrt->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) && 1073 conf_id == FW_DBG_START_FROM_ALIVE) 1074 return 0; 1075 1076 if (!fwrt->fw->dbg_conf_tlv[conf_id]) 1077 return -EINVAL; 1078 1079 if (fwrt->dump.conf != FW_DBG_INVALID) 1080 IWL_WARN(fwrt, "FW already configured (%d) - re-configuring\n", 1081 fwrt->dump.conf); 1082 1083 /* Send all HCMDs for configuring the FW debug */ 1084 ptr = (void *)&fwrt->fw->dbg_conf_tlv[conf_id]->hcmd; 1085 for (i = 0; i < fwrt->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) { 1086 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 1087 struct iwl_host_cmd hcmd = { 1088 .id = cmd->id, 1089 .len = { le16_to_cpu(cmd->len), }, 1090 .data = { cmd->data, }, 1091 }; 1092 1093 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 1094 if (ret) 1095 return ret; 1096 1097 ptr += sizeof(*cmd); 1098 ptr += le16_to_cpu(cmd->len); 1099 } 1100 1101 fwrt->dump.conf = conf_id; 1102 1103 return 0; 1104 } 1105 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 1106 1107 void iwl_fw_error_dump_wk(struct work_struct *work) 1108 { 1109 struct iwl_fw_runtime *fwrt = 1110 container_of(work, struct iwl_fw_runtime, dump.wk.work); 1111 1112 if (fwrt->ops && fwrt->ops->dump_start && 1113 fwrt->ops->dump_start(fwrt->ops_ctx)) 1114 return; 1115 1116 if (fwrt->ops && fwrt->ops->fw_running && 1117 !fwrt->ops->fw_running(fwrt->ops_ctx)) { 1118 IWL_ERR(fwrt, "Firmware not running - cannot dump error\n"); 1119 iwl_fw_free_dump_desc(fwrt); 1120 clear_bit(IWL_FWRT_STATUS_DUMPING, &fwrt->status); 1121 goto out; 1122 } 1123 1124 if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1125 /* stop recording */ 1126 iwl_fw_dbg_stop_recording(fwrt); 1127 1128 iwl_fw_error_dump(fwrt); 1129 1130 /* start recording again if the firmware is not crashed */ 1131 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && 1132 fwrt->fw->dbg_dest_tlv) { 1133 iwl_clear_bits_prph(fwrt->trans, 1134 MON_BUFF_SAMPLE_CTL, 0x100); 1135 iwl_clear_bits_prph(fwrt->trans, 1136 MON_BUFF_SAMPLE_CTL, 0x1); 1137 iwl_set_bits_prph(fwrt->trans, 1138 MON_BUFF_SAMPLE_CTL, 0x1); 1139 } 1140 } else { 1141 u32 in_sample = iwl_read_prph(fwrt->trans, DBGC_IN_SAMPLE); 1142 u32 out_ctrl = iwl_read_prph(fwrt->trans, DBGC_OUT_CTRL); 1143 1144 iwl_fw_dbg_stop_recording(fwrt); 1145 /* wait before we collect the data till the DBGC stop */ 1146 udelay(500); 1147 1148 iwl_fw_error_dump(fwrt); 1149 1150 /* start recording again if the firmware is not crashed */ 1151 if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) && 1152 fwrt->fw->dbg_dest_tlv) { 1153 iwl_write_prph(fwrt->trans, DBGC_IN_SAMPLE, in_sample); 1154 iwl_write_prph(fwrt->trans, DBGC_OUT_CTRL, out_ctrl); 1155 } 1156 } 1157 out: 1158 if (fwrt->ops && fwrt->ops->dump_end) 1159 fwrt->ops->dump_end(fwrt->ops_ctx); 1160 } 1161 1162