1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "iwl-fh.h" 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @fwrt_len: length of the valid data in fwrt_ptr 23 */ 24 struct iwl_fw_dump_ptrs { 25 struct iwl_trans_dump_data *trans_ptr; 26 void *fwrt_ptr; 27 u32 fwrt_len; 28 }; 29 30 #define RADIO_REG_MAX_READ 0x2ad 31 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 32 struct iwl_fw_error_dump_data **dump_data) 33 { 34 u8 *pos = (void *)(*dump_data)->data; 35 int i; 36 37 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 38 39 if (!iwl_trans_grab_nic_access(fwrt->trans)) 40 return; 41 42 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 43 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 44 45 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 46 u32 rd_cmd = RADIO_RSP_RD_CMD; 47 48 rd_cmd |= i << RADIO_RSP_ADDR_POS; 49 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 50 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 51 52 pos++; 53 } 54 55 *dump_data = iwl_fw_error_next_data(*dump_data); 56 57 iwl_trans_release_nic_access(fwrt->trans); 58 } 59 60 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 61 struct iwl_fw_error_dump_data **dump_data, 62 int size, u32 offset, int fifo_num) 63 { 64 struct iwl_fw_error_dump_fifo *fifo_hdr; 65 u32 *fifo_data; 66 u32 fifo_len; 67 int i; 68 69 fifo_hdr = (void *)(*dump_data)->data; 70 fifo_data = (void *)fifo_hdr->data; 71 fifo_len = size; 72 73 /* No need to try to read the data if the length is 0 */ 74 if (fifo_len == 0) 75 return; 76 77 /* Add a TLV for the RXF */ 78 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 79 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 80 81 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 82 fifo_hdr->available_bytes = 83 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 84 RXF_RD_D_SPACE + offset)); 85 fifo_hdr->wr_ptr = 86 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 87 RXF_RD_WR_PTR + offset)); 88 fifo_hdr->rd_ptr = 89 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 90 RXF_RD_RD_PTR + offset)); 91 fifo_hdr->fence_ptr = 92 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 93 RXF_RD_FENCE_PTR + offset)); 94 fifo_hdr->fence_mode = 95 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 96 RXF_SET_FENCE_MODE + offset)); 97 98 /* Lock fence */ 99 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 100 /* Set fence pointer to the same place like WR pointer */ 101 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 102 /* Set fence offset */ 103 iwl_trans_write_prph(fwrt->trans, 104 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 105 106 /* Read FIFO */ 107 fifo_len /= sizeof(u32); /* Size in DWORDS */ 108 for (i = 0; i < fifo_len; i++) 109 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 110 RXF_FIFO_RD_FENCE_INC + 111 offset); 112 *dump_data = iwl_fw_error_next_data(*dump_data); 113 } 114 115 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 116 struct iwl_fw_error_dump_data **dump_data, 117 int size, u32 offset, int fifo_num) 118 { 119 struct iwl_fw_error_dump_fifo *fifo_hdr; 120 u32 *fifo_data; 121 u32 fifo_len; 122 int i; 123 124 fifo_hdr = (void *)(*dump_data)->data; 125 fifo_data = (void *)fifo_hdr->data; 126 fifo_len = size; 127 128 /* No need to try to read the data if the length is 0 */ 129 if (fifo_len == 0) 130 return; 131 132 /* Add a TLV for the FIFO */ 133 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 134 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 135 136 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 137 fifo_hdr->available_bytes = 138 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 139 TXF_FIFO_ITEM_CNT + offset)); 140 fifo_hdr->wr_ptr = 141 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 142 TXF_WR_PTR + offset)); 143 fifo_hdr->rd_ptr = 144 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 145 TXF_RD_PTR + offset)); 146 fifo_hdr->fence_ptr = 147 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 148 TXF_FENCE_PTR + offset)); 149 fifo_hdr->fence_mode = 150 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 151 TXF_LOCK_FENCE + offset)); 152 153 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 154 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 155 TXF_WR_PTR + offset); 156 157 /* Dummy-read to advance the read pointer to the head */ 158 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 159 160 /* Read FIFO */ 161 for (i = 0; i < fifo_len / sizeof(u32); i++) 162 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 163 TXF_READ_MODIFY_DATA + 164 offset); 165 166 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 167 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 168 fifo_data, fifo_len); 169 170 *dump_data = iwl_fw_error_next_data(*dump_data); 171 } 172 173 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 174 struct iwl_fw_error_dump_data **dump_data) 175 { 176 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 177 178 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 179 180 if (!iwl_trans_grab_nic_access(fwrt->trans)) 181 return; 182 183 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 184 /* Pull RXF1 */ 185 iwl_fwrt_dump_rxf(fwrt, dump_data, 186 cfg->lmac[0].rxfifo1_size, 0, 0); 187 /* Pull RXF2 */ 188 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 189 RXF_DIFF_FROM_PREV + 190 fwrt->trans->trans_cfg->umac_prph_offset, 1); 191 /* Pull LMAC2 RXF1 */ 192 if (fwrt->smem_cfg.num_lmacs > 1) 193 iwl_fwrt_dump_rxf(fwrt, dump_data, 194 cfg->lmac[1].rxfifo1_size, 195 LMAC2_PRPH_OFFSET, 2); 196 } 197 198 iwl_trans_release_nic_access(fwrt->trans); 199 } 200 201 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 202 struct iwl_fw_error_dump_data **dump_data) 203 { 204 struct iwl_fw_error_dump_fifo *fifo_hdr; 205 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 206 u32 *fifo_data; 207 u32 fifo_len; 208 int i, j; 209 210 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 211 212 if (!iwl_trans_grab_nic_access(fwrt->trans)) 213 return; 214 215 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 216 /* Pull TXF data from LMAC1 */ 217 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 218 /* Mark the number of TXF we're pulling now */ 219 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 220 iwl_fwrt_dump_txf(fwrt, dump_data, 221 cfg->lmac[0].txfifo_size[i], 0, i); 222 } 223 224 /* Pull TXF data from LMAC2 */ 225 if (fwrt->smem_cfg.num_lmacs > 1) { 226 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 227 i++) { 228 /* Mark the number of TXF we're pulling now */ 229 iwl_trans_write_prph(fwrt->trans, 230 TXF_LARC_NUM + 231 LMAC2_PRPH_OFFSET, i); 232 iwl_fwrt_dump_txf(fwrt, dump_data, 233 cfg->lmac[1].txfifo_size[i], 234 LMAC2_PRPH_OFFSET, 235 i + cfg->num_txfifo_entries); 236 } 237 } 238 } 239 240 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 241 fw_has_capa(&fwrt->fw->ucode_capa, 242 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 243 /* Pull UMAC internal TXF data from all TXFs */ 244 for (i = 0; 245 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 246 i++) { 247 fifo_hdr = (void *)(*dump_data)->data; 248 fifo_data = (void *)fifo_hdr->data; 249 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 250 251 /* No need to try to read the data if the length is 0 */ 252 if (fifo_len == 0) 253 continue; 254 255 /* Add a TLV for the internal FIFOs */ 256 (*dump_data)->type = 257 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 258 (*dump_data)->len = 259 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 260 261 fifo_hdr->fifo_num = cpu_to_le32(i); 262 263 /* Mark the number of TXF we're pulling now */ 264 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 265 fwrt->smem_cfg.num_txfifo_entries); 266 267 fifo_hdr->available_bytes = 268 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 269 TXF_CPU2_FIFO_ITEM_CNT)); 270 fifo_hdr->wr_ptr = 271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 272 TXF_CPU2_WR_PTR)); 273 fifo_hdr->rd_ptr = 274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 275 TXF_CPU2_RD_PTR)); 276 fifo_hdr->fence_ptr = 277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 278 TXF_CPU2_FENCE_PTR)); 279 fifo_hdr->fence_mode = 280 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 281 TXF_CPU2_LOCK_FENCE)); 282 283 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 284 iwl_trans_write_prph(fwrt->trans, 285 TXF_CPU2_READ_MODIFY_ADDR, 286 TXF_CPU2_WR_PTR); 287 288 /* Dummy-read to advance the read pointer to head */ 289 iwl_trans_read_prph(fwrt->trans, 290 TXF_CPU2_READ_MODIFY_DATA); 291 292 /* Read FIFO */ 293 fifo_len /= sizeof(u32); /* Size in DWORDS */ 294 for (j = 0; j < fifo_len; j++) 295 fifo_data[j] = 296 iwl_trans_read_prph(fwrt->trans, 297 TXF_CPU2_READ_MODIFY_DATA); 298 *dump_data = iwl_fw_error_next_data(*dump_data); 299 } 300 } 301 302 iwl_trans_release_nic_access(fwrt->trans); 303 } 304 305 struct iwl_prph_range { 306 u32 start, end; 307 }; 308 309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 310 { .start = 0x00a00000, .end = 0x00a00000 }, 311 { .start = 0x00a0000c, .end = 0x00a00024 }, 312 { .start = 0x00a0002c, .end = 0x00a0003c }, 313 { .start = 0x00a00410, .end = 0x00a00418 }, 314 { .start = 0x00a00420, .end = 0x00a00420 }, 315 { .start = 0x00a00428, .end = 0x00a00428 }, 316 { .start = 0x00a00430, .end = 0x00a0043c }, 317 { .start = 0x00a00444, .end = 0x00a00444 }, 318 { .start = 0x00a004c0, .end = 0x00a004cc }, 319 { .start = 0x00a004d8, .end = 0x00a004d8 }, 320 { .start = 0x00a004e0, .end = 0x00a004f0 }, 321 { .start = 0x00a00840, .end = 0x00a00840 }, 322 { .start = 0x00a00850, .end = 0x00a00858 }, 323 { .start = 0x00a01004, .end = 0x00a01008 }, 324 { .start = 0x00a01010, .end = 0x00a01010 }, 325 { .start = 0x00a01018, .end = 0x00a01018 }, 326 { .start = 0x00a01024, .end = 0x00a01024 }, 327 { .start = 0x00a0102c, .end = 0x00a01034 }, 328 { .start = 0x00a0103c, .end = 0x00a01040 }, 329 { .start = 0x00a01048, .end = 0x00a01094 }, 330 { .start = 0x00a01c00, .end = 0x00a01c20 }, 331 { .start = 0x00a01c58, .end = 0x00a01c58 }, 332 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 333 { .start = 0x00a01c28, .end = 0x00a01c54 }, 334 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 335 { .start = 0x00a01c60, .end = 0x00a01cdc }, 336 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 337 { .start = 0x00a01d18, .end = 0x00a01d20 }, 338 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 339 { .start = 0x00a01d40, .end = 0x00a01d5c }, 340 { .start = 0x00a01d80, .end = 0x00a01d80 }, 341 { .start = 0x00a01d98, .end = 0x00a01d9c }, 342 { .start = 0x00a01da8, .end = 0x00a01da8 }, 343 { .start = 0x00a01db8, .end = 0x00a01df4 }, 344 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 345 { .start = 0x00a01e00, .end = 0x00a01e2c }, 346 { .start = 0x00a01e40, .end = 0x00a01e60 }, 347 { .start = 0x00a01e68, .end = 0x00a01e6c }, 348 { .start = 0x00a01e74, .end = 0x00a01e74 }, 349 { .start = 0x00a01e84, .end = 0x00a01e90 }, 350 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 351 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 352 { .start = 0x00a01f00, .end = 0x00a01f1c }, 353 { .start = 0x00a01f44, .end = 0x00a01ffc }, 354 { .start = 0x00a02000, .end = 0x00a02048 }, 355 { .start = 0x00a02068, .end = 0x00a020f0 }, 356 { .start = 0x00a02100, .end = 0x00a02118 }, 357 { .start = 0x00a02140, .end = 0x00a0214c }, 358 { .start = 0x00a02168, .end = 0x00a0218c }, 359 { .start = 0x00a021c0, .end = 0x00a021c0 }, 360 { .start = 0x00a02400, .end = 0x00a02410 }, 361 { .start = 0x00a02418, .end = 0x00a02420 }, 362 { .start = 0x00a02428, .end = 0x00a0242c }, 363 { .start = 0x00a02434, .end = 0x00a02434 }, 364 { .start = 0x00a02440, .end = 0x00a02460 }, 365 { .start = 0x00a02468, .end = 0x00a024b0 }, 366 { .start = 0x00a024c8, .end = 0x00a024cc }, 367 { .start = 0x00a02500, .end = 0x00a02504 }, 368 { .start = 0x00a0250c, .end = 0x00a02510 }, 369 { .start = 0x00a02540, .end = 0x00a02554 }, 370 { .start = 0x00a02580, .end = 0x00a025f4 }, 371 { .start = 0x00a02600, .end = 0x00a0260c }, 372 { .start = 0x00a02648, .end = 0x00a02650 }, 373 { .start = 0x00a02680, .end = 0x00a02680 }, 374 { .start = 0x00a026c0, .end = 0x00a026d0 }, 375 { .start = 0x00a02700, .end = 0x00a0270c }, 376 { .start = 0x00a02804, .end = 0x00a02804 }, 377 { .start = 0x00a02818, .end = 0x00a0281c }, 378 { .start = 0x00a02c00, .end = 0x00a02db4 }, 379 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 380 { .start = 0x00a03000, .end = 0x00a03014 }, 381 { .start = 0x00a0301c, .end = 0x00a0302c }, 382 { .start = 0x00a03034, .end = 0x00a03038 }, 383 { .start = 0x00a03040, .end = 0x00a03048 }, 384 { .start = 0x00a03060, .end = 0x00a03068 }, 385 { .start = 0x00a03070, .end = 0x00a03074 }, 386 { .start = 0x00a0307c, .end = 0x00a0307c }, 387 { .start = 0x00a03080, .end = 0x00a03084 }, 388 { .start = 0x00a0308c, .end = 0x00a03090 }, 389 { .start = 0x00a03098, .end = 0x00a03098 }, 390 { .start = 0x00a030a0, .end = 0x00a030a0 }, 391 { .start = 0x00a030a8, .end = 0x00a030b4 }, 392 { .start = 0x00a030bc, .end = 0x00a030bc }, 393 { .start = 0x00a030c0, .end = 0x00a0312c }, 394 { .start = 0x00a03c00, .end = 0x00a03c5c }, 395 { .start = 0x00a04400, .end = 0x00a04454 }, 396 { .start = 0x00a04460, .end = 0x00a04474 }, 397 { .start = 0x00a044c0, .end = 0x00a044ec }, 398 { .start = 0x00a04500, .end = 0x00a04504 }, 399 { .start = 0x00a04510, .end = 0x00a04538 }, 400 { .start = 0x00a04540, .end = 0x00a04548 }, 401 { .start = 0x00a04560, .end = 0x00a0457c }, 402 { .start = 0x00a04590, .end = 0x00a04598 }, 403 { .start = 0x00a045c0, .end = 0x00a045f4 }, 404 }; 405 406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 407 { .start = 0x00a05c00, .end = 0x00a05c18 }, 408 { .start = 0x00a05400, .end = 0x00a056e8 }, 409 { .start = 0x00a08000, .end = 0x00a098bc }, 410 { .start = 0x00a02400, .end = 0x00a02758 }, 411 { .start = 0x00a04764, .end = 0x00a0476c }, 412 { .start = 0x00a04770, .end = 0x00a04774 }, 413 { .start = 0x00a04620, .end = 0x00a04624 }, 414 }; 415 416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 417 { .start = 0x00a00000, .end = 0x00a00000 }, 418 { .start = 0x00a0000c, .end = 0x00a00024 }, 419 { .start = 0x00a0002c, .end = 0x00a00034 }, 420 { .start = 0x00a0003c, .end = 0x00a0003c }, 421 { .start = 0x00a00410, .end = 0x00a00418 }, 422 { .start = 0x00a00420, .end = 0x00a00420 }, 423 { .start = 0x00a00428, .end = 0x00a00428 }, 424 { .start = 0x00a00430, .end = 0x00a0043c }, 425 { .start = 0x00a00444, .end = 0x00a00444 }, 426 { .start = 0x00a00840, .end = 0x00a00840 }, 427 { .start = 0x00a00850, .end = 0x00a00858 }, 428 { .start = 0x00a01004, .end = 0x00a01008 }, 429 { .start = 0x00a01010, .end = 0x00a01010 }, 430 { .start = 0x00a01018, .end = 0x00a01018 }, 431 { .start = 0x00a01024, .end = 0x00a01024 }, 432 { .start = 0x00a0102c, .end = 0x00a01034 }, 433 { .start = 0x00a0103c, .end = 0x00a01040 }, 434 { .start = 0x00a01048, .end = 0x00a01050 }, 435 { .start = 0x00a01058, .end = 0x00a01058 }, 436 { .start = 0x00a01060, .end = 0x00a01070 }, 437 { .start = 0x00a0108c, .end = 0x00a0108c }, 438 { .start = 0x00a01c20, .end = 0x00a01c28 }, 439 { .start = 0x00a01d10, .end = 0x00a01d10 }, 440 { .start = 0x00a01e28, .end = 0x00a01e2c }, 441 { .start = 0x00a01e60, .end = 0x00a01e60 }, 442 { .start = 0x00a01e80, .end = 0x00a01e80 }, 443 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 444 { .start = 0x00a02000, .end = 0x00a0201c }, 445 { .start = 0x00a02024, .end = 0x00a02024 }, 446 { .start = 0x00a02040, .end = 0x00a02048 }, 447 { .start = 0x00a020c0, .end = 0x00a020e0 }, 448 { .start = 0x00a02400, .end = 0x00a02404 }, 449 { .start = 0x00a0240c, .end = 0x00a02414 }, 450 { .start = 0x00a0241c, .end = 0x00a0243c }, 451 { .start = 0x00a02448, .end = 0x00a024bc }, 452 { .start = 0x00a024c4, .end = 0x00a024cc }, 453 { .start = 0x00a02508, .end = 0x00a02508 }, 454 { .start = 0x00a02510, .end = 0x00a02514 }, 455 { .start = 0x00a0251c, .end = 0x00a0251c }, 456 { .start = 0x00a0252c, .end = 0x00a0255c }, 457 { .start = 0x00a02564, .end = 0x00a025a0 }, 458 { .start = 0x00a025a8, .end = 0x00a025b4 }, 459 { .start = 0x00a025c0, .end = 0x00a025c0 }, 460 { .start = 0x00a025e8, .end = 0x00a025f4 }, 461 { .start = 0x00a02c08, .end = 0x00a02c18 }, 462 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 463 { .start = 0x00a02c68, .end = 0x00a02c78 }, 464 { .start = 0x00a03000, .end = 0x00a03000 }, 465 { .start = 0x00a03010, .end = 0x00a03014 }, 466 { .start = 0x00a0301c, .end = 0x00a0302c }, 467 { .start = 0x00a03034, .end = 0x00a03038 }, 468 { .start = 0x00a03040, .end = 0x00a03044 }, 469 { .start = 0x00a03060, .end = 0x00a03068 }, 470 { .start = 0x00a03070, .end = 0x00a03070 }, 471 { .start = 0x00a0307c, .end = 0x00a03084 }, 472 { .start = 0x00a0308c, .end = 0x00a03090 }, 473 { .start = 0x00a03098, .end = 0x00a03098 }, 474 { .start = 0x00a030a0, .end = 0x00a030a0 }, 475 { .start = 0x00a030a8, .end = 0x00a030b4 }, 476 { .start = 0x00a030bc, .end = 0x00a030c0 }, 477 { .start = 0x00a030c8, .end = 0x00a030f4 }, 478 { .start = 0x00a03100, .end = 0x00a0312c }, 479 { .start = 0x00a03c00, .end = 0x00a03c5c }, 480 { .start = 0x00a04400, .end = 0x00a04454 }, 481 { .start = 0x00a04460, .end = 0x00a04474 }, 482 { .start = 0x00a044c0, .end = 0x00a044ec }, 483 { .start = 0x00a04500, .end = 0x00a04504 }, 484 { .start = 0x00a04510, .end = 0x00a04538 }, 485 { .start = 0x00a04540, .end = 0x00a04548 }, 486 { .start = 0x00a04560, .end = 0x00a04560 }, 487 { .start = 0x00a04570, .end = 0x00a0457c }, 488 { .start = 0x00a04590, .end = 0x00a04590 }, 489 { .start = 0x00a04598, .end = 0x00a04598 }, 490 { .start = 0x00a045c0, .end = 0x00a045f4 }, 491 { .start = 0x00a05c18, .end = 0x00a05c1c }, 492 { .start = 0x00a0c000, .end = 0x00a0c018 }, 493 { .start = 0x00a0c020, .end = 0x00a0c028 }, 494 { .start = 0x00a0c038, .end = 0x00a0c094 }, 495 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 496 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 497 { .start = 0x00a0c150, .end = 0x00a0c174 }, 498 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 499 { .start = 0x00a0c190, .end = 0x00a0c198 }, 500 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 501 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 502 }; 503 504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 505 { .start = 0x00d03c00, .end = 0x00d03c64 }, 506 { .start = 0x00d05c18, .end = 0x00d05c1c }, 507 { .start = 0x00d0c000, .end = 0x00d0c174 }, 508 }; 509 510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 511 u32 len_bytes, __le32 *data) 512 { 513 u32 i; 514 515 for (i = 0; i < len_bytes; i += 4) 516 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 517 } 518 519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 520 const struct iwl_prph_range *iwl_prph_dump_addr, 521 u32 range_len, void *ptr) 522 { 523 struct iwl_fw_error_dump_prph *prph; 524 struct iwl_trans *trans = fwrt->trans; 525 struct iwl_fw_error_dump_data **data = 526 (struct iwl_fw_error_dump_data **)ptr; 527 u32 i; 528 529 if (!data) 530 return; 531 532 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 533 534 if (!iwl_trans_grab_nic_access(trans)) 535 return; 536 537 for (i = 0; i < range_len; i++) { 538 /* The range includes both boundaries */ 539 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 540 iwl_prph_dump_addr[i].start + 4; 541 542 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 543 (*data)->len = cpu_to_le32(sizeof(*prph) + 544 num_bytes_in_chunk); 545 prph = (void *)(*data)->data; 546 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 547 548 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 549 /* our range is inclusive, hence + 4 */ 550 iwl_prph_dump_addr[i].end - 551 iwl_prph_dump_addr[i].start + 4, 552 (void *)prph->data); 553 554 *data = iwl_fw_error_next_data(*data); 555 } 556 557 iwl_trans_release_nic_access(trans); 558 } 559 560 /* 561 * alloc_sgtable - allocates scallerlist table in the given size, 562 * fills it with pages and returns it 563 * @size: the size (in bytes) of the table 564 */ 565 static struct scatterlist *alloc_sgtable(int size) 566 { 567 int alloc_size, nents, i; 568 struct page *new_page; 569 struct scatterlist *iter; 570 struct scatterlist *table; 571 572 nents = DIV_ROUND_UP(size, PAGE_SIZE); 573 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 574 if (!table) 575 return NULL; 576 sg_init_table(table, nents); 577 iter = table; 578 for_each_sg(table, iter, sg_nents(table), i) { 579 new_page = alloc_page(GFP_KERNEL); 580 if (!new_page) { 581 /* release all previous allocated pages in the table */ 582 iter = table; 583 for_each_sg(table, iter, sg_nents(table), i) { 584 new_page = sg_page(iter); 585 if (new_page) 586 __free_page(new_page); 587 } 588 kfree(table); 589 return NULL; 590 } 591 alloc_size = min_t(int, size, PAGE_SIZE); 592 size -= PAGE_SIZE; 593 sg_set_page(iter, new_page, alloc_size, 0); 594 } 595 return table; 596 } 597 598 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 599 const struct iwl_prph_range *iwl_prph_dump_addr, 600 u32 range_len, void *ptr) 601 { 602 u32 *prph_len = (u32 *)ptr; 603 int i, num_bytes_in_chunk; 604 605 if (!prph_len) 606 return; 607 608 for (i = 0; i < range_len; i++) { 609 /* The range includes both boundaries */ 610 num_bytes_in_chunk = 611 iwl_prph_dump_addr[i].end - 612 iwl_prph_dump_addr[i].start + 4; 613 614 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 615 sizeof(struct iwl_fw_error_dump_prph) + 616 num_bytes_in_chunk; 617 } 618 } 619 620 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 621 void (*handler)(struct iwl_fw_runtime *, 622 const struct iwl_prph_range *, 623 u32, void *)) 624 { 625 u32 range_len; 626 627 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 628 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 629 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 630 } else if (fwrt->trans->trans_cfg->device_family >= 631 IWL_DEVICE_FAMILY_22000) { 632 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 633 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 634 } else { 635 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 636 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 637 638 if (fwrt->trans->trans_cfg->mq_rx_supported) { 639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 640 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 641 } 642 } 643 } 644 645 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 646 struct iwl_fw_error_dump_data **dump_data, 647 u32 len, u32 ofs, u32 type) 648 { 649 struct iwl_fw_error_dump_mem *dump_mem; 650 651 if (!len) 652 return; 653 654 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 655 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 656 dump_mem = (void *)(*dump_data)->data; 657 dump_mem->type = cpu_to_le32(type); 658 dump_mem->offset = cpu_to_le32(ofs); 659 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 660 *dump_data = iwl_fw_error_next_data(*dump_data); 661 662 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 663 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 664 dump_mem->data, len); 665 666 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 667 } 668 669 #define ADD_LEN(len, item_len, const_len) \ 670 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 671 while (0) 672 673 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 674 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 675 { 676 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 677 sizeof(struct iwl_fw_error_dump_fifo); 678 u32 fifo_len = 0; 679 int i; 680 681 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 682 return 0; 683 684 /* Count RXF2 size */ 685 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 686 687 /* Count RXF1 sizes */ 688 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 689 mem_cfg->num_lmacs = MAX_NUM_LMAC; 690 691 for (i = 0; i < mem_cfg->num_lmacs; i++) 692 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 693 694 return fifo_len; 695 } 696 697 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 698 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 699 { 700 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 701 sizeof(struct iwl_fw_error_dump_fifo); 702 u32 fifo_len = 0; 703 int i; 704 705 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 706 goto dump_internal_txf; 707 708 /* Count TXF sizes */ 709 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 710 mem_cfg->num_lmacs = MAX_NUM_LMAC; 711 712 for (i = 0; i < mem_cfg->num_lmacs; i++) { 713 int j; 714 715 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 716 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 717 hdr_len); 718 } 719 720 dump_internal_txf: 721 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 722 fw_has_capa(&fwrt->fw->ucode_capa, 723 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 724 goto out; 725 726 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 727 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 728 729 out: 730 return fifo_len; 731 } 732 733 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 734 struct iwl_fw_error_dump_data **data) 735 { 736 int i; 737 738 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 739 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 740 struct iwl_fw_error_dump_paging *paging; 741 struct page *pages = 742 fwrt->fw_paging_db[i].fw_paging_block; 743 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 744 745 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 746 (*data)->len = cpu_to_le32(sizeof(*paging) + 747 PAGING_BLOCK_SIZE); 748 paging = (void *)(*data)->data; 749 paging->index = cpu_to_le32(i); 750 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 751 PAGING_BLOCK_SIZE, 752 DMA_BIDIRECTIONAL); 753 memcpy(paging->data, page_address(pages), 754 PAGING_BLOCK_SIZE); 755 dma_sync_single_for_device(fwrt->trans->dev, addr, 756 PAGING_BLOCK_SIZE, 757 DMA_BIDIRECTIONAL); 758 (*data) = iwl_fw_error_next_data(*data); 759 760 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 761 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 762 fwrt->fw_paging_db[i].fw_offs, 763 paging->data, 764 PAGING_BLOCK_SIZE); 765 } 766 } 767 768 static struct iwl_fw_error_dump_file * 769 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 770 struct iwl_fw_dump_ptrs *fw_error_dump, 771 struct iwl_fwrt_dump_data *data) 772 { 773 struct iwl_fw_error_dump_file *dump_file; 774 struct iwl_fw_error_dump_data *dump_data; 775 struct iwl_fw_error_dump_info *dump_info; 776 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 777 struct iwl_fw_error_dump_trigger_desc *dump_trig; 778 u32 sram_len, sram_ofs; 779 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 780 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 781 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 782 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 783 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 784 0 : fwrt->trans->cfg->dccm2_len; 785 int i; 786 787 /* SRAM - include stack CCM if driver knows the values for it */ 788 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 789 const struct fw_img *img; 790 791 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 792 return NULL; 793 img = &fwrt->fw->img[fwrt->cur_fw_img]; 794 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 795 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 796 } else { 797 sram_ofs = fwrt->trans->cfg->dccm_offset; 798 sram_len = fwrt->trans->cfg->dccm_len; 799 } 800 801 /* reading RXF/TXF sizes */ 802 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 803 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 804 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 805 806 /* Make room for PRPH registers */ 807 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 808 iwl_fw_prph_handler(fwrt, &prph_len, 809 iwl_fw_get_prph_len); 810 811 if (fwrt->trans->trans_cfg->device_family == 812 IWL_DEVICE_FAMILY_7000 && 813 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 814 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 815 } 816 817 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 818 819 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 820 file_len += sizeof(*dump_data) + sizeof(*dump_info); 821 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 822 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 823 824 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 825 size_t hdr_len = sizeof(*dump_data) + 826 sizeof(struct iwl_fw_error_dump_mem); 827 828 /* Dump SRAM only if no mem_tlvs */ 829 if (!fwrt->fw->dbg.n_mem_tlv) 830 ADD_LEN(file_len, sram_len, hdr_len); 831 832 /* Make room for all mem types that exist */ 833 ADD_LEN(file_len, smem_len, hdr_len); 834 ADD_LEN(file_len, sram2_len, hdr_len); 835 836 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 837 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 838 } 839 840 /* Make room for fw's virtual image pages, if it exists */ 841 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 842 file_len += fwrt->num_of_paging_blk * 843 (sizeof(*dump_data) + 844 sizeof(struct iwl_fw_error_dump_paging) + 845 PAGING_BLOCK_SIZE); 846 847 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 848 file_len += sizeof(*dump_data) + 849 fwrt->trans->cfg->d3_debug_data_length * 2; 850 } 851 852 /* If we only want a monitor dump, reset the file length */ 853 if (data->monitor_only) { 854 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 855 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 856 } 857 858 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 859 data->desc) 860 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 861 data->desc->len; 862 863 dump_file = vzalloc(file_len); 864 if (!dump_file) 865 return NULL; 866 867 fw_error_dump->fwrt_ptr = dump_file; 868 869 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 870 dump_data = (void *)dump_file->data; 871 872 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 873 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 874 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 875 dump_info = (void *)dump_data->data; 876 dump_info->hw_type = 877 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 878 dump_info->hw_step = 879 cpu_to_le32(fwrt->trans->hw_rev_step); 880 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 881 sizeof(dump_info->fw_human_readable)); 882 strscpy_pad(dump_info->dev_human_readable, fwrt->trans->name, 883 sizeof(dump_info->dev_human_readable)); 884 strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name, 885 sizeof(dump_info->bus_human_readable)); 886 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 887 dump_info->lmac_err_id[0] = 888 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 889 if (fwrt->smem_cfg.num_lmacs > 1) 890 dump_info->lmac_err_id[1] = 891 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 892 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 893 894 dump_data = iwl_fw_error_next_data(dump_data); 895 } 896 897 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 898 /* Dump shared memory configuration */ 899 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 900 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 901 dump_smem_cfg = (void *)dump_data->data; 902 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 903 dump_smem_cfg->num_txfifo_entries = 904 cpu_to_le32(mem_cfg->num_txfifo_entries); 905 for (i = 0; i < MAX_NUM_LMAC; i++) { 906 int j; 907 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 908 909 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 910 dump_smem_cfg->lmac[i].txfifo_size[j] = 911 cpu_to_le32(txf_size[j]); 912 dump_smem_cfg->lmac[i].rxfifo1_size = 913 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 914 } 915 dump_smem_cfg->rxfifo2_size = 916 cpu_to_le32(mem_cfg->rxfifo2_size); 917 dump_smem_cfg->internal_txfifo_addr = 918 cpu_to_le32(mem_cfg->internal_txfifo_addr); 919 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 920 dump_smem_cfg->internal_txfifo_size[i] = 921 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 922 } 923 924 dump_data = iwl_fw_error_next_data(dump_data); 925 } 926 927 /* We only dump the FIFOs if the FW is in error state */ 928 if (fifo_len) { 929 iwl_fw_dump_rxf(fwrt, &dump_data); 930 iwl_fw_dump_txf(fwrt, &dump_data); 931 } 932 933 if (radio_len) 934 iwl_read_radio_regs(fwrt, &dump_data); 935 936 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 937 data->desc) { 938 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 939 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 940 data->desc->len); 941 dump_trig = (void *)dump_data->data; 942 memcpy(dump_trig, &data->desc->trig_desc, 943 sizeof(*dump_trig) + data->desc->len); 944 945 dump_data = iwl_fw_error_next_data(dump_data); 946 } 947 948 /* In case we only want monitor dump, skip to dump trasport data */ 949 if (data->monitor_only) 950 goto out; 951 952 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 953 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 954 fwrt->fw->dbg.mem_tlv; 955 956 if (!fwrt->fw->dbg.n_mem_tlv) 957 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 958 IWL_FW_ERROR_DUMP_MEM_SRAM); 959 960 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 961 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 962 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 963 964 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 965 le32_to_cpu(fw_dbg_mem[i].data_type)); 966 } 967 968 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 969 fwrt->trans->cfg->smem_offset, 970 IWL_FW_ERROR_DUMP_MEM_SMEM); 971 972 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 973 fwrt->trans->cfg->dccm2_offset, 974 IWL_FW_ERROR_DUMP_MEM_SRAM); 975 } 976 977 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 978 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 979 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 980 981 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 982 dump_data->len = cpu_to_le32(data_size * 2); 983 984 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 985 986 kfree(fwrt->dump.d3_debug_data); 987 fwrt->dump.d3_debug_data = NULL; 988 989 iwl_trans_read_mem_bytes(fwrt->trans, addr, 990 dump_data->data + data_size, 991 data_size); 992 993 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 994 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 995 dump_data->data + data_size, 996 data_size); 997 998 dump_data = iwl_fw_error_next_data(dump_data); 999 } 1000 1001 /* Dump fw's virtual image */ 1002 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1003 iwl_dump_paging(fwrt, &dump_data); 1004 1005 if (prph_len) 1006 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1007 1008 out: 1009 dump_file->file_len = cpu_to_le32(file_len); 1010 return dump_file; 1011 } 1012 1013 /** 1014 * struct iwl_dump_ini_region_data - region data 1015 * @reg_tlv: region TLV 1016 * @dump_data: dump data 1017 */ 1018 struct iwl_dump_ini_region_data { 1019 struct iwl_ucode_tlv *reg_tlv; 1020 struct iwl_fwrt_dump_data *dump_data; 1021 }; 1022 1023 static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt, 1024 void *range_ptr, u32 addr, 1025 __le32 size) 1026 { 1027 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1028 __le32 *val = range->data; 1029 u32 prph_val; 1030 int i; 1031 1032 range->internal_base_addr = cpu_to_le32(addr); 1033 range->range_data_size = size; 1034 for (i = 0; i < le32_to_cpu(size); i += 4) { 1035 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1036 if (iwl_trans_is_hw_error_value(prph_val)) 1037 return -EBUSY; 1038 *val++ = cpu_to_le32(prph_val); 1039 } 1040 1041 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1042 } 1043 1044 static int 1045 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1046 struct iwl_dump_ini_region_data *reg_data, 1047 void *range_ptr, u32 range_len, int idx) 1048 { 1049 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1050 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1051 le32_to_cpu(reg->dev_addr.offset); 1052 1053 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1054 reg->dev_addr.size); 1055 } 1056 1057 static int 1058 iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime *fwrt, 1059 struct iwl_dump_ini_region_data *reg_data, 1060 void *range_ptr, u32 range_len, int idx) 1061 { 1062 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1063 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1064 u32 addr = le32_to_cpu(reg->dev_addr_range.offset) + 1065 le32_to_cpu(pairs[idx].addr); 1066 1067 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1068 pairs[idx].size); 1069 } 1070 1071 static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt, 1072 void *range_ptr, u32 addr, 1073 __le32 size, __le32 offset) 1074 { 1075 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1076 __le32 *val = range->data; 1077 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1078 u32 indirect_rd_addr = WMAL_MRSPF_1; 1079 u32 prph_val; 1080 u32 dphy_state; 1081 u32 dphy_addr; 1082 int i; 1083 1084 range->internal_base_addr = cpu_to_le32(addr); 1085 range->range_data_size = size; 1086 1087 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1088 indirect_wr_addr = WMAL_INDRCT_CMD1; 1089 1090 indirect_wr_addr += le32_to_cpu(offset); 1091 indirect_rd_addr += le32_to_cpu(offset); 1092 1093 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1094 return -EBUSY; 1095 1096 dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1097 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1098 1099 for (i = 0; i < le32_to_cpu(size); i += 4) { 1100 if (dphy_state == HBUS_TIMEOUT || 1101 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1102 WFPM_PHYRF_STATE_ON) { 1103 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1104 continue; 1105 } 1106 1107 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1108 WMAL_INDRCT_CMD(addr + i)); 1109 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1110 indirect_rd_addr); 1111 *val++ = cpu_to_le32(prph_val); 1112 } 1113 1114 iwl_trans_release_nic_access(fwrt->trans); 1115 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1116 } 1117 1118 static int 1119 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1120 struct iwl_dump_ini_region_data *reg_data, 1121 void *range_ptr, u32 range_len, int idx) 1122 { 1123 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1124 u32 addr = le32_to_cpu(reg->addrs[idx]); 1125 1126 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1127 reg->dev_addr.size, 1128 reg->dev_addr.offset); 1129 } 1130 1131 static int 1132 iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime *fwrt, 1133 struct iwl_dump_ini_region_data *reg_data, 1134 void *range_ptr, u32 range_len, int idx) 1135 { 1136 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1137 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1138 u32 addr = le32_to_cpu(pairs[idx].addr); 1139 1140 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1141 pairs[idx].size, 1142 reg->dev_addr_range.offset); 1143 } 1144 1145 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1146 struct iwl_dump_ini_region_data *reg_data, 1147 void *range_ptr, u32 range_len, int idx) 1148 { 1149 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1150 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1151 __le32 *val = range->data; 1152 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1153 le32_to_cpu(reg->dev_addr.offset); 1154 int i; 1155 1156 range->internal_base_addr = cpu_to_le32(addr); 1157 range->range_data_size = reg->dev_addr.size; 1158 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1159 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1160 1161 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1162 } 1163 1164 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1165 struct iwl_dump_ini_region_data *reg_data, 1166 void *range_ptr, u32 range_len, int idx) 1167 { 1168 struct iwl_trans *trans = fwrt->trans; 1169 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1170 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1171 __le32 *val = range->data; 1172 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1173 le32_to_cpu(reg->dev_addr.offset); 1174 int i; 1175 1176 /* we shouldn't get here if the trans doesn't have read_config32 */ 1177 if (WARN_ON_ONCE(!trans->ops->read_config32)) 1178 return -EOPNOTSUPP; 1179 1180 range->internal_base_addr = cpu_to_le32(addr); 1181 range->range_data_size = reg->dev_addr.size; 1182 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1183 int ret; 1184 u32 tmp; 1185 1186 ret = trans->ops->read_config32(trans, addr + i, &tmp); 1187 if (ret < 0) 1188 return ret; 1189 1190 *val++ = cpu_to_le32(tmp); 1191 } 1192 1193 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1194 } 1195 1196 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1197 struct iwl_dump_ini_region_data *reg_data, 1198 void *range_ptr, u32 range_len, int idx) 1199 { 1200 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1201 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1202 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1203 le32_to_cpu(reg->dev_addr.offset); 1204 1205 range->internal_base_addr = cpu_to_le32(addr); 1206 range->range_data_size = reg->dev_addr.size; 1207 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1208 le32_to_cpu(reg->dev_addr.size)); 1209 1210 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1211 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1212 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1213 range->data, 1214 le32_to_cpu(reg->dev_addr.size)); 1215 1216 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1217 } 1218 1219 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1220 void *range_ptr, u32 range_len, int idx) 1221 { 1222 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1223 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1224 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1225 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1226 1227 range->page_num = cpu_to_le32(idx); 1228 range->range_data_size = cpu_to_le32(page_size); 1229 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1230 DMA_BIDIRECTIONAL); 1231 memcpy(range->data, page_address(page), page_size); 1232 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1233 DMA_BIDIRECTIONAL); 1234 1235 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1236 } 1237 1238 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1239 struct iwl_dump_ini_region_data *reg_data, 1240 void *range_ptr, u32 range_len, int idx) 1241 { 1242 struct iwl_fw_ini_error_dump_range *range; 1243 u32 page_size; 1244 1245 /* all paged index start from 1 to skip CSS section */ 1246 idx++; 1247 1248 if (!fwrt->trans->trans_cfg->gen2) 1249 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1250 1251 range = range_ptr; 1252 page_size = fwrt->trans->init_dram.paging[idx].size; 1253 1254 range->page_num = cpu_to_le32(idx); 1255 range->range_data_size = cpu_to_le32(page_size); 1256 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1257 page_size); 1258 1259 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1260 } 1261 1262 static int 1263 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1264 struct iwl_dump_ini_region_data *reg_data, 1265 void *range_ptr, u32 range_len, int idx) 1266 { 1267 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1268 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1269 struct iwl_dram_data *frag; 1270 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1271 1272 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1273 1274 range->dram_base_addr = cpu_to_le64(frag->physical); 1275 range->range_data_size = cpu_to_le32(frag->size); 1276 1277 memcpy(range->data, frag->block, frag->size); 1278 1279 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1280 } 1281 1282 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1283 struct iwl_dump_ini_region_data *reg_data, 1284 void *range_ptr, u32 range_len, int idx) 1285 { 1286 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1287 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1288 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1289 1290 range->internal_base_addr = cpu_to_le32(addr); 1291 range->range_data_size = reg->internal_buffer.size; 1292 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1293 le32_to_cpu(reg->internal_buffer.size)); 1294 1295 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1296 } 1297 1298 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1299 struct iwl_dump_ini_region_data *reg_data, int idx) 1300 { 1301 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1302 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1303 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1304 int txf_num = cfg->num_txfifo_entries; 1305 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1306 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1307 1308 if (!idx) { 1309 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1310 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1311 le32_to_cpu(reg->fifos.offset)); 1312 return false; 1313 } 1314 1315 iter->internal_txf = 0; 1316 iter->fifo_size = 0; 1317 iter->fifo = -1; 1318 if (le32_to_cpu(reg->fifos.offset)) 1319 iter->lmac = 1; 1320 else 1321 iter->lmac = 0; 1322 } 1323 1324 if (!iter->internal_txf) { 1325 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1326 iter->fifo_size = 1327 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1328 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1329 return true; 1330 } 1331 iter->fifo--; 1332 } 1333 1334 iter->internal_txf = 1; 1335 1336 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1337 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1338 return false; 1339 1340 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1341 iter->fifo_size = 1342 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1343 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1344 return true; 1345 } 1346 1347 return false; 1348 } 1349 1350 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1351 struct iwl_dump_ini_region_data *reg_data, 1352 void *range_ptr, u32 range_len, int idx) 1353 { 1354 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1355 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1356 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1357 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1358 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1359 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1360 u32 registers_size = registers_num * sizeof(*reg_dump); 1361 __le32 *data; 1362 int i; 1363 1364 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1365 return -EIO; 1366 1367 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1368 return -EBUSY; 1369 1370 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1371 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1372 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1373 1374 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1375 1376 /* 1377 * read txf registers. for each register, write to the dump the 1378 * register address and its value 1379 */ 1380 for (i = 0; i < registers_num; i++) { 1381 addr = le32_to_cpu(reg->addrs[i]) + offs; 1382 1383 reg_dump->addr = cpu_to_le32(addr); 1384 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1385 addr)); 1386 1387 reg_dump++; 1388 } 1389 1390 if (reg->fifos.hdr_only) { 1391 range->range_data_size = cpu_to_le32(registers_size); 1392 goto out; 1393 } 1394 1395 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1396 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1397 TXF_WR_PTR + offs); 1398 1399 /* Dummy-read to advance the read pointer to the head */ 1400 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1401 1402 /* Read FIFO */ 1403 addr = TXF_READ_MODIFY_DATA + offs; 1404 data = (void *)reg_dump; 1405 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1406 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1407 1408 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1409 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1410 reg_dump, iter->fifo_size); 1411 1412 out: 1413 iwl_trans_release_nic_access(fwrt->trans); 1414 1415 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1416 } 1417 1418 static int 1419 iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt, 1420 struct iwl_dump_ini_region_data *reg_data, 1421 void *range_ptr, u32 range_len, int idx) 1422 { 1423 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1424 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1425 __le32 *val = range->data; 1426 __le32 offset = reg->dev_addr.offset; 1427 u32 indirect_rd_wr_addr = DPHYIP_INDIRECT; 1428 u32 addr = le32_to_cpu(reg->addrs[idx]); 1429 u32 dphy_state, dphy_addr, prph_val; 1430 int i; 1431 1432 range->internal_base_addr = cpu_to_le32(addr); 1433 range->range_data_size = reg->dev_addr.size; 1434 1435 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1436 return -EBUSY; 1437 1438 indirect_rd_wr_addr += le32_to_cpu(offset); 1439 1440 dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1441 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1442 1443 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1444 if (dphy_state == HBUS_TIMEOUT || 1445 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1446 WFPM_PHYRF_STATE_ON) { 1447 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1448 continue; 1449 } 1450 1451 iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr, 1452 addr + i); 1453 /* wait a bit for value to be ready in register */ 1454 udelay(1); 1455 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1456 indirect_rd_wr_addr); 1457 *val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >> 1458 DPHYIP_INDIRECT_RD_SHIFT); 1459 } 1460 1461 iwl_trans_release_nic_access(fwrt->trans); 1462 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1463 } 1464 1465 struct iwl_ini_rxf_data { 1466 u32 fifo_num; 1467 u32 size; 1468 u32 offset; 1469 }; 1470 1471 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1472 struct iwl_dump_ini_region_data *reg_data, 1473 struct iwl_ini_rxf_data *data) 1474 { 1475 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1476 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1477 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1478 u8 fifo_idx; 1479 1480 if (!data) 1481 return; 1482 1483 memset(data, 0, sizeof(*data)); 1484 1485 /* make sure only one bit is set in only one fid */ 1486 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1487 "fid1=%x, fid2=%x\n", fid1, fid2)) 1488 return; 1489 1490 if (fid1) { 1491 fifo_idx = ffs(fid1) - 1; 1492 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1493 fifo_idx)) 1494 return; 1495 1496 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1497 data->fifo_num = fifo_idx; 1498 } else { 1499 u8 max_idx; 1500 1501 fifo_idx = ffs(fid2) - 1; 1502 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1503 SHARED_MEM_CFG_CMD, 0) <= 3) 1504 max_idx = 0; 1505 else 1506 max_idx = 1; 1507 1508 if (WARN_ONCE(fifo_idx > max_idx, 1509 "invalid umac fifo idx %d", fifo_idx)) 1510 return; 1511 1512 /* use bit 31 to distinguish between umac and lmac rxf while 1513 * parsing the dump 1514 */ 1515 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1516 1517 switch (fifo_idx) { 1518 case 0: 1519 data->size = fwrt->smem_cfg.rxfifo2_size; 1520 data->offset = iwl_umac_prph(fwrt->trans, 1521 RXF_DIFF_FROM_PREV); 1522 break; 1523 case 1: 1524 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1525 data->offset = iwl_umac_prph(fwrt->trans, 1526 RXF2C_DIFF_FROM_PREV); 1527 break; 1528 } 1529 } 1530 } 1531 1532 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1533 struct iwl_dump_ini_region_data *reg_data, 1534 void *range_ptr, u32 range_len, int idx) 1535 { 1536 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1537 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1538 struct iwl_ini_rxf_data rxf_data; 1539 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1540 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1541 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1542 u32 registers_size = registers_num * sizeof(*reg_dump); 1543 __le32 *data; 1544 int i; 1545 1546 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1547 if (!rxf_data.size) 1548 return -EIO; 1549 1550 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1551 return -EBUSY; 1552 1553 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1554 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1555 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1556 1557 /* 1558 * read rxf registers. for each register, write to the dump the 1559 * register address and its value 1560 */ 1561 for (i = 0; i < registers_num; i++) { 1562 addr = le32_to_cpu(reg->addrs[i]) + offs; 1563 1564 reg_dump->addr = cpu_to_le32(addr); 1565 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1566 addr)); 1567 1568 reg_dump++; 1569 } 1570 1571 if (reg->fifos.hdr_only) { 1572 range->range_data_size = cpu_to_le32(registers_size); 1573 goto out; 1574 } 1575 1576 offs = rxf_data.offset; 1577 1578 /* Lock fence */ 1579 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1580 /* Set fence pointer to the same place like WR pointer */ 1581 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1582 /* Set fence offset */ 1583 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1584 0x0); 1585 1586 /* Read FIFO */ 1587 addr = RXF_FIFO_RD_FENCE_INC + offs; 1588 data = (void *)reg_dump; 1589 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1590 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1591 1592 out: 1593 iwl_trans_release_nic_access(fwrt->trans); 1594 1595 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1596 } 1597 1598 static int 1599 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1600 struct iwl_dump_ini_region_data *reg_data, 1601 void *range_ptr, u32 range_len, int idx) 1602 { 1603 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1604 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1605 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1606 u32 addr = le32_to_cpu(err_table->base_addr) + 1607 le32_to_cpu(err_table->offset); 1608 1609 range->internal_base_addr = cpu_to_le32(addr); 1610 range->range_data_size = err_table->size; 1611 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1612 le32_to_cpu(err_table->size)); 1613 1614 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1615 } 1616 1617 static int 1618 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1619 struct iwl_dump_ini_region_data *reg_data, 1620 void *range_ptr, u32 range_len, int idx) 1621 { 1622 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1623 struct iwl_fw_ini_region_special_device_memory *special_mem = 1624 ®->special_mem; 1625 1626 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1627 u32 addr = le32_to_cpu(special_mem->base_addr) + 1628 le32_to_cpu(special_mem->offset); 1629 1630 range->internal_base_addr = cpu_to_le32(addr); 1631 range->range_data_size = special_mem->size; 1632 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1633 le32_to_cpu(special_mem->size)); 1634 1635 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1636 } 1637 1638 static int 1639 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1640 struct iwl_dump_ini_region_data *reg_data, 1641 void *range_ptr, u32 range_len, int idx) 1642 { 1643 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1644 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1645 __le32 *val = range->data; 1646 u32 prph_data; 1647 int i; 1648 1649 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1650 return -EBUSY; 1651 1652 range->range_data_size = reg->dev_addr.size; 1653 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1654 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1655 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1656 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1657 if (iwl_trans_is_hw_error_value(prph_data)) { 1658 iwl_trans_release_nic_access(fwrt->trans); 1659 return -EBUSY; 1660 } 1661 *val++ = cpu_to_le32(prph_data); 1662 } 1663 iwl_trans_release_nic_access(fwrt->trans); 1664 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1665 } 1666 1667 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1668 struct iwl_dump_ini_region_data *reg_data, 1669 void *range_ptr, u32 range_len, int idx) 1670 { 1671 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1672 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1673 u32 pkt_len; 1674 1675 if (!pkt) 1676 return -EIO; 1677 1678 pkt_len = iwl_rx_packet_payload_len(pkt); 1679 1680 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1681 range->range_data_size = cpu_to_le32(pkt_len); 1682 1683 memcpy(range->data, pkt->data, pkt_len); 1684 1685 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1686 } 1687 1688 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1689 struct iwl_dump_ini_region_data *reg_data, 1690 void *range_ptr, u32 range_len, int idx) 1691 { 1692 /* read the IMR memory and DMA it to SRAM */ 1693 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1694 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1695 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1696 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1697 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1698 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1699 1700 range->range_data_size = cpu_to_le32(size_to_dump); 1701 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1702 imr_curr_addr, size_to_dump)) { 1703 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1704 return -1; 1705 } 1706 1707 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1708 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1709 1710 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1711 size_to_dump); 1712 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1713 } 1714 1715 static void * 1716 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1717 struct iwl_dump_ini_region_data *reg_data, 1718 void *data, u32 data_len) 1719 { 1720 struct iwl_fw_ini_error_dump *dump = data; 1721 1722 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1723 1724 return dump->data; 1725 } 1726 1727 /** 1728 * mask_apply_and_normalize - applies mask on val and normalize the result 1729 * 1730 * The normalization is based on the first set bit in the mask 1731 * 1732 * @val: value 1733 * @mask: mask to apply and to normalize with 1734 */ 1735 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1736 { 1737 return (val & mask) >> (ffs(mask) - 1); 1738 } 1739 1740 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1741 const struct iwl_fw_mon_reg *reg_info) 1742 { 1743 u32 val, offs; 1744 1745 /* The header addresses of DBGCi is calculate as follows: 1746 * DBGC1 address + (0x100 * i) 1747 */ 1748 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1749 1750 if (!reg_info || !reg_info->addr || !reg_info->mask) 1751 return 0; 1752 1753 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1754 1755 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1756 } 1757 1758 static void * 1759 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1760 struct iwl_fw_ini_monitor_dump *data, 1761 const struct iwl_fw_mon_regs *addrs) 1762 { 1763 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1764 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1765 return NULL; 1766 } 1767 1768 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1769 &addrs->write_ptr); 1770 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1771 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1772 1773 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1774 } 1775 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1776 &addrs->cycle_cnt); 1777 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1778 &addrs->cur_frag); 1779 1780 iwl_trans_release_nic_access(fwrt->trans); 1781 1782 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1783 1784 return data->data; 1785 } 1786 1787 static void * 1788 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1789 struct iwl_dump_ini_region_data *reg_data, 1790 void *data, u32 data_len) 1791 { 1792 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1793 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1794 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1795 1796 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1797 &fwrt->trans->cfg->mon_dram_regs); 1798 } 1799 1800 static void * 1801 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1802 struct iwl_dump_ini_region_data *reg_data, 1803 void *data, u32 data_len) 1804 { 1805 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1806 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1807 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1808 1809 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1810 &fwrt->trans->cfg->mon_smem_regs); 1811 } 1812 1813 static void * 1814 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1815 struct iwl_dump_ini_region_data *reg_data, 1816 void *data, u32 data_len) 1817 { 1818 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1819 1820 return iwl_dump_ini_mon_fill_header(fwrt, 1821 /* no offset calculation later */ 1822 IWL_FW_INI_ALLOCATION_ID_DBGC1, 1823 mon_dump, 1824 &fwrt->trans->cfg->mon_dbgi_regs); 1825 } 1826 1827 static void * 1828 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1829 struct iwl_dump_ini_region_data *reg_data, 1830 void *data, u32 data_len) 1831 { 1832 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1833 struct iwl_fw_ini_err_table_dump *dump = data; 1834 1835 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1836 dump->version = reg->err_table.version; 1837 1838 return dump->data; 1839 } 1840 1841 static void * 1842 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1843 struct iwl_dump_ini_region_data *reg_data, 1844 void *data, u32 data_len) 1845 { 1846 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1847 struct iwl_fw_ini_special_device_memory *dump = data; 1848 1849 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1850 dump->type = reg->special_mem.type; 1851 dump->version = reg->special_mem.version; 1852 1853 return dump->data; 1854 } 1855 1856 static void * 1857 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1858 struct iwl_dump_ini_region_data *reg_data, 1859 void *data, u32 data_len) 1860 { 1861 struct iwl_fw_ini_error_dump *dump = data; 1862 1863 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1864 1865 return dump->data; 1866 } 1867 1868 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1869 struct iwl_dump_ini_region_data *reg_data) 1870 { 1871 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1872 1873 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1874 } 1875 1876 static u32 1877 iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime *fwrt, 1878 struct iwl_dump_ini_region_data *reg_data) 1879 { 1880 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1881 size_t size = sizeof(struct iwl_fw_ini_addr_size); 1882 1883 return iwl_tlv_array_len_with_size(reg_data->reg_tlv, reg, size); 1884 } 1885 1886 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1887 struct iwl_dump_ini_region_data *reg_data) 1888 { 1889 if (fwrt->trans->trans_cfg->gen2) { 1890 if (fwrt->trans->init_dram.paging_cnt) 1891 return fwrt->trans->init_dram.paging_cnt - 1; 1892 else 1893 return 0; 1894 } 1895 1896 return fwrt->num_of_paging_blk; 1897 } 1898 1899 static u32 1900 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1901 struct iwl_dump_ini_region_data *reg_data) 1902 { 1903 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1904 struct iwl_fw_mon *fw_mon; 1905 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1906 int i; 1907 1908 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1909 1910 for (i = 0; i < fw_mon->num_frags; i++) { 1911 if (!fw_mon->frags[i].size) 1912 break; 1913 1914 ranges++; 1915 } 1916 1917 return ranges; 1918 } 1919 1920 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1921 struct iwl_dump_ini_region_data *reg_data) 1922 { 1923 u32 num_of_fifos = 0; 1924 1925 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1926 num_of_fifos++; 1927 1928 return num_of_fifos; 1929 } 1930 1931 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1932 struct iwl_dump_ini_region_data *reg_data) 1933 { 1934 return 1; 1935 } 1936 1937 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1938 struct iwl_dump_ini_region_data *reg_data) 1939 { 1940 /* range is total number of pages need to copied from 1941 *IMR memory to SRAM and later from SRAM to DRAM 1942 */ 1943 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1944 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1945 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1946 1947 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1948 IWL_DEBUG_INFO(fwrt, 1949 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1950 imr_enable, imr_size, sram_size); 1951 return 0; 1952 } 1953 1954 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1955 } 1956 1957 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1958 struct iwl_dump_ini_region_data *reg_data) 1959 { 1960 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1961 u32 size = le32_to_cpu(reg->dev_addr.size); 1962 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1963 1964 if (!size || !ranges) 1965 return 0; 1966 1967 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1968 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1969 } 1970 1971 static u32 1972 iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime *fwrt, 1973 struct iwl_dump_ini_region_data *reg_data) 1974 { 1975 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1976 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1977 u32 ranges = iwl_dump_ini_mem_block_ranges(fwrt, reg_data); 1978 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1979 int range; 1980 1981 if (!ranges) 1982 return 0; 1983 1984 for (range = 0; range < ranges; range++) 1985 size += le32_to_cpu(pairs[range].size); 1986 1987 return size + ranges * sizeof(struct iwl_fw_ini_error_dump_range); 1988 } 1989 1990 static u32 1991 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1992 struct iwl_dump_ini_region_data *reg_data) 1993 { 1994 int i; 1995 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1996 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1997 1998 /* start from 1 to skip CSS section */ 1999 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 2000 size += range_header_len; 2001 if (fwrt->trans->trans_cfg->gen2) 2002 size += fwrt->trans->init_dram.paging[i].size; 2003 else 2004 size += fwrt->fw_paging_db[i].fw_paging_size; 2005 } 2006 2007 return size; 2008 } 2009 2010 static u32 2011 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 2012 struct iwl_dump_ini_region_data *reg_data) 2013 { 2014 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2015 struct iwl_fw_mon *fw_mon; 2016 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 2017 int i; 2018 2019 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 2020 2021 for (i = 0; i < fw_mon->num_frags; i++) { 2022 struct iwl_dram_data *frag = &fw_mon->frags[i]; 2023 2024 if (!frag->size) 2025 break; 2026 2027 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 2028 } 2029 2030 if (size) 2031 size += sizeof(struct iwl_fw_ini_monitor_dump); 2032 2033 return size; 2034 } 2035 2036 static u32 2037 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 2038 struct iwl_dump_ini_region_data *reg_data) 2039 { 2040 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2041 u32 size; 2042 2043 size = le32_to_cpu(reg->internal_buffer.size); 2044 if (!size) 2045 return 0; 2046 2047 size += sizeof(struct iwl_fw_ini_monitor_dump) + 2048 sizeof(struct iwl_fw_ini_error_dump_range); 2049 2050 return size; 2051 } 2052 2053 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 2054 struct iwl_dump_ini_region_data *reg_data) 2055 { 2056 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2057 u32 size = le32_to_cpu(reg->dev_addr.size); 2058 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 2059 2060 if (!size || !ranges) 2061 return 0; 2062 2063 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 2064 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 2065 } 2066 2067 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 2068 struct iwl_dump_ini_region_data *reg_data) 2069 { 2070 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2071 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 2072 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2073 u32 size = 0; 2074 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 2075 registers_num * 2076 sizeof(struct iwl_fw_ini_error_dump_register); 2077 2078 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 2079 size += fifo_hdr; 2080 if (!reg->fifos.hdr_only) 2081 size += iter->fifo_size; 2082 } 2083 2084 if (!size) 2085 return 0; 2086 2087 return size + sizeof(struct iwl_fw_ini_error_dump); 2088 } 2089 2090 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 2091 struct iwl_dump_ini_region_data *reg_data) 2092 { 2093 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2094 struct iwl_ini_rxf_data rx_data; 2095 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2096 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 2097 sizeof(struct iwl_fw_ini_error_dump_range) + 2098 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 2099 2100 if (reg->fifos.hdr_only) 2101 return size; 2102 2103 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 2104 size += rx_data.size; 2105 2106 return size; 2107 } 2108 2109 static u32 2110 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 2111 struct iwl_dump_ini_region_data *reg_data) 2112 { 2113 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2114 u32 size = le32_to_cpu(reg->err_table.size); 2115 2116 if (size) 2117 size += sizeof(struct iwl_fw_ini_err_table_dump) + 2118 sizeof(struct iwl_fw_ini_error_dump_range); 2119 2120 return size; 2121 } 2122 2123 static u32 2124 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2125 struct iwl_dump_ini_region_data *reg_data) 2126 { 2127 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2128 u32 size = le32_to_cpu(reg->special_mem.size); 2129 2130 if (size) 2131 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2132 sizeof(struct iwl_fw_ini_error_dump_range); 2133 2134 return size; 2135 } 2136 2137 static u32 2138 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2139 struct iwl_dump_ini_region_data *reg_data) 2140 { 2141 u32 size = 0; 2142 2143 if (!reg_data->dump_data->fw_pkt) 2144 return 0; 2145 2146 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2147 if (size) 2148 size += sizeof(struct iwl_fw_ini_error_dump) + 2149 sizeof(struct iwl_fw_ini_error_dump_range); 2150 2151 return size; 2152 } 2153 2154 static u32 2155 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2156 struct iwl_dump_ini_region_data *reg_data) 2157 { 2158 u32 ranges = 0; 2159 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2160 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2161 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2162 2163 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2164 IWL_DEBUG_INFO(fwrt, 2165 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2166 imr_enable, imr_size, sram_size); 2167 return 0; 2168 } 2169 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2170 if (!ranges) { 2171 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges); 2172 return 0; 2173 } 2174 imr_size += sizeof(struct iwl_fw_ini_error_dump) + 2175 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2176 return imr_size; 2177 } 2178 2179 /** 2180 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2181 * @get_num_of_ranges: returns the number of memory ranges in the region. 2182 * @get_size: returns the total size of the region. 2183 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2184 * the first range or NULL if failed to fill headers. 2185 * @fill_range: copies a given memory range into the dump. 2186 * Returns the size of the range or negative error value otherwise. 2187 */ 2188 struct iwl_dump_ini_mem_ops { 2189 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2190 struct iwl_dump_ini_region_data *reg_data); 2191 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2192 struct iwl_dump_ini_region_data *reg_data); 2193 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2194 struct iwl_dump_ini_region_data *reg_data, 2195 void *data, u32 data_len); 2196 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2197 struct iwl_dump_ini_region_data *reg_data, 2198 void *range, u32 range_len, int idx); 2199 }; 2200 2201 /** 2202 * iwl_dump_ini_mem 2203 * 2204 * Creates a dump tlv and copy a memory region into it. 2205 * Returns the size of the current dump tlv or 0 if failed 2206 * 2207 * @fwrt: fw runtime struct 2208 * @list: list to add the dump tlv to 2209 * @reg_data: memory region 2210 * @ops: memory dump operations 2211 */ 2212 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2213 struct iwl_dump_ini_region_data *reg_data, 2214 const struct iwl_dump_ini_mem_ops *ops) 2215 { 2216 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2217 struct iwl_fw_ini_dump_entry *entry; 2218 struct iwl_fw_ini_error_dump_data *tlv; 2219 struct iwl_fw_ini_error_dump_header *header; 2220 u32 type = reg->type; 2221 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK); 2222 u32 num_of_ranges, i, size; 2223 u8 *range; 2224 u32 free_size; 2225 u64 header_size; 2226 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE; 2227 2228 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n", 2229 dump_policy, id, type); 2230 2231 if (le32_to_cpu(reg->hdr.version) >= 2) { 2232 u32 dp = le32_get_bits(reg->id, 2233 IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2234 2235 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE && 2236 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) { 2237 IWL_DEBUG_FW(fwrt, 2238 "WRT: no dump - type %d and policy mismatch=%d\n", 2239 dump_policy, dp); 2240 return 0; 2241 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM && 2242 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) { 2243 IWL_DEBUG_FW(fwrt, 2244 "WRT: no dump - type %d and policy mismatch=%d\n", 2245 dump_policy, dp); 2246 return 0; 2247 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF && 2248 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) { 2249 IWL_DEBUG_FW(fwrt, 2250 "WRT: no dump - type %d and policy mismatch=%d\n", 2251 dump_policy, dp); 2252 return 0; 2253 } 2254 } 2255 2256 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2257 !ops->fill_range) { 2258 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2259 return 0; 2260 } 2261 2262 size = ops->get_size(fwrt, reg_data); 2263 2264 if (size < sizeof(*header)) { 2265 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2266 return 0; 2267 } 2268 2269 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2270 if (!entry) 2271 return 0; 2272 2273 entry->size = sizeof(*tlv) + size; 2274 2275 tlv = (void *)entry->data; 2276 tlv->type = reg->type; 2277 tlv->sub_type = reg->sub_type; 2278 tlv->sub_type_ver = reg->sub_type_ver; 2279 tlv->reserved = reg->reserved; 2280 tlv->len = cpu_to_le32(size); 2281 2282 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2283 2284 header = (void *)tlv->data; 2285 header->region_id = cpu_to_le32(id); 2286 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2287 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2288 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2289 2290 free_size = size; 2291 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2292 if (!range) { 2293 IWL_ERR(fwrt, 2294 "WRT: Failed to fill region header: id=%d, type=%d\n", 2295 id, type); 2296 goto out_err; 2297 } 2298 2299 header_size = range - (u8 *)header; 2300 2301 if (WARN(header_size > free_size, 2302 "header size %llu > free_size %d", 2303 header_size, free_size)) { 2304 IWL_ERR(fwrt, 2305 "WRT: fill_mem_hdr used more than given free_size\n"); 2306 goto out_err; 2307 } 2308 2309 free_size -= header_size; 2310 2311 for (i = 0; i < num_of_ranges; i++) { 2312 int range_size = ops->fill_range(fwrt, reg_data, range, 2313 free_size, i); 2314 2315 if (range_size < 0) { 2316 IWL_ERR(fwrt, 2317 "WRT: Failed to dump region: id=%d, type=%d\n", 2318 id, type); 2319 goto out_err; 2320 } 2321 2322 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2323 range_size, free_size)) { 2324 IWL_ERR(fwrt, 2325 "WRT: fill_raged used more than given free_size\n"); 2326 goto out_err; 2327 } 2328 2329 free_size -= range_size; 2330 range = range + range_size; 2331 } 2332 2333 list_add_tail(&entry->list, list); 2334 2335 return entry->size; 2336 2337 out_err: 2338 vfree(entry); 2339 2340 return 0; 2341 } 2342 2343 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2344 struct iwl_fw_ini_trigger_tlv *trigger, 2345 struct list_head *list) 2346 { 2347 struct iwl_fw_ini_dump_entry *entry; 2348 struct iwl_fw_error_dump_data *tlv; 2349 struct iwl_fw_ini_dump_info *dump; 2350 struct iwl_dbg_tlv_node *node; 2351 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2352 u32 size = sizeof(*tlv) + sizeof(*dump); 2353 u32 num_of_cfg_names = 0; 2354 u32 hw_type; 2355 2356 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2357 size += sizeof(*cfg_name); 2358 num_of_cfg_names++; 2359 } 2360 2361 entry = vzalloc(sizeof(*entry) + size); 2362 if (!entry) 2363 return 0; 2364 2365 entry->size = size; 2366 2367 tlv = (void *)entry->data; 2368 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2369 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2370 2371 dump = (void *)tlv->data; 2372 2373 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2374 dump->time_point = trigger->time_point; 2375 dump->trigger_reason = trigger->trigger_reason; 2376 dump->external_cfg_state = 2377 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2378 2379 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2380 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2381 2382 dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step); 2383 2384 /* 2385 * Several HWs all have type == 0x42, so we'll override this value 2386 * according to the detected HW 2387 */ 2388 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2389 if (hw_type == IWL_AX210_HW_TYPE) { 2390 u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR); 2391 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2392 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2393 u32 masked_bits = is_jacket | (is_cdb << 1); 2394 2395 /* 2396 * The HW type depends on certain bits in this case, so add 2397 * these bits to the HW type. We won't have collisions since we 2398 * add these bits after the highest possible bit in the mask. 2399 */ 2400 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2401 } 2402 dump->hw_type = cpu_to_le32(hw_type); 2403 2404 dump->rf_id_flavor = 2405 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2406 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2407 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2408 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2409 2410 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2411 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2412 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2413 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2414 2415 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2416 dump->regions_mask = trigger->regions_mask & 2417 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2418 2419 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2420 memcpy(dump->build_tag, fwrt->fw->human_readable, 2421 sizeof(dump->build_tag)); 2422 2423 cfg_name = dump->cfg_names; 2424 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2425 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2426 struct iwl_fw_ini_debug_info_tlv *debug_info = 2427 (void *)node->tlv.data; 2428 2429 cfg_name->image_type = debug_info->image_type; 2430 cfg_name->cfg_name_len = 2431 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME); 2432 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2433 sizeof(cfg_name->cfg_name)); 2434 cfg_name++; 2435 } 2436 2437 /* add dump info TLV to the beginning of the list since it needs to be 2438 * the first TLV in the dump 2439 */ 2440 list_add(&entry->list, list); 2441 2442 return entry->size; 2443 } 2444 2445 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt, 2446 struct list_head *list) 2447 { 2448 struct iwl_fw_ini_dump_entry *entry; 2449 struct iwl_dump_file_name_info *tlv; 2450 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext, 2451 IWL_FW_INI_MAX_NAME); 2452 2453 if (!fwrt->trans->dbg.dump_file_name_ext_valid) 2454 return 0; 2455 2456 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len); 2457 if (!entry) 2458 return 0; 2459 2460 entry->size = sizeof(*tlv) + len; 2461 2462 tlv = (void *)entry->data; 2463 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE); 2464 tlv->len = cpu_to_le32(len); 2465 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len); 2466 2467 /* add the dump file name extension tlv to the list */ 2468 list_add_tail(&entry->list, list); 2469 2470 fwrt->trans->dbg.dump_file_name_ext_valid = false; 2471 2472 return entry->size; 2473 } 2474 2475 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2476 [IWL_FW_INI_REGION_INVALID] = {}, 2477 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2478 .get_num_of_ranges = iwl_dump_ini_single_range, 2479 .get_size = iwl_dump_ini_mon_smem_get_size, 2480 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2481 .fill_range = iwl_dump_ini_mon_smem_iter, 2482 }, 2483 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2484 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2485 .get_size = iwl_dump_ini_mon_dram_get_size, 2486 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2487 .fill_range = iwl_dump_ini_mon_dram_iter, 2488 }, 2489 [IWL_FW_INI_REGION_TXF] = { 2490 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2491 .get_size = iwl_dump_ini_txf_get_size, 2492 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2493 .fill_range = iwl_dump_ini_txf_iter, 2494 }, 2495 [IWL_FW_INI_REGION_RXF] = { 2496 .get_num_of_ranges = iwl_dump_ini_single_range, 2497 .get_size = iwl_dump_ini_rxf_get_size, 2498 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2499 .fill_range = iwl_dump_ini_rxf_iter, 2500 }, 2501 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2502 .get_num_of_ranges = iwl_dump_ini_single_range, 2503 .get_size = iwl_dump_ini_err_table_get_size, 2504 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2505 .fill_range = iwl_dump_ini_err_table_iter, 2506 }, 2507 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2508 .get_num_of_ranges = iwl_dump_ini_single_range, 2509 .get_size = iwl_dump_ini_err_table_get_size, 2510 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2511 .fill_range = iwl_dump_ini_err_table_iter, 2512 }, 2513 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2514 .get_num_of_ranges = iwl_dump_ini_single_range, 2515 .get_size = iwl_dump_ini_fw_pkt_get_size, 2516 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2517 .fill_range = iwl_dump_ini_fw_pkt_iter, 2518 }, 2519 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2520 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2521 .get_size = iwl_dump_ini_mem_get_size, 2522 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2523 .fill_range = iwl_dump_ini_dev_mem_iter, 2524 }, 2525 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2526 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2527 .get_size = iwl_dump_ini_mem_get_size, 2528 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2529 .fill_range = iwl_dump_ini_prph_mac_iter, 2530 }, 2531 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2532 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2533 .get_size = iwl_dump_ini_mem_get_size, 2534 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2535 .fill_range = iwl_dump_ini_prph_phy_iter, 2536 }, 2537 [IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE] = { 2538 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2539 .get_size = iwl_dump_ini_mem_block_get_size, 2540 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2541 .fill_range = iwl_dump_ini_prph_mac_block_iter, 2542 }, 2543 [IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE] = { 2544 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2545 .get_size = iwl_dump_ini_mem_block_get_size, 2546 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2547 .fill_range = iwl_dump_ini_prph_phy_block_iter, 2548 }, 2549 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2550 [IWL_FW_INI_REGION_PAGING] = { 2551 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2552 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2553 .get_size = iwl_dump_ini_paging_get_size, 2554 .fill_range = iwl_dump_ini_paging_iter, 2555 }, 2556 [IWL_FW_INI_REGION_CSR] = { 2557 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2558 .get_size = iwl_dump_ini_mem_get_size, 2559 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2560 .fill_range = iwl_dump_ini_csr_iter, 2561 }, 2562 [IWL_FW_INI_REGION_DRAM_IMR] = { 2563 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2564 .get_size = iwl_dump_ini_imr_get_size, 2565 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2566 .fill_range = iwl_dump_ini_imr_iter, 2567 }, 2568 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2569 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2570 .get_size = iwl_dump_ini_mem_get_size, 2571 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2572 .fill_range = iwl_dump_ini_config_iter, 2573 }, 2574 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2575 .get_num_of_ranges = iwl_dump_ini_single_range, 2576 .get_size = iwl_dump_ini_special_mem_get_size, 2577 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2578 .fill_range = iwl_dump_ini_special_mem_iter, 2579 }, 2580 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2581 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2582 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2583 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2584 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2585 }, 2586 [IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = { 2587 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2588 .get_size = iwl_dump_ini_mem_get_size, 2589 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2590 .fill_range = iwl_dump_ini_prph_snps_dphyip_iter, 2591 }, 2592 }; 2593 2594 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2595 struct iwl_fwrt_dump_data *dump_data, 2596 struct list_head *list) 2597 { 2598 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2599 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2600 struct iwl_dump_ini_region_data reg_data = { 2601 .dump_data = dump_data, 2602 }; 2603 struct iwl_dump_ini_region_data imr_reg_data = { 2604 .dump_data = dump_data, 2605 }; 2606 int i; 2607 u32 size = 0; 2608 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2609 ~(fwrt->trans->dbg.unsupported_region_msk); 2610 2611 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2612 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2613 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2614 2615 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2616 u32 reg_type; 2617 struct iwl_fw_ini_region_tlv *reg; 2618 2619 if (!(BIT_ULL(i) & regions_mask)) 2620 continue; 2621 2622 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2623 if (!reg_data.reg_tlv) { 2624 IWL_WARN(fwrt, 2625 "WRT: Unassigned region id %d, skipping\n", i); 2626 continue; 2627 } 2628 2629 reg = (void *)reg_data.reg_tlv->data; 2630 reg_type = reg->type; 2631 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2632 continue; 2633 2634 if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2635 reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE || 2636 reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) && 2637 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2638 IWL_WARN(fwrt, 2639 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2640 tp_id); 2641 continue; 2642 } 2643 /* 2644 * DRAM_IMR can be collected only for FW/HW error timepoint 2645 * when fw is not alive. In addition, it must be collected 2646 * lastly as it overwrites SRAM that can possibly contain 2647 * debug data which also need to be collected. 2648 */ 2649 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { 2650 if (tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT || 2651 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR) 2652 imr_reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2653 else 2654 IWL_INFO(fwrt, 2655 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n", 2656 tp_id); 2657 /* continue to next region */ 2658 continue; 2659 } 2660 2661 2662 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2663 &iwl_dump_ini_region_ops[reg_type]); 2664 } 2665 /* collect DRAM_IMR region in the last */ 2666 if (imr_reg_data.reg_tlv) 2667 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2668 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]); 2669 2670 if (size) { 2671 size += iwl_dump_ini_file_name_info(fwrt, list); 2672 size += iwl_dump_ini_info(fwrt, trigger, list); 2673 } 2674 2675 return size; 2676 } 2677 2678 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2679 struct iwl_fw_ini_trigger_tlv *trig) 2680 { 2681 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2682 u32 usec = le32_to_cpu(trig->ignore_consec); 2683 2684 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2685 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2686 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2687 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2688 return false; 2689 2690 return true; 2691 } 2692 2693 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2694 struct iwl_fwrt_dump_data *dump_data, 2695 struct list_head *list) 2696 { 2697 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2698 struct iwl_fw_ini_dump_entry *entry; 2699 struct iwl_fw_ini_dump_file_hdr *hdr; 2700 u32 size; 2701 2702 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2703 !le64_to_cpu(trigger->regions_mask)) 2704 return 0; 2705 2706 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2707 if (!entry) 2708 return 0; 2709 2710 entry->size = sizeof(*hdr); 2711 2712 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2713 if (!size) { 2714 vfree(entry); 2715 return 0; 2716 } 2717 2718 hdr = (void *)entry->data; 2719 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2720 hdr->file_len = cpu_to_le32(size + entry->size); 2721 2722 list_add(&entry->list, list); 2723 2724 return le32_to_cpu(hdr->file_len); 2725 } 2726 2727 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2728 const struct iwl_fw_dump_desc *desc) 2729 { 2730 if (desc && desc != &iwl_dump_desc_assert) 2731 kfree(desc); 2732 2733 fwrt->dump.lmac_err_id[0] = 0; 2734 if (fwrt->smem_cfg.num_lmacs > 1) 2735 fwrt->dump.lmac_err_id[1] = 0; 2736 fwrt->dump.umac_err_id = 0; 2737 } 2738 2739 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2740 struct iwl_fwrt_dump_data *dump_data) 2741 { 2742 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2743 struct iwl_fw_error_dump_file *dump_file; 2744 struct scatterlist *sg_dump_data; 2745 u32 file_len; 2746 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2747 2748 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2749 if (!dump_file) 2750 return; 2751 2752 if (dump_data->monitor_only) 2753 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2754 2755 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2756 fwrt->sanitize_ops, 2757 fwrt->sanitize_ctx); 2758 file_len = le32_to_cpu(dump_file->file_len); 2759 fw_error_dump.fwrt_len = file_len; 2760 2761 if (fw_error_dump.trans_ptr) { 2762 file_len += fw_error_dump.trans_ptr->len; 2763 dump_file->file_len = cpu_to_le32(file_len); 2764 } 2765 2766 sg_dump_data = alloc_sgtable(file_len); 2767 if (sg_dump_data) { 2768 sg_pcopy_from_buffer(sg_dump_data, 2769 sg_nents(sg_dump_data), 2770 fw_error_dump.fwrt_ptr, 2771 fw_error_dump.fwrt_len, 0); 2772 if (fw_error_dump.trans_ptr) 2773 sg_pcopy_from_buffer(sg_dump_data, 2774 sg_nents(sg_dump_data), 2775 fw_error_dump.trans_ptr->data, 2776 fw_error_dump.trans_ptr->len, 2777 fw_error_dump.fwrt_len); 2778 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2779 GFP_KERNEL); 2780 } 2781 vfree(fw_error_dump.fwrt_ptr); 2782 vfree(fw_error_dump.trans_ptr); 2783 } 2784 2785 static void iwl_dump_ini_list_free(struct list_head *list) 2786 { 2787 while (!list_empty(list)) { 2788 struct iwl_fw_ini_dump_entry *entry = 2789 list_entry(list->next, typeof(*entry), list); 2790 2791 list_del(&entry->list); 2792 vfree(entry); 2793 } 2794 } 2795 2796 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2797 { 2798 dump_data->trig = NULL; 2799 kfree(dump_data->fw_pkt); 2800 dump_data->fw_pkt = NULL; 2801 } 2802 2803 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2804 struct iwl_fwrt_dump_data *dump_data) 2805 { 2806 LIST_HEAD(dump_list); 2807 struct scatterlist *sg_dump_data; 2808 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2809 2810 if (!file_len) 2811 return; 2812 2813 sg_dump_data = alloc_sgtable(file_len); 2814 if (sg_dump_data) { 2815 struct iwl_fw_ini_dump_entry *entry; 2816 int sg_entries = sg_nents(sg_dump_data); 2817 u32 offs = 0; 2818 2819 list_for_each_entry(entry, &dump_list, list) { 2820 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2821 entry->data, entry->size, offs); 2822 offs += entry->size; 2823 } 2824 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2825 GFP_KERNEL); 2826 } 2827 iwl_dump_ini_list_free(&dump_list); 2828 } 2829 2830 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2831 .trig_desc = { 2832 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2833 }, 2834 }; 2835 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2836 2837 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2838 const struct iwl_fw_dump_desc *desc, 2839 bool monitor_only, 2840 unsigned int delay) 2841 { 2842 struct iwl_fwrt_wk_data *wk_data; 2843 unsigned long idx; 2844 2845 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2846 iwl_fw_free_dump_desc(fwrt, desc); 2847 return 0; 2848 } 2849 2850 /* 2851 * Check there is an available worker. 2852 * ffz return value is undefined if no zero exists, 2853 * so check against ~0UL first. 2854 */ 2855 if (fwrt->dump.active_wks == ~0UL) 2856 return -EBUSY; 2857 2858 idx = ffz(fwrt->dump.active_wks); 2859 2860 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2861 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2862 return -EBUSY; 2863 2864 wk_data = &fwrt->dump.wks[idx]; 2865 2866 if (WARN_ON(wk_data->dump_data.desc)) 2867 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2868 2869 wk_data->dump_data.desc = desc; 2870 wk_data->dump_data.monitor_only = monitor_only; 2871 2872 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2873 le32_to_cpu(desc->trig_desc.type)); 2874 2875 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay)); 2876 2877 return 0; 2878 } 2879 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2880 2881 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2882 enum iwl_fw_dbg_trigger trig_type) 2883 { 2884 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2885 return -EIO; 2886 2887 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2888 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2889 trig_type != FW_DBG_TRIGGER_DRIVER) 2890 return -EIO; 2891 2892 iwl_dbg_tlv_time_point(fwrt, 2893 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2894 NULL); 2895 } else { 2896 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2897 int ret; 2898 2899 iwl_dump_error_desc = 2900 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2901 2902 if (!iwl_dump_error_desc) 2903 return -ENOMEM; 2904 2905 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2906 iwl_dump_error_desc->len = 0; 2907 2908 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2909 false, 0); 2910 if (ret) { 2911 kfree(iwl_dump_error_desc); 2912 return ret; 2913 } 2914 } 2915 2916 iwl_trans_sync_nmi(fwrt->trans); 2917 2918 return 0; 2919 } 2920 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2921 2922 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2923 enum iwl_fw_dbg_trigger trig, 2924 const char *str, size_t len, 2925 struct iwl_fw_dbg_trigger_tlv *trigger) 2926 { 2927 struct iwl_fw_dump_desc *desc; 2928 unsigned int delay = 0; 2929 bool monitor_only = false; 2930 2931 if (trigger) { 2932 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2933 2934 if (!le16_to_cpu(trigger->occurrences)) 2935 return 0; 2936 2937 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2938 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2939 trig); 2940 iwl_force_nmi(fwrt->trans); 2941 return 0; 2942 } 2943 2944 trigger->occurrences = cpu_to_le16(occurrences); 2945 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2946 2947 /* convert msec to usec */ 2948 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2949 } 2950 2951 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC); 2952 if (!desc) 2953 return -ENOMEM; 2954 2955 2956 desc->len = len; 2957 desc->trig_desc.type = cpu_to_le32(trig); 2958 memcpy(desc->trig_desc.data, str, len); 2959 2960 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2961 } 2962 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2963 2964 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2965 struct iwl_fw_dbg_trigger_tlv *trigger, 2966 const char *fmt, ...) 2967 { 2968 int ret, len = 0; 2969 char buf[64]; 2970 2971 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2972 return 0; 2973 2974 if (fmt) { 2975 va_list ap; 2976 2977 buf[sizeof(buf) - 1] = '\0'; 2978 2979 va_start(ap, fmt); 2980 vsnprintf(buf, sizeof(buf), fmt, ap); 2981 va_end(ap); 2982 2983 /* check for truncation */ 2984 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2985 buf[sizeof(buf) - 1] = '\0'; 2986 2987 len = strlen(buf) + 1; 2988 } 2989 2990 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2991 trigger); 2992 2993 if (ret) 2994 return ret; 2995 2996 return 0; 2997 } 2998 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2999 3000 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 3001 { 3002 u8 *ptr; 3003 int ret; 3004 int i; 3005 3006 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 3007 "Invalid configuration %d\n", conf_id)) 3008 return -EINVAL; 3009 3010 /* EARLY START - firmware's configuration is hard coded */ 3011 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 3012 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 3013 conf_id == FW_DBG_START_FROM_ALIVE) 3014 return 0; 3015 3016 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 3017 return -EINVAL; 3018 3019 if (fwrt->dump.conf != FW_DBG_INVALID) 3020 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 3021 fwrt->dump.conf); 3022 3023 /* Send all HCMDs for configuring the FW debug */ 3024 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 3025 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 3026 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 3027 struct iwl_host_cmd hcmd = { 3028 .id = cmd->id, 3029 .len = { le16_to_cpu(cmd->len), }, 3030 .data = { cmd->data, }, 3031 }; 3032 3033 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3034 if (ret) 3035 return ret; 3036 3037 ptr += sizeof(*cmd); 3038 ptr += le16_to_cpu(cmd->len); 3039 } 3040 3041 fwrt->dump.conf = conf_id; 3042 3043 return 0; 3044 } 3045 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 3046 3047 void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt, 3048 u32 timepoint, 3049 u32 timepoint_data) 3050 { 3051 struct iwl_dbg_dump_complete_cmd hcmd_data; 3052 struct iwl_host_cmd hcmd = { 3053 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD), 3054 .data[0] = &hcmd_data, 3055 .len[0] = sizeof(hcmd_data), 3056 }; 3057 3058 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3059 return; 3060 3061 if (fw_has_capa(&fwrt->fw->ucode_capa, 3062 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) { 3063 hcmd_data.tp = cpu_to_le32(timepoint); 3064 hcmd_data.tp_data = cpu_to_le32(timepoint_data); 3065 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3066 } 3067 } 3068 3069 /* this function assumes dump_start was called beforehand and dump_end will be 3070 * called afterwards 3071 */ 3072 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 3073 { 3074 struct iwl_fw_dbg_params params = {0}; 3075 struct iwl_fwrt_dump_data *dump_data = 3076 &fwrt->dump.wks[wk_idx].dump_data; 3077 u32 policy; 3078 u32 time_point; 3079 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 3080 return; 3081 3082 if (!dump_data->trig) { 3083 IWL_ERR(fwrt, "dump trigger data is not set\n"); 3084 goto out; 3085 } 3086 3087 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 3088 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 3089 goto out; 3090 } 3091 3092 /* there's no point in fw dump if the bus is dead */ 3093 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 3094 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 3095 goto out; 3096 } 3097 3098 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 3099 3100 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 3101 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 3102 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 3103 else 3104 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 3105 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 3106 3107 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3108 3109 policy = le32_to_cpu(dump_data->trig->apply_policy); 3110 time_point = le32_to_cpu(dump_data->trig->time_point); 3111 3112 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) { 3113 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n"); 3114 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0); 3115 } 3116 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 3117 iwl_force_nmi(fwrt->trans); 3118 3119 out: 3120 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3121 iwl_fw_error_dump_data_free(dump_data); 3122 } else { 3123 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 3124 dump_data->desc = NULL; 3125 } 3126 3127 clear_bit(wk_idx, &fwrt->dump.active_wks); 3128 } 3129 3130 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 3131 struct iwl_fwrt_dump_data *dump_data, 3132 bool sync) 3133 { 3134 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 3135 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 3136 u32 occur, delay; 3137 unsigned long idx; 3138 3139 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 3140 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 3141 tp_id); 3142 return -EINVAL; 3143 } 3144 3145 delay = le32_to_cpu(trig->dump_delay); 3146 occur = le32_to_cpu(trig->occurrences); 3147 if (!occur) 3148 return 0; 3149 3150 trig->occurrences = cpu_to_le32(--occur); 3151 3152 /* Check there is an available worker. 3153 * ffz return value is undefined if no zero exists, 3154 * so check against ~0UL first. 3155 */ 3156 if (fwrt->dump.active_wks == ~0UL) 3157 return -EBUSY; 3158 3159 idx = ffz(fwrt->dump.active_wks); 3160 3161 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 3162 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 3163 return -EBUSY; 3164 3165 fwrt->dump.wks[idx].dump_data = *dump_data; 3166 3167 if (sync) 3168 delay = 0; 3169 3170 IWL_WARN(fwrt, 3171 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 3172 tp_id, (u32)(delay / USEC_PER_MSEC)); 3173 3174 if (sync) 3175 iwl_fw_dbg_collect_sync(fwrt, idx); 3176 else 3177 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 3178 3179 return 0; 3180 } 3181 3182 void iwl_fw_error_dump_wk(struct work_struct *work) 3183 { 3184 struct iwl_fwrt_wk_data *wks = 3185 container_of(work, typeof(*wks), wk.work); 3186 struct iwl_fw_runtime *fwrt = 3187 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 3188 3189 /* assumes the op mode mutex is locked in dump_start since 3190 * iwl_fw_dbg_collect_sync can't run in parallel 3191 */ 3192 if (fwrt->ops && fwrt->ops->dump_start) 3193 fwrt->ops->dump_start(fwrt->ops_ctx); 3194 3195 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 3196 3197 if (fwrt->ops && fwrt->ops->dump_end) 3198 fwrt->ops->dump_end(fwrt->ops_ctx); 3199 } 3200 3201 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 3202 { 3203 const struct iwl_cfg *cfg = fwrt->trans->cfg; 3204 3205 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 3206 return; 3207 3208 if (!fwrt->dump.d3_debug_data) { 3209 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 3210 GFP_KERNEL); 3211 if (!fwrt->dump.d3_debug_data) { 3212 IWL_ERR(fwrt, 3213 "failed to allocate memory for D3 debug data\n"); 3214 return; 3215 } 3216 } 3217 3218 /* if the buffer holds previous debug data it is overwritten */ 3219 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 3220 fwrt->dump.d3_debug_data, 3221 cfg->d3_debug_data_length); 3222 3223 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 3224 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 3225 cfg->d3_debug_data_base_addr, 3226 fwrt->dump.d3_debug_data, 3227 cfg->d3_debug_data_length); 3228 } 3229 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 3230 3231 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 3232 { 3233 int i; 3234 3235 iwl_dbg_tlv_del_timers(fwrt->trans); 3236 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 3237 iwl_fw_dbg_collect_sync(fwrt, i); 3238 3239 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 3240 } 3241 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 3242 3243 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 3244 { 3245 struct iwl_dbg_suspend_resume_cmd cmd = { 3246 .operation = suspend ? 3247 cpu_to_le32(DBGC_SUSPEND_CMD) : 3248 cpu_to_le32(DBGC_RESUME_CMD), 3249 }; 3250 struct iwl_host_cmd hcmd = { 3251 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3252 .data[0] = &cmd, 3253 .len[0] = sizeof(cmd), 3254 }; 3255 3256 return iwl_trans_send_cmd(trans, &hcmd); 3257 } 3258 3259 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3260 struct iwl_fw_dbg_params *params) 3261 { 3262 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3263 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3264 return; 3265 } 3266 3267 if (params) { 3268 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3269 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3270 } 3271 3272 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3273 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3274 * avoid halting the HW while writing 3275 */ 3276 usleep_range(700, 1000); 3277 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3278 } 3279 3280 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3281 struct iwl_fw_dbg_params *params) 3282 { 3283 if (!params) 3284 return -EIO; 3285 3286 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3287 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3288 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3289 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3290 } else { 3291 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3292 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3293 } 3294 3295 return 0; 3296 } 3297 3298 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt) 3299 { 3300 struct iwl_mvm_marker marker = { 3301 .dw_len = sizeof(struct iwl_mvm_marker) / 4, 3302 .marker_id = MARKER_ID_SYNC_CLOCK, 3303 }; 3304 struct iwl_host_cmd hcmd = { 3305 .flags = CMD_ASYNC, 3306 .id = WIDE_ID(LONG_GROUP, MARKER_CMD), 3307 .dataflags = {}, 3308 }; 3309 struct iwl_mvm_marker_rsp *resp; 3310 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw, 3311 WIDE_ID(LONG_GROUP, MARKER_CMD), 3312 IWL_FW_CMD_VER_UNKNOWN); 3313 int ret; 3314 3315 if (cmd_ver == 1) { 3316 /* the real timestamp is taken from the ftrace clock 3317 * this is for finding the match between fw and kernel logs 3318 */ 3319 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++); 3320 } else if (cmd_ver == 2) { 3321 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns()); 3322 } else { 3323 IWL_DEBUG_INFO(fwrt, 3324 "Invalid version of Marker CMD. Ver = %d\n", 3325 cmd_ver); 3326 return -EINVAL; 3327 } 3328 3329 hcmd.data[0] = ▮ 3330 hcmd.len[0] = sizeof(marker); 3331 3332 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3333 3334 if (cmd_ver > 1 && hcmd.resp_pkt) { 3335 resp = (void *)hcmd.resp_pkt->data; 3336 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n", 3337 le32_to_cpu(resp->gp2)); 3338 } 3339 3340 return ret; 3341 } 3342 3343 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3344 struct iwl_fw_dbg_params *params, 3345 bool stop) 3346 { 3347 int ret __maybe_unused = 0; 3348 3349 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3350 return; 3351 3352 if (fw_has_capa(&fwrt->fw->ucode_capa, 3353 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) { 3354 if (stop) 3355 iwl_fw_send_timestamp_marker_cmd(fwrt); 3356 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3357 } else if (stop) { 3358 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3359 } else { 3360 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3361 } 3362 #ifdef CONFIG_IWLWIFI_DEBUGFS 3363 if (!ret) { 3364 if (stop) 3365 fwrt->trans->dbg.rec_on = false; 3366 else 3367 iwl_fw_set_dbg_rec_on(fwrt); 3368 } 3369 #endif 3370 } 3371 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3372 3373 void iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime *fwrt) 3374 { 3375 struct iwl_fw_dbg_config_cmd cmd = { 3376 .type = cpu_to_le32(DEBUG_TOKEN_CONFIG_TYPE), 3377 .conf = cpu_to_le32(IWL_FW_DBG_CONFIG_TOKEN), 3378 }; 3379 struct iwl_host_cmd hcmd = { 3380 .id = WIDE_ID(LONG_GROUP, LDBG_CONFIG_CMD), 3381 .data[0] = &cmd, 3382 .len[0] = sizeof(cmd), 3383 }; 3384 u32 preset = u32_get_bits(fwrt->trans->dbg.domains_bitmap, 3385 GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1)); 3386 3387 /* supported starting from 9000 devices */ 3388 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000) 3389 return; 3390 3391 if (fwrt->trans->dbg.yoyo_bin_loaded || (preset && preset != 1)) 3392 return; 3393 3394 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3395 } 3396 IWL_EXPORT_SYMBOL(iwl_fw_disable_dbg_asserts); 3397 3398 void iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime *fwrt) 3399 { 3400 struct iwl_fw_dbg_params params = {0}; 3401 3402 iwl_fw_dbg_stop_sync(fwrt); 3403 3404 if (fw_has_api(&fwrt->fw->ucode_capa, 3405 IWL_UCODE_TLV_API_INT_DBG_BUF_CLEAR)) { 3406 struct iwl_host_cmd hcmd = { 3407 .id = WIDE_ID(DEBUG_GROUP, FW_CLEAR_BUFFER), 3408 }; 3409 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3410 } 3411 3412 iwl_dbg_tlv_init_cfg(fwrt); 3413 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3414 } 3415 IWL_EXPORT_SYMBOL(iwl_fw_dbg_clear_monitor_buf); 3416