1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "iwl-fh.h" 16 /** 17 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 18 * 19 * @fwrt_ptr: pointer to the buffer coming from fwrt 20 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 21 * transport's data. 22 * @fwrt_len: length of the valid data in fwrt_ptr 23 */ 24 struct iwl_fw_dump_ptrs { 25 struct iwl_trans_dump_data *trans_ptr; 26 void *fwrt_ptr; 27 u32 fwrt_len; 28 }; 29 30 #define RADIO_REG_MAX_READ 0x2ad 31 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 32 struct iwl_fw_error_dump_data **dump_data) 33 { 34 u8 *pos = (void *)(*dump_data)->data; 35 int i; 36 37 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 38 39 if (!iwl_trans_grab_nic_access(fwrt->trans)) 40 return; 41 42 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 43 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 44 45 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 46 u32 rd_cmd = RADIO_RSP_RD_CMD; 47 48 rd_cmd |= i << RADIO_RSP_ADDR_POS; 49 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 50 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 51 52 pos++; 53 } 54 55 *dump_data = iwl_fw_error_next_data(*dump_data); 56 57 iwl_trans_release_nic_access(fwrt->trans); 58 } 59 60 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 61 struct iwl_fw_error_dump_data **dump_data, 62 int size, u32 offset, int fifo_num) 63 { 64 struct iwl_fw_error_dump_fifo *fifo_hdr; 65 u32 *fifo_data; 66 u32 fifo_len; 67 int i; 68 69 fifo_hdr = (void *)(*dump_data)->data; 70 fifo_data = (void *)fifo_hdr->data; 71 fifo_len = size; 72 73 /* No need to try to read the data if the length is 0 */ 74 if (fifo_len == 0) 75 return; 76 77 /* Add a TLV for the RXF */ 78 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 79 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 80 81 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 82 fifo_hdr->available_bytes = 83 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 84 RXF_RD_D_SPACE + offset)); 85 fifo_hdr->wr_ptr = 86 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 87 RXF_RD_WR_PTR + offset)); 88 fifo_hdr->rd_ptr = 89 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 90 RXF_RD_RD_PTR + offset)); 91 fifo_hdr->fence_ptr = 92 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 93 RXF_RD_FENCE_PTR + offset)); 94 fifo_hdr->fence_mode = 95 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 96 RXF_SET_FENCE_MODE + offset)); 97 98 /* Lock fence */ 99 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 100 /* Set fence pointer to the same place like WR pointer */ 101 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 102 /* Set fence offset */ 103 iwl_trans_write_prph(fwrt->trans, 104 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 105 106 /* Read FIFO */ 107 fifo_len /= sizeof(u32); /* Size in DWORDS */ 108 for (i = 0; i < fifo_len; i++) 109 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 110 RXF_FIFO_RD_FENCE_INC + 111 offset); 112 *dump_data = iwl_fw_error_next_data(*dump_data); 113 } 114 115 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 116 struct iwl_fw_error_dump_data **dump_data, 117 int size, u32 offset, int fifo_num) 118 { 119 struct iwl_fw_error_dump_fifo *fifo_hdr; 120 u32 *fifo_data; 121 u32 fifo_len; 122 int i; 123 124 fifo_hdr = (void *)(*dump_data)->data; 125 fifo_data = (void *)fifo_hdr->data; 126 fifo_len = size; 127 128 /* No need to try to read the data if the length is 0 */ 129 if (fifo_len == 0) 130 return; 131 132 /* Add a TLV for the FIFO */ 133 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 134 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 135 136 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 137 fifo_hdr->available_bytes = 138 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 139 TXF_FIFO_ITEM_CNT + offset)); 140 fifo_hdr->wr_ptr = 141 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 142 TXF_WR_PTR + offset)); 143 fifo_hdr->rd_ptr = 144 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 145 TXF_RD_PTR + offset)); 146 fifo_hdr->fence_ptr = 147 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 148 TXF_FENCE_PTR + offset)); 149 fifo_hdr->fence_mode = 150 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 151 TXF_LOCK_FENCE + offset)); 152 153 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 154 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 155 TXF_WR_PTR + offset); 156 157 /* Dummy-read to advance the read pointer to the head */ 158 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 159 160 /* Read FIFO */ 161 for (i = 0; i < fifo_len / sizeof(u32); i++) 162 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 163 TXF_READ_MODIFY_DATA + 164 offset); 165 166 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 167 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 168 fifo_data, fifo_len); 169 170 *dump_data = iwl_fw_error_next_data(*dump_data); 171 } 172 173 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 174 struct iwl_fw_error_dump_data **dump_data) 175 { 176 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 177 178 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 179 180 if (!iwl_trans_grab_nic_access(fwrt->trans)) 181 return; 182 183 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 184 /* Pull RXF1 */ 185 iwl_fwrt_dump_rxf(fwrt, dump_data, 186 cfg->lmac[0].rxfifo1_size, 0, 0); 187 /* Pull RXF2 */ 188 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 189 RXF_DIFF_FROM_PREV + 190 fwrt->trans->trans_cfg->umac_prph_offset, 1); 191 /* Pull LMAC2 RXF1 */ 192 if (fwrt->smem_cfg.num_lmacs > 1) 193 iwl_fwrt_dump_rxf(fwrt, dump_data, 194 cfg->lmac[1].rxfifo1_size, 195 LMAC2_PRPH_OFFSET, 2); 196 } 197 198 iwl_trans_release_nic_access(fwrt->trans); 199 } 200 201 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 202 struct iwl_fw_error_dump_data **dump_data) 203 { 204 struct iwl_fw_error_dump_fifo *fifo_hdr; 205 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 206 u32 *fifo_data; 207 u32 fifo_len; 208 int i, j; 209 210 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 211 212 if (!iwl_trans_grab_nic_access(fwrt->trans)) 213 return; 214 215 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 216 /* Pull TXF data from LMAC1 */ 217 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 218 /* Mark the number of TXF we're pulling now */ 219 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 220 iwl_fwrt_dump_txf(fwrt, dump_data, 221 cfg->lmac[0].txfifo_size[i], 0, i); 222 } 223 224 /* Pull TXF data from LMAC2 */ 225 if (fwrt->smem_cfg.num_lmacs > 1) { 226 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 227 i++) { 228 /* Mark the number of TXF we're pulling now */ 229 iwl_trans_write_prph(fwrt->trans, 230 TXF_LARC_NUM + 231 LMAC2_PRPH_OFFSET, i); 232 iwl_fwrt_dump_txf(fwrt, dump_data, 233 cfg->lmac[1].txfifo_size[i], 234 LMAC2_PRPH_OFFSET, 235 i + cfg->num_txfifo_entries); 236 } 237 } 238 } 239 240 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 241 fw_has_capa(&fwrt->fw->ucode_capa, 242 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 243 /* Pull UMAC internal TXF data from all TXFs */ 244 for (i = 0; 245 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 246 i++) { 247 fifo_hdr = (void *)(*dump_data)->data; 248 fifo_data = (void *)fifo_hdr->data; 249 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 250 251 /* No need to try to read the data if the length is 0 */ 252 if (fifo_len == 0) 253 continue; 254 255 /* Add a TLV for the internal FIFOs */ 256 (*dump_data)->type = 257 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 258 (*dump_data)->len = 259 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 260 261 fifo_hdr->fifo_num = cpu_to_le32(i); 262 263 /* Mark the number of TXF we're pulling now */ 264 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 265 fwrt->smem_cfg.num_txfifo_entries); 266 267 fifo_hdr->available_bytes = 268 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 269 TXF_CPU2_FIFO_ITEM_CNT)); 270 fifo_hdr->wr_ptr = 271 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 272 TXF_CPU2_WR_PTR)); 273 fifo_hdr->rd_ptr = 274 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 275 TXF_CPU2_RD_PTR)); 276 fifo_hdr->fence_ptr = 277 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 278 TXF_CPU2_FENCE_PTR)); 279 fifo_hdr->fence_mode = 280 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 281 TXF_CPU2_LOCK_FENCE)); 282 283 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 284 iwl_trans_write_prph(fwrt->trans, 285 TXF_CPU2_READ_MODIFY_ADDR, 286 TXF_CPU2_WR_PTR); 287 288 /* Dummy-read to advance the read pointer to head */ 289 iwl_trans_read_prph(fwrt->trans, 290 TXF_CPU2_READ_MODIFY_DATA); 291 292 /* Read FIFO */ 293 fifo_len /= sizeof(u32); /* Size in DWORDS */ 294 for (j = 0; j < fifo_len; j++) 295 fifo_data[j] = 296 iwl_trans_read_prph(fwrt->trans, 297 TXF_CPU2_READ_MODIFY_DATA); 298 *dump_data = iwl_fw_error_next_data(*dump_data); 299 } 300 } 301 302 iwl_trans_release_nic_access(fwrt->trans); 303 } 304 305 struct iwl_prph_range { 306 u32 start, end; 307 }; 308 309 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 310 { .start = 0x00a00000, .end = 0x00a00000 }, 311 { .start = 0x00a0000c, .end = 0x00a00024 }, 312 { .start = 0x00a0002c, .end = 0x00a0003c }, 313 { .start = 0x00a00410, .end = 0x00a00418 }, 314 { .start = 0x00a00420, .end = 0x00a00420 }, 315 { .start = 0x00a00428, .end = 0x00a00428 }, 316 { .start = 0x00a00430, .end = 0x00a0043c }, 317 { .start = 0x00a00444, .end = 0x00a00444 }, 318 { .start = 0x00a004c0, .end = 0x00a004cc }, 319 { .start = 0x00a004d8, .end = 0x00a004d8 }, 320 { .start = 0x00a004e0, .end = 0x00a004f0 }, 321 { .start = 0x00a00840, .end = 0x00a00840 }, 322 { .start = 0x00a00850, .end = 0x00a00858 }, 323 { .start = 0x00a01004, .end = 0x00a01008 }, 324 { .start = 0x00a01010, .end = 0x00a01010 }, 325 { .start = 0x00a01018, .end = 0x00a01018 }, 326 { .start = 0x00a01024, .end = 0x00a01024 }, 327 { .start = 0x00a0102c, .end = 0x00a01034 }, 328 { .start = 0x00a0103c, .end = 0x00a01040 }, 329 { .start = 0x00a01048, .end = 0x00a01094 }, 330 { .start = 0x00a01c00, .end = 0x00a01c20 }, 331 { .start = 0x00a01c58, .end = 0x00a01c58 }, 332 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 333 { .start = 0x00a01c28, .end = 0x00a01c54 }, 334 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 335 { .start = 0x00a01c60, .end = 0x00a01cdc }, 336 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 337 { .start = 0x00a01d18, .end = 0x00a01d20 }, 338 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 339 { .start = 0x00a01d40, .end = 0x00a01d5c }, 340 { .start = 0x00a01d80, .end = 0x00a01d80 }, 341 { .start = 0x00a01d98, .end = 0x00a01d9c }, 342 { .start = 0x00a01da8, .end = 0x00a01da8 }, 343 { .start = 0x00a01db8, .end = 0x00a01df4 }, 344 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 345 { .start = 0x00a01e00, .end = 0x00a01e2c }, 346 { .start = 0x00a01e40, .end = 0x00a01e60 }, 347 { .start = 0x00a01e68, .end = 0x00a01e6c }, 348 { .start = 0x00a01e74, .end = 0x00a01e74 }, 349 { .start = 0x00a01e84, .end = 0x00a01e90 }, 350 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 351 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 352 { .start = 0x00a01f00, .end = 0x00a01f1c }, 353 { .start = 0x00a01f44, .end = 0x00a01ffc }, 354 { .start = 0x00a02000, .end = 0x00a02048 }, 355 { .start = 0x00a02068, .end = 0x00a020f0 }, 356 { .start = 0x00a02100, .end = 0x00a02118 }, 357 { .start = 0x00a02140, .end = 0x00a0214c }, 358 { .start = 0x00a02168, .end = 0x00a0218c }, 359 { .start = 0x00a021c0, .end = 0x00a021c0 }, 360 { .start = 0x00a02400, .end = 0x00a02410 }, 361 { .start = 0x00a02418, .end = 0x00a02420 }, 362 { .start = 0x00a02428, .end = 0x00a0242c }, 363 { .start = 0x00a02434, .end = 0x00a02434 }, 364 { .start = 0x00a02440, .end = 0x00a02460 }, 365 { .start = 0x00a02468, .end = 0x00a024b0 }, 366 { .start = 0x00a024c8, .end = 0x00a024cc }, 367 { .start = 0x00a02500, .end = 0x00a02504 }, 368 { .start = 0x00a0250c, .end = 0x00a02510 }, 369 { .start = 0x00a02540, .end = 0x00a02554 }, 370 { .start = 0x00a02580, .end = 0x00a025f4 }, 371 { .start = 0x00a02600, .end = 0x00a0260c }, 372 { .start = 0x00a02648, .end = 0x00a02650 }, 373 { .start = 0x00a02680, .end = 0x00a02680 }, 374 { .start = 0x00a026c0, .end = 0x00a026d0 }, 375 { .start = 0x00a02700, .end = 0x00a0270c }, 376 { .start = 0x00a02804, .end = 0x00a02804 }, 377 { .start = 0x00a02818, .end = 0x00a0281c }, 378 { .start = 0x00a02c00, .end = 0x00a02db4 }, 379 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 380 { .start = 0x00a03000, .end = 0x00a03014 }, 381 { .start = 0x00a0301c, .end = 0x00a0302c }, 382 { .start = 0x00a03034, .end = 0x00a03038 }, 383 { .start = 0x00a03040, .end = 0x00a03048 }, 384 { .start = 0x00a03060, .end = 0x00a03068 }, 385 { .start = 0x00a03070, .end = 0x00a03074 }, 386 { .start = 0x00a0307c, .end = 0x00a0307c }, 387 { .start = 0x00a03080, .end = 0x00a03084 }, 388 { .start = 0x00a0308c, .end = 0x00a03090 }, 389 { .start = 0x00a03098, .end = 0x00a03098 }, 390 { .start = 0x00a030a0, .end = 0x00a030a0 }, 391 { .start = 0x00a030a8, .end = 0x00a030b4 }, 392 { .start = 0x00a030bc, .end = 0x00a030bc }, 393 { .start = 0x00a030c0, .end = 0x00a0312c }, 394 { .start = 0x00a03c00, .end = 0x00a03c5c }, 395 { .start = 0x00a04400, .end = 0x00a04454 }, 396 { .start = 0x00a04460, .end = 0x00a04474 }, 397 { .start = 0x00a044c0, .end = 0x00a044ec }, 398 { .start = 0x00a04500, .end = 0x00a04504 }, 399 { .start = 0x00a04510, .end = 0x00a04538 }, 400 { .start = 0x00a04540, .end = 0x00a04548 }, 401 { .start = 0x00a04560, .end = 0x00a0457c }, 402 { .start = 0x00a04590, .end = 0x00a04598 }, 403 { .start = 0x00a045c0, .end = 0x00a045f4 }, 404 }; 405 406 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 407 { .start = 0x00a05c00, .end = 0x00a05c18 }, 408 { .start = 0x00a05400, .end = 0x00a056e8 }, 409 { .start = 0x00a08000, .end = 0x00a098bc }, 410 { .start = 0x00a02400, .end = 0x00a02758 }, 411 { .start = 0x00a04764, .end = 0x00a0476c }, 412 { .start = 0x00a04770, .end = 0x00a04774 }, 413 { .start = 0x00a04620, .end = 0x00a04624 }, 414 }; 415 416 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 417 { .start = 0x00a00000, .end = 0x00a00000 }, 418 { .start = 0x00a0000c, .end = 0x00a00024 }, 419 { .start = 0x00a0002c, .end = 0x00a00034 }, 420 { .start = 0x00a0003c, .end = 0x00a0003c }, 421 { .start = 0x00a00410, .end = 0x00a00418 }, 422 { .start = 0x00a00420, .end = 0x00a00420 }, 423 { .start = 0x00a00428, .end = 0x00a00428 }, 424 { .start = 0x00a00430, .end = 0x00a0043c }, 425 { .start = 0x00a00444, .end = 0x00a00444 }, 426 { .start = 0x00a00840, .end = 0x00a00840 }, 427 { .start = 0x00a00850, .end = 0x00a00858 }, 428 { .start = 0x00a01004, .end = 0x00a01008 }, 429 { .start = 0x00a01010, .end = 0x00a01010 }, 430 { .start = 0x00a01018, .end = 0x00a01018 }, 431 { .start = 0x00a01024, .end = 0x00a01024 }, 432 { .start = 0x00a0102c, .end = 0x00a01034 }, 433 { .start = 0x00a0103c, .end = 0x00a01040 }, 434 { .start = 0x00a01048, .end = 0x00a01050 }, 435 { .start = 0x00a01058, .end = 0x00a01058 }, 436 { .start = 0x00a01060, .end = 0x00a01070 }, 437 { .start = 0x00a0108c, .end = 0x00a0108c }, 438 { .start = 0x00a01c20, .end = 0x00a01c28 }, 439 { .start = 0x00a01d10, .end = 0x00a01d10 }, 440 { .start = 0x00a01e28, .end = 0x00a01e2c }, 441 { .start = 0x00a01e60, .end = 0x00a01e60 }, 442 { .start = 0x00a01e80, .end = 0x00a01e80 }, 443 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 444 { .start = 0x00a02000, .end = 0x00a0201c }, 445 { .start = 0x00a02024, .end = 0x00a02024 }, 446 { .start = 0x00a02040, .end = 0x00a02048 }, 447 { .start = 0x00a020c0, .end = 0x00a020e0 }, 448 { .start = 0x00a02400, .end = 0x00a02404 }, 449 { .start = 0x00a0240c, .end = 0x00a02414 }, 450 { .start = 0x00a0241c, .end = 0x00a0243c }, 451 { .start = 0x00a02448, .end = 0x00a024bc }, 452 { .start = 0x00a024c4, .end = 0x00a024cc }, 453 { .start = 0x00a02508, .end = 0x00a02508 }, 454 { .start = 0x00a02510, .end = 0x00a02514 }, 455 { .start = 0x00a0251c, .end = 0x00a0251c }, 456 { .start = 0x00a0252c, .end = 0x00a0255c }, 457 { .start = 0x00a02564, .end = 0x00a025a0 }, 458 { .start = 0x00a025a8, .end = 0x00a025b4 }, 459 { .start = 0x00a025c0, .end = 0x00a025c0 }, 460 { .start = 0x00a025e8, .end = 0x00a025f4 }, 461 { .start = 0x00a02c08, .end = 0x00a02c18 }, 462 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 463 { .start = 0x00a02c68, .end = 0x00a02c78 }, 464 { .start = 0x00a03000, .end = 0x00a03000 }, 465 { .start = 0x00a03010, .end = 0x00a03014 }, 466 { .start = 0x00a0301c, .end = 0x00a0302c }, 467 { .start = 0x00a03034, .end = 0x00a03038 }, 468 { .start = 0x00a03040, .end = 0x00a03044 }, 469 { .start = 0x00a03060, .end = 0x00a03068 }, 470 { .start = 0x00a03070, .end = 0x00a03070 }, 471 { .start = 0x00a0307c, .end = 0x00a03084 }, 472 { .start = 0x00a0308c, .end = 0x00a03090 }, 473 { .start = 0x00a03098, .end = 0x00a03098 }, 474 { .start = 0x00a030a0, .end = 0x00a030a0 }, 475 { .start = 0x00a030a8, .end = 0x00a030b4 }, 476 { .start = 0x00a030bc, .end = 0x00a030c0 }, 477 { .start = 0x00a030c8, .end = 0x00a030f4 }, 478 { .start = 0x00a03100, .end = 0x00a0312c }, 479 { .start = 0x00a03c00, .end = 0x00a03c5c }, 480 { .start = 0x00a04400, .end = 0x00a04454 }, 481 { .start = 0x00a04460, .end = 0x00a04474 }, 482 { .start = 0x00a044c0, .end = 0x00a044ec }, 483 { .start = 0x00a04500, .end = 0x00a04504 }, 484 { .start = 0x00a04510, .end = 0x00a04538 }, 485 { .start = 0x00a04540, .end = 0x00a04548 }, 486 { .start = 0x00a04560, .end = 0x00a04560 }, 487 { .start = 0x00a04570, .end = 0x00a0457c }, 488 { .start = 0x00a04590, .end = 0x00a04590 }, 489 { .start = 0x00a04598, .end = 0x00a04598 }, 490 { .start = 0x00a045c0, .end = 0x00a045f4 }, 491 { .start = 0x00a05c18, .end = 0x00a05c1c }, 492 { .start = 0x00a0c000, .end = 0x00a0c018 }, 493 { .start = 0x00a0c020, .end = 0x00a0c028 }, 494 { .start = 0x00a0c038, .end = 0x00a0c094 }, 495 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 496 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 497 { .start = 0x00a0c150, .end = 0x00a0c174 }, 498 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 499 { .start = 0x00a0c190, .end = 0x00a0c198 }, 500 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 501 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 502 }; 503 504 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 505 { .start = 0x00d03c00, .end = 0x00d03c64 }, 506 { .start = 0x00d05c18, .end = 0x00d05c1c }, 507 { .start = 0x00d0c000, .end = 0x00d0c174 }, 508 }; 509 510 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 511 u32 len_bytes, __le32 *data) 512 { 513 u32 i; 514 515 for (i = 0; i < len_bytes; i += 4) 516 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 517 } 518 519 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 520 const struct iwl_prph_range *iwl_prph_dump_addr, 521 u32 range_len, void *ptr) 522 { 523 struct iwl_fw_error_dump_prph *prph; 524 struct iwl_trans *trans = fwrt->trans; 525 struct iwl_fw_error_dump_data **data = 526 (struct iwl_fw_error_dump_data **)ptr; 527 u32 i; 528 529 if (!data) 530 return; 531 532 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 533 534 if (!iwl_trans_grab_nic_access(trans)) 535 return; 536 537 for (i = 0; i < range_len; i++) { 538 /* The range includes both boundaries */ 539 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 540 iwl_prph_dump_addr[i].start + 4; 541 542 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 543 (*data)->len = cpu_to_le32(sizeof(*prph) + 544 num_bytes_in_chunk); 545 prph = (void *)(*data)->data; 546 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 547 548 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 549 /* our range is inclusive, hence + 4 */ 550 iwl_prph_dump_addr[i].end - 551 iwl_prph_dump_addr[i].start + 4, 552 (void *)prph->data); 553 554 *data = iwl_fw_error_next_data(*data); 555 } 556 557 iwl_trans_release_nic_access(trans); 558 } 559 560 /* 561 * alloc_sgtable - allocates scallerlist table in the given size, 562 * fills it with pages and returns it 563 * @size: the size (in bytes) of the table 564 */ 565 static struct scatterlist *alloc_sgtable(int size) 566 { 567 int alloc_size, nents, i; 568 struct page *new_page; 569 struct scatterlist *iter; 570 struct scatterlist *table; 571 572 nents = DIV_ROUND_UP(size, PAGE_SIZE); 573 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 574 if (!table) 575 return NULL; 576 sg_init_table(table, nents); 577 iter = table; 578 for_each_sg(table, iter, sg_nents(table), i) { 579 new_page = alloc_page(GFP_KERNEL); 580 if (!new_page) { 581 /* release all previous allocated pages in the table */ 582 iter = table; 583 for_each_sg(table, iter, sg_nents(table), i) { 584 new_page = sg_page(iter); 585 if (new_page) 586 __free_page(new_page); 587 } 588 kfree(table); 589 return NULL; 590 } 591 alloc_size = min_t(int, size, PAGE_SIZE); 592 size -= PAGE_SIZE; 593 sg_set_page(iter, new_page, alloc_size, 0); 594 } 595 return table; 596 } 597 598 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 599 const struct iwl_prph_range *iwl_prph_dump_addr, 600 u32 range_len, void *ptr) 601 { 602 u32 *prph_len = (u32 *)ptr; 603 int i, num_bytes_in_chunk; 604 605 if (!prph_len) 606 return; 607 608 for (i = 0; i < range_len; i++) { 609 /* The range includes both boundaries */ 610 num_bytes_in_chunk = 611 iwl_prph_dump_addr[i].end - 612 iwl_prph_dump_addr[i].start + 4; 613 614 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 615 sizeof(struct iwl_fw_error_dump_prph) + 616 num_bytes_in_chunk; 617 } 618 } 619 620 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 621 void (*handler)(struct iwl_fw_runtime *, 622 const struct iwl_prph_range *, 623 u32, void *)) 624 { 625 u32 range_len; 626 627 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 628 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 629 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 630 } else if (fwrt->trans->trans_cfg->device_family >= 631 IWL_DEVICE_FAMILY_22000) { 632 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 633 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 634 } else { 635 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 636 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 637 638 if (fwrt->trans->trans_cfg->mq_rx_supported) { 639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 640 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 641 } 642 } 643 } 644 645 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 646 struct iwl_fw_error_dump_data **dump_data, 647 u32 len, u32 ofs, u32 type) 648 { 649 struct iwl_fw_error_dump_mem *dump_mem; 650 651 if (!len) 652 return; 653 654 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 655 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 656 dump_mem = (void *)(*dump_data)->data; 657 dump_mem->type = cpu_to_le32(type); 658 dump_mem->offset = cpu_to_le32(ofs); 659 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 660 *dump_data = iwl_fw_error_next_data(*dump_data); 661 662 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 663 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 664 dump_mem->data, len); 665 666 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 667 } 668 669 #define ADD_LEN(len, item_len, const_len) \ 670 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 671 while (0) 672 673 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 674 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 675 { 676 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 677 sizeof(struct iwl_fw_error_dump_fifo); 678 u32 fifo_len = 0; 679 int i; 680 681 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 682 return 0; 683 684 /* Count RXF2 size */ 685 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 686 687 /* Count RXF1 sizes */ 688 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 689 mem_cfg->num_lmacs = MAX_NUM_LMAC; 690 691 for (i = 0; i < mem_cfg->num_lmacs; i++) 692 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 693 694 return fifo_len; 695 } 696 697 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 698 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 699 { 700 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 701 sizeof(struct iwl_fw_error_dump_fifo); 702 u32 fifo_len = 0; 703 int i; 704 705 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 706 goto dump_internal_txf; 707 708 /* Count TXF sizes */ 709 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 710 mem_cfg->num_lmacs = MAX_NUM_LMAC; 711 712 for (i = 0; i < mem_cfg->num_lmacs; i++) { 713 int j; 714 715 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 716 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 717 hdr_len); 718 } 719 720 dump_internal_txf: 721 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 722 fw_has_capa(&fwrt->fw->ucode_capa, 723 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 724 goto out; 725 726 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 727 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 728 729 out: 730 return fifo_len; 731 } 732 733 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 734 struct iwl_fw_error_dump_data **data) 735 { 736 int i; 737 738 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 739 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 740 struct iwl_fw_error_dump_paging *paging; 741 struct page *pages = 742 fwrt->fw_paging_db[i].fw_paging_block; 743 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 744 745 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 746 (*data)->len = cpu_to_le32(sizeof(*paging) + 747 PAGING_BLOCK_SIZE); 748 paging = (void *)(*data)->data; 749 paging->index = cpu_to_le32(i); 750 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 751 PAGING_BLOCK_SIZE, 752 DMA_BIDIRECTIONAL); 753 memcpy(paging->data, page_address(pages), 754 PAGING_BLOCK_SIZE); 755 dma_sync_single_for_device(fwrt->trans->dev, addr, 756 PAGING_BLOCK_SIZE, 757 DMA_BIDIRECTIONAL); 758 (*data) = iwl_fw_error_next_data(*data); 759 760 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 761 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 762 fwrt->fw_paging_db[i].fw_offs, 763 paging->data, 764 PAGING_BLOCK_SIZE); 765 } 766 } 767 768 static struct iwl_fw_error_dump_file * 769 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 770 struct iwl_fw_dump_ptrs *fw_error_dump, 771 struct iwl_fwrt_dump_data *data) 772 { 773 struct iwl_fw_error_dump_file *dump_file; 774 struct iwl_fw_error_dump_data *dump_data; 775 struct iwl_fw_error_dump_info *dump_info; 776 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 777 struct iwl_fw_error_dump_trigger_desc *dump_trig; 778 u32 sram_len, sram_ofs; 779 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 780 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 781 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 782 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 783 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 784 0 : fwrt->trans->cfg->dccm2_len; 785 int i; 786 787 /* SRAM - include stack CCM if driver knows the values for it */ 788 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 789 const struct fw_img *img; 790 791 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 792 return NULL; 793 img = &fwrt->fw->img[fwrt->cur_fw_img]; 794 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 795 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 796 } else { 797 sram_ofs = fwrt->trans->cfg->dccm_offset; 798 sram_len = fwrt->trans->cfg->dccm_len; 799 } 800 801 /* reading RXF/TXF sizes */ 802 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 803 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 804 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 805 806 /* Make room for PRPH registers */ 807 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 808 iwl_fw_prph_handler(fwrt, &prph_len, 809 iwl_fw_get_prph_len); 810 811 if (fwrt->trans->trans_cfg->device_family == 812 IWL_DEVICE_FAMILY_7000 && 813 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 814 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 815 } 816 817 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 818 819 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 820 file_len += sizeof(*dump_data) + sizeof(*dump_info); 821 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 822 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 823 824 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 825 size_t hdr_len = sizeof(*dump_data) + 826 sizeof(struct iwl_fw_error_dump_mem); 827 828 /* Dump SRAM only if no mem_tlvs */ 829 if (!fwrt->fw->dbg.n_mem_tlv) 830 ADD_LEN(file_len, sram_len, hdr_len); 831 832 /* Make room for all mem types that exist */ 833 ADD_LEN(file_len, smem_len, hdr_len); 834 ADD_LEN(file_len, sram2_len, hdr_len); 835 836 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 837 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 838 } 839 840 /* Make room for fw's virtual image pages, if it exists */ 841 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 842 file_len += fwrt->num_of_paging_blk * 843 (sizeof(*dump_data) + 844 sizeof(struct iwl_fw_error_dump_paging) + 845 PAGING_BLOCK_SIZE); 846 847 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 848 file_len += sizeof(*dump_data) + 849 fwrt->trans->cfg->d3_debug_data_length * 2; 850 } 851 852 /* If we only want a monitor dump, reset the file length */ 853 if (data->monitor_only) { 854 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 855 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 856 } 857 858 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 859 data->desc) 860 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 861 data->desc->len; 862 863 dump_file = vzalloc(file_len); 864 if (!dump_file) 865 return NULL; 866 867 fw_error_dump->fwrt_ptr = dump_file; 868 869 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 870 dump_data = (void *)dump_file->data; 871 872 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 873 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 874 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 875 dump_info = (void *)dump_data->data; 876 dump_info->hw_type = 877 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 878 dump_info->hw_step = 879 cpu_to_le32(fwrt->trans->hw_rev_step); 880 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 881 sizeof(dump_info->fw_human_readable)); 882 strscpy_pad(dump_info->dev_human_readable, fwrt->trans->name, 883 sizeof(dump_info->dev_human_readable)); 884 strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name, 885 sizeof(dump_info->bus_human_readable)); 886 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 887 dump_info->lmac_err_id[0] = 888 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 889 if (fwrt->smem_cfg.num_lmacs > 1) 890 dump_info->lmac_err_id[1] = 891 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 892 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 893 894 dump_data = iwl_fw_error_next_data(dump_data); 895 } 896 897 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 898 /* Dump shared memory configuration */ 899 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 900 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 901 dump_smem_cfg = (void *)dump_data->data; 902 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 903 dump_smem_cfg->num_txfifo_entries = 904 cpu_to_le32(mem_cfg->num_txfifo_entries); 905 for (i = 0; i < MAX_NUM_LMAC; i++) { 906 int j; 907 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 908 909 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 910 dump_smem_cfg->lmac[i].txfifo_size[j] = 911 cpu_to_le32(txf_size[j]); 912 dump_smem_cfg->lmac[i].rxfifo1_size = 913 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 914 } 915 dump_smem_cfg->rxfifo2_size = 916 cpu_to_le32(mem_cfg->rxfifo2_size); 917 dump_smem_cfg->internal_txfifo_addr = 918 cpu_to_le32(mem_cfg->internal_txfifo_addr); 919 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 920 dump_smem_cfg->internal_txfifo_size[i] = 921 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 922 } 923 924 dump_data = iwl_fw_error_next_data(dump_data); 925 } 926 927 /* We only dump the FIFOs if the FW is in error state */ 928 if (fifo_len) { 929 iwl_fw_dump_rxf(fwrt, &dump_data); 930 iwl_fw_dump_txf(fwrt, &dump_data); 931 } 932 933 if (radio_len) 934 iwl_read_radio_regs(fwrt, &dump_data); 935 936 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 937 data->desc) { 938 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 939 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 940 data->desc->len); 941 dump_trig = (void *)dump_data->data; 942 memcpy(dump_trig, &data->desc->trig_desc, 943 sizeof(*dump_trig) + data->desc->len); 944 945 dump_data = iwl_fw_error_next_data(dump_data); 946 } 947 948 /* In case we only want monitor dump, skip to dump trasport data */ 949 if (data->monitor_only) 950 goto out; 951 952 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 953 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 954 fwrt->fw->dbg.mem_tlv; 955 956 if (!fwrt->fw->dbg.n_mem_tlv) 957 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 958 IWL_FW_ERROR_DUMP_MEM_SRAM); 959 960 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 961 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 962 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 963 964 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 965 le32_to_cpu(fw_dbg_mem[i].data_type)); 966 } 967 968 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 969 fwrt->trans->cfg->smem_offset, 970 IWL_FW_ERROR_DUMP_MEM_SMEM); 971 972 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 973 fwrt->trans->cfg->dccm2_offset, 974 IWL_FW_ERROR_DUMP_MEM_SRAM); 975 } 976 977 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 978 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 979 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 980 981 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 982 dump_data->len = cpu_to_le32(data_size * 2); 983 984 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 985 986 kfree(fwrt->dump.d3_debug_data); 987 fwrt->dump.d3_debug_data = NULL; 988 989 iwl_trans_read_mem_bytes(fwrt->trans, addr, 990 dump_data->data + data_size, 991 data_size); 992 993 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 994 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 995 dump_data->data + data_size, 996 data_size); 997 998 dump_data = iwl_fw_error_next_data(dump_data); 999 } 1000 1001 /* Dump fw's virtual image */ 1002 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1003 iwl_dump_paging(fwrt, &dump_data); 1004 1005 if (prph_len) 1006 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1007 1008 out: 1009 dump_file->file_len = cpu_to_le32(file_len); 1010 return dump_file; 1011 } 1012 1013 /** 1014 * struct iwl_dump_ini_region_data - region data 1015 * @reg_tlv: region TLV 1016 * @dump_data: dump data 1017 */ 1018 struct iwl_dump_ini_region_data { 1019 struct iwl_ucode_tlv *reg_tlv; 1020 struct iwl_fwrt_dump_data *dump_data; 1021 }; 1022 1023 static int iwl_dump_ini_prph_mac_iter_common(struct iwl_fw_runtime *fwrt, 1024 void *range_ptr, u32 addr, 1025 __le32 size) 1026 { 1027 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1028 __le32 *val = range->data; 1029 int i; 1030 1031 range->internal_base_addr = cpu_to_le32(addr); 1032 range->range_data_size = size; 1033 for (i = 0; i < le32_to_cpu(size); i += 4) 1034 *val++ = cpu_to_le32(iwl_read_prph(fwrt->trans, addr + i)); 1035 1036 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1037 } 1038 1039 static int 1040 iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1041 struct iwl_dump_ini_region_data *reg_data, 1042 void *range_ptr, u32 range_len, int idx) 1043 { 1044 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1045 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1046 le32_to_cpu(reg->dev_addr.offset); 1047 1048 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1049 reg->dev_addr.size); 1050 } 1051 1052 static int 1053 iwl_dump_ini_prph_mac_block_iter(struct iwl_fw_runtime *fwrt, 1054 struct iwl_dump_ini_region_data *reg_data, 1055 void *range_ptr, u32 range_len, int idx) 1056 { 1057 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1058 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1059 u32 addr = le32_to_cpu(reg->dev_addr_range.offset) + 1060 le32_to_cpu(pairs[idx].addr); 1061 1062 return iwl_dump_ini_prph_mac_iter_common(fwrt, range_ptr, addr, 1063 pairs[idx].size); 1064 } 1065 1066 static int iwl_dump_ini_prph_phy_iter_common(struct iwl_fw_runtime *fwrt, 1067 void *range_ptr, u32 addr, 1068 __le32 size, __le32 offset) 1069 { 1070 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1071 __le32 *val = range->data; 1072 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1073 u32 indirect_rd_addr = WMAL_MRSPF_1; 1074 u32 prph_val; 1075 u32 dphy_state; 1076 u32 dphy_addr; 1077 int i; 1078 1079 range->internal_base_addr = cpu_to_le32(addr); 1080 range->range_data_size = size; 1081 1082 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1083 indirect_wr_addr = WMAL_INDRCT_CMD1; 1084 1085 indirect_wr_addr += le32_to_cpu(offset); 1086 indirect_rd_addr += le32_to_cpu(offset); 1087 1088 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1089 return -EBUSY; 1090 1091 dphy_addr = (offset) ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1092 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1093 1094 for (i = 0; i < le32_to_cpu(size); i += 4) { 1095 if (dphy_state == HBUS_TIMEOUT || 1096 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1097 WFPM_PHYRF_STATE_ON) { 1098 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1099 continue; 1100 } 1101 1102 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1103 WMAL_INDRCT_CMD(addr + i)); 1104 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1105 indirect_rd_addr); 1106 *val++ = cpu_to_le32(prph_val); 1107 } 1108 1109 iwl_trans_release_nic_access(fwrt->trans); 1110 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1111 } 1112 1113 static int 1114 iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1115 struct iwl_dump_ini_region_data *reg_data, 1116 void *range_ptr, u32 range_len, int idx) 1117 { 1118 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1119 u32 addr = le32_to_cpu(reg->addrs[idx]); 1120 1121 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1122 reg->dev_addr.size, 1123 reg->dev_addr.offset); 1124 } 1125 1126 static int 1127 iwl_dump_ini_prph_phy_block_iter(struct iwl_fw_runtime *fwrt, 1128 struct iwl_dump_ini_region_data *reg_data, 1129 void *range_ptr, u32 range_len, int idx) 1130 { 1131 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1132 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1133 u32 addr = le32_to_cpu(pairs[idx].addr); 1134 1135 return iwl_dump_ini_prph_phy_iter_common(fwrt, range_ptr, addr, 1136 pairs[idx].size, 1137 reg->dev_addr_range.offset); 1138 } 1139 1140 static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1141 struct iwl_dump_ini_region_data *reg_data, 1142 void *range_ptr, u32 range_len, int idx) 1143 { 1144 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1145 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1146 __le32 *val = range->data; 1147 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1148 le32_to_cpu(reg->dev_addr.offset); 1149 int i; 1150 1151 range->internal_base_addr = cpu_to_le32(addr); 1152 range->range_data_size = reg->dev_addr.size; 1153 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1154 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1155 1156 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1157 } 1158 1159 static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1160 struct iwl_dump_ini_region_data *reg_data, 1161 void *range_ptr, u32 range_len, int idx) 1162 { 1163 struct iwl_trans *trans = fwrt->trans; 1164 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1165 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1166 __le32 *val = range->data; 1167 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1168 le32_to_cpu(reg->dev_addr.offset); 1169 int i; 1170 1171 /* we shouldn't get here if the trans doesn't have read_config32 */ 1172 if (WARN_ON_ONCE(!trans->ops->read_config32)) 1173 return -EOPNOTSUPP; 1174 1175 range->internal_base_addr = cpu_to_le32(addr); 1176 range->range_data_size = reg->dev_addr.size; 1177 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1178 int ret; 1179 u32 tmp; 1180 1181 ret = trans->ops->read_config32(trans, addr + i, &tmp); 1182 if (ret < 0) 1183 return ret; 1184 1185 *val++ = cpu_to_le32(tmp); 1186 } 1187 1188 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1189 } 1190 1191 static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1192 struct iwl_dump_ini_region_data *reg_data, 1193 void *range_ptr, u32 range_len, int idx) 1194 { 1195 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1196 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1197 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1198 le32_to_cpu(reg->dev_addr.offset); 1199 1200 range->internal_base_addr = cpu_to_le32(addr); 1201 range->range_data_size = reg->dev_addr.size; 1202 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1203 le32_to_cpu(reg->dev_addr.size)); 1204 1205 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1206 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1207 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1208 range->data, 1209 le32_to_cpu(reg->dev_addr.size)); 1210 1211 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1212 } 1213 1214 static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1215 void *range_ptr, u32 range_len, int idx) 1216 { 1217 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1218 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1219 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1220 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1221 1222 range->page_num = cpu_to_le32(idx); 1223 range->range_data_size = cpu_to_le32(page_size); 1224 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1225 DMA_BIDIRECTIONAL); 1226 memcpy(range->data, page_address(page), page_size); 1227 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1228 DMA_BIDIRECTIONAL); 1229 1230 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1231 } 1232 1233 static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1234 struct iwl_dump_ini_region_data *reg_data, 1235 void *range_ptr, u32 range_len, int idx) 1236 { 1237 struct iwl_fw_ini_error_dump_range *range; 1238 u32 page_size; 1239 1240 /* all paged index start from 1 to skip CSS section */ 1241 idx++; 1242 1243 if (!fwrt->trans->trans_cfg->gen2) 1244 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1245 1246 range = range_ptr; 1247 page_size = fwrt->trans->init_dram.paging[idx].size; 1248 1249 range->page_num = cpu_to_le32(idx); 1250 range->range_data_size = cpu_to_le32(page_size); 1251 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1252 page_size); 1253 1254 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1255 } 1256 1257 static int 1258 iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1259 struct iwl_dump_ini_region_data *reg_data, 1260 void *range_ptr, u32 range_len, int idx) 1261 { 1262 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1263 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1264 struct iwl_dram_data *frag; 1265 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1266 1267 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1268 1269 range->dram_base_addr = cpu_to_le64(frag->physical); 1270 range->range_data_size = cpu_to_le32(frag->size); 1271 1272 memcpy(range->data, frag->block, frag->size); 1273 1274 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1275 } 1276 1277 static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1278 struct iwl_dump_ini_region_data *reg_data, 1279 void *range_ptr, u32 range_len, int idx) 1280 { 1281 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1282 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1283 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1284 1285 range->internal_base_addr = cpu_to_le32(addr); 1286 range->range_data_size = reg->internal_buffer.size; 1287 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1288 le32_to_cpu(reg->internal_buffer.size)); 1289 1290 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1291 } 1292 1293 static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1294 struct iwl_dump_ini_region_data *reg_data, int idx) 1295 { 1296 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1297 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1298 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1299 int txf_num = cfg->num_txfifo_entries; 1300 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1301 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1302 1303 if (!idx) { 1304 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1305 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1306 le32_to_cpu(reg->fifos.offset)); 1307 return false; 1308 } 1309 1310 iter->internal_txf = 0; 1311 iter->fifo_size = 0; 1312 iter->fifo = -1; 1313 if (le32_to_cpu(reg->fifos.offset)) 1314 iter->lmac = 1; 1315 else 1316 iter->lmac = 0; 1317 } 1318 1319 if (!iter->internal_txf) { 1320 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1321 iter->fifo_size = 1322 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1323 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1324 return true; 1325 } 1326 iter->fifo--; 1327 } 1328 1329 iter->internal_txf = 1; 1330 1331 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1332 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1333 return false; 1334 1335 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1336 iter->fifo_size = 1337 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1338 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1339 return true; 1340 } 1341 1342 return false; 1343 } 1344 1345 static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1346 struct iwl_dump_ini_region_data *reg_data, 1347 void *range_ptr, u32 range_len, int idx) 1348 { 1349 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1350 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1351 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1352 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1353 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1354 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1355 u32 registers_size = registers_num * sizeof(*reg_dump); 1356 __le32 *data; 1357 int i; 1358 1359 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1360 return -EIO; 1361 1362 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1363 return -EBUSY; 1364 1365 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1366 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1367 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1368 1369 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1370 1371 /* 1372 * read txf registers. for each register, write to the dump the 1373 * register address and its value 1374 */ 1375 for (i = 0; i < registers_num; i++) { 1376 addr = le32_to_cpu(reg->addrs[i]) + offs; 1377 1378 reg_dump->addr = cpu_to_le32(addr); 1379 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1380 addr)); 1381 1382 reg_dump++; 1383 } 1384 1385 if (reg->fifos.hdr_only) { 1386 range->range_data_size = cpu_to_le32(registers_size); 1387 goto out; 1388 } 1389 1390 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1391 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1392 TXF_WR_PTR + offs); 1393 1394 /* Dummy-read to advance the read pointer to the head */ 1395 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1396 1397 /* Read FIFO */ 1398 addr = TXF_READ_MODIFY_DATA + offs; 1399 data = (void *)reg_dump; 1400 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1401 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1402 1403 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1404 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1405 reg_dump, iter->fifo_size); 1406 1407 out: 1408 iwl_trans_release_nic_access(fwrt->trans); 1409 1410 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1411 } 1412 1413 static int 1414 iwl_dump_ini_prph_snps_dphyip_iter(struct iwl_fw_runtime *fwrt, 1415 struct iwl_dump_ini_region_data *reg_data, 1416 void *range_ptr, u32 range_len, int idx) 1417 { 1418 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1419 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1420 __le32 *val = range->data; 1421 __le32 offset = reg->dev_addr.offset; 1422 u32 indirect_rd_wr_addr = DPHYIP_INDIRECT; 1423 u32 addr = le32_to_cpu(reg->addrs[idx]); 1424 u32 dphy_state, dphy_addr, prph_val; 1425 int i; 1426 1427 range->internal_base_addr = cpu_to_le32(addr); 1428 range->range_data_size = reg->dev_addr.size; 1429 1430 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1431 return -EBUSY; 1432 1433 indirect_rd_wr_addr += le32_to_cpu(offset); 1434 1435 dphy_addr = offset ? WFPM_LMAC2_PS_CTL_RW : WFPM_LMAC1_PS_CTL_RW; 1436 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1437 1438 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1439 if (dphy_state == HBUS_TIMEOUT || 1440 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1441 WFPM_PHYRF_STATE_ON) { 1442 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1443 continue; 1444 } 1445 1446 iwl_write_prph_no_grab(fwrt->trans, indirect_rd_wr_addr, 1447 addr + i); 1448 /* wait a bit for value to be ready in register */ 1449 udelay(1); 1450 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1451 indirect_rd_wr_addr); 1452 *val++ = cpu_to_le32((prph_val & DPHYIP_INDIRECT_RD_MSK) >> 1453 DPHYIP_INDIRECT_RD_SHIFT); 1454 } 1455 1456 iwl_trans_release_nic_access(fwrt->trans); 1457 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1458 } 1459 1460 struct iwl_ini_rxf_data { 1461 u32 fifo_num; 1462 u32 size; 1463 u32 offset; 1464 }; 1465 1466 static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1467 struct iwl_dump_ini_region_data *reg_data, 1468 struct iwl_ini_rxf_data *data) 1469 { 1470 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1471 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1472 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1473 u8 fifo_idx; 1474 1475 if (!data) 1476 return; 1477 1478 memset(data, 0, sizeof(*data)); 1479 1480 /* make sure only one bit is set in only one fid */ 1481 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1482 "fid1=%x, fid2=%x\n", fid1, fid2)) 1483 return; 1484 1485 if (fid1) { 1486 fifo_idx = ffs(fid1) - 1; 1487 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1488 fifo_idx)) 1489 return; 1490 1491 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1492 data->fifo_num = fifo_idx; 1493 } else { 1494 u8 max_idx; 1495 1496 fifo_idx = ffs(fid2) - 1; 1497 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1498 SHARED_MEM_CFG_CMD, 0) <= 3) 1499 max_idx = 0; 1500 else 1501 max_idx = 1; 1502 1503 if (WARN_ONCE(fifo_idx > max_idx, 1504 "invalid umac fifo idx %d", fifo_idx)) 1505 return; 1506 1507 /* use bit 31 to distinguish between umac and lmac rxf while 1508 * parsing the dump 1509 */ 1510 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1511 1512 switch (fifo_idx) { 1513 case 0: 1514 data->size = fwrt->smem_cfg.rxfifo2_size; 1515 data->offset = iwl_umac_prph(fwrt->trans, 1516 RXF_DIFF_FROM_PREV); 1517 break; 1518 case 1: 1519 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1520 data->offset = iwl_umac_prph(fwrt->trans, 1521 RXF2C_DIFF_FROM_PREV); 1522 break; 1523 } 1524 } 1525 } 1526 1527 static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1528 struct iwl_dump_ini_region_data *reg_data, 1529 void *range_ptr, u32 range_len, int idx) 1530 { 1531 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1532 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1533 struct iwl_ini_rxf_data rxf_data; 1534 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1535 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1536 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1537 u32 registers_size = registers_num * sizeof(*reg_dump); 1538 __le32 *data; 1539 int i; 1540 1541 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1542 if (!rxf_data.size) 1543 return -EIO; 1544 1545 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1546 return -EBUSY; 1547 1548 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1549 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1550 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1551 1552 /* 1553 * read rxf registers. for each register, write to the dump the 1554 * register address and its value 1555 */ 1556 for (i = 0; i < registers_num; i++) { 1557 addr = le32_to_cpu(reg->addrs[i]) + offs; 1558 1559 reg_dump->addr = cpu_to_le32(addr); 1560 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1561 addr)); 1562 1563 reg_dump++; 1564 } 1565 1566 if (reg->fifos.hdr_only) { 1567 range->range_data_size = cpu_to_le32(registers_size); 1568 goto out; 1569 } 1570 1571 offs = rxf_data.offset; 1572 1573 /* Lock fence */ 1574 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1575 /* Set fence pointer to the same place like WR pointer */ 1576 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1577 /* Set fence offset */ 1578 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1579 0x0); 1580 1581 /* Read FIFO */ 1582 addr = RXF_FIFO_RD_FENCE_INC + offs; 1583 data = (void *)reg_dump; 1584 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1585 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1586 1587 out: 1588 iwl_trans_release_nic_access(fwrt->trans); 1589 1590 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1591 } 1592 1593 static int 1594 iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1595 struct iwl_dump_ini_region_data *reg_data, 1596 void *range_ptr, u32 range_len, int idx) 1597 { 1598 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1599 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1600 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1601 u32 addr = le32_to_cpu(err_table->base_addr) + 1602 le32_to_cpu(err_table->offset); 1603 1604 range->internal_base_addr = cpu_to_le32(addr); 1605 range->range_data_size = err_table->size; 1606 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1607 le32_to_cpu(err_table->size)); 1608 1609 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1610 } 1611 1612 static int 1613 iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1614 struct iwl_dump_ini_region_data *reg_data, 1615 void *range_ptr, u32 range_len, int idx) 1616 { 1617 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1618 struct iwl_fw_ini_region_special_device_memory *special_mem = 1619 ®->special_mem; 1620 1621 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1622 u32 addr = le32_to_cpu(special_mem->base_addr) + 1623 le32_to_cpu(special_mem->offset); 1624 1625 range->internal_base_addr = cpu_to_le32(addr); 1626 range->range_data_size = special_mem->size; 1627 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1628 le32_to_cpu(special_mem->size)); 1629 1630 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1631 } 1632 1633 static int 1634 iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1635 struct iwl_dump_ini_region_data *reg_data, 1636 void *range_ptr, u32 range_len, int idx) 1637 { 1638 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1639 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1640 __le32 *val = range->data; 1641 u32 prph_data; 1642 int i; 1643 1644 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1645 return -EBUSY; 1646 1647 range->range_data_size = reg->dev_addr.size; 1648 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1649 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1650 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1651 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1652 if (iwl_trans_is_hw_error_value(prph_data)) { 1653 iwl_trans_release_nic_access(fwrt->trans); 1654 return -EBUSY; 1655 } 1656 *val++ = cpu_to_le32(prph_data); 1657 } 1658 iwl_trans_release_nic_access(fwrt->trans); 1659 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1660 } 1661 1662 static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1663 struct iwl_dump_ini_region_data *reg_data, 1664 void *range_ptr, u32 range_len, int idx) 1665 { 1666 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1667 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1668 u32 pkt_len; 1669 1670 if (!pkt) 1671 return -EIO; 1672 1673 pkt_len = iwl_rx_packet_payload_len(pkt); 1674 1675 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1676 range->range_data_size = cpu_to_le32(pkt_len); 1677 1678 memcpy(range->data, pkt->data, pkt_len); 1679 1680 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1681 } 1682 1683 static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1684 struct iwl_dump_ini_region_data *reg_data, 1685 void *range_ptr, u32 range_len, int idx) 1686 { 1687 /* read the IMR memory and DMA it to SRAM */ 1688 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1689 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1690 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1691 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1692 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1693 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1694 1695 range->range_data_size = cpu_to_le32(size_to_dump); 1696 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1697 imr_curr_addr, size_to_dump)) { 1698 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1699 return -1; 1700 } 1701 1702 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1703 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1704 1705 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1706 size_to_dump); 1707 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1708 } 1709 1710 static void * 1711 iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1712 struct iwl_dump_ini_region_data *reg_data, 1713 void *data, u32 data_len) 1714 { 1715 struct iwl_fw_ini_error_dump *dump = data; 1716 1717 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1718 1719 return dump->data; 1720 } 1721 1722 /** 1723 * mask_apply_and_normalize - applies mask on val and normalize the result 1724 * 1725 * @val: value 1726 * @mask: mask to apply and to normalize with 1727 * 1728 * The normalization is based on the first set bit in the mask 1729 * 1730 * Returns: the extracted value 1731 */ 1732 static u32 mask_apply_and_normalize(u32 val, u32 mask) 1733 { 1734 return (val & mask) >> (ffs(mask) - 1); 1735 } 1736 1737 static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1738 const struct iwl_fw_mon_reg *reg_info) 1739 { 1740 u32 val, offs; 1741 1742 /* The header addresses of DBGCi is calculate as follows: 1743 * DBGC1 address + (0x100 * i) 1744 */ 1745 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1746 1747 if (!reg_info || !reg_info->addr || !reg_info->mask) 1748 return 0; 1749 1750 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1751 1752 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1753 } 1754 1755 static void * 1756 iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1757 struct iwl_fw_ini_monitor_dump *data, 1758 const struct iwl_fw_mon_regs *addrs) 1759 { 1760 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1761 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1762 return NULL; 1763 } 1764 1765 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1766 &addrs->write_ptr); 1767 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1768 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1769 1770 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1771 } 1772 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1773 &addrs->cycle_cnt); 1774 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1775 &addrs->cur_frag); 1776 1777 iwl_trans_release_nic_access(fwrt->trans); 1778 1779 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1780 1781 return data->data; 1782 } 1783 1784 static void * 1785 iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1786 struct iwl_dump_ini_region_data *reg_data, 1787 void *data, u32 data_len) 1788 { 1789 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1790 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1791 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1792 1793 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1794 &fwrt->trans->cfg->mon_dram_regs); 1795 } 1796 1797 static void * 1798 iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1799 struct iwl_dump_ini_region_data *reg_data, 1800 void *data, u32 data_len) 1801 { 1802 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1803 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1804 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1805 1806 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1807 &fwrt->trans->cfg->mon_smem_regs); 1808 } 1809 1810 static void * 1811 iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1812 struct iwl_dump_ini_region_data *reg_data, 1813 void *data, u32 data_len) 1814 { 1815 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1816 1817 return iwl_dump_ini_mon_fill_header(fwrt, 1818 /* no offset calculation later */ 1819 IWL_FW_INI_ALLOCATION_ID_DBGC1, 1820 mon_dump, 1821 &fwrt->trans->cfg->mon_dbgi_regs); 1822 } 1823 1824 static void * 1825 iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1826 struct iwl_dump_ini_region_data *reg_data, 1827 void *data, u32 data_len) 1828 { 1829 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1830 struct iwl_fw_ini_err_table_dump *dump = data; 1831 1832 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1833 dump->version = reg->err_table.version; 1834 1835 return dump->data; 1836 } 1837 1838 static void * 1839 iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1840 struct iwl_dump_ini_region_data *reg_data, 1841 void *data, u32 data_len) 1842 { 1843 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1844 struct iwl_fw_ini_special_device_memory *dump = data; 1845 1846 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1847 dump->type = reg->special_mem.type; 1848 dump->version = reg->special_mem.version; 1849 1850 return dump->data; 1851 } 1852 1853 static void * 1854 iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1855 struct iwl_dump_ini_region_data *reg_data, 1856 void *data, u32 data_len) 1857 { 1858 struct iwl_fw_ini_error_dump *dump = data; 1859 1860 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1861 1862 return dump->data; 1863 } 1864 1865 static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1866 struct iwl_dump_ini_region_data *reg_data) 1867 { 1868 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1869 1870 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1871 } 1872 1873 static u32 1874 iwl_dump_ini_mem_block_ranges(struct iwl_fw_runtime *fwrt, 1875 struct iwl_dump_ini_region_data *reg_data) 1876 { 1877 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1878 size_t size = sizeof(struct iwl_fw_ini_addr_size); 1879 1880 return iwl_tlv_array_len_with_size(reg_data->reg_tlv, reg, size); 1881 } 1882 1883 static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1884 struct iwl_dump_ini_region_data *reg_data) 1885 { 1886 if (fwrt->trans->trans_cfg->gen2) { 1887 if (fwrt->trans->init_dram.paging_cnt) 1888 return fwrt->trans->init_dram.paging_cnt - 1; 1889 else 1890 return 0; 1891 } 1892 1893 return fwrt->num_of_paging_blk; 1894 } 1895 1896 static u32 1897 iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1898 struct iwl_dump_ini_region_data *reg_data) 1899 { 1900 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1901 struct iwl_fw_mon *fw_mon; 1902 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1903 int i; 1904 1905 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1906 1907 for (i = 0; i < fw_mon->num_frags; i++) { 1908 if (!fw_mon->frags[i].size) 1909 break; 1910 1911 ranges++; 1912 } 1913 1914 return ranges; 1915 } 1916 1917 static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1918 struct iwl_dump_ini_region_data *reg_data) 1919 { 1920 u32 num_of_fifos = 0; 1921 1922 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1923 num_of_fifos++; 1924 1925 return num_of_fifos; 1926 } 1927 1928 static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1929 struct iwl_dump_ini_region_data *reg_data) 1930 { 1931 return 1; 1932 } 1933 1934 static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1935 struct iwl_dump_ini_region_data *reg_data) 1936 { 1937 /* range is total number of pages need to copied from 1938 *IMR memory to SRAM and later from SRAM to DRAM 1939 */ 1940 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1941 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1942 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1943 1944 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1945 IWL_DEBUG_INFO(fwrt, 1946 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1947 imr_enable, imr_size, sram_size); 1948 return 0; 1949 } 1950 1951 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1952 } 1953 1954 static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1955 struct iwl_dump_ini_region_data *reg_data) 1956 { 1957 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1958 u32 size = le32_to_cpu(reg->dev_addr.size); 1959 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1960 1961 if (!size || !ranges) 1962 return 0; 1963 1964 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1965 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1966 } 1967 1968 static u32 1969 iwl_dump_ini_mem_block_get_size(struct iwl_fw_runtime *fwrt, 1970 struct iwl_dump_ini_region_data *reg_data) 1971 { 1972 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1973 struct iwl_fw_ini_addr_size *pairs = (void *)reg->addrs; 1974 u32 ranges = iwl_dump_ini_mem_block_ranges(fwrt, reg_data); 1975 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1976 int range; 1977 1978 if (!ranges) 1979 return 0; 1980 1981 for (range = 0; range < ranges; range++) 1982 size += le32_to_cpu(pairs[range].size); 1983 1984 return size + ranges * sizeof(struct iwl_fw_ini_error_dump_range); 1985 } 1986 1987 static u32 1988 iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1989 struct iwl_dump_ini_region_data *reg_data) 1990 { 1991 int i; 1992 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1993 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1994 1995 /* start from 1 to skip CSS section */ 1996 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 1997 size += range_header_len; 1998 if (fwrt->trans->trans_cfg->gen2) 1999 size += fwrt->trans->init_dram.paging[i].size; 2000 else 2001 size += fwrt->fw_paging_db[i].fw_paging_size; 2002 } 2003 2004 return size; 2005 } 2006 2007 static u32 2008 iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 2009 struct iwl_dump_ini_region_data *reg_data) 2010 { 2011 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2012 struct iwl_fw_mon *fw_mon; 2013 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 2014 int i; 2015 2016 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 2017 2018 for (i = 0; i < fw_mon->num_frags; i++) { 2019 struct iwl_dram_data *frag = &fw_mon->frags[i]; 2020 2021 if (!frag->size) 2022 break; 2023 2024 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 2025 } 2026 2027 if (size) 2028 size += sizeof(struct iwl_fw_ini_monitor_dump); 2029 2030 return size; 2031 } 2032 2033 static u32 2034 iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 2035 struct iwl_dump_ini_region_data *reg_data) 2036 { 2037 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2038 u32 size; 2039 2040 size = le32_to_cpu(reg->internal_buffer.size); 2041 if (!size) 2042 return 0; 2043 2044 size += sizeof(struct iwl_fw_ini_monitor_dump) + 2045 sizeof(struct iwl_fw_ini_error_dump_range); 2046 2047 return size; 2048 } 2049 2050 static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 2051 struct iwl_dump_ini_region_data *reg_data) 2052 { 2053 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2054 u32 size = le32_to_cpu(reg->dev_addr.size); 2055 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 2056 2057 if (!size || !ranges) 2058 return 0; 2059 2060 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 2061 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 2062 } 2063 2064 static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 2065 struct iwl_dump_ini_region_data *reg_data) 2066 { 2067 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2068 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 2069 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2070 u32 size = 0; 2071 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 2072 registers_num * 2073 sizeof(struct iwl_fw_ini_error_dump_register); 2074 2075 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 2076 size += fifo_hdr; 2077 if (!reg->fifos.hdr_only) 2078 size += iter->fifo_size; 2079 } 2080 2081 if (!size) 2082 return 0; 2083 2084 return size + sizeof(struct iwl_fw_ini_error_dump); 2085 } 2086 2087 static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 2088 struct iwl_dump_ini_region_data *reg_data) 2089 { 2090 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2091 struct iwl_ini_rxf_data rx_data; 2092 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 2093 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 2094 sizeof(struct iwl_fw_ini_error_dump_range) + 2095 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 2096 2097 if (reg->fifos.hdr_only) 2098 return size; 2099 2100 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 2101 size += rx_data.size; 2102 2103 return size; 2104 } 2105 2106 static u32 2107 iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 2108 struct iwl_dump_ini_region_data *reg_data) 2109 { 2110 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2111 u32 size = le32_to_cpu(reg->err_table.size); 2112 2113 if (size) 2114 size += sizeof(struct iwl_fw_ini_err_table_dump) + 2115 sizeof(struct iwl_fw_ini_error_dump_range); 2116 2117 return size; 2118 } 2119 2120 static u32 2121 iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2122 struct iwl_dump_ini_region_data *reg_data) 2123 { 2124 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2125 u32 size = le32_to_cpu(reg->special_mem.size); 2126 2127 if (size) 2128 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2129 sizeof(struct iwl_fw_ini_error_dump_range); 2130 2131 return size; 2132 } 2133 2134 static u32 2135 iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2136 struct iwl_dump_ini_region_data *reg_data) 2137 { 2138 u32 size = 0; 2139 2140 if (!reg_data->dump_data->fw_pkt) 2141 return 0; 2142 2143 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2144 if (size) 2145 size += sizeof(struct iwl_fw_ini_error_dump) + 2146 sizeof(struct iwl_fw_ini_error_dump_range); 2147 2148 return size; 2149 } 2150 2151 static u32 2152 iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2153 struct iwl_dump_ini_region_data *reg_data) 2154 { 2155 u32 ranges = 0; 2156 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2157 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2158 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2159 2160 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2161 IWL_DEBUG_INFO(fwrt, 2162 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2163 imr_enable, imr_size, sram_size); 2164 return 0; 2165 } 2166 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2167 if (!ranges) { 2168 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges); 2169 return 0; 2170 } 2171 imr_size += sizeof(struct iwl_fw_ini_error_dump) + 2172 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2173 return imr_size; 2174 } 2175 2176 /** 2177 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2178 * @get_num_of_ranges: returns the number of memory ranges in the region. 2179 * @get_size: returns the total size of the region. 2180 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2181 * the first range or NULL if failed to fill headers. 2182 * @fill_range: copies a given memory range into the dump. 2183 * Returns the size of the range or negative error value otherwise. 2184 */ 2185 struct iwl_dump_ini_mem_ops { 2186 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2187 struct iwl_dump_ini_region_data *reg_data); 2188 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2189 struct iwl_dump_ini_region_data *reg_data); 2190 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2191 struct iwl_dump_ini_region_data *reg_data, 2192 void *data, u32 data_len); 2193 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2194 struct iwl_dump_ini_region_data *reg_data, 2195 void *range, u32 range_len, int idx); 2196 }; 2197 2198 /** 2199 * iwl_dump_ini_mem - dump memory region 2200 * 2201 * @fwrt: fw runtime struct 2202 * @list: list to add the dump tlv to 2203 * @reg_data: memory region 2204 * @ops: memory dump operations 2205 * 2206 * Creates a dump tlv and copy a memory region into it. 2207 * 2208 * Returns: the size of the current dump tlv or 0 if failed 2209 */ 2210 static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2211 struct iwl_dump_ini_region_data *reg_data, 2212 const struct iwl_dump_ini_mem_ops *ops) 2213 { 2214 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2215 struct iwl_fw_ini_dump_entry *entry; 2216 struct iwl_fw_ini_error_dump_data *tlv; 2217 struct iwl_fw_ini_error_dump_header *header; 2218 u32 type = reg->type; 2219 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK); 2220 u32 num_of_ranges, i, size; 2221 u8 *range; 2222 u32 free_size; 2223 u64 header_size; 2224 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE; 2225 2226 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n", 2227 dump_policy, id, type); 2228 2229 if (le32_to_cpu(reg->hdr.version) >= 2) { 2230 u32 dp = le32_get_bits(reg->id, 2231 IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2232 2233 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE && 2234 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) { 2235 IWL_DEBUG_FW(fwrt, 2236 "WRT: no dump - type %d and policy mismatch=%d\n", 2237 dump_policy, dp); 2238 return 0; 2239 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM && 2240 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) { 2241 IWL_DEBUG_FW(fwrt, 2242 "WRT: no dump - type %d and policy mismatch=%d\n", 2243 dump_policy, dp); 2244 return 0; 2245 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF && 2246 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) { 2247 IWL_DEBUG_FW(fwrt, 2248 "WRT: no dump - type %d and policy mismatch=%d\n", 2249 dump_policy, dp); 2250 return 0; 2251 } 2252 } 2253 2254 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2255 !ops->fill_range) { 2256 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2257 return 0; 2258 } 2259 2260 size = ops->get_size(fwrt, reg_data); 2261 2262 if (size < sizeof(*header)) { 2263 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2264 return 0; 2265 } 2266 2267 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2268 if (!entry) 2269 return 0; 2270 2271 entry->size = sizeof(*tlv) + size; 2272 2273 tlv = (void *)entry->data; 2274 tlv->type = reg->type; 2275 tlv->sub_type = reg->sub_type; 2276 tlv->sub_type_ver = reg->sub_type_ver; 2277 tlv->reserved = reg->reserved; 2278 tlv->len = cpu_to_le32(size); 2279 2280 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2281 2282 header = (void *)tlv->data; 2283 header->region_id = cpu_to_le32(id); 2284 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2285 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2286 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2287 2288 free_size = size; 2289 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2290 if (!range) { 2291 IWL_ERR(fwrt, 2292 "WRT: Failed to fill region header: id=%d, type=%d\n", 2293 id, type); 2294 goto out_err; 2295 } 2296 2297 header_size = range - (u8 *)header; 2298 2299 if (WARN(header_size > free_size, 2300 "header size %llu > free_size %d", 2301 header_size, free_size)) { 2302 IWL_ERR(fwrt, 2303 "WRT: fill_mem_hdr used more than given free_size\n"); 2304 goto out_err; 2305 } 2306 2307 free_size -= header_size; 2308 2309 for (i = 0; i < num_of_ranges; i++) { 2310 int range_size = ops->fill_range(fwrt, reg_data, range, 2311 free_size, i); 2312 2313 if (range_size < 0) { 2314 IWL_ERR(fwrt, 2315 "WRT: Failed to dump region: id=%d, type=%d\n", 2316 id, type); 2317 goto out_err; 2318 } 2319 2320 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2321 range_size, free_size)) { 2322 IWL_ERR(fwrt, 2323 "WRT: fill_raged used more than given free_size\n"); 2324 goto out_err; 2325 } 2326 2327 free_size -= range_size; 2328 range = range + range_size; 2329 } 2330 2331 list_add_tail(&entry->list, list); 2332 2333 return entry->size; 2334 2335 out_err: 2336 vfree(entry); 2337 2338 return 0; 2339 } 2340 2341 static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2342 struct iwl_fw_ini_trigger_tlv *trigger, 2343 struct list_head *list) 2344 { 2345 struct iwl_fw_ini_dump_entry *entry; 2346 struct iwl_fw_error_dump_data *tlv; 2347 struct iwl_fw_ini_dump_info *dump; 2348 struct iwl_dbg_tlv_node *node; 2349 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2350 u32 size = sizeof(*tlv) + sizeof(*dump); 2351 u32 num_of_cfg_names = 0; 2352 u32 hw_type; 2353 2354 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2355 size += sizeof(*cfg_name); 2356 num_of_cfg_names++; 2357 } 2358 2359 entry = vzalloc(sizeof(*entry) + size); 2360 if (!entry) 2361 return 0; 2362 2363 entry->size = size; 2364 2365 tlv = (void *)entry->data; 2366 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2367 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2368 2369 dump = (void *)tlv->data; 2370 2371 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2372 dump->time_point = trigger->time_point; 2373 dump->trigger_reason = trigger->trigger_reason; 2374 dump->external_cfg_state = 2375 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2376 2377 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2378 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2379 2380 dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step); 2381 2382 /* 2383 * Several HWs all have type == 0x42, so we'll override this value 2384 * according to the detected HW 2385 */ 2386 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2387 if (hw_type == IWL_AX210_HW_TYPE) { 2388 u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR); 2389 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2390 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2391 u32 masked_bits = is_jacket | (is_cdb << 1); 2392 2393 /* 2394 * The HW type depends on certain bits in this case, so add 2395 * these bits to the HW type. We won't have collisions since we 2396 * add these bits after the highest possible bit in the mask. 2397 */ 2398 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2399 } 2400 dump->hw_type = cpu_to_le32(hw_type); 2401 2402 dump->rf_id_flavor = 2403 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2404 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2405 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2406 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2407 2408 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2409 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2410 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2411 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2412 2413 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2414 dump->regions_mask = trigger->regions_mask & 2415 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2416 2417 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2418 memcpy(dump->build_tag, fwrt->fw->human_readable, 2419 sizeof(dump->build_tag)); 2420 2421 cfg_name = dump->cfg_names; 2422 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2423 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2424 struct iwl_fw_ini_debug_info_tlv *debug_info = 2425 (void *)node->tlv.data; 2426 2427 BUILD_BUG_ON(sizeof(cfg_name->cfg_name) != 2428 sizeof(debug_info->debug_cfg_name)); 2429 2430 cfg_name->image_type = debug_info->image_type; 2431 cfg_name->cfg_name_len = 2432 cpu_to_le32(sizeof(cfg_name->cfg_name)); 2433 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2434 sizeof(cfg_name->cfg_name)); 2435 cfg_name++; 2436 } 2437 2438 /* add dump info TLV to the beginning of the list since it needs to be 2439 * the first TLV in the dump 2440 */ 2441 list_add(&entry->list, list); 2442 2443 return entry->size; 2444 } 2445 2446 static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt, 2447 struct list_head *list) 2448 { 2449 struct iwl_fw_ini_dump_entry *entry; 2450 struct iwl_dump_file_name_info *tlv; 2451 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext, 2452 IWL_FW_INI_MAX_NAME); 2453 2454 if (!fwrt->trans->dbg.dump_file_name_ext_valid) 2455 return 0; 2456 2457 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len); 2458 if (!entry) 2459 return 0; 2460 2461 entry->size = sizeof(*tlv) + len; 2462 2463 tlv = (void *)entry->data; 2464 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE); 2465 tlv->len = cpu_to_le32(len); 2466 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len); 2467 2468 /* add the dump file name extension tlv to the list */ 2469 list_add_tail(&entry->list, list); 2470 2471 fwrt->trans->dbg.dump_file_name_ext_valid = false; 2472 2473 return entry->size; 2474 } 2475 2476 static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2477 [IWL_FW_INI_REGION_INVALID] = {}, 2478 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2479 .get_num_of_ranges = iwl_dump_ini_single_range, 2480 .get_size = iwl_dump_ini_mon_smem_get_size, 2481 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2482 .fill_range = iwl_dump_ini_mon_smem_iter, 2483 }, 2484 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2485 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2486 .get_size = iwl_dump_ini_mon_dram_get_size, 2487 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2488 .fill_range = iwl_dump_ini_mon_dram_iter, 2489 }, 2490 [IWL_FW_INI_REGION_TXF] = { 2491 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2492 .get_size = iwl_dump_ini_txf_get_size, 2493 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2494 .fill_range = iwl_dump_ini_txf_iter, 2495 }, 2496 [IWL_FW_INI_REGION_RXF] = { 2497 .get_num_of_ranges = iwl_dump_ini_single_range, 2498 .get_size = iwl_dump_ini_rxf_get_size, 2499 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2500 .fill_range = iwl_dump_ini_rxf_iter, 2501 }, 2502 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2503 .get_num_of_ranges = iwl_dump_ini_single_range, 2504 .get_size = iwl_dump_ini_err_table_get_size, 2505 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2506 .fill_range = iwl_dump_ini_err_table_iter, 2507 }, 2508 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2509 .get_num_of_ranges = iwl_dump_ini_single_range, 2510 .get_size = iwl_dump_ini_err_table_get_size, 2511 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2512 .fill_range = iwl_dump_ini_err_table_iter, 2513 }, 2514 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2515 .get_num_of_ranges = iwl_dump_ini_single_range, 2516 .get_size = iwl_dump_ini_fw_pkt_get_size, 2517 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2518 .fill_range = iwl_dump_ini_fw_pkt_iter, 2519 }, 2520 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2521 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2522 .get_size = iwl_dump_ini_mem_get_size, 2523 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2524 .fill_range = iwl_dump_ini_dev_mem_iter, 2525 }, 2526 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2527 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2528 .get_size = iwl_dump_ini_mem_get_size, 2529 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2530 .fill_range = iwl_dump_ini_prph_mac_iter, 2531 }, 2532 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2533 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2534 .get_size = iwl_dump_ini_mem_get_size, 2535 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2536 .fill_range = iwl_dump_ini_prph_phy_iter, 2537 }, 2538 [IWL_FW_INI_REGION_PERIPHERY_MAC_RANGE] = { 2539 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2540 .get_size = iwl_dump_ini_mem_block_get_size, 2541 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2542 .fill_range = iwl_dump_ini_prph_mac_block_iter, 2543 }, 2544 [IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE] = { 2545 .get_num_of_ranges = iwl_dump_ini_mem_block_ranges, 2546 .get_size = iwl_dump_ini_mem_block_get_size, 2547 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2548 .fill_range = iwl_dump_ini_prph_phy_block_iter, 2549 }, 2550 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2551 [IWL_FW_INI_REGION_PAGING] = { 2552 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2553 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2554 .get_size = iwl_dump_ini_paging_get_size, 2555 .fill_range = iwl_dump_ini_paging_iter, 2556 }, 2557 [IWL_FW_INI_REGION_CSR] = { 2558 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2559 .get_size = iwl_dump_ini_mem_get_size, 2560 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2561 .fill_range = iwl_dump_ini_csr_iter, 2562 }, 2563 [IWL_FW_INI_REGION_DRAM_IMR] = { 2564 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2565 .get_size = iwl_dump_ini_imr_get_size, 2566 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2567 .fill_range = iwl_dump_ini_imr_iter, 2568 }, 2569 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2570 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2571 .get_size = iwl_dump_ini_mem_get_size, 2572 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2573 .fill_range = iwl_dump_ini_config_iter, 2574 }, 2575 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2576 .get_num_of_ranges = iwl_dump_ini_single_range, 2577 .get_size = iwl_dump_ini_special_mem_get_size, 2578 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2579 .fill_range = iwl_dump_ini_special_mem_iter, 2580 }, 2581 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2582 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2583 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2584 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2585 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2586 }, 2587 [IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP] = { 2588 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2589 .get_size = iwl_dump_ini_mem_get_size, 2590 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2591 .fill_range = iwl_dump_ini_prph_snps_dphyip_iter, 2592 }, 2593 }; 2594 2595 static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2596 struct iwl_fwrt_dump_data *dump_data, 2597 struct list_head *list) 2598 { 2599 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2600 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2601 struct iwl_dump_ini_region_data reg_data = { 2602 .dump_data = dump_data, 2603 }; 2604 struct iwl_dump_ini_region_data imr_reg_data = { 2605 .dump_data = dump_data, 2606 }; 2607 int i; 2608 u32 size = 0; 2609 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2610 ~(fwrt->trans->dbg.unsupported_region_msk); 2611 2612 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2613 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2614 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2615 2616 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2617 u32 reg_type; 2618 struct iwl_fw_ini_region_tlv *reg; 2619 2620 if (!(BIT_ULL(i) & regions_mask)) 2621 continue; 2622 2623 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2624 if (!reg_data.reg_tlv) { 2625 IWL_WARN(fwrt, 2626 "WRT: Unassigned region id %d, skipping\n", i); 2627 continue; 2628 } 2629 2630 reg = (void *)reg_data.reg_tlv->data; 2631 reg_type = reg->type; 2632 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2633 continue; 2634 2635 if ((reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY || 2636 reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY_RANGE || 2637 reg_type == IWL_FW_INI_REGION_PERIPHERY_SNPS_DPHYIP) && 2638 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2639 IWL_WARN(fwrt, 2640 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2641 tp_id); 2642 continue; 2643 } 2644 /* 2645 * DRAM_IMR can be collected only for FW/HW error timepoint 2646 * when fw is not alive. In addition, it must be collected 2647 * lastly as it overwrites SRAM that can possibly contain 2648 * debug data which also need to be collected. 2649 */ 2650 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { 2651 if (tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT || 2652 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR) 2653 imr_reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2654 else 2655 IWL_INFO(fwrt, 2656 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n", 2657 tp_id); 2658 /* continue to next region */ 2659 continue; 2660 } 2661 2662 2663 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2664 &iwl_dump_ini_region_ops[reg_type]); 2665 } 2666 /* collect DRAM_IMR region in the last */ 2667 if (imr_reg_data.reg_tlv) 2668 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2669 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]); 2670 2671 if (size) { 2672 size += iwl_dump_ini_file_name_info(fwrt, list); 2673 size += iwl_dump_ini_info(fwrt, trigger, list); 2674 } 2675 2676 return size; 2677 } 2678 2679 static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2680 struct iwl_fw_ini_trigger_tlv *trig) 2681 { 2682 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2683 u32 usec = le32_to_cpu(trig->ignore_consec); 2684 2685 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2686 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2687 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2688 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2689 return false; 2690 2691 return true; 2692 } 2693 2694 static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2695 struct iwl_fwrt_dump_data *dump_data, 2696 struct list_head *list) 2697 { 2698 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2699 struct iwl_fw_ini_dump_entry *entry; 2700 struct iwl_fw_ini_dump_file_hdr *hdr; 2701 u32 size; 2702 2703 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2704 !le64_to_cpu(trigger->regions_mask)) 2705 return 0; 2706 2707 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2708 if (!entry) 2709 return 0; 2710 2711 entry->size = sizeof(*hdr); 2712 2713 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2714 if (!size) { 2715 vfree(entry); 2716 return 0; 2717 } 2718 2719 hdr = (void *)entry->data; 2720 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2721 hdr->file_len = cpu_to_le32(size + entry->size); 2722 2723 list_add(&entry->list, list); 2724 2725 return le32_to_cpu(hdr->file_len); 2726 } 2727 2728 static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2729 const struct iwl_fw_dump_desc *desc) 2730 { 2731 if (desc && desc != &iwl_dump_desc_assert) 2732 kfree(desc); 2733 2734 fwrt->dump.lmac_err_id[0] = 0; 2735 if (fwrt->smem_cfg.num_lmacs > 1) 2736 fwrt->dump.lmac_err_id[1] = 0; 2737 fwrt->dump.umac_err_id = 0; 2738 } 2739 2740 static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2741 struct iwl_fwrt_dump_data *dump_data) 2742 { 2743 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2744 struct iwl_fw_error_dump_file *dump_file; 2745 struct scatterlist *sg_dump_data; 2746 u32 file_len; 2747 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2748 2749 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2750 if (!dump_file) 2751 return; 2752 2753 if (dump_data->monitor_only) 2754 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2755 2756 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2757 fwrt->sanitize_ops, 2758 fwrt->sanitize_ctx); 2759 file_len = le32_to_cpu(dump_file->file_len); 2760 fw_error_dump.fwrt_len = file_len; 2761 2762 if (fw_error_dump.trans_ptr) { 2763 file_len += fw_error_dump.trans_ptr->len; 2764 dump_file->file_len = cpu_to_le32(file_len); 2765 } 2766 2767 sg_dump_data = alloc_sgtable(file_len); 2768 if (sg_dump_data) { 2769 sg_pcopy_from_buffer(sg_dump_data, 2770 sg_nents(sg_dump_data), 2771 fw_error_dump.fwrt_ptr, 2772 fw_error_dump.fwrt_len, 0); 2773 if (fw_error_dump.trans_ptr) 2774 sg_pcopy_from_buffer(sg_dump_data, 2775 sg_nents(sg_dump_data), 2776 fw_error_dump.trans_ptr->data, 2777 fw_error_dump.trans_ptr->len, 2778 fw_error_dump.fwrt_len); 2779 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2780 GFP_KERNEL); 2781 } 2782 vfree(fw_error_dump.fwrt_ptr); 2783 vfree(fw_error_dump.trans_ptr); 2784 } 2785 2786 static void iwl_dump_ini_list_free(struct list_head *list) 2787 { 2788 while (!list_empty(list)) { 2789 struct iwl_fw_ini_dump_entry *entry = 2790 list_entry(list->next, typeof(*entry), list); 2791 2792 list_del(&entry->list); 2793 vfree(entry); 2794 } 2795 } 2796 2797 static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2798 { 2799 dump_data->trig = NULL; 2800 kfree(dump_data->fw_pkt); 2801 dump_data->fw_pkt = NULL; 2802 } 2803 2804 static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2805 struct iwl_fwrt_dump_data *dump_data) 2806 { 2807 LIST_HEAD(dump_list); 2808 struct scatterlist *sg_dump_data; 2809 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2810 2811 if (!file_len) 2812 return; 2813 2814 sg_dump_data = alloc_sgtable(file_len); 2815 if (sg_dump_data) { 2816 struct iwl_fw_ini_dump_entry *entry; 2817 int sg_entries = sg_nents(sg_dump_data); 2818 u32 offs = 0; 2819 2820 list_for_each_entry(entry, &dump_list, list) { 2821 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2822 entry->data, entry->size, offs); 2823 offs += entry->size; 2824 } 2825 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2826 GFP_KERNEL); 2827 } 2828 iwl_dump_ini_list_free(&dump_list); 2829 } 2830 2831 const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2832 .trig_desc = { 2833 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2834 }, 2835 }; 2836 IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2837 2838 int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2839 const struct iwl_fw_dump_desc *desc, 2840 bool monitor_only, 2841 unsigned int delay) 2842 { 2843 struct iwl_fwrt_wk_data *wk_data; 2844 unsigned long idx; 2845 2846 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2847 iwl_fw_free_dump_desc(fwrt, desc); 2848 return 0; 2849 } 2850 2851 /* 2852 * Check there is an available worker. 2853 * ffz return value is undefined if no zero exists, 2854 * so check against ~0UL first. 2855 */ 2856 if (fwrt->dump.active_wks == ~0UL) 2857 return -EBUSY; 2858 2859 idx = ffz(fwrt->dump.active_wks); 2860 2861 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2862 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2863 return -EBUSY; 2864 2865 wk_data = &fwrt->dump.wks[idx]; 2866 2867 if (WARN_ON(wk_data->dump_data.desc)) 2868 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2869 2870 wk_data->dump_data.desc = desc; 2871 wk_data->dump_data.monitor_only = monitor_only; 2872 2873 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2874 le32_to_cpu(desc->trig_desc.type)); 2875 2876 queue_delayed_work(system_unbound_wq, &wk_data->wk, 2877 usecs_to_jiffies(delay)); 2878 2879 return 0; 2880 } 2881 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2882 2883 int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2884 enum iwl_fw_dbg_trigger trig_type) 2885 { 2886 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2887 return -EIO; 2888 2889 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2890 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2891 trig_type != FW_DBG_TRIGGER_DRIVER) 2892 return -EIO; 2893 2894 iwl_dbg_tlv_time_point(fwrt, 2895 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2896 NULL); 2897 } else { 2898 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2899 int ret; 2900 2901 iwl_dump_error_desc = 2902 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2903 2904 if (!iwl_dump_error_desc) 2905 return -ENOMEM; 2906 2907 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2908 iwl_dump_error_desc->len = 0; 2909 2910 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2911 false, 0); 2912 if (ret) { 2913 kfree(iwl_dump_error_desc); 2914 return ret; 2915 } 2916 } 2917 2918 iwl_trans_sync_nmi(fwrt->trans); 2919 2920 return 0; 2921 } 2922 IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2923 2924 int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2925 enum iwl_fw_dbg_trigger trig, 2926 const char *str, size_t len, 2927 struct iwl_fw_dbg_trigger_tlv *trigger) 2928 { 2929 struct iwl_fw_dump_desc *desc; 2930 unsigned int delay = 0; 2931 bool monitor_only = false; 2932 2933 if (trigger) { 2934 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2935 2936 if (!le16_to_cpu(trigger->occurrences)) 2937 return 0; 2938 2939 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2940 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2941 trig); 2942 iwl_force_nmi(fwrt->trans); 2943 return 0; 2944 } 2945 2946 trigger->occurrences = cpu_to_le16(occurrences); 2947 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2948 2949 /* convert msec to usec */ 2950 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2951 } 2952 2953 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC); 2954 if (!desc) 2955 return -ENOMEM; 2956 2957 2958 desc->len = len; 2959 desc->trig_desc.type = cpu_to_le32(trig); 2960 memcpy(desc->trig_desc.data, str, len); 2961 2962 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2963 } 2964 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2965 2966 int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2967 struct iwl_fw_dbg_trigger_tlv *trigger, 2968 const char *fmt, ...) 2969 { 2970 int ret, len = 0; 2971 char buf[64]; 2972 2973 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2974 return 0; 2975 2976 if (fmt) { 2977 va_list ap; 2978 2979 buf[sizeof(buf) - 1] = '\0'; 2980 2981 va_start(ap, fmt); 2982 vsnprintf(buf, sizeof(buf), fmt, ap); 2983 va_end(ap); 2984 2985 /* check for truncation */ 2986 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2987 buf[sizeof(buf) - 1] = '\0'; 2988 2989 len = strlen(buf) + 1; 2990 } 2991 2992 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2993 trigger); 2994 2995 if (ret) 2996 return ret; 2997 2998 return 0; 2999 } 3000 IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 3001 3002 int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 3003 { 3004 u8 *ptr; 3005 int ret; 3006 int i; 3007 3008 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 3009 "Invalid configuration %d\n", conf_id)) 3010 return -EINVAL; 3011 3012 /* EARLY START - firmware's configuration is hard coded */ 3013 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 3014 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 3015 conf_id == FW_DBG_START_FROM_ALIVE) 3016 return 0; 3017 3018 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 3019 return -EINVAL; 3020 3021 if (fwrt->dump.conf != FW_DBG_INVALID) 3022 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 3023 fwrt->dump.conf); 3024 3025 /* Send all HCMDs for configuring the FW debug */ 3026 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 3027 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 3028 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 3029 struct iwl_host_cmd hcmd = { 3030 .id = cmd->id, 3031 .len = { le16_to_cpu(cmd->len), }, 3032 .data = { cmd->data, }, 3033 }; 3034 3035 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3036 if (ret) 3037 return ret; 3038 3039 ptr += sizeof(*cmd); 3040 ptr += le16_to_cpu(cmd->len); 3041 } 3042 3043 fwrt->dump.conf = conf_id; 3044 3045 return 0; 3046 } 3047 IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 3048 3049 void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt, 3050 u32 timepoint, 3051 u32 timepoint_data) 3052 { 3053 struct iwl_dbg_dump_complete_cmd hcmd_data; 3054 struct iwl_host_cmd hcmd = { 3055 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD), 3056 .data[0] = &hcmd_data, 3057 .len[0] = sizeof(hcmd_data), 3058 }; 3059 3060 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3061 return; 3062 3063 if (fw_has_capa(&fwrt->fw->ucode_capa, 3064 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) { 3065 hcmd_data.tp = cpu_to_le32(timepoint); 3066 hcmd_data.tp_data = cpu_to_le32(timepoint_data); 3067 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3068 } 3069 } 3070 3071 /* this function assumes dump_start was called beforehand and dump_end will be 3072 * called afterwards 3073 */ 3074 static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 3075 { 3076 struct iwl_fw_dbg_params params = {0}; 3077 struct iwl_fwrt_dump_data *dump_data = 3078 &fwrt->dump.wks[wk_idx].dump_data; 3079 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 3080 return; 3081 3082 /* also checks 'desc' for pre-ini mode, since that shadows in union */ 3083 if (!dump_data->trig) { 3084 IWL_ERR(fwrt, "dump trigger data is not set\n"); 3085 goto out; 3086 } 3087 3088 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 3089 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 3090 goto out; 3091 } 3092 3093 /* there's no point in fw dump if the bus is dead */ 3094 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 3095 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 3096 goto out; 3097 } 3098 3099 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 3100 3101 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 3102 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 3103 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 3104 else 3105 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 3106 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 3107 3108 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3109 3110 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3111 u32 policy = le32_to_cpu(dump_data->trig->apply_policy); 3112 u32 time_point = le32_to_cpu(dump_data->trig->time_point); 3113 3114 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) { 3115 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n"); 3116 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0); 3117 } 3118 } 3119 3120 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 3121 iwl_force_nmi(fwrt->trans); 3122 3123 out: 3124 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3125 iwl_fw_error_dump_data_free(dump_data); 3126 } else { 3127 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 3128 dump_data->desc = NULL; 3129 } 3130 3131 clear_bit(wk_idx, &fwrt->dump.active_wks); 3132 } 3133 3134 int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 3135 struct iwl_fwrt_dump_data *dump_data, 3136 bool sync) 3137 { 3138 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 3139 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 3140 u32 occur, delay; 3141 unsigned long idx; 3142 3143 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 3144 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 3145 tp_id); 3146 return -EINVAL; 3147 } 3148 3149 delay = le32_to_cpu(trig->dump_delay); 3150 occur = le32_to_cpu(trig->occurrences); 3151 if (!occur) 3152 return 0; 3153 3154 trig->occurrences = cpu_to_le32(--occur); 3155 3156 /* Check there is an available worker. 3157 * ffz return value is undefined if no zero exists, 3158 * so check against ~0UL first. 3159 */ 3160 if (fwrt->dump.active_wks == ~0UL) 3161 return -EBUSY; 3162 3163 idx = ffz(fwrt->dump.active_wks); 3164 3165 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 3166 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 3167 return -EBUSY; 3168 3169 fwrt->dump.wks[idx].dump_data = *dump_data; 3170 3171 if (sync) 3172 delay = 0; 3173 3174 IWL_WARN(fwrt, 3175 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 3176 tp_id, (u32)(delay / USEC_PER_MSEC)); 3177 3178 if (sync) 3179 iwl_fw_dbg_collect_sync(fwrt, idx); 3180 else 3181 queue_delayed_work(system_unbound_wq, 3182 &fwrt->dump.wks[idx].wk, 3183 usecs_to_jiffies(delay)); 3184 3185 return 0; 3186 } 3187 3188 void iwl_fw_error_dump_wk(struct work_struct *work) 3189 { 3190 struct iwl_fwrt_wk_data *wks = 3191 container_of(work, typeof(*wks), wk.work); 3192 struct iwl_fw_runtime *fwrt = 3193 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 3194 3195 /* assumes the op mode mutex is locked in dump_start since 3196 * iwl_fw_dbg_collect_sync can't run in parallel 3197 */ 3198 if (fwrt->ops && fwrt->ops->dump_start) 3199 fwrt->ops->dump_start(fwrt->ops_ctx); 3200 3201 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 3202 3203 if (fwrt->ops && fwrt->ops->dump_end) 3204 fwrt->ops->dump_end(fwrt->ops_ctx); 3205 } 3206 3207 void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 3208 { 3209 const struct iwl_cfg *cfg = fwrt->trans->cfg; 3210 3211 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 3212 return; 3213 3214 if (!fwrt->dump.d3_debug_data) { 3215 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 3216 GFP_KERNEL); 3217 if (!fwrt->dump.d3_debug_data) { 3218 IWL_ERR(fwrt, 3219 "failed to allocate memory for D3 debug data\n"); 3220 return; 3221 } 3222 } 3223 3224 /* if the buffer holds previous debug data it is overwritten */ 3225 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 3226 fwrt->dump.d3_debug_data, 3227 cfg->d3_debug_data_length); 3228 3229 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 3230 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 3231 cfg->d3_debug_data_base_addr, 3232 fwrt->dump.d3_debug_data, 3233 cfg->d3_debug_data_length); 3234 } 3235 IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 3236 3237 void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 3238 { 3239 int i; 3240 3241 iwl_dbg_tlv_del_timers(fwrt->trans); 3242 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 3243 iwl_fw_dbg_collect_sync(fwrt, i); 3244 3245 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 3246 } 3247 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 3248 3249 static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 3250 { 3251 struct iwl_dbg_suspend_resume_cmd cmd = { 3252 .operation = suspend ? 3253 cpu_to_le32(DBGC_SUSPEND_CMD) : 3254 cpu_to_le32(DBGC_RESUME_CMD), 3255 }; 3256 struct iwl_host_cmd hcmd = { 3257 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3258 .data[0] = &cmd, 3259 .len[0] = sizeof(cmd), 3260 }; 3261 3262 return iwl_trans_send_cmd(trans, &hcmd); 3263 } 3264 3265 static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3266 struct iwl_fw_dbg_params *params) 3267 { 3268 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3269 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3270 return; 3271 } 3272 3273 if (params) { 3274 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3275 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3276 } 3277 3278 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3279 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3280 * avoid halting the HW while writing 3281 */ 3282 usleep_range(700, 1000); 3283 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3284 } 3285 3286 static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3287 struct iwl_fw_dbg_params *params) 3288 { 3289 if (!params) 3290 return -EIO; 3291 3292 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3293 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3294 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3295 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3296 } else { 3297 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3298 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3299 } 3300 3301 return 0; 3302 } 3303 3304 int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt) 3305 { 3306 struct iwl_mvm_marker marker = { 3307 .dw_len = sizeof(struct iwl_mvm_marker) / 4, 3308 .marker_id = MARKER_ID_SYNC_CLOCK, 3309 }; 3310 struct iwl_host_cmd hcmd = { 3311 .flags = CMD_ASYNC, 3312 .id = WIDE_ID(LONG_GROUP, MARKER_CMD), 3313 .dataflags = {}, 3314 }; 3315 struct iwl_mvm_marker_rsp *resp; 3316 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw, 3317 WIDE_ID(LONG_GROUP, MARKER_CMD), 3318 IWL_FW_CMD_VER_UNKNOWN); 3319 int ret; 3320 3321 if (cmd_ver == 1) { 3322 /* the real timestamp is taken from the ftrace clock 3323 * this is for finding the match between fw and kernel logs 3324 */ 3325 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++); 3326 } else if (cmd_ver == 2) { 3327 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns()); 3328 } else { 3329 IWL_DEBUG_INFO(fwrt, 3330 "Invalid version of Marker CMD. Ver = %d\n", 3331 cmd_ver); 3332 return -EINVAL; 3333 } 3334 3335 hcmd.data[0] = ▮ 3336 hcmd.len[0] = sizeof(marker); 3337 3338 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3339 3340 if (cmd_ver > 1 && hcmd.resp_pkt) { 3341 resp = (void *)hcmd.resp_pkt->data; 3342 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n", 3343 le32_to_cpu(resp->gp2)); 3344 } 3345 3346 return ret; 3347 } 3348 3349 void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3350 struct iwl_fw_dbg_params *params, 3351 bool stop) 3352 { 3353 int ret __maybe_unused = 0; 3354 3355 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3356 return; 3357 3358 if (fw_has_capa(&fwrt->fw->ucode_capa, 3359 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) { 3360 if (stop) 3361 iwl_fw_send_timestamp_marker_cmd(fwrt); 3362 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3363 } else if (stop) { 3364 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3365 } else { 3366 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3367 } 3368 #ifdef CONFIG_IWLWIFI_DEBUGFS 3369 if (!ret) { 3370 if (stop) 3371 fwrt->trans->dbg.rec_on = false; 3372 else 3373 iwl_fw_set_dbg_rec_on(fwrt); 3374 } 3375 #endif 3376 } 3377 IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3378 3379 void iwl_fw_disable_dbg_asserts(struct iwl_fw_runtime *fwrt) 3380 { 3381 struct iwl_fw_dbg_config_cmd cmd = { 3382 .type = cpu_to_le32(DEBUG_TOKEN_CONFIG_TYPE), 3383 .conf = cpu_to_le32(IWL_FW_DBG_CONFIG_TOKEN), 3384 }; 3385 struct iwl_host_cmd hcmd = { 3386 .id = WIDE_ID(LONG_GROUP, LDBG_CONFIG_CMD), 3387 .data[0] = &cmd, 3388 .len[0] = sizeof(cmd), 3389 }; 3390 u32 preset = u32_get_bits(fwrt->trans->dbg.domains_bitmap, 3391 GENMASK(31, IWL_FW_DBG_DOMAIN_POS + 1)); 3392 3393 /* supported starting from 9000 devices */ 3394 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000) 3395 return; 3396 3397 if (fwrt->trans->dbg.yoyo_bin_loaded || (preset && preset != 1)) 3398 return; 3399 3400 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3401 } 3402 IWL_EXPORT_SYMBOL(iwl_fw_disable_dbg_asserts); 3403 3404 void iwl_fw_dbg_clear_monitor_buf(struct iwl_fw_runtime *fwrt) 3405 { 3406 struct iwl_fw_dbg_params params = {0}; 3407 3408 iwl_fw_dbg_stop_sync(fwrt); 3409 3410 if (fw_has_api(&fwrt->fw->ucode_capa, 3411 IWL_UCODE_TLV_API_INT_DBG_BUF_CLEAR)) { 3412 struct iwl_host_cmd hcmd = { 3413 .id = WIDE_ID(DEBUG_GROUP, FW_CLEAR_BUFFER), 3414 }; 3415 iwl_trans_send_cmd(fwrt->trans, &hcmd); 3416 } 3417 3418 iwl_dbg_tlv_init_cfg(fwrt); 3419 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 3420 } 3421 IWL_EXPORT_SYMBOL(iwl_fw_dbg_clear_monitor_buf); 3422