1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2022, 2024-2025 Intel Corporation 4 * Copyright (C) 2017 Intel Deutschland GmbH 5 */ 6 #ifndef __iwl_fw_api_rs_h__ 7 #define __iwl_fw_api_rs_h__ 8 #include <linux/bitfield.h> 9 #include <linux/types.h> 10 #include <linux/bits.h> 11 #include "mac.h" 12 13 /** 14 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags 15 * @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for 16 * bandwidths <= 80MHz 17 * @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC 18 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz 19 * bandwidth 20 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation 21 * for BPSK (MCS 0) with 1 spatial 22 * stream 23 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation 24 * for BPSK (MCS 0) with 2 spatial 25 * streams 26 * @IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK: enable support for EHT extra LTF 27 */ 28 enum iwl_tlc_mng_cfg_flags { 29 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0), 30 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1), 31 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2), 32 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3), 33 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4), 34 IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK = BIT(6), 35 }; 36 37 /** 38 * enum iwl_tlc_mng_cfg_cw - channel width options 39 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel 40 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel 41 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel 42 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel 43 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel 44 */ 45 enum iwl_tlc_mng_cfg_cw { 46 IWL_TLC_MNG_CH_WIDTH_20MHZ, 47 IWL_TLC_MNG_CH_WIDTH_40MHZ, 48 IWL_TLC_MNG_CH_WIDTH_80MHZ, 49 IWL_TLC_MNG_CH_WIDTH_160MHZ, 50 IWL_TLC_MNG_CH_WIDTH_320MHZ, 51 }; 52 53 /** 54 * enum iwl_tlc_mng_cfg_chains - possible chains 55 * @IWL_TLC_MNG_CHAIN_A_MSK: chain A 56 * @IWL_TLC_MNG_CHAIN_B_MSK: chain B 57 */ 58 enum iwl_tlc_mng_cfg_chains { 59 IWL_TLC_MNG_CHAIN_A_MSK = BIT(0), 60 IWL_TLC_MNG_CHAIN_B_MSK = BIT(1), 61 }; 62 63 /** 64 * enum iwl_tlc_mng_cfg_mode - supported modes 65 * @IWL_TLC_MNG_MODE_CCK: enable CCK 66 * @IWL_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT) 67 * @IWL_TLC_MNG_MODE_NON_HT: enable non HT 68 * @IWL_TLC_MNG_MODE_HT: enable HT 69 * @IWL_TLC_MNG_MODE_VHT: enable VHT 70 * @IWL_TLC_MNG_MODE_HE: enable HE 71 * @IWL_TLC_MNG_MODE_EHT: enable EHT 72 */ 73 enum iwl_tlc_mng_cfg_mode { 74 IWL_TLC_MNG_MODE_CCK = 0, 75 IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK, 76 IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK, 77 IWL_TLC_MNG_MODE_HT, 78 IWL_TLC_MNG_MODE_VHT, 79 IWL_TLC_MNG_MODE_HE, 80 IWL_TLC_MNG_MODE_EHT, 81 }; 82 83 /** 84 * enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates 85 * @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0 86 * @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1 87 * @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2 88 * @IWL_TLC_MNG_HT_RATE_MCS3: index of MCS3 89 * @IWL_TLC_MNG_HT_RATE_MCS4: index of MCS4 90 * @IWL_TLC_MNG_HT_RATE_MCS5: index of MCS5 91 * @IWL_TLC_MNG_HT_RATE_MCS6: index of MCS6 92 * @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7 93 * @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8 94 * @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9 95 * @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10 96 * @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11 97 * @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT 98 */ 99 enum iwl_tlc_mng_ht_rates { 100 IWL_TLC_MNG_HT_RATE_MCS0 = 0, 101 IWL_TLC_MNG_HT_RATE_MCS1, 102 IWL_TLC_MNG_HT_RATE_MCS2, 103 IWL_TLC_MNG_HT_RATE_MCS3, 104 IWL_TLC_MNG_HT_RATE_MCS4, 105 IWL_TLC_MNG_HT_RATE_MCS5, 106 IWL_TLC_MNG_HT_RATE_MCS6, 107 IWL_TLC_MNG_HT_RATE_MCS7, 108 IWL_TLC_MNG_HT_RATE_MCS8, 109 IWL_TLC_MNG_HT_RATE_MCS9, 110 IWL_TLC_MNG_HT_RATE_MCS10, 111 IWL_TLC_MNG_HT_RATE_MCS11, 112 IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11, 113 }; 114 115 enum IWL_TLC_MNG_NSS { 116 IWL_TLC_NSS_1, 117 IWL_TLC_NSS_2, 118 IWL_TLC_NSS_MAX 119 }; 120 121 /** 122 * enum IWL_TLC_MCS_PER_BW - mcs index per BW 123 * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz 124 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz 125 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz 126 * @IWL_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3 127 * @IWL_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4 128 */ 129 enum IWL_TLC_MCS_PER_BW { 130 IWL_TLC_MCS_PER_BW_80, 131 IWL_TLC_MCS_PER_BW_160, 132 IWL_TLC_MCS_PER_BW_320, 133 IWL_TLC_MCS_PER_BW_NUM_V3 = IWL_TLC_MCS_PER_BW_160 + 1, 134 IWL_TLC_MCS_PER_BW_NUM_V4 = IWL_TLC_MCS_PER_BW_320 + 1, 135 }; 136 137 /** 138 * struct iwl_tlc_config_cmd_v3 - TLC configuration 139 * @sta_id: station id 140 * @reserved1: reserved 141 * @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw 142 * @mode: &enum iwl_tlc_mng_cfg_mode 143 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 144 * @amsdu: TX amsdu is supported 145 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 146 * @non_ht_rates: bitmap of supported legacy rates 147 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per &enum IWL_TLC_MCS_PER_BW 148 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz). 149 * @max_mpdu_len: max MPDU length, in bytes 150 * @sgi_ch_width_supp: bitmap of SGI support per channel width 151 * use BIT(@enum iwl_tlc_mng_cfg_cw) 152 * @reserved2: reserved 153 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 154 * set zero for no limit. 155 */ 156 struct iwl_tlc_config_cmd_v3 { 157 u8 sta_id; 158 u8 reserved1[3]; 159 u8 max_ch_width; 160 u8 mode; 161 u8 chains; 162 u8 amsdu; 163 __le16 flags; 164 __le16 non_ht_rates; 165 __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V3]; 166 __le16 max_mpdu_len; 167 u8 sgi_ch_width_supp; 168 u8 reserved2; 169 __le32 max_tx_op; 170 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */ 171 172 /** 173 * struct iwl_tlc_config_cmd_v4 - TLC configuration 174 * @sta_id: station id 175 * @reserved1: reserved 176 * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw 177 * @mode: &enum iwl_tlc_mng_cfg_mode 178 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 179 * @sgi_ch_width_supp: bitmap of SGI support per channel width 180 * use BIT(&enum iwl_tlc_mng_cfg_cw) 181 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 182 * @non_ht_rates: bitmap of supported legacy rates 183 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width> 184 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz). 185 * @max_mpdu_len: max MPDU length, in bytes 186 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 187 * set zero for no limit. 188 */ 189 struct iwl_tlc_config_cmd_v4 { 190 u8 sta_id; 191 u8 reserved1[3]; 192 u8 max_ch_width; 193 u8 mode; 194 u8 chains; 195 u8 sgi_ch_width_supp; 196 __le16 flags; 197 __le16 non_ht_rates; 198 __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4]; 199 __le16 max_mpdu_len; 200 __le16 max_tx_op; 201 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */ 202 203 /** 204 * enum iwl_tlc_update_flags - updated fields 205 * @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update 206 * @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update 207 */ 208 enum iwl_tlc_update_flags { 209 IWL_TLC_NOTIF_FLAG_RATE = BIT(0), 210 IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1), 211 }; 212 213 /** 214 * struct iwl_tlc_update_notif - TLC notification from FW 215 * @sta_id: station id 216 * @reserved: reserved 217 * @flags: bitmap of notifications reported 218 * @rate: current initial rate, format depends on the notification 219 * version 220 * @amsdu_size: Max AMSDU size, in bytes 221 * @amsdu_enabled: bitmap for per-TID AMSDU enablement 222 */ 223 struct iwl_tlc_update_notif { 224 u8 sta_id; 225 u8 reserved[3]; 226 __le32 flags; 227 __le32 rate; 228 __le32 amsdu_size; 229 __le32 amsdu_enabled; 230 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2, _VER_3, _VER_4 */ 231 232 /** 233 * enum iwl_tlc_debug_types - debug options 234 */ 235 enum iwl_tlc_debug_types { 236 /** 237 * @IWL_TLC_DEBUG_FIXED_RATE: set fixed rate for rate scaling 238 */ 239 IWL_TLC_DEBUG_FIXED_RATE, 240 /** 241 * @IWL_TLC_DEBUG_AGG_DURATION_LIM: time limit for a BA 242 * session, in usec 243 */ 244 IWL_TLC_DEBUG_AGG_DURATION_LIM, 245 /** 246 * @IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM: set max number of frames 247 * in an aggregation 248 */ 249 IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM, 250 /** 251 * @IWL_TLC_DEBUG_TPC_ENABLED: enable or disable tpc 252 */ 253 IWL_TLC_DEBUG_TPC_ENABLED, 254 /** 255 * @IWL_TLC_DEBUG_TPC_STATS: get number of frames Tx'ed in each 256 * tpc step 257 */ 258 IWL_TLC_DEBUG_TPC_STATS, 259 /** 260 * @IWL_TLC_DEBUG_RTS_DISABLE: disable RTS (bool true/false). 261 */ 262 IWL_TLC_DEBUG_RTS_DISABLE, 263 /** 264 * @IWL_TLC_DEBUG_PARTIAL_FIXED_RATE: set partial fixed rate to fw 265 */ 266 IWL_TLC_DEBUG_PARTIAL_FIXED_RATE, 267 }; /* TLC_MNG_DEBUG_TYPES_API_E */ 268 269 #define MAX_DATA_IN_DHC_TLC_CMD 10 270 271 /** 272 * struct iwl_dhc_tlc_cmd - fixed debug config 273 * @sta_id: bit 0 - enable/disable, bits 1 - 7 hold station id 274 * @reserved1: reserved 275 * @type: type id of %enum iwl_tlc_debug_types 276 * @data: data to send 277 */ 278 struct iwl_dhc_tlc_cmd { 279 u8 sta_id; 280 u8 reserved1[3]; 281 __le32 type; 282 __le32 data[MAX_DATA_IN_DHC_TLC_CMD]; 283 } __packed; /* TLC_MNG_DEBUG_CMD_S */ 284 285 #define IWL_MAX_MCS_DISPLAY_SIZE 12 286 287 struct iwl_rate_mcs_info { 288 char mbps[IWL_MAX_MCS_DISPLAY_SIZE]; 289 char mcs[IWL_MAX_MCS_DISPLAY_SIZE]; 290 }; 291 292 /* 293 * These serve as indexes into 294 * struct iwl_rate_info fw_rate_idx_to_plcp[IWL_RATE_COUNT]; 295 * TODO: avoid overlap between legacy and HT rates 296 */ 297 enum { 298 IWL_RATE_1M_INDEX = 0, 299 IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX, 300 IWL_RATE_2M_INDEX, 301 IWL_RATE_5M_INDEX, 302 IWL_RATE_11M_INDEX, 303 IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX, 304 IWL_RATE_6M_INDEX, 305 IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX, 306 IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX, 307 IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX, 308 IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX, 309 IWL_RATE_9M_INDEX, 310 IWL_RATE_12M_INDEX, 311 IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX, 312 IWL_RATE_18M_INDEX, 313 IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX, 314 IWL_RATE_24M_INDEX, 315 IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX, 316 IWL_RATE_36M_INDEX, 317 IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX, 318 IWL_RATE_48M_INDEX, 319 IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX, 320 IWL_RATE_54M_INDEX, 321 IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX, 322 IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX, 323 IWL_RATE_60M_INDEX, 324 IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX, 325 IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX, 326 IWL_RATE_MCS_8_INDEX, 327 IWL_RATE_MCS_9_INDEX, 328 IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX, 329 IWL_RATE_MCS_10_INDEX, 330 IWL_RATE_MCS_11_INDEX, 331 IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX, 332 IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1, 333 IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1, 334 IWL_RATE_INVM_INDEX = IWL_RATE_COUNT, 335 IWL_RATE_INVALID = IWL_RATE_COUNT, 336 }; 337 338 #define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX) 339 340 /* fw API values for legacy bit rates, both OFDM and CCK */ 341 enum { 342 IWL_RATE_6M_PLCP = 13, 343 IWL_RATE_9M_PLCP = 15, 344 IWL_RATE_12M_PLCP = 5, 345 IWL_RATE_18M_PLCP = 7, 346 IWL_RATE_24M_PLCP = 9, 347 IWL_RATE_36M_PLCP = 11, 348 IWL_RATE_48M_PLCP = 1, 349 IWL_RATE_54M_PLCP = 3, 350 IWL_RATE_1M_PLCP = 10, 351 IWL_RATE_2M_PLCP = 20, 352 IWL_RATE_5M_PLCP = 55, 353 IWL_RATE_11M_PLCP = 110, 354 IWL_RATE_INVM_PLCP = -1, 355 }; 356 357 /* 358 * rate_n_flags bit fields version 1 359 * 360 * The 32-bit value has different layouts in the low 8 bites depending on the 361 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 362 * for CCK and OFDM). 363 * 364 * High-throughput (HT) rate format 365 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 366 * Very High-throughput (VHT) rate format 367 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 368 * Legacy OFDM rate format for bits 7:0 369 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 370 * Legacy CCK rate format for bits 7:0: 371 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 372 */ 373 374 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 375 #define RATE_MCS_HT_POS 8 376 #define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS) 377 378 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 379 #define RATE_MCS_CCK_POS_V1 9 380 #define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1) 381 382 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 383 #define RATE_MCS_VHT_POS_V1 26 384 #define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1) 385 386 387 /* 388 * High-throughput (HT) rate format for bits 7:0 389 * 390 * 2-0: MCS rate base 391 * 0) 6 Mbps 392 * 1) 12 Mbps 393 * 2) 18 Mbps 394 * 3) 24 Mbps 395 * 4) 36 Mbps 396 * 5) 48 Mbps 397 * 6) 54 Mbps 398 * 7) 60 Mbps 399 * 4-3: 0) Single stream (SISO) 400 * 1) Dual stream (MIMO) 401 * 2) Triple stream (MIMO) 402 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 403 * (bits 7-6 are zero) 404 * 405 * Together the low 5 bits work out to the MCS index because we don't 406 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 407 * streams and 16-23 have three streams. We could also support MCS 32 408 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 409 */ 410 #define RATE_HT_MCS_RATE_CODE_MSK_V1 0x7 411 #define RATE_HT_MCS_NSS_POS_V1 3 412 #define RATE_HT_MCS_NSS_MSK_V1 (3 << RATE_HT_MCS_NSS_POS_V1) 413 #define RATE_HT_MCS_MIMO2_MSK BIT(RATE_HT_MCS_NSS_POS_V1) 414 415 /* Bit 10: (1) Use Green Field preamble */ 416 #define RATE_HT_MCS_GF_POS 10 417 #define RATE_HT_MCS_GF_MSK (1 << RATE_HT_MCS_GF_POS) 418 419 #define RATE_HT_MCS_INDEX_MSK_V1 0x3f 420 421 /* 422 * Very High-throughput (VHT) rate format for bits 7:0 423 * 424 * 3-0: VHT MCS (0-9) 425 * 5-4: number of streams - 1: 426 * 0) Single stream (SISO) 427 * 1) Dual stream (MIMO) 428 * 2) Triple stream (MIMO) 429 */ 430 431 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 432 #define RATE_VHT_MCS_RATE_CODE_MSK 0xf 433 #define RATE_VHT_MCS_NSS_MSK 0x30 434 435 /* 436 * Legacy OFDM rate format for bits 7:0 437 * 438 * 3-0: 0xD) 6 Mbps 439 * 0xF) 9 Mbps 440 * 0x5) 12 Mbps 441 * 0x7) 18 Mbps 442 * 0x9) 24 Mbps 443 * 0xB) 36 Mbps 444 * 0x1) 48 Mbps 445 * 0x3) 54 Mbps 446 * (bits 7-4 are 0) 447 * 448 * Legacy CCK rate format for bits 7:0: 449 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 450 * 451 * 6-0: 10) 1 Mbps 452 * 20) 2 Mbps 453 * 55) 5.5 Mbps 454 * 110) 11 Mbps 455 * (bit 7 is 0) 456 */ 457 #define RATE_LEGACY_RATE_MSK_V1 0xff 458 459 /* Bit 10 - OFDM HE */ 460 #define RATE_MCS_HE_POS_V1 10 461 #define RATE_MCS_HE_MSK_V1 BIT(RATE_MCS_HE_POS_V1) 462 463 /* 464 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 465 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 466 */ 467 #define RATE_MCS_CHAN_WIDTH_POS 11 468 #define RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << RATE_MCS_CHAN_WIDTH_POS) 469 470 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 471 #define RATE_MCS_SGI_POS_V1 13 472 #define RATE_MCS_SGI_MSK_V1 BIT(RATE_MCS_SGI_POS_V1) 473 474 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 475 #define RATE_MCS_ANT_POS 14 476 #define RATE_MCS_ANT_A_MSK (1 << RATE_MCS_ANT_POS) 477 #define RATE_MCS_ANT_B_MSK (2 << RATE_MCS_ANT_POS) 478 #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | \ 479 RATE_MCS_ANT_B_MSK) 480 #define RATE_MCS_ANT_MSK RATE_MCS_ANT_AB_MSK 481 482 /* Bit 17: (0) SS, (1) SS*2 */ 483 #define RATE_MCS_STBC_POS 17 484 #define RATE_MCS_STBC_MSK BIT(RATE_MCS_STBC_POS) 485 486 /* Bit 18: OFDM-HE dual carrier mode */ 487 #define RATE_HE_DUAL_CARRIER_MODE 18 488 #define RATE_HE_DUAL_CARRIER_MODE_MSK BIT(RATE_HE_DUAL_CARRIER_MODE) 489 490 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 491 #define RATE_MCS_BF_POS 19 492 #define RATE_MCS_BF_MSK (1 << RATE_MCS_BF_POS) 493 494 /* 495 * Bit 20-21: HE LTF type and guard interval 496 * HE (ext) SU: 497 * 0 1xLTF+0.8us 498 * 1 2xLTF+0.8us 499 * 2 2xLTF+1.6us 500 * 3 & SGI (bit 13) clear 4xLTF+3.2us 501 * 3 & SGI (bit 13) set 4xLTF+0.8us 502 * HE MU: 503 * 0 4xLTF+0.8us 504 * 1 2xLTF+0.8us 505 * 2 2xLTF+1.6us 506 * 3 4xLTF+3.2us 507 * HE-EHT TRIG: 508 * 0 1xLTF+1.6us 509 * 1 2xLTF+1.6us 510 * 2 4xLTF+3.2us 511 * 3 (does not occur) 512 * EHT MU: 513 * 0 2xLTF+0.8us 514 * 1 2xLTF+1.6us 515 * 2 4xLTF+0.8us 516 * 3 4xLTF+3.2us 517 */ 518 #define RATE_MCS_HE_GI_LTF_POS 20 519 #define RATE_MCS_HE_GI_LTF_MSK_V1 (3 << RATE_MCS_HE_GI_LTF_POS) 520 521 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 522 #define RATE_MCS_HE_TYPE_POS_V1 22 523 #define RATE_MCS_HE_TYPE_SU_V1 (0 << RATE_MCS_HE_TYPE_POS_V1) 524 #define RATE_MCS_HE_TYPE_EXT_SU_V1 BIT(RATE_MCS_HE_TYPE_POS_V1) 525 #define RATE_MCS_HE_TYPE_MU_V1 (2 << RATE_MCS_HE_TYPE_POS_V1) 526 #define RATE_MCS_HE_TYPE_TRIG_V1 (3 << RATE_MCS_HE_TYPE_POS_V1) 527 #define RATE_MCS_HE_TYPE_MSK_V1 (3 << RATE_MCS_HE_TYPE_POS_V1) 528 529 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 530 #define RATE_MCS_DUP_POS_V1 24 531 #define RATE_MCS_DUP_MSK_V1 (3 << RATE_MCS_DUP_POS_V1) 532 533 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 534 #define RATE_MCS_LDPC_POS_V1 27 535 #define RATE_MCS_LDPC_MSK_V1 BIT(RATE_MCS_LDPC_POS_V1) 536 537 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 538 #define RATE_MCS_HE_106T_POS_V1 28 539 #define RATE_MCS_HE_106T_MSK_V1 BIT(RATE_MCS_HE_106T_POS_V1) 540 541 /* Bit 30-31: (1) RTS, (2) CTS */ 542 #define RATE_MCS_RTS_REQUIRED_POS (30) 543 #define RATE_MCS_RTS_REQUIRED_MSK (0x1 << RATE_MCS_RTS_REQUIRED_POS) 544 545 #define RATE_MCS_CTS_REQUIRED_POS (31) 546 #define RATE_MCS_CTS_REQUIRED_MSK (0x1 << RATE_MCS_CTS_REQUIRED_POS) 547 548 /* rate_n_flags bit field version 2 and 3 549 * 550 * The 32-bit value has different layouts in the low 8 bits depending on the 551 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 552 * for CCK and OFDM). 553 * 554 */ 555 556 /* Bits 10-8: rate format 557 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT) 558 * (3) Very High-throughput (VHT) (4) High-efficiency (HE) 559 * (5) Extremely High-throughput (EHT) 560 * (6) Ultra High Reliability (UHR) (v3 rate format only) 561 */ 562 #define RATE_MCS_MOD_TYPE_POS 8 563 #define RATE_MCS_MOD_TYPE_MSK (0x7 << RATE_MCS_MOD_TYPE_POS) 564 #define RATE_MCS_MOD_TYPE_CCK (0 << RATE_MCS_MOD_TYPE_POS) 565 #define RATE_MCS_MOD_TYPE_LEGACY_OFDM (1 << RATE_MCS_MOD_TYPE_POS) 566 #define RATE_MCS_MOD_TYPE_HT (2 << RATE_MCS_MOD_TYPE_POS) 567 #define RATE_MCS_MOD_TYPE_VHT (3 << RATE_MCS_MOD_TYPE_POS) 568 #define RATE_MCS_MOD_TYPE_HE (4 << RATE_MCS_MOD_TYPE_POS) 569 #define RATE_MCS_MOD_TYPE_EHT (5 << RATE_MCS_MOD_TYPE_POS) 570 #define RATE_MCS_MOD_TYPE_UHR (6 << RATE_MCS_MOD_TYPE_POS) 571 572 /* 573 * Legacy CCK rate format for bits 0:3: 574 * 575 * (0) 1 Mbps 576 * (1) 2 Mbps 577 * (2) 5.5 Mbps 578 * (3) 11 Mbps 579 * 580 * Legacy OFDM rate format for bis 3:0: 581 * 582 * (0) 6 Mbps 583 * (1) 9 Mbps 584 * (2) 12 Mbps 585 * (3) 18 Mbps 586 * (4) 24 Mbps 587 * (5) 36 Mbps 588 * (6) 48 Mbps 589 * (7) 54 Mbps 590 * 591 */ 592 #define RATE_LEGACY_RATE_MSK 0x7 593 594 /* 595 * HT, VHT, HE, EHT, UHR rate format 596 * Version 2: (not applicable for UHR) 597 * 3-0: MCS 598 * 4: NSS==2 indicator 599 * Version 3: 600 * 4-0: MCS 601 * 5: NSS==2 indicator 602 */ 603 #define RATE_HT_MCS_CODE_MSK 0x7 604 #define RATE_MCS_NSS_MSK_V2 0x10 605 #define RATE_MCS_NSS_MSK 0x20 606 #define RATE_MCS_CODE_MSK 0x1f 607 #define RATE_HT_MCS_INDEX(r) ((((r) & RATE_MCS_NSS_MSK) >> 2) | \ 608 ((r) & RATE_HT_MCS_CODE_MSK)) 609 610 /* Bits 7-5: reserved */ 611 612 /* 613 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz 614 */ 615 #define RATE_MCS_CHAN_WIDTH_MSK (0x7 << RATE_MCS_CHAN_WIDTH_POS) 616 #define RATE_MCS_CHAN_WIDTH_20_VAL 0 617 #define RATE_MCS_CHAN_WIDTH_20 (RATE_MCS_CHAN_WIDTH_20_VAL << RATE_MCS_CHAN_WIDTH_POS) 618 #define RATE_MCS_CHAN_WIDTH_40_VAL 1 619 #define RATE_MCS_CHAN_WIDTH_40 (RATE_MCS_CHAN_WIDTH_40_VAL << RATE_MCS_CHAN_WIDTH_POS) 620 #define RATE_MCS_CHAN_WIDTH_80_VAL 2 621 #define RATE_MCS_CHAN_WIDTH_80 (RATE_MCS_CHAN_WIDTH_80_VAL << RATE_MCS_CHAN_WIDTH_POS) 622 #define RATE_MCS_CHAN_WIDTH_160_VAL 3 623 #define RATE_MCS_CHAN_WIDTH_160 (RATE_MCS_CHAN_WIDTH_160_VAL << RATE_MCS_CHAN_WIDTH_POS) 624 #define RATE_MCS_CHAN_WIDTH_320_VAL 4 625 #define RATE_MCS_CHAN_WIDTH_320 (RATE_MCS_CHAN_WIDTH_320_VAL << RATE_MCS_CHAN_WIDTH_POS) 626 627 /* Bit 15-14: Antenna selection: 628 * Bit 14: Ant A active 629 * Bit 15: Ant B active 630 * 631 * All relevant definitions are same as in v1 632 */ 633 634 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */ 635 #define RATE_MCS_LDPC_POS 16 636 #define RATE_MCS_LDPC_MSK (1 << RATE_MCS_LDPC_POS) 637 638 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */ 639 640 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */ 641 642 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */ 643 644 /* 645 * Bit 22-20: HE LTF type and guard interval 646 * CCK: 647 * 0 long preamble 648 * 1 short preamble 649 * HT/VHT: 650 * 0 0.8us 651 * 1 0.4us 652 * HE (ext) SU: 653 * 0 1xLTF+0.8us 654 * 1 2xLTF+0.8us 655 * 2 2xLTF+1.6us 656 * 3 4xLTF+3.2us 657 * 4 4xLTF+0.8us 658 * HE MU: 659 * 0 4xLTF+0.8us 660 * 1 2xLTF+0.8us 661 * 2 2xLTF+1.6us 662 * 3 4xLTF+3.2us 663 * HE TRIG: 664 * 0 1xLTF+1.6us 665 * 1 2xLTF+1.6us 666 * 2 4xLTF+3.2us 667 * */ 668 #define RATE_MCS_HE_GI_LTF_MSK (0x7 << RATE_MCS_HE_GI_LTF_POS) 669 #define RATE_MCS_SGI_POS RATE_MCS_HE_GI_LTF_POS 670 #define RATE_MCS_SGI_MSK (1 << RATE_MCS_SGI_POS) 671 #define RATE_MCS_HE_SU_4_LTF 3 672 #define RATE_MCS_HE_SU_4_LTF_08_GI 4 673 674 /* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 675 #define RATE_MCS_HE_TYPE_POS 23 676 #define RATE_MCS_HE_TYPE_SU (0 << RATE_MCS_HE_TYPE_POS) 677 #define RATE_MCS_HE_TYPE_EXT_SU (1 << RATE_MCS_HE_TYPE_POS) 678 #define RATE_MCS_HE_TYPE_MU (2 << RATE_MCS_HE_TYPE_POS) 679 #define RATE_MCS_HE_TYPE_TRIG (3 << RATE_MCS_HE_TYPE_POS) 680 #define RATE_MCS_HE_TYPE_MSK (3 << RATE_MCS_HE_TYPE_POS) 681 682 /* Bit 25: duplicate channel enabled 683 * 684 * if this bit is set, duplicate is according to BW (bits 11-13): 685 * 686 * CCK: 2x 20MHz 687 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16) 688 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160) 689 * */ 690 #define RATE_MCS_DUP_POS 25 691 #define RATE_MCS_DUP_MSK (1 << RATE_MCS_DUP_POS) 692 693 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 694 #define RATE_MCS_HE_106T_POS 26 695 #define RATE_MCS_HE_106T_MSK (1 << RATE_MCS_HE_106T_POS) 696 697 /* Bit 27: EHT extra LTF: 698 * instead of 1 LTF for SISO use 2 LTFs, 699 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/ 700 #define RATE_MCS_EHT_EXTRA_LTF_POS 27 701 #define RATE_MCS_EHT_EXTRA_LTF_MSK (1 << RATE_MCS_EHT_EXTRA_LTF_POS) 702 703 /* Bit 31-28: reserved */ 704 705 /* Link Quality definitions */ 706 707 /* # entries in rate scale table to support Tx retries */ 708 #define LQ_MAX_RETRY_NUM 16 709 710 /* Link quality command flags bit fields */ 711 712 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 713 #define LQ_FLAG_USE_RTS_POS 0 714 #define LQ_FLAG_USE_RTS_MSK (1 << LQ_FLAG_USE_RTS_POS) 715 716 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 717 #define LQ_FLAG_COLOR_POS 1 718 #define LQ_FLAG_COLOR_MSK (7 << LQ_FLAG_COLOR_POS) 719 #define LQ_FLAG_COLOR_GET(_f) (((_f) & LQ_FLAG_COLOR_MSK) >>\ 720 LQ_FLAG_COLOR_POS) 721 #define LQ_FLAGS_COLOR_INC(_c) ((((_c) + 1) << LQ_FLAG_COLOR_POS) &\ 722 LQ_FLAG_COLOR_MSK) 723 #define LQ_FLAG_COLOR_SET(_f, _c) ((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK)) 724 725 /* Bit 4-5: Tx RTS BW Signalling 726 * (0) No RTS BW signalling 727 * (1) Static BW signalling 728 * (2) Dynamic BW signalling 729 */ 730 #define LQ_FLAG_RTS_BW_SIG_POS 4 731 #define LQ_FLAG_RTS_BW_SIG_NONE (0 << LQ_FLAG_RTS_BW_SIG_POS) 732 #define LQ_FLAG_RTS_BW_SIG_STATIC (1 << LQ_FLAG_RTS_BW_SIG_POS) 733 #define LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << LQ_FLAG_RTS_BW_SIG_POS) 734 735 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 736 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 737 */ 738 #define LQ_FLAG_DYNAMIC_BW_POS 6 739 #define LQ_FLAG_DYNAMIC_BW_MSK (1 << LQ_FLAG_DYNAMIC_BW_POS) 740 741 /* Single Stream Tx Parameters (lq_cmd->ss_params) 742 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 743 * used for single stream Tx. 744 */ 745 746 /* Bit 0-1: Max STBC streams allowed. Can be 0-3. 747 * (0) - No STBC allowed 748 * (1) - 2x1 STBC allowed (HT/VHT) 749 * (2) - 4x2 STBC allowed (HT/VHT) 750 * (3) - 3x2 STBC allowed (HT only) 751 * All our chips are at most 2 antennas so only (1) is valid for now. 752 */ 753 #define LQ_SS_STBC_ALLOWED_POS 0 754 #define LQ_SS_STBC_ALLOWED_MSK (3 << LQ_SS_STBC_ALLOWED_MSK) 755 756 /* 2x1 STBC is allowed */ 757 #define LQ_SS_STBC_1SS_ALLOWED (1 << LQ_SS_STBC_ALLOWED_POS) 758 759 /* Bit 2: Beamformer (VHT only) is allowed */ 760 #define LQ_SS_BFER_ALLOWED_POS 2 761 #define LQ_SS_BFER_ALLOWED (1 << LQ_SS_BFER_ALLOWED_POS) 762 763 /* Bit 3: Force BFER or STBC for testing 764 * If this is set: 765 * If BFER is allowed then force the ucode to choose BFER else 766 * If STBC is allowed then force the ucode to choose STBC over SISO 767 */ 768 #define LQ_SS_FORCE_POS 3 769 #define LQ_SS_FORCE (1 << LQ_SS_FORCE_POS) 770 771 /* Bit 31: ss_params field is valid. Used for FW backward compatibility 772 * with other drivers which don't support the ss_params API yet 773 */ 774 #define LQ_SS_PARAMS_VALID_POS 31 775 #define LQ_SS_PARAMS_VALID (1 << LQ_SS_PARAMS_VALID_POS) 776 777 /** 778 * struct iwl_lq_cmd - link quality command 779 * @sta_id: station to update 780 * @reduced_tpc: reduced transmit power control value 781 * @control: not used 782 * @flags: combination of LQ_FLAG_* 783 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 784 * and SISO rates 785 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 786 * Should be ANT_[ABC] 787 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 788 * @initial_rate_index: first index from rs_table per AC category 789 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 790 * value of 100 is one usec. Range is 100 to 8000 791 * @agg_disable_start_th: try-count threshold for starting aggregation. 792 * If a frame has higher try-count, it should not be selected for 793 * starting an aggregation sequence. 794 * @agg_frame_cnt_limit: max frame count in an aggregation. 795 * 0: no limit 796 * 1: no aggregation (one frame per aggregation) 797 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 798 * @reserved2: reserved 799 * @rs_table: array of rates for each TX try, each is rate_n_flags, 800 * meaning it is a combination of RATE_MCS_* and IWL_RATE_*_PLCP 801 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 802 */ 803 struct iwl_lq_cmd { 804 u8 sta_id; 805 u8 reduced_tpc; 806 __le16 control; 807 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 808 u8 flags; 809 u8 mimo_delim; 810 u8 single_stream_ant_msk; 811 u8 dual_stream_ant_msk; 812 u8 initial_rate_index[AC_NUM]; 813 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 814 __le16 agg_time_limit; 815 u8 agg_disable_start_th; 816 u8 agg_frame_cnt_limit; 817 __le32 reserved2; 818 __le32 rs_table[LQ_MAX_RETRY_NUM]; 819 __le32 ss_params; 820 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 821 822 u8 iwl_fw_rate_idx_to_plcp(int idx); 823 const struct iwl_rate_mcs_info *iwl_rate_mcs(int idx); 824 const char *iwl_rs_pretty_ant(u8 ant); 825 const char *iwl_rs_pretty_bw(int bw); 826 int rs_pretty_print_rate(char *buf, int bufsz, const u32 rate); 827 bool iwl_he_is_sgi(u32 rate_n_flags); 828 829 static inline u32 iwl_v3_rate_from_v2_v3(__le32 rate, bool fw_v3) 830 { 831 u32 val; 832 833 if (fw_v3) 834 return le32_to_cpu(rate); 835 836 val = le32_to_cpu(rate) & ~RATE_MCS_NSS_MSK_V2; 837 val |= u32_encode_bits(le32_get_bits(rate, RATE_MCS_NSS_MSK_V2), 838 RATE_MCS_NSS_MSK); 839 840 return val; 841 } 842 843 static inline __le32 iwl_v3_rate_to_v2_v3(u32 rate, bool fw_v3) 844 { 845 __le32 val; 846 847 if (fw_v3) 848 return cpu_to_le32(rate); 849 850 val = cpu_to_le32(rate & ~RATE_MCS_NSS_MSK); 851 val |= le32_encode_bits(u32_get_bits(rate, RATE_MCS_NSS_MSK), 852 RATE_MCS_NSS_MSK_V2); 853 854 return val; 855 } 856 857 #endif /* __iwl_fw_api_rs_h__ */ 858