1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2022, 2024-2025 Intel Corporation 4 * Copyright (C) 2017 Intel Deutschland GmbH 5 */ 6 #ifndef __iwl_fw_api_rs_h__ 7 #define __iwl_fw_api_rs_h__ 8 #include <linux/bitfield.h> 9 #include <linux/types.h> 10 #include <linux/bits.h> 11 #include "mac.h" 12 13 /** 14 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags 15 * @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for 16 * bandwidths <= 80MHz 17 * @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC 18 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz 19 * bandwidth 20 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation 21 * for BPSK (MCS 0) with 1 spatial 22 * stream 23 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation 24 * for BPSK (MCS 0) with 2 spatial 25 * streams 26 * @IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK: enable support for EHT extra LTF 27 * @IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_1_5_MBPS_MSK: support ELR 1.5 Mbps 28 * @IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_3_MBPS_MSK: support ELR 3 Mbps 29 */ 30 enum iwl_tlc_mng_cfg_flags { 31 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0), 32 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1), 33 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2), 34 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3), 35 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4), 36 IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK = BIT(6), 37 IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_1_5_MBPS_MSK = BIT(7), 38 IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_3_MBPS_MSK = BIT(8), 39 }; 40 41 /** 42 * enum iwl_tlc_mng_cfg_cw - channel width options 43 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel 44 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel 45 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel 46 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel 47 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel 48 */ 49 enum iwl_tlc_mng_cfg_cw { 50 IWL_TLC_MNG_CH_WIDTH_20MHZ, 51 IWL_TLC_MNG_CH_WIDTH_40MHZ, 52 IWL_TLC_MNG_CH_WIDTH_80MHZ, 53 IWL_TLC_MNG_CH_WIDTH_160MHZ, 54 IWL_TLC_MNG_CH_WIDTH_320MHZ, 55 }; 56 57 /** 58 * enum iwl_tlc_mng_cfg_chains - possible chains 59 * @IWL_TLC_MNG_CHAIN_A_MSK: chain A 60 * @IWL_TLC_MNG_CHAIN_B_MSK: chain B 61 */ 62 enum iwl_tlc_mng_cfg_chains { 63 IWL_TLC_MNG_CHAIN_A_MSK = BIT(0), 64 IWL_TLC_MNG_CHAIN_B_MSK = BIT(1), 65 }; 66 67 /** 68 * enum iwl_tlc_mng_cfg_mode - supported modes 69 * @IWL_TLC_MNG_MODE_CCK: enable CCK 70 * @IWL_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT) 71 * @IWL_TLC_MNG_MODE_NON_HT: enable non HT 72 * @IWL_TLC_MNG_MODE_HT: enable HT 73 * @IWL_TLC_MNG_MODE_VHT: enable VHT 74 * @IWL_TLC_MNG_MODE_HE: enable HE 75 * @IWL_TLC_MNG_MODE_EHT: enable EHT 76 * @IWL_TLC_MNG_MODE_UHR: enable UHR 77 */ 78 enum iwl_tlc_mng_cfg_mode { 79 IWL_TLC_MNG_MODE_CCK = 0, 80 IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK, 81 IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK, 82 IWL_TLC_MNG_MODE_HT, 83 IWL_TLC_MNG_MODE_VHT, 84 IWL_TLC_MNG_MODE_HE, 85 IWL_TLC_MNG_MODE_EHT, 86 IWL_TLC_MNG_MODE_UHR, 87 }; 88 89 /** 90 * enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates 91 * @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0 92 * @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1 93 * @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2 94 * @IWL_TLC_MNG_HT_RATE_MCS3: index of MCS3 95 * @IWL_TLC_MNG_HT_RATE_MCS4: index of MCS4 96 * @IWL_TLC_MNG_HT_RATE_MCS5: index of MCS5 97 * @IWL_TLC_MNG_HT_RATE_MCS6: index of MCS6 98 * @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7 99 * @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8 100 * @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9 101 * @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10 102 * @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11 103 * @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT 104 */ 105 enum iwl_tlc_mng_ht_rates { 106 IWL_TLC_MNG_HT_RATE_MCS0 = 0, 107 IWL_TLC_MNG_HT_RATE_MCS1, 108 IWL_TLC_MNG_HT_RATE_MCS2, 109 IWL_TLC_MNG_HT_RATE_MCS3, 110 IWL_TLC_MNG_HT_RATE_MCS4, 111 IWL_TLC_MNG_HT_RATE_MCS5, 112 IWL_TLC_MNG_HT_RATE_MCS6, 113 IWL_TLC_MNG_HT_RATE_MCS7, 114 IWL_TLC_MNG_HT_RATE_MCS8, 115 IWL_TLC_MNG_HT_RATE_MCS9, 116 IWL_TLC_MNG_HT_RATE_MCS10, 117 IWL_TLC_MNG_HT_RATE_MCS11, 118 IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11, 119 }; 120 121 enum IWL_TLC_MNG_NSS { 122 IWL_TLC_NSS_1, 123 IWL_TLC_NSS_2, 124 IWL_TLC_NSS_MAX 125 }; 126 127 /** 128 * enum IWL_TLC_MCS_PER_BW - mcs index per BW 129 * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz 130 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz 131 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz 132 * @IWL_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3 133 * @IWL_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4 134 */ 135 enum IWL_TLC_MCS_PER_BW { 136 IWL_TLC_MCS_PER_BW_80, 137 IWL_TLC_MCS_PER_BW_160, 138 IWL_TLC_MCS_PER_BW_320, 139 IWL_TLC_MCS_PER_BW_NUM_V3 = IWL_TLC_MCS_PER_BW_160 + 1, 140 IWL_TLC_MCS_PER_BW_NUM_V4 = IWL_TLC_MCS_PER_BW_320 + 1, 141 }; 142 143 /** 144 * struct iwl_tlc_config_cmd_v3 - TLC configuration 145 * @sta_id: station id 146 * @reserved1: reserved 147 * @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw 148 * @mode: &enum iwl_tlc_mng_cfg_mode 149 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 150 * @amsdu: TX amsdu is supported 151 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 152 * @non_ht_rates: bitmap of supported legacy rates 153 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per &enum IWL_TLC_MCS_PER_BW 154 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz). 155 * @max_mpdu_len: max MPDU length, in bytes 156 * @sgi_ch_width_supp: bitmap of SGI support per channel width 157 * use BIT(@enum iwl_tlc_mng_cfg_cw) 158 * @reserved2: reserved 159 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 160 * set zero for no limit. 161 */ 162 struct iwl_tlc_config_cmd_v3 { 163 u8 sta_id; 164 u8 reserved1[3]; 165 u8 max_ch_width; 166 u8 mode; 167 u8 chains; 168 u8 amsdu; 169 __le16 flags; 170 __le16 non_ht_rates; 171 __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V3]; 172 __le16 max_mpdu_len; 173 u8 sgi_ch_width_supp; 174 u8 reserved2; 175 __le32 max_tx_op; 176 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */ 177 178 /** 179 * struct iwl_tlc_config_cmd_v4 - TLC configuration 180 * @sta_id: station id 181 * @reserved1: reserved 182 * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw 183 * @mode: &enum iwl_tlc_mng_cfg_mode 184 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 185 * @sgi_ch_width_supp: bitmap of SGI support per channel width 186 * use BIT(&enum iwl_tlc_mng_cfg_cw) 187 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 188 * @non_ht_rates: bitmap of supported legacy rates 189 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width> 190 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz). 191 * @max_mpdu_len: max MPDU length, in bytes 192 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 193 * set zero for no limit. 194 */ 195 struct iwl_tlc_config_cmd_v4 { 196 u8 sta_id; 197 u8 reserved1[3]; 198 u8 max_ch_width; 199 u8 mode; 200 u8 chains; 201 u8 sgi_ch_width_supp; 202 __le16 flags; 203 __le16 non_ht_rates; 204 __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4]; 205 __le16 max_mpdu_len; 206 __le16 max_tx_op; 207 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */ 208 209 /** 210 * struct iwl_tlc_config_cmd_v5 - TLC configuration 211 * @sta_id: station id 212 * @reserved1: reserved 213 * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw 214 * @mode: &enum iwl_tlc_mng_cfg_mode 215 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 216 * @sgi_ch_width_supp: bitmap of SGI support per channel width 217 * use BIT(&enum iwl_tlc_mng_cfg_cw) 218 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 219 * @non_ht_rates: bitmap of supported legacy rates 220 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width> 221 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz). 222 * @max_mpdu_len: max MPDU length, in bytes 223 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 224 * set zero for no limit. 225 */ 226 struct iwl_tlc_config_cmd_v5 { 227 u8 sta_id; 228 u8 reserved1[3]; 229 u8 max_ch_width; 230 u8 mode; 231 u8 chains; 232 u8 sgi_ch_width_supp; 233 __le16 flags; 234 __le16 non_ht_rates; 235 __le32 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4]; 236 __le16 max_mpdu_len; 237 __le16 max_tx_op; 238 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_5 */ 239 240 /** 241 * struct iwl_tlc_config_cmd - TLC configuration 242 * @sta_mask: station mask (in NAN we can have multiple logical stations of 243 * the same peer (with the same TLC configuration)). 244 * @phy_id: the phy id to used for this TLC configuration 245 * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw 246 * @mode: &enum iwl_tlc_mng_cfg_mode 247 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 248 * @sgi_ch_width_supp: bitmap of SGI support per channel width 249 * use BIT(&enum iwl_tlc_mng_cfg_cw) 250 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 251 * @non_ht_rates: bitmap of supported legacy rates 252 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width> 253 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz). 254 * @max_mpdu_len: max MPDU length, in bytes 255 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 256 * set zero for no limit. 257 */ 258 struct iwl_tlc_config_cmd { 259 __le32 sta_mask; 260 __le32 phy_id; 261 u8 max_ch_width; 262 u8 mode; 263 u8 chains; 264 u8 sgi_ch_width_supp; 265 __le16 flags; 266 __le16 non_ht_rates; 267 __le32 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4]; 268 __le16 max_mpdu_len; 269 __le16 max_tx_op; 270 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_6 */ 271 272 /** 273 * enum iwl_tlc_update_flags - updated fields 274 * @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update 275 * @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update 276 */ 277 enum iwl_tlc_update_flags { 278 IWL_TLC_NOTIF_FLAG_RATE = BIT(0), 279 IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1), 280 }; 281 282 /** 283 * struct iwl_tlc_update_notif - TLC notification from FW 284 * @sta_id: station id 285 * @reserved: reserved 286 * @flags: bitmap of notifications reported 287 * @rate: current initial rate, format depends on the notification 288 * version 289 * @amsdu_size: Max AMSDU size, in bytes 290 * @amsdu_enabled: bitmap for per-TID AMSDU enablement 291 */ 292 struct iwl_tlc_update_notif { 293 u8 sta_id; 294 u8 reserved[3]; 295 __le32 flags; 296 __le32 rate; 297 __le32 amsdu_size; 298 __le32 amsdu_enabled; 299 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2, _VER_3, _VER_4 */ 300 301 /** 302 * enum iwl_tlc_debug_types - debug options 303 */ 304 enum iwl_tlc_debug_types { 305 /** 306 * @IWL_TLC_DEBUG_FIXED_RATE: set fixed rate for rate scaling 307 */ 308 IWL_TLC_DEBUG_FIXED_RATE, 309 /** 310 * @IWL_TLC_DEBUG_AGG_DURATION_LIM: time limit for a BA 311 * session, in usec 312 */ 313 IWL_TLC_DEBUG_AGG_DURATION_LIM, 314 /** 315 * @IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM: set max number of frames 316 * in an aggregation 317 */ 318 IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM, 319 /** 320 * @IWL_TLC_DEBUG_TPC_ENABLED: enable or disable tpc 321 */ 322 IWL_TLC_DEBUG_TPC_ENABLED, 323 /** 324 * @IWL_TLC_DEBUG_TPC_STATS: get number of frames Tx'ed in each 325 * tpc step 326 */ 327 IWL_TLC_DEBUG_TPC_STATS, 328 /** 329 * @IWL_TLC_DEBUG_RTS_DISABLE: disable RTS (bool true/false). 330 */ 331 IWL_TLC_DEBUG_RTS_DISABLE, 332 /** 333 * @IWL_TLC_DEBUG_PARTIAL_FIXED_RATE: set partial fixed rate to fw 334 */ 335 IWL_TLC_DEBUG_PARTIAL_FIXED_RATE, 336 }; /* TLC_MNG_DEBUG_TYPES_API_E */ 337 338 #define MAX_DATA_IN_DHC_TLC_CMD 10 339 340 /** 341 * struct iwl_dhc_tlc_cmd - fixed debug config 342 * @sta_id: bit 0 - enable/disable, bits 1 - 7 hold station id 343 * @reserved1: reserved 344 * @type: type id of %enum iwl_tlc_debug_types 345 * @data: data to send 346 */ 347 struct iwl_dhc_tlc_cmd { 348 u8 sta_id; 349 u8 reserved1[3]; 350 __le32 type; 351 __le32 data[MAX_DATA_IN_DHC_TLC_CMD]; 352 } __packed; /* TLC_MNG_DEBUG_CMD_S */ 353 354 #define IWL_MAX_MCS_DISPLAY_SIZE 12 355 356 struct iwl_rate_mcs_info { 357 char mbps[IWL_MAX_MCS_DISPLAY_SIZE]; 358 char mcs[IWL_MAX_MCS_DISPLAY_SIZE]; 359 }; 360 361 /* 362 * These serve as indexes into 363 * struct iwl_rate_info fw_rate_idx_to_plcp[IWL_RATE_COUNT]; 364 * TODO: avoid overlap between legacy and HT rates 365 */ 366 enum { 367 IWL_RATE_1M_INDEX = 0, 368 IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX, 369 IWL_RATE_2M_INDEX, 370 IWL_RATE_5M_INDEX, 371 IWL_RATE_11M_INDEX, 372 IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX, 373 IWL_RATE_6M_INDEX, 374 IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX, 375 IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX, 376 IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX, 377 IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX, 378 IWL_RATE_9M_INDEX, 379 IWL_RATE_12M_INDEX, 380 IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX, 381 IWL_RATE_18M_INDEX, 382 IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX, 383 IWL_RATE_24M_INDEX, 384 IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX, 385 IWL_RATE_36M_INDEX, 386 IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX, 387 IWL_RATE_48M_INDEX, 388 IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX, 389 IWL_RATE_54M_INDEX, 390 IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX, 391 IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX, 392 IWL_RATE_60M_INDEX, 393 IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX, 394 IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX, 395 IWL_RATE_MCS_8_INDEX, 396 IWL_RATE_MCS_9_INDEX, 397 IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX, 398 IWL_RATE_MCS_10_INDEX, 399 IWL_RATE_MCS_11_INDEX, 400 IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX, 401 IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1, 402 IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1, 403 IWL_RATE_INVM_INDEX = IWL_RATE_COUNT, 404 IWL_RATE_INVALID = IWL_RATE_COUNT, 405 }; 406 407 #define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX) 408 409 /* fw API values for legacy bit rates, both OFDM and CCK */ 410 enum { 411 IWL_RATE_6M_PLCP = 13, 412 IWL_RATE_9M_PLCP = 15, 413 IWL_RATE_12M_PLCP = 5, 414 IWL_RATE_18M_PLCP = 7, 415 IWL_RATE_24M_PLCP = 9, 416 IWL_RATE_36M_PLCP = 11, 417 IWL_RATE_48M_PLCP = 1, 418 IWL_RATE_54M_PLCP = 3, 419 IWL_RATE_1M_PLCP = 10, 420 IWL_RATE_2M_PLCP = 20, 421 IWL_RATE_5M_PLCP = 55, 422 IWL_RATE_11M_PLCP = 110, 423 IWL_RATE_INVM_PLCP = -1, 424 }; 425 426 /* 427 * rate_n_flags bit fields version 1 428 * 429 * The 32-bit value has different layouts in the low 8 bites depending on the 430 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 431 * for CCK and OFDM). 432 * 433 * High-throughput (HT) rate format 434 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 435 * Very High-throughput (VHT) rate format 436 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 437 * Legacy OFDM rate format for bits 7:0 438 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 439 * Legacy CCK rate format for bits 7:0: 440 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 441 */ 442 443 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 444 #define RATE_MCS_HT_POS 8 445 #define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS) 446 447 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 448 #define RATE_MCS_CCK_POS_V1 9 449 #define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1) 450 451 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 452 #define RATE_MCS_VHT_POS_V1 26 453 #define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1) 454 455 456 /* 457 * High-throughput (HT) rate format for bits 7:0 458 * 459 * 2-0: MCS rate base 460 * 0) 6 Mbps 461 * 1) 12 Mbps 462 * 2) 18 Mbps 463 * 3) 24 Mbps 464 * 4) 36 Mbps 465 * 5) 48 Mbps 466 * 6) 54 Mbps 467 * 7) 60 Mbps 468 * 4-3: 0) Single stream (SISO) 469 * 1) Dual stream (MIMO) 470 * 2) Triple stream (MIMO) 471 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 472 * (bits 7-6 are zero) 473 * 474 * Together the low 5 bits work out to the MCS index because we don't 475 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 476 * streams and 16-23 have three streams. We could also support MCS 32 477 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 478 */ 479 #define RATE_HT_MCS_RATE_CODE_MSK_V1 0x7 480 #define RATE_HT_MCS_NSS_POS_V1 3 481 #define RATE_HT_MCS_NSS_MSK_V1 (3 << RATE_HT_MCS_NSS_POS_V1) 482 #define RATE_HT_MCS_MIMO2_MSK BIT(RATE_HT_MCS_NSS_POS_V1) 483 484 /* Bit 10: (1) Use Green Field preamble */ 485 #define RATE_HT_MCS_GF_POS 10 486 #define RATE_HT_MCS_GF_MSK (1 << RATE_HT_MCS_GF_POS) 487 488 #define RATE_HT_MCS_INDEX_MSK_V1 0x3f 489 490 /* 491 * Very High-throughput (VHT) rate format for bits 7:0 492 * 493 * 3-0: VHT MCS (0-9) 494 * 5-4: number of streams - 1: 495 * 0) Single stream (SISO) 496 * 1) Dual stream (MIMO) 497 * 2) Triple stream (MIMO) 498 */ 499 500 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 501 #define RATE_VHT_MCS_RATE_CODE_MSK 0xf 502 #define RATE_VHT_MCS_NSS_MSK 0x30 503 504 /* 505 * Legacy OFDM rate format for bits 7:0 506 * 507 * 3-0: 0xD) 6 Mbps 508 * 0xF) 9 Mbps 509 * 0x5) 12 Mbps 510 * 0x7) 18 Mbps 511 * 0x9) 24 Mbps 512 * 0xB) 36 Mbps 513 * 0x1) 48 Mbps 514 * 0x3) 54 Mbps 515 * (bits 7-4 are 0) 516 * 517 * Legacy CCK rate format for bits 7:0: 518 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 519 * 520 * 6-0: 10) 1 Mbps 521 * 20) 2 Mbps 522 * 55) 5.5 Mbps 523 * 110) 11 Mbps 524 * (bit 7 is 0) 525 */ 526 #define RATE_LEGACY_RATE_MSK_V1 0xff 527 528 /* Bit 10 - OFDM HE */ 529 #define RATE_MCS_HE_POS_V1 10 530 #define RATE_MCS_HE_MSK_V1 BIT(RATE_MCS_HE_POS_V1) 531 532 /* 533 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 534 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 535 */ 536 #define RATE_MCS_CHAN_WIDTH_POS 11 537 #define RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << RATE_MCS_CHAN_WIDTH_POS) 538 539 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 540 #define RATE_MCS_SGI_POS_V1 13 541 #define RATE_MCS_SGI_MSK_V1 BIT(RATE_MCS_SGI_POS_V1) 542 543 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 544 #define RATE_MCS_ANT_POS 14 545 #define RATE_MCS_ANT_A_MSK (1 << RATE_MCS_ANT_POS) 546 #define RATE_MCS_ANT_B_MSK (2 << RATE_MCS_ANT_POS) 547 #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | \ 548 RATE_MCS_ANT_B_MSK) 549 #define RATE_MCS_ANT_MSK RATE_MCS_ANT_AB_MSK 550 551 /* Bit 17: (0) SS, (1) SS*2 */ 552 #define RATE_MCS_STBC_POS 17 553 #define RATE_MCS_STBC_MSK BIT(RATE_MCS_STBC_POS) 554 555 /* Bit 18: OFDM-HE dual carrier mode */ 556 #define RATE_HE_DUAL_CARRIER_MODE 18 557 #define RATE_HE_DUAL_CARRIER_MODE_MSK BIT(RATE_HE_DUAL_CARRIER_MODE) 558 559 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 560 #define RATE_MCS_BF_POS 19 561 #define RATE_MCS_BF_MSK (1 << RATE_MCS_BF_POS) 562 563 /* 564 * Bit 20-21: HE LTF type and guard interval 565 * HE (ext) SU: 566 * 0 1xLTF+0.8us 567 * 1 2xLTF+0.8us 568 * 2 2xLTF+1.6us 569 * 3 & SGI (bit 13) clear 4xLTF+3.2us 570 * 3 & SGI (bit 13) set 4xLTF+0.8us 571 * HE MU: 572 * 0 4xLTF+0.8us 573 * 1 2xLTF+0.8us 574 * 2 2xLTF+1.6us 575 * 3 4xLTF+3.2us 576 * HE-EHT TRIG: 577 * 0 1xLTF+1.6us 578 * 1 2xLTF+1.6us 579 * 2 4xLTF+3.2us 580 * 3 (does not occur) 581 * EHT MU: 582 * 0 2xLTF+0.8us 583 * 1 2xLTF+1.6us 584 * 2 4xLTF+0.8us 585 * 3 4xLTF+3.2us 586 */ 587 #define RATE_MCS_HE_GI_LTF_POS 20 588 #define RATE_MCS_HE_GI_LTF_MSK_V1 (3 << RATE_MCS_HE_GI_LTF_POS) 589 590 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 591 #define RATE_MCS_HE_TYPE_POS_V1 22 592 #define RATE_MCS_HE_TYPE_SU_V1 (0 << RATE_MCS_HE_TYPE_POS_V1) 593 #define RATE_MCS_HE_TYPE_EXT_SU_V1 BIT(RATE_MCS_HE_TYPE_POS_V1) 594 #define RATE_MCS_HE_TYPE_MU_V1 (2 << RATE_MCS_HE_TYPE_POS_V1) 595 #define RATE_MCS_HE_TYPE_TRIG_V1 (3 << RATE_MCS_HE_TYPE_POS_V1) 596 #define RATE_MCS_HE_TYPE_MSK_V1 (3 << RATE_MCS_HE_TYPE_POS_V1) 597 598 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 599 #define RATE_MCS_DUP_POS_V1 24 600 #define RATE_MCS_DUP_MSK_V1 (3 << RATE_MCS_DUP_POS_V1) 601 602 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 603 #define RATE_MCS_LDPC_POS_V1 27 604 #define RATE_MCS_LDPC_MSK_V1 BIT(RATE_MCS_LDPC_POS_V1) 605 606 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 607 #define RATE_MCS_HE_106T_POS_V1 28 608 #define RATE_MCS_HE_106T_MSK_V1 BIT(RATE_MCS_HE_106T_POS_V1) 609 610 /* Bit 30-31: (1) RTS, (2) CTS */ 611 #define RATE_MCS_RTS_REQUIRED_POS (30) 612 #define RATE_MCS_RTS_REQUIRED_MSK (0x1 << RATE_MCS_RTS_REQUIRED_POS) 613 614 #define RATE_MCS_CTS_REQUIRED_POS (31) 615 #define RATE_MCS_CTS_REQUIRED_MSK (0x1 << RATE_MCS_CTS_REQUIRED_POS) 616 617 /* rate_n_flags bit field version 2 and 3 618 * 619 * The 32-bit value has different layouts in the low 8 bits depending on the 620 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 621 * for CCK and OFDM). 622 * 623 */ 624 625 /* Bits 10-8: rate format 626 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT) 627 * (3) Very High-throughput (VHT) (4) High-efficiency (HE) 628 * (5) Extremely High-throughput (EHT) 629 * (6) Ultra High Reliability (UHR) (v3 rate format only) 630 */ 631 #define RATE_MCS_MOD_TYPE_POS 8 632 #define RATE_MCS_MOD_TYPE_MSK (0x7 << RATE_MCS_MOD_TYPE_POS) 633 #define RATE_MCS_MOD_TYPE_CCK (0 << RATE_MCS_MOD_TYPE_POS) 634 #define RATE_MCS_MOD_TYPE_LEGACY_OFDM (1 << RATE_MCS_MOD_TYPE_POS) 635 #define RATE_MCS_MOD_TYPE_HT (2 << RATE_MCS_MOD_TYPE_POS) 636 #define RATE_MCS_MOD_TYPE_VHT (3 << RATE_MCS_MOD_TYPE_POS) 637 #define RATE_MCS_MOD_TYPE_HE (4 << RATE_MCS_MOD_TYPE_POS) 638 #define RATE_MCS_MOD_TYPE_EHT (5 << RATE_MCS_MOD_TYPE_POS) 639 #define RATE_MCS_MOD_TYPE_UHR (6 << RATE_MCS_MOD_TYPE_POS) 640 641 /* 642 * Legacy CCK rate format for bits 0:3: 643 * 644 * (0) 1 Mbps 645 * (1) 2 Mbps 646 * (2) 5.5 Mbps 647 * (3) 11 Mbps 648 * 649 * Legacy OFDM rate format for bis 3:0: 650 * 651 * (0) 6 Mbps 652 * (1) 9 Mbps 653 * (2) 12 Mbps 654 * (3) 18 Mbps 655 * (4) 24 Mbps 656 * (5) 36 Mbps 657 * (6) 48 Mbps 658 * (7) 54 Mbps 659 * 660 */ 661 #define RATE_LEGACY_RATE_MSK 0x7 662 663 /* 664 * HT, VHT, HE, EHT, UHR rate format 665 * Version 2: (not applicable for UHR) 666 * 3-0: MCS 667 * 4: NSS==2 indicator 668 * Version 3: 669 * 4-0: MCS 670 * 5: NSS==2 indicator 671 */ 672 #define RATE_HT_MCS_CODE_MSK 0x7 673 #define RATE_MCS_NSS_MSK_V2 0x10 674 #define RATE_MCS_NSS_MSK 0x20 675 #define RATE_MCS_CODE_MSK 0x1f 676 #define RATE_HT_MCS_INDEX(r) ((((r) & RATE_MCS_NSS_MSK) >> 2) | \ 677 ((r) & RATE_HT_MCS_CODE_MSK)) 678 679 /* Bits 7-5: reserved */ 680 681 /* 682 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz 683 */ 684 #define RATE_MCS_CHAN_WIDTH_MSK (0x7 << RATE_MCS_CHAN_WIDTH_POS) 685 #define RATE_MCS_CHAN_WIDTH_20_VAL 0 686 #define RATE_MCS_CHAN_WIDTH_20 (RATE_MCS_CHAN_WIDTH_20_VAL << RATE_MCS_CHAN_WIDTH_POS) 687 #define RATE_MCS_CHAN_WIDTH_40_VAL 1 688 #define RATE_MCS_CHAN_WIDTH_40 (RATE_MCS_CHAN_WIDTH_40_VAL << RATE_MCS_CHAN_WIDTH_POS) 689 #define RATE_MCS_CHAN_WIDTH_80_VAL 2 690 #define RATE_MCS_CHAN_WIDTH_80 (RATE_MCS_CHAN_WIDTH_80_VAL << RATE_MCS_CHAN_WIDTH_POS) 691 #define RATE_MCS_CHAN_WIDTH_160_VAL 3 692 #define RATE_MCS_CHAN_WIDTH_160 (RATE_MCS_CHAN_WIDTH_160_VAL << RATE_MCS_CHAN_WIDTH_POS) 693 #define RATE_MCS_CHAN_WIDTH_320_VAL 4 694 #define RATE_MCS_CHAN_WIDTH_320 (RATE_MCS_CHAN_WIDTH_320_VAL << RATE_MCS_CHAN_WIDTH_POS) 695 696 /* Bit 15-14: Antenna selection: 697 * Bit 14: Ant A active 698 * Bit 15: Ant B active 699 * 700 * All relevant definitions are same as in v1 701 */ 702 703 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */ 704 #define RATE_MCS_LDPC_POS 16 705 #define RATE_MCS_LDPC_MSK (1 << RATE_MCS_LDPC_POS) 706 707 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */ 708 709 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */ 710 711 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */ 712 713 /* 714 * Bit 22-20: HE LTF type and guard interval 715 * CCK: 716 * 0 long preamble 717 * 1 short preamble 718 * HT/VHT: 719 * 0 0.8us 720 * 1 0.4us 721 * HE (ext) SU: 722 * 0 1xLTF+0.8us 723 * 1 2xLTF+0.8us 724 * 2 2xLTF+1.6us 725 * 3 4xLTF+3.2us 726 * 4 4xLTF+0.8us 727 * HE MU: 728 * 0 4xLTF+0.8us 729 * 1 2xLTF+0.8us 730 * 2 2xLTF+1.6us 731 * 3 4xLTF+3.2us 732 * HE TRIG: 733 * 0 1xLTF+1.6us 734 * 1 2xLTF+1.6us 735 * 2 4xLTF+3.2us 736 * */ 737 #define RATE_MCS_HE_GI_LTF_MSK (0x7 << RATE_MCS_HE_GI_LTF_POS) 738 #define RATE_MCS_SGI_POS RATE_MCS_HE_GI_LTF_POS 739 #define RATE_MCS_SGI_MSK (1 << RATE_MCS_SGI_POS) 740 #define RATE_MCS_HE_SU_4_LTF 3 741 #define RATE_MCS_HE_SU_4_LTF_08_GI 4 742 743 /* Bit 24-23: HE type. (0) SU, (1) HE SU_EXT/UHR ELR, (2) MU, (3) trigger based */ 744 #define RATE_MCS_HE_TYPE_POS 23 745 #define RATE_MCS_HE_TYPE_SU (0 << RATE_MCS_HE_TYPE_POS) 746 #define RATE_MCS_HE_TYPE_EXT_SU (1 << RATE_MCS_HE_TYPE_POS) 747 #define RATE_MCS_HE_TYPE_UHR_ELR (1 << RATE_MCS_HE_TYPE_POS) 748 #define RATE_MCS_HE_TYPE_MU (2 << RATE_MCS_HE_TYPE_POS) 749 #define RATE_MCS_HE_TYPE_TRIG (3 << RATE_MCS_HE_TYPE_POS) 750 #define RATE_MCS_HE_TYPE_MSK (3 << RATE_MCS_HE_TYPE_POS) 751 752 /* Bit 25: duplicate channel enabled 753 * 754 * if this bit is set, duplicate is according to BW (bits 11-13): 755 * 756 * CCK: 2x 20MHz 757 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16) 758 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160) 759 * */ 760 #define RATE_MCS_DUP_POS 25 761 #define RATE_MCS_DUP_MSK (1 << RATE_MCS_DUP_POS) 762 763 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 764 #define RATE_MCS_HE_106T_POS 26 765 #define RATE_MCS_HE_106T_MSK (1 << RATE_MCS_HE_106T_POS) 766 767 /* Bit 27: EHT extra LTF: 768 * instead of 1 LTF for SISO use 2 LTFs, 769 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/ 770 #define RATE_MCS_EHT_EXTRA_LTF_POS 27 771 #define RATE_MCS_EHT_EXTRA_LTF_MSK (1 << RATE_MCS_EHT_EXTRA_LTF_POS) 772 773 /* Bit 31-28: reserved */ 774 775 /* Link Quality definitions */ 776 777 /* # entries in rate scale table to support Tx retries */ 778 #define LQ_MAX_RETRY_NUM 16 779 780 /* Link quality command flags bit fields */ 781 782 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 783 #define LQ_FLAG_USE_RTS_POS 0 784 #define LQ_FLAG_USE_RTS_MSK (1 << LQ_FLAG_USE_RTS_POS) 785 786 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 787 #define LQ_FLAG_COLOR_POS 1 788 #define LQ_FLAG_COLOR_MSK (7 << LQ_FLAG_COLOR_POS) 789 #define LQ_FLAG_COLOR_GET(_f) (((_f) & LQ_FLAG_COLOR_MSK) >>\ 790 LQ_FLAG_COLOR_POS) 791 #define LQ_FLAGS_COLOR_INC(_c) ((((_c) + 1) << LQ_FLAG_COLOR_POS) &\ 792 LQ_FLAG_COLOR_MSK) 793 #define LQ_FLAG_COLOR_SET(_f, _c) ((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK)) 794 795 /* Bit 4-5: Tx RTS BW Signalling 796 * (0) No RTS BW signalling 797 * (1) Static BW signalling 798 * (2) Dynamic BW signalling 799 */ 800 #define LQ_FLAG_RTS_BW_SIG_POS 4 801 #define LQ_FLAG_RTS_BW_SIG_NONE (0 << LQ_FLAG_RTS_BW_SIG_POS) 802 #define LQ_FLAG_RTS_BW_SIG_STATIC (1 << LQ_FLAG_RTS_BW_SIG_POS) 803 #define LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << LQ_FLAG_RTS_BW_SIG_POS) 804 805 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 806 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 807 */ 808 #define LQ_FLAG_DYNAMIC_BW_POS 6 809 #define LQ_FLAG_DYNAMIC_BW_MSK (1 << LQ_FLAG_DYNAMIC_BW_POS) 810 811 /* Single Stream Tx Parameters (lq_cmd->ss_params) 812 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 813 * used for single stream Tx. 814 */ 815 816 /* Bit 0-1: Max STBC streams allowed. Can be 0-3. 817 * (0) - No STBC allowed 818 * (1) - 2x1 STBC allowed (HT/VHT) 819 * (2) - 4x2 STBC allowed (HT/VHT) 820 * (3) - 3x2 STBC allowed (HT only) 821 * All our chips are at most 2 antennas so only (1) is valid for now. 822 */ 823 #define LQ_SS_STBC_ALLOWED_POS 0 824 #define LQ_SS_STBC_ALLOWED_MSK (3 << LQ_SS_STBC_ALLOWED_MSK) 825 826 /* 2x1 STBC is allowed */ 827 #define LQ_SS_STBC_1SS_ALLOWED (1 << LQ_SS_STBC_ALLOWED_POS) 828 829 /* Bit 2: Beamformer (VHT only) is allowed */ 830 #define LQ_SS_BFER_ALLOWED_POS 2 831 #define LQ_SS_BFER_ALLOWED (1 << LQ_SS_BFER_ALLOWED_POS) 832 833 /* Bit 3: Force BFER or STBC for testing 834 * If this is set: 835 * If BFER is allowed then force the ucode to choose BFER else 836 * If STBC is allowed then force the ucode to choose STBC over SISO 837 */ 838 #define LQ_SS_FORCE_POS 3 839 #define LQ_SS_FORCE (1 << LQ_SS_FORCE_POS) 840 841 /* Bit 31: ss_params field is valid. Used for FW backward compatibility 842 * with other drivers which don't support the ss_params API yet 843 */ 844 #define LQ_SS_PARAMS_VALID_POS 31 845 #define LQ_SS_PARAMS_VALID (1 << LQ_SS_PARAMS_VALID_POS) 846 847 /** 848 * struct iwl_lq_cmd - link quality command 849 * @sta_id: station to update 850 * @reduced_tpc: reduced transmit power control value 851 * @control: not used 852 * @flags: combination of LQ_FLAG_* 853 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 854 * and SISO rates 855 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 856 * Should be ANT_[ABC] 857 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 858 * @initial_rate_index: first index from rs_table per AC category 859 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 860 * value of 100 is one usec. Range is 100 to 8000 861 * @agg_disable_start_th: try-count threshold for starting aggregation. 862 * If a frame has higher try-count, it should not be selected for 863 * starting an aggregation sequence. 864 * @agg_frame_cnt_limit: max frame count in an aggregation. 865 * 0: no limit 866 * 1: no aggregation (one frame per aggregation) 867 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 868 * @reserved2: reserved 869 * @rs_table: array of rates for each TX try, each is rate_n_flags, 870 * meaning it is a combination of RATE_MCS_* and IWL_RATE_*_PLCP 871 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 872 */ 873 struct iwl_lq_cmd { 874 u8 sta_id; 875 u8 reduced_tpc; 876 __le16 control; 877 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 878 u8 flags; 879 u8 mimo_delim; 880 u8 single_stream_ant_msk; 881 u8 dual_stream_ant_msk; 882 u8 initial_rate_index[AC_NUM]; 883 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 884 __le16 agg_time_limit; 885 u8 agg_disable_start_th; 886 u8 agg_frame_cnt_limit; 887 __le32 reserved2; 888 __le32 rs_table[LQ_MAX_RETRY_NUM]; 889 __le32 ss_params; 890 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 891 892 u8 iwl_fw_rate_idx_to_plcp(int idx); 893 const struct iwl_rate_mcs_info *iwl_rate_mcs(int idx); 894 const char *iwl_rs_pretty_ant(u8 ant); 895 const char *iwl_rs_pretty_bw(int bw); 896 int rs_pretty_print_rate(char *buf, int bufsz, const u32 rate); 897 bool iwl_he_is_sgi(u32 rate_n_flags); 898 899 static inline u32 iwl_v3_rate_from_v2_v3(__le32 rate, bool fw_v3) 900 { 901 u32 val; 902 903 if (fw_v3) 904 return le32_to_cpu(rate); 905 906 val = le32_to_cpu(rate) & ~RATE_MCS_NSS_MSK_V2; 907 val |= u32_encode_bits(le32_get_bits(rate, RATE_MCS_NSS_MSK_V2), 908 RATE_MCS_NSS_MSK); 909 910 return val; 911 } 912 913 static inline __le32 iwl_v3_rate_to_v2_v3(u32 rate, bool fw_v3) 914 { 915 __le32 val; 916 917 if (fw_v3) 918 return cpu_to_le32(rate); 919 920 val = cpu_to_le32(rate & ~RATE_MCS_NSS_MSK); 921 val |= le32_encode_bits(u32_get_bits(rate, RATE_MCS_NSS_MSK), 922 RATE_MCS_NSS_MSK_V2); 923 924 return val; 925 } 926 927 #endif /* __iwl_fw_api_rs_h__ */ 928