1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2022, 2024-2025 Intel Corporation 4 * Copyright (C) 2017 Intel Deutschland GmbH 5 */ 6 #ifndef __iwl_fw_api_rs_h__ 7 #define __iwl_fw_api_rs_h__ 8 9 #include "mac.h" 10 11 /** 12 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags 13 * @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for 14 * bandwidths <= 80MHz 15 * @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC 16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz 17 * bandwidth 18 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation 19 * for BPSK (MCS 0) with 1 spatial 20 * stream 21 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation 22 * for BPSK (MCS 0) with 2 spatial 23 * streams 24 * @IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK: enable support for EHT extra LTF 25 */ 26 enum iwl_tlc_mng_cfg_flags { 27 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0), 28 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1), 29 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2), 30 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3), 31 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4), 32 IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK = BIT(6), 33 }; 34 35 /** 36 * enum iwl_tlc_mng_cfg_cw - channel width options 37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel 38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel 39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel 40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel 41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel 42 */ 43 enum iwl_tlc_mng_cfg_cw { 44 IWL_TLC_MNG_CH_WIDTH_20MHZ, 45 IWL_TLC_MNG_CH_WIDTH_40MHZ, 46 IWL_TLC_MNG_CH_WIDTH_80MHZ, 47 IWL_TLC_MNG_CH_WIDTH_160MHZ, 48 IWL_TLC_MNG_CH_WIDTH_320MHZ, 49 }; 50 51 /** 52 * enum iwl_tlc_mng_cfg_chains - possible chains 53 * @IWL_TLC_MNG_CHAIN_A_MSK: chain A 54 * @IWL_TLC_MNG_CHAIN_B_MSK: chain B 55 */ 56 enum iwl_tlc_mng_cfg_chains { 57 IWL_TLC_MNG_CHAIN_A_MSK = BIT(0), 58 IWL_TLC_MNG_CHAIN_B_MSK = BIT(1), 59 }; 60 61 /** 62 * enum iwl_tlc_mng_cfg_mode - supported modes 63 * @IWL_TLC_MNG_MODE_CCK: enable CCK 64 * @IWL_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT) 65 * @IWL_TLC_MNG_MODE_NON_HT: enable non HT 66 * @IWL_TLC_MNG_MODE_HT: enable HT 67 * @IWL_TLC_MNG_MODE_VHT: enable VHT 68 * @IWL_TLC_MNG_MODE_HE: enable HE 69 * @IWL_TLC_MNG_MODE_EHT: enable EHT 70 */ 71 enum iwl_tlc_mng_cfg_mode { 72 IWL_TLC_MNG_MODE_CCK = 0, 73 IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK, 74 IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK, 75 IWL_TLC_MNG_MODE_HT, 76 IWL_TLC_MNG_MODE_VHT, 77 IWL_TLC_MNG_MODE_HE, 78 IWL_TLC_MNG_MODE_EHT, 79 }; 80 81 /** 82 * enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates 83 * @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0 84 * @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1 85 * @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2 86 * @IWL_TLC_MNG_HT_RATE_MCS3: index of MCS3 87 * @IWL_TLC_MNG_HT_RATE_MCS4: index of MCS4 88 * @IWL_TLC_MNG_HT_RATE_MCS5: index of MCS5 89 * @IWL_TLC_MNG_HT_RATE_MCS6: index of MCS6 90 * @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7 91 * @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8 92 * @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9 93 * @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10 94 * @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11 95 * @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT 96 */ 97 enum iwl_tlc_mng_ht_rates { 98 IWL_TLC_MNG_HT_RATE_MCS0 = 0, 99 IWL_TLC_MNG_HT_RATE_MCS1, 100 IWL_TLC_MNG_HT_RATE_MCS2, 101 IWL_TLC_MNG_HT_RATE_MCS3, 102 IWL_TLC_MNG_HT_RATE_MCS4, 103 IWL_TLC_MNG_HT_RATE_MCS5, 104 IWL_TLC_MNG_HT_RATE_MCS6, 105 IWL_TLC_MNG_HT_RATE_MCS7, 106 IWL_TLC_MNG_HT_RATE_MCS8, 107 IWL_TLC_MNG_HT_RATE_MCS9, 108 IWL_TLC_MNG_HT_RATE_MCS10, 109 IWL_TLC_MNG_HT_RATE_MCS11, 110 IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11, 111 }; 112 113 enum IWL_TLC_MNG_NSS { 114 IWL_TLC_NSS_1, 115 IWL_TLC_NSS_2, 116 IWL_TLC_NSS_MAX 117 }; 118 119 /** 120 * enum IWL_TLC_MCS_PER_BW - mcs index per BW 121 * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz 122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz 123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz 124 * @IWL_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3 125 * @IWL_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4 126 */ 127 enum IWL_TLC_MCS_PER_BW { 128 IWL_TLC_MCS_PER_BW_80, 129 IWL_TLC_MCS_PER_BW_160, 130 IWL_TLC_MCS_PER_BW_320, 131 IWL_TLC_MCS_PER_BW_NUM_V3 = IWL_TLC_MCS_PER_BW_160 + 1, 132 IWL_TLC_MCS_PER_BW_NUM_V4 = IWL_TLC_MCS_PER_BW_320 + 1, 133 }; 134 135 /** 136 * struct iwl_tlc_config_cmd_v3 - TLC configuration 137 * @sta_id: station id 138 * @reserved1: reserved 139 * @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw 140 * @mode: &enum iwl_tlc_mng_cfg_mode 141 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 142 * @amsdu: TX amsdu is supported 143 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 144 * @non_ht_rates: bitmap of supported legacy rates 145 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per &enum IWL_TLC_MCS_PER_BW 146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz). 147 * @max_mpdu_len: max MPDU length, in bytes 148 * @sgi_ch_width_supp: bitmap of SGI support per channel width 149 * use BIT(@enum iwl_tlc_mng_cfg_cw) 150 * @reserved2: reserved 151 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 152 * set zero for no limit. 153 */ 154 struct iwl_tlc_config_cmd_v3 { 155 u8 sta_id; 156 u8 reserved1[3]; 157 u8 max_ch_width; 158 u8 mode; 159 u8 chains; 160 u8 amsdu; 161 __le16 flags; 162 __le16 non_ht_rates; 163 __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V3]; 164 __le16 max_mpdu_len; 165 u8 sgi_ch_width_supp; 166 u8 reserved2; 167 __le32 max_tx_op; 168 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */ 169 170 /** 171 * struct iwl_tlc_config_cmd_v4 - TLC configuration 172 * @sta_id: station id 173 * @reserved1: reserved 174 * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw 175 * @mode: &enum iwl_tlc_mng_cfg_mode 176 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains 177 * @sgi_ch_width_supp: bitmap of SGI support per channel width 178 * use BIT(&enum iwl_tlc_mng_cfg_cw) 179 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags 180 * @non_ht_rates: bitmap of supported legacy rates 181 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width> 182 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz). 183 * @max_mpdu_len: max MPDU length, in bytes 184 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 185 * set zero for no limit. 186 */ 187 struct iwl_tlc_config_cmd_v4 { 188 u8 sta_id; 189 u8 reserved1[3]; 190 u8 max_ch_width; 191 u8 mode; 192 u8 chains; 193 u8 sgi_ch_width_supp; 194 __le16 flags; 195 __le16 non_ht_rates; 196 __le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4]; 197 __le16 max_mpdu_len; 198 __le16 max_tx_op; 199 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */ 200 201 /** 202 * enum iwl_tlc_update_flags - updated fields 203 * @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update 204 * @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update 205 */ 206 enum iwl_tlc_update_flags { 207 IWL_TLC_NOTIF_FLAG_RATE = BIT(0), 208 IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1), 209 }; 210 211 /** 212 * struct iwl_tlc_update_notif - TLC notification from FW 213 * @sta_id: station id 214 * @reserved: reserved 215 * @flags: bitmap of notifications reported 216 * @rate: current initial rate, format depends on the notification 217 * version 218 * @amsdu_size: Max AMSDU size, in bytes 219 * @amsdu_enabled: bitmap for per-TID AMSDU enablement 220 */ 221 struct iwl_tlc_update_notif { 222 u8 sta_id; 223 u8 reserved[3]; 224 __le32 flags; 225 __le32 rate; 226 __le32 amsdu_size; 227 __le32 amsdu_enabled; 228 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2, _VER_3, _VER_4 */ 229 230 /** 231 * enum iwl_tlc_debug_types - debug options 232 */ 233 enum iwl_tlc_debug_types { 234 /** 235 * @IWL_TLC_DEBUG_FIXED_RATE: set fixed rate for rate scaling 236 */ 237 IWL_TLC_DEBUG_FIXED_RATE, 238 /** 239 * @IWL_TLC_DEBUG_AGG_DURATION_LIM: time limit for a BA 240 * session, in usec 241 */ 242 IWL_TLC_DEBUG_AGG_DURATION_LIM, 243 /** 244 * @IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM: set max number of frames 245 * in an aggregation 246 */ 247 IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM, 248 /** 249 * @IWL_TLC_DEBUG_TPC_ENABLED: enable or disable tpc 250 */ 251 IWL_TLC_DEBUG_TPC_ENABLED, 252 /** 253 * @IWL_TLC_DEBUG_TPC_STATS: get number of frames Tx'ed in each 254 * tpc step 255 */ 256 IWL_TLC_DEBUG_TPC_STATS, 257 /** 258 * @IWL_TLC_DEBUG_RTS_DISABLE: disable RTS (bool true/false). 259 */ 260 IWL_TLC_DEBUG_RTS_DISABLE, 261 /** 262 * @IWL_TLC_DEBUG_PARTIAL_FIXED_RATE: set partial fixed rate to fw 263 */ 264 IWL_TLC_DEBUG_PARTIAL_FIXED_RATE, 265 }; /* TLC_MNG_DEBUG_TYPES_API_E */ 266 267 #define MAX_DATA_IN_DHC_TLC_CMD 10 268 269 /** 270 * struct iwl_dhc_tlc_cmd - fixed debug config 271 * @sta_id: bit 0 - enable/disable, bits 1 - 7 hold station id 272 * @reserved1: reserved 273 * @type: type id of %enum iwl_tlc_debug_types 274 * @data: data to send 275 */ 276 struct iwl_dhc_tlc_cmd { 277 u8 sta_id; 278 u8 reserved1[3]; 279 __le32 type; 280 __le32 data[MAX_DATA_IN_DHC_TLC_CMD]; 281 } __packed; /* TLC_MNG_DEBUG_CMD_S */ 282 283 #define IWL_MAX_MCS_DISPLAY_SIZE 12 284 285 struct iwl_rate_mcs_info { 286 char mbps[IWL_MAX_MCS_DISPLAY_SIZE]; 287 char mcs[IWL_MAX_MCS_DISPLAY_SIZE]; 288 }; 289 290 /* 291 * These serve as indexes into 292 * struct iwl_rate_info fw_rate_idx_to_plcp[IWL_RATE_COUNT]; 293 * TODO: avoid overlap between legacy and HT rates 294 */ 295 enum { 296 IWL_RATE_1M_INDEX = 0, 297 IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX, 298 IWL_RATE_2M_INDEX, 299 IWL_RATE_5M_INDEX, 300 IWL_RATE_11M_INDEX, 301 IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX, 302 IWL_RATE_6M_INDEX, 303 IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX, 304 IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX, 305 IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX, 306 IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX, 307 IWL_RATE_9M_INDEX, 308 IWL_RATE_12M_INDEX, 309 IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX, 310 IWL_RATE_18M_INDEX, 311 IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX, 312 IWL_RATE_24M_INDEX, 313 IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX, 314 IWL_RATE_36M_INDEX, 315 IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX, 316 IWL_RATE_48M_INDEX, 317 IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX, 318 IWL_RATE_54M_INDEX, 319 IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX, 320 IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX, 321 IWL_RATE_60M_INDEX, 322 IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX, 323 IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX, 324 IWL_RATE_MCS_8_INDEX, 325 IWL_RATE_MCS_9_INDEX, 326 IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX, 327 IWL_RATE_MCS_10_INDEX, 328 IWL_RATE_MCS_11_INDEX, 329 IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX, 330 IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1, 331 IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1, 332 IWL_RATE_INVM_INDEX = IWL_RATE_COUNT, 333 IWL_RATE_INVALID = IWL_RATE_COUNT, 334 }; 335 336 #define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX) 337 338 /* fw API values for legacy bit rates, both OFDM and CCK */ 339 enum { 340 IWL_RATE_6M_PLCP = 13, 341 IWL_RATE_9M_PLCP = 15, 342 IWL_RATE_12M_PLCP = 5, 343 IWL_RATE_18M_PLCP = 7, 344 IWL_RATE_24M_PLCP = 9, 345 IWL_RATE_36M_PLCP = 11, 346 IWL_RATE_48M_PLCP = 1, 347 IWL_RATE_54M_PLCP = 3, 348 IWL_RATE_1M_PLCP = 10, 349 IWL_RATE_2M_PLCP = 20, 350 IWL_RATE_5M_PLCP = 55, 351 IWL_RATE_11M_PLCP = 110, 352 IWL_RATE_INVM_PLCP = -1, 353 }; 354 355 /* 356 * rate_n_flags bit fields version 1 357 * 358 * The 32-bit value has different layouts in the low 8 bites depending on the 359 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 360 * for CCK and OFDM). 361 * 362 * High-throughput (HT) rate format 363 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 364 * Very High-throughput (VHT) rate format 365 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 366 * Legacy OFDM rate format for bits 7:0 367 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 368 * Legacy CCK rate format for bits 7:0: 369 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 370 */ 371 372 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 373 #define RATE_MCS_HT_POS 8 374 #define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS) 375 376 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 377 #define RATE_MCS_CCK_POS_V1 9 378 #define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1) 379 380 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 381 #define RATE_MCS_VHT_POS_V1 26 382 #define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1) 383 384 385 /* 386 * High-throughput (HT) rate format for bits 7:0 387 * 388 * 2-0: MCS rate base 389 * 0) 6 Mbps 390 * 1) 12 Mbps 391 * 2) 18 Mbps 392 * 3) 24 Mbps 393 * 4) 36 Mbps 394 * 5) 48 Mbps 395 * 6) 54 Mbps 396 * 7) 60 Mbps 397 * 4-3: 0) Single stream (SISO) 398 * 1) Dual stream (MIMO) 399 * 2) Triple stream (MIMO) 400 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 401 * (bits 7-6 are zero) 402 * 403 * Together the low 5 bits work out to the MCS index because we don't 404 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 405 * streams and 16-23 have three streams. We could also support MCS 32 406 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 407 */ 408 #define RATE_HT_MCS_RATE_CODE_MSK_V1 0x7 409 #define RATE_HT_MCS_NSS_POS_V1 3 410 #define RATE_HT_MCS_NSS_MSK_V1 (3 << RATE_HT_MCS_NSS_POS_V1) 411 #define RATE_HT_MCS_MIMO2_MSK BIT(RATE_HT_MCS_NSS_POS_V1) 412 413 /* Bit 10: (1) Use Green Field preamble */ 414 #define RATE_HT_MCS_GF_POS 10 415 #define RATE_HT_MCS_GF_MSK (1 << RATE_HT_MCS_GF_POS) 416 417 #define RATE_HT_MCS_INDEX_MSK_V1 0x3f 418 419 /* 420 * Very High-throughput (VHT) rate format for bits 7:0 421 * 422 * 3-0: VHT MCS (0-9) 423 * 5-4: number of streams - 1: 424 * 0) Single stream (SISO) 425 * 1) Dual stream (MIMO) 426 * 2) Triple stream (MIMO) 427 */ 428 429 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 430 #define RATE_VHT_MCS_RATE_CODE_MSK 0xf 431 #define RATE_VHT_MCS_NSS_MSK 0x30 432 433 /* 434 * Legacy OFDM rate format for bits 7:0 435 * 436 * 3-0: 0xD) 6 Mbps 437 * 0xF) 9 Mbps 438 * 0x5) 12 Mbps 439 * 0x7) 18 Mbps 440 * 0x9) 24 Mbps 441 * 0xB) 36 Mbps 442 * 0x1) 48 Mbps 443 * 0x3) 54 Mbps 444 * (bits 7-4 are 0) 445 * 446 * Legacy CCK rate format for bits 7:0: 447 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 448 * 449 * 6-0: 10) 1 Mbps 450 * 20) 2 Mbps 451 * 55) 5.5 Mbps 452 * 110) 11 Mbps 453 * (bit 7 is 0) 454 */ 455 #define RATE_LEGACY_RATE_MSK_V1 0xff 456 457 /* Bit 10 - OFDM HE */ 458 #define RATE_MCS_HE_POS_V1 10 459 #define RATE_MCS_HE_MSK_V1 BIT(RATE_MCS_HE_POS_V1) 460 461 /* 462 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 463 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 464 */ 465 #define RATE_MCS_CHAN_WIDTH_POS 11 466 #define RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << RATE_MCS_CHAN_WIDTH_POS) 467 468 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 469 #define RATE_MCS_SGI_POS_V1 13 470 #define RATE_MCS_SGI_MSK_V1 BIT(RATE_MCS_SGI_POS_V1) 471 472 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 473 #define RATE_MCS_ANT_POS 14 474 #define RATE_MCS_ANT_A_MSK (1 << RATE_MCS_ANT_POS) 475 #define RATE_MCS_ANT_B_MSK (2 << RATE_MCS_ANT_POS) 476 #define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | \ 477 RATE_MCS_ANT_B_MSK) 478 #define RATE_MCS_ANT_MSK RATE_MCS_ANT_AB_MSK 479 480 /* Bit 17: (0) SS, (1) SS*2 */ 481 #define RATE_MCS_STBC_POS 17 482 #define RATE_MCS_STBC_MSK BIT(RATE_MCS_STBC_POS) 483 484 /* Bit 18: OFDM-HE dual carrier mode */ 485 #define RATE_HE_DUAL_CARRIER_MODE 18 486 #define RATE_HE_DUAL_CARRIER_MODE_MSK BIT(RATE_HE_DUAL_CARRIER_MODE) 487 488 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 489 #define RATE_MCS_BF_POS 19 490 #define RATE_MCS_BF_MSK (1 << RATE_MCS_BF_POS) 491 492 /* 493 * Bit 20-21: HE LTF type and guard interval 494 * HE (ext) SU: 495 * 0 1xLTF+0.8us 496 * 1 2xLTF+0.8us 497 * 2 2xLTF+1.6us 498 * 3 & SGI (bit 13) clear 4xLTF+3.2us 499 * 3 & SGI (bit 13) set 4xLTF+0.8us 500 * HE MU: 501 * 0 4xLTF+0.8us 502 * 1 2xLTF+0.8us 503 * 2 2xLTF+1.6us 504 * 3 4xLTF+3.2us 505 * HE-EHT TRIG: 506 * 0 1xLTF+1.6us 507 * 1 2xLTF+1.6us 508 * 2 4xLTF+3.2us 509 * 3 (does not occur) 510 * EHT MU: 511 * 0 2xLTF+0.8us 512 * 1 2xLTF+1.6us 513 * 2 4xLTF+0.8us 514 * 3 4xLTF+3.2us 515 */ 516 #define RATE_MCS_HE_GI_LTF_POS 20 517 #define RATE_MCS_HE_GI_LTF_MSK_V1 (3 << RATE_MCS_HE_GI_LTF_POS) 518 519 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 520 #define RATE_MCS_HE_TYPE_POS_V1 22 521 #define RATE_MCS_HE_TYPE_SU_V1 (0 << RATE_MCS_HE_TYPE_POS_V1) 522 #define RATE_MCS_HE_TYPE_EXT_SU_V1 BIT(RATE_MCS_HE_TYPE_POS_V1) 523 #define RATE_MCS_HE_TYPE_MU_V1 (2 << RATE_MCS_HE_TYPE_POS_V1) 524 #define RATE_MCS_HE_TYPE_TRIG_V1 (3 << RATE_MCS_HE_TYPE_POS_V1) 525 #define RATE_MCS_HE_TYPE_MSK_V1 (3 << RATE_MCS_HE_TYPE_POS_V1) 526 527 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 528 #define RATE_MCS_DUP_POS_V1 24 529 #define RATE_MCS_DUP_MSK_V1 (3 << RATE_MCS_DUP_POS_V1) 530 531 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 532 #define RATE_MCS_LDPC_POS_V1 27 533 #define RATE_MCS_LDPC_MSK_V1 BIT(RATE_MCS_LDPC_POS_V1) 534 535 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 536 #define RATE_MCS_HE_106T_POS_V1 28 537 #define RATE_MCS_HE_106T_MSK_V1 BIT(RATE_MCS_HE_106T_POS_V1) 538 539 /* Bit 30-31: (1) RTS, (2) CTS */ 540 #define RATE_MCS_RTS_REQUIRED_POS (30) 541 #define RATE_MCS_RTS_REQUIRED_MSK (0x1 << RATE_MCS_RTS_REQUIRED_POS) 542 543 #define RATE_MCS_CTS_REQUIRED_POS (31) 544 #define RATE_MCS_CTS_REQUIRED_MSK (0x1 << RATE_MCS_CTS_REQUIRED_POS) 545 546 /* rate_n_flags bit field version 2 and 3 547 * 548 * The 32-bit value has different layouts in the low 8 bits depending on the 549 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 550 * for CCK and OFDM). 551 * 552 */ 553 554 /* Bits 10-8: rate format 555 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT) 556 * (3) Very High-throughput (VHT) (4) High-efficiency (HE) 557 * (5) Extremely High-throughput (EHT) 558 * (6) Ultra High Reliability (UHR) (v3 rate format only) 559 */ 560 #define RATE_MCS_MOD_TYPE_POS 8 561 #define RATE_MCS_MOD_TYPE_MSK (0x7 << RATE_MCS_MOD_TYPE_POS) 562 #define RATE_MCS_MOD_TYPE_CCK (0 << RATE_MCS_MOD_TYPE_POS) 563 #define RATE_MCS_MOD_TYPE_LEGACY_OFDM (1 << RATE_MCS_MOD_TYPE_POS) 564 #define RATE_MCS_MOD_TYPE_HT (2 << RATE_MCS_MOD_TYPE_POS) 565 #define RATE_MCS_MOD_TYPE_VHT (3 << RATE_MCS_MOD_TYPE_POS) 566 #define RATE_MCS_MOD_TYPE_HE (4 << RATE_MCS_MOD_TYPE_POS) 567 #define RATE_MCS_MOD_TYPE_EHT (5 << RATE_MCS_MOD_TYPE_POS) 568 #define RATE_MCS_MOD_TYPE_UHR (6 << RATE_MCS_MOD_TYPE_POS) 569 570 /* 571 * Legacy CCK rate format for bits 0:3: 572 * 573 * (0) 1 Mbps 574 * (1) 2 Mbps 575 * (2) 5.5 Mbps 576 * (3) 11 Mbps 577 * 578 * Legacy OFDM rate format for bis 3:0: 579 * 580 * (0) 6 Mbps 581 * (1) 9 Mbps 582 * (2) 12 Mbps 583 * (3) 18 Mbps 584 * (4) 24 Mbps 585 * (5) 36 Mbps 586 * (6) 48 Mbps 587 * (7) 54 Mbps 588 * 589 */ 590 #define RATE_LEGACY_RATE_MSK 0x7 591 592 /* 593 * HT, VHT, HE, EHT, UHR rate format 594 * Version 2: (not applicable for UHR) 595 * 3-0: MCS 596 * 4: NSS==2 indicator 597 * Version 3: 598 * 4-0: MCS 599 * 5: NSS==2 indicator 600 */ 601 #define RATE_HT_MCS_CODE_MSK 0x7 602 #define RATE_MCS_NSS_MSK_V2 0x10 603 #define RATE_MCS_NSS_MSK 0x20 604 #define RATE_MCS_CODE_MSK 0x1f 605 #define RATE_HT_MCS_INDEX(r) ((((r) & RATE_MCS_NSS_MSK) >> 2) | \ 606 ((r) & RATE_HT_MCS_CODE_MSK)) 607 608 /* Bits 7-5: reserved */ 609 610 /* 611 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz 612 */ 613 #define RATE_MCS_CHAN_WIDTH_MSK (0x7 << RATE_MCS_CHAN_WIDTH_POS) 614 #define RATE_MCS_CHAN_WIDTH_20_VAL 0 615 #define RATE_MCS_CHAN_WIDTH_20 (RATE_MCS_CHAN_WIDTH_20_VAL << RATE_MCS_CHAN_WIDTH_POS) 616 #define RATE_MCS_CHAN_WIDTH_40_VAL 1 617 #define RATE_MCS_CHAN_WIDTH_40 (RATE_MCS_CHAN_WIDTH_40_VAL << RATE_MCS_CHAN_WIDTH_POS) 618 #define RATE_MCS_CHAN_WIDTH_80_VAL 2 619 #define RATE_MCS_CHAN_WIDTH_80 (RATE_MCS_CHAN_WIDTH_80_VAL << RATE_MCS_CHAN_WIDTH_POS) 620 #define RATE_MCS_CHAN_WIDTH_160_VAL 3 621 #define RATE_MCS_CHAN_WIDTH_160 (RATE_MCS_CHAN_WIDTH_160_VAL << RATE_MCS_CHAN_WIDTH_POS) 622 #define RATE_MCS_CHAN_WIDTH_320_VAL 4 623 #define RATE_MCS_CHAN_WIDTH_320 (RATE_MCS_CHAN_WIDTH_320_VAL << RATE_MCS_CHAN_WIDTH_POS) 624 625 /* Bit 15-14: Antenna selection: 626 * Bit 14: Ant A active 627 * Bit 15: Ant B active 628 * 629 * All relevant definitions are same as in v1 630 */ 631 632 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */ 633 #define RATE_MCS_LDPC_POS 16 634 #define RATE_MCS_LDPC_MSK (1 << RATE_MCS_LDPC_POS) 635 636 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */ 637 638 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */ 639 640 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */ 641 642 /* 643 * Bit 22-20: HE LTF type and guard interval 644 * CCK: 645 * 0 long preamble 646 * 1 short preamble 647 * HT/VHT: 648 * 0 0.8us 649 * 1 0.4us 650 * HE (ext) SU: 651 * 0 1xLTF+0.8us 652 * 1 2xLTF+0.8us 653 * 2 2xLTF+1.6us 654 * 3 4xLTF+3.2us 655 * 4 4xLTF+0.8us 656 * HE MU: 657 * 0 4xLTF+0.8us 658 * 1 2xLTF+0.8us 659 * 2 2xLTF+1.6us 660 * 3 4xLTF+3.2us 661 * HE TRIG: 662 * 0 1xLTF+1.6us 663 * 1 2xLTF+1.6us 664 * 2 4xLTF+3.2us 665 * */ 666 #define RATE_MCS_HE_GI_LTF_MSK (0x7 << RATE_MCS_HE_GI_LTF_POS) 667 #define RATE_MCS_SGI_POS RATE_MCS_HE_GI_LTF_POS 668 #define RATE_MCS_SGI_MSK (1 << RATE_MCS_SGI_POS) 669 #define RATE_MCS_HE_SU_4_LTF 3 670 #define RATE_MCS_HE_SU_4_LTF_08_GI 4 671 672 /* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 673 #define RATE_MCS_HE_TYPE_POS 23 674 #define RATE_MCS_HE_TYPE_SU (0 << RATE_MCS_HE_TYPE_POS) 675 #define RATE_MCS_HE_TYPE_EXT_SU (1 << RATE_MCS_HE_TYPE_POS) 676 #define RATE_MCS_HE_TYPE_MU (2 << RATE_MCS_HE_TYPE_POS) 677 #define RATE_MCS_HE_TYPE_TRIG (3 << RATE_MCS_HE_TYPE_POS) 678 #define RATE_MCS_HE_TYPE_MSK (3 << RATE_MCS_HE_TYPE_POS) 679 680 /* Bit 25: duplicate channel enabled 681 * 682 * if this bit is set, duplicate is according to BW (bits 11-13): 683 * 684 * CCK: 2x 20MHz 685 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16) 686 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160) 687 * */ 688 #define RATE_MCS_DUP_POS 25 689 #define RATE_MCS_DUP_MSK (1 << RATE_MCS_DUP_POS) 690 691 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 692 #define RATE_MCS_HE_106T_POS 26 693 #define RATE_MCS_HE_106T_MSK (1 << RATE_MCS_HE_106T_POS) 694 695 /* Bit 27: EHT extra LTF: 696 * instead of 1 LTF for SISO use 2 LTFs, 697 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/ 698 #define RATE_MCS_EHT_EXTRA_LTF_POS 27 699 #define RATE_MCS_EHT_EXTRA_LTF_MSK (1 << RATE_MCS_EHT_EXTRA_LTF_POS) 700 701 /* Bit 31-28: reserved */ 702 703 /* Link Quality definitions */ 704 705 /* # entries in rate scale table to support Tx retries */ 706 #define LQ_MAX_RETRY_NUM 16 707 708 /* Link quality command flags bit fields */ 709 710 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 711 #define LQ_FLAG_USE_RTS_POS 0 712 #define LQ_FLAG_USE_RTS_MSK (1 << LQ_FLAG_USE_RTS_POS) 713 714 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 715 #define LQ_FLAG_COLOR_POS 1 716 #define LQ_FLAG_COLOR_MSK (7 << LQ_FLAG_COLOR_POS) 717 #define LQ_FLAG_COLOR_GET(_f) (((_f) & LQ_FLAG_COLOR_MSK) >>\ 718 LQ_FLAG_COLOR_POS) 719 #define LQ_FLAGS_COLOR_INC(_c) ((((_c) + 1) << LQ_FLAG_COLOR_POS) &\ 720 LQ_FLAG_COLOR_MSK) 721 #define LQ_FLAG_COLOR_SET(_f, _c) ((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK)) 722 723 /* Bit 4-5: Tx RTS BW Signalling 724 * (0) No RTS BW signalling 725 * (1) Static BW signalling 726 * (2) Dynamic BW signalling 727 */ 728 #define LQ_FLAG_RTS_BW_SIG_POS 4 729 #define LQ_FLAG_RTS_BW_SIG_NONE (0 << LQ_FLAG_RTS_BW_SIG_POS) 730 #define LQ_FLAG_RTS_BW_SIG_STATIC (1 << LQ_FLAG_RTS_BW_SIG_POS) 731 #define LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << LQ_FLAG_RTS_BW_SIG_POS) 732 733 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 734 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 735 */ 736 #define LQ_FLAG_DYNAMIC_BW_POS 6 737 #define LQ_FLAG_DYNAMIC_BW_MSK (1 << LQ_FLAG_DYNAMIC_BW_POS) 738 739 /* Single Stream Tx Parameters (lq_cmd->ss_params) 740 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 741 * used for single stream Tx. 742 */ 743 744 /* Bit 0-1: Max STBC streams allowed. Can be 0-3. 745 * (0) - No STBC allowed 746 * (1) - 2x1 STBC allowed (HT/VHT) 747 * (2) - 4x2 STBC allowed (HT/VHT) 748 * (3) - 3x2 STBC allowed (HT only) 749 * All our chips are at most 2 antennas so only (1) is valid for now. 750 */ 751 #define LQ_SS_STBC_ALLOWED_POS 0 752 #define LQ_SS_STBC_ALLOWED_MSK (3 << LQ_SS_STBC_ALLOWED_MSK) 753 754 /* 2x1 STBC is allowed */ 755 #define LQ_SS_STBC_1SS_ALLOWED (1 << LQ_SS_STBC_ALLOWED_POS) 756 757 /* Bit 2: Beamformer (VHT only) is allowed */ 758 #define LQ_SS_BFER_ALLOWED_POS 2 759 #define LQ_SS_BFER_ALLOWED (1 << LQ_SS_BFER_ALLOWED_POS) 760 761 /* Bit 3: Force BFER or STBC for testing 762 * If this is set: 763 * If BFER is allowed then force the ucode to choose BFER else 764 * If STBC is allowed then force the ucode to choose STBC over SISO 765 */ 766 #define LQ_SS_FORCE_POS 3 767 #define LQ_SS_FORCE (1 << LQ_SS_FORCE_POS) 768 769 /* Bit 31: ss_params field is valid. Used for FW backward compatibility 770 * with other drivers which don't support the ss_params API yet 771 */ 772 #define LQ_SS_PARAMS_VALID_POS 31 773 #define LQ_SS_PARAMS_VALID (1 << LQ_SS_PARAMS_VALID_POS) 774 775 /** 776 * struct iwl_lq_cmd - link quality command 777 * @sta_id: station to update 778 * @reduced_tpc: reduced transmit power control value 779 * @control: not used 780 * @flags: combination of LQ_FLAG_* 781 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 782 * and SISO rates 783 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 784 * Should be ANT_[ABC] 785 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 786 * @initial_rate_index: first index from rs_table per AC category 787 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 788 * value of 100 is one usec. Range is 100 to 8000 789 * @agg_disable_start_th: try-count threshold for starting aggregation. 790 * If a frame has higher try-count, it should not be selected for 791 * starting an aggregation sequence. 792 * @agg_frame_cnt_limit: max frame count in an aggregation. 793 * 0: no limit 794 * 1: no aggregation (one frame per aggregation) 795 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 796 * @reserved2: reserved 797 * @rs_table: array of rates for each TX try, each is rate_n_flags, 798 * meaning it is a combination of RATE_MCS_* and IWL_RATE_*_PLCP 799 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 800 */ 801 struct iwl_lq_cmd { 802 u8 sta_id; 803 u8 reduced_tpc; 804 __le16 control; 805 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 806 u8 flags; 807 u8 mimo_delim; 808 u8 single_stream_ant_msk; 809 u8 dual_stream_ant_msk; 810 u8 initial_rate_index[AC_NUM]; 811 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 812 __le16 agg_time_limit; 813 u8 agg_disable_start_th; 814 u8 agg_frame_cnt_limit; 815 __le32 reserved2; 816 __le32 rs_table[LQ_MAX_RETRY_NUM]; 817 __le32 ss_params; 818 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 819 820 u8 iwl_fw_rate_idx_to_plcp(int idx); 821 const struct iwl_rate_mcs_info *iwl_rate_mcs(int idx); 822 const char *iwl_rs_pretty_ant(u8 ant); 823 const char *iwl_rs_pretty_bw(int bw); 824 int rs_pretty_print_rate(char *buf, int bufsz, const u32 rate); 825 bool iwl_he_is_sgi(u32 rate_n_flags); 826 827 static inline u32 iwl_v3_rate_from_v2_v3(__le32 rate, bool fw_v3) 828 { 829 u32 val; 830 831 if (fw_v3) 832 return le32_to_cpu(rate); 833 834 val = le32_to_cpu(rate) & ~RATE_MCS_NSS_MSK_V2; 835 val |= u32_encode_bits(le32_get_bits(rate, RATE_MCS_NSS_MSK_V2), 836 RATE_MCS_NSS_MSK); 837 838 return val; 839 } 840 841 static inline __le32 iwl_v3_rate_to_v2_v3(u32 rate, bool fw_v3) 842 { 843 __le32 val; 844 845 if (fw_v3) 846 return cpu_to_le32(rate); 847 848 val = cpu_to_le32(rate & ~RATE_MCS_NSS_MSK); 849 val |= le32_encode_bits(u32_get_bits(rate, RATE_MCS_NSS_MSK), 850 RATE_MCS_NSS_MSK_V2); 851 852 return val; 853 } 854 855 #endif /* __iwl_fw_api_rs_h__ */ 856