1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2019, 2021, 2024 Intel Corporation 4 */ 5 #include <linux/types.h> 6 #include <linux/slab.h> 7 #include <linux/export.h> 8 9 #include "iwl-drv.h" 10 #include "iwl-debug.h" 11 #include "iwl-io.h" 12 #include "iwl-prph.h" 13 #include "iwl-csr.h" 14 #include "agn.h" 15 16 /* EEPROM offset definitions */ 17 18 /* indirect access definitions */ 19 #define ADDRESS_MSK 0x0000FFFF 20 #define INDIRECT_TYPE_MSK 0x000F0000 21 #define INDIRECT_HOST 0x00010000 22 #define INDIRECT_GENERAL 0x00020000 23 #define INDIRECT_REGULATORY 0x00030000 24 #define INDIRECT_CALIBRATION 0x00040000 25 #define INDIRECT_PROCESS_ADJST 0x00050000 26 #define INDIRECT_OTHERS 0x00060000 27 #define INDIRECT_TXP_LIMIT 0x00070000 28 #define INDIRECT_TXP_LIMIT_SIZE 0x00080000 29 #define INDIRECT_ADDRESS 0x00100000 30 31 /* corresponding link offsets in EEPROM */ 32 #define EEPROM_LINK_HOST (2*0x64) 33 #define EEPROM_LINK_GENERAL (2*0x65) 34 #define EEPROM_LINK_REGULATORY (2*0x66) 35 #define EEPROM_LINK_CALIBRATION (2*0x67) 36 #define EEPROM_LINK_PROCESS_ADJST (2*0x68) 37 #define EEPROM_LINK_OTHERS (2*0x69) 38 #define EEPROM_LINK_TXP_LIMIT (2*0x6a) 39 #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b) 40 41 /* General */ 42 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ 43 #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */ 44 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ 45 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ 46 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ 47 #define EEPROM_VERSION (2*0x44) /* 2 bytes */ 48 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ 49 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ 50 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ 51 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ 52 53 /* calibration */ 54 struct iwl_eeprom_calib_hdr { 55 u8 version; 56 u8 pa_type; 57 __le16 voltage; 58 } __packed; 59 60 #define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION) 61 #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL) 62 63 /* temperature */ 64 #define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL) 65 #define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL) 66 67 /* SKU Capabilities (actual values from EEPROM definition) */ 68 enum eeprom_sku_bits { 69 EEPROM_SKU_CAP_BAND_24GHZ = BIT(4), 70 EEPROM_SKU_CAP_BAND_52GHZ = BIT(5), 71 EEPROM_SKU_CAP_11N_ENABLE = BIT(6), 72 EEPROM_SKU_CAP_AMT_ENABLE = BIT(7), 73 EEPROM_SKU_CAP_IPAN_ENABLE = BIT(8) 74 }; 75 76 /* radio config bits (actual values from EEPROM definition) */ 77 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ 78 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 79 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 80 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 81 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 82 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 83 84 /* 85 * EEPROM bands 86 * These are the channel numbers from each band in the order 87 * that they are stored in the EEPROM band information. Note 88 * that EEPROM bands aren't the same as mac80211 bands, and 89 * there are even special "ht40 bands" in the EEPROM. 90 */ 91 static const u8 iwl_eeprom_band_1[14] = { /* 2.4 GHz */ 92 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 93 }; 94 95 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */ 96 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 97 }; 98 99 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */ 100 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 101 }; 102 103 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */ 104 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 105 }; 106 107 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */ 108 145, 149, 153, 157, 161, 165 109 }; 110 111 static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */ 112 1, 2, 3, 4, 5, 6, 7 113 }; 114 115 static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */ 116 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 117 }; 118 119 #define IWL_NUM_CHANNELS (ARRAY_SIZE(iwl_eeprom_band_1) + \ 120 ARRAY_SIZE(iwl_eeprom_band_2) + \ 121 ARRAY_SIZE(iwl_eeprom_band_3) + \ 122 ARRAY_SIZE(iwl_eeprom_band_4) + \ 123 ARRAY_SIZE(iwl_eeprom_band_5)) 124 125 /* rate data (static) */ 126 static struct ieee80211_rate iwl_cfg80211_rates[] = { 127 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 128 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 129 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 130 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 131 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 132 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 133 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 134 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 135 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 136 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 137 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 138 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 139 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 140 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 141 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 142 }; 143 #define RATES_24_OFFS 0 144 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 145 #define RATES_52_OFFS 4 146 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 147 148 /* EEPROM reading functions */ 149 150 static u16 iwl_eeprom_query16(const u8 *eeprom, size_t eeprom_size, int offset) 151 { 152 if (WARN_ON(offset + sizeof(u16) > eeprom_size)) 153 return 0; 154 return le16_to_cpup((__le16 *)(eeprom + offset)); 155 } 156 157 static u32 eeprom_indirect_address(const u8 *eeprom, size_t eeprom_size, 158 u32 address) 159 { 160 u16 offset = 0; 161 162 if ((address & INDIRECT_ADDRESS) == 0) 163 return address; 164 165 switch (address & INDIRECT_TYPE_MSK) { 166 case INDIRECT_HOST: 167 offset = iwl_eeprom_query16(eeprom, eeprom_size, 168 EEPROM_LINK_HOST); 169 break; 170 case INDIRECT_GENERAL: 171 offset = iwl_eeprom_query16(eeprom, eeprom_size, 172 EEPROM_LINK_GENERAL); 173 break; 174 case INDIRECT_REGULATORY: 175 offset = iwl_eeprom_query16(eeprom, eeprom_size, 176 EEPROM_LINK_REGULATORY); 177 break; 178 case INDIRECT_TXP_LIMIT: 179 offset = iwl_eeprom_query16(eeprom, eeprom_size, 180 EEPROM_LINK_TXP_LIMIT); 181 break; 182 case INDIRECT_TXP_LIMIT_SIZE: 183 offset = iwl_eeprom_query16(eeprom, eeprom_size, 184 EEPROM_LINK_TXP_LIMIT_SIZE); 185 break; 186 case INDIRECT_CALIBRATION: 187 offset = iwl_eeprom_query16(eeprom, eeprom_size, 188 EEPROM_LINK_CALIBRATION); 189 break; 190 case INDIRECT_PROCESS_ADJST: 191 offset = iwl_eeprom_query16(eeprom, eeprom_size, 192 EEPROM_LINK_PROCESS_ADJST); 193 break; 194 case INDIRECT_OTHERS: 195 offset = iwl_eeprom_query16(eeprom, eeprom_size, 196 EEPROM_LINK_OTHERS); 197 break; 198 default: 199 WARN_ON(1); 200 break; 201 } 202 203 /* translate the offset from words to byte */ 204 return (address & ADDRESS_MSK) + (offset << 1); 205 } 206 207 static const u8 *iwl_eeprom_query_addr(const u8 *eeprom, size_t eeprom_size, 208 u32 offset) 209 { 210 u32 address = eeprom_indirect_address(eeprom, eeprom_size, offset); 211 212 if (WARN_ON(address >= eeprom_size)) 213 return NULL; 214 215 return &eeprom[address]; 216 } 217 218 static int iwl_eeprom_read_calib(const u8 *eeprom, size_t eeprom_size, 219 struct iwl_nvm_data *data) 220 { 221 struct iwl_eeprom_calib_hdr *hdr; 222 223 hdr = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, 224 EEPROM_CALIB_ALL); 225 if (!hdr) 226 return -ENODATA; 227 data->calib_version = hdr->version; 228 data->calib_voltage = hdr->voltage; 229 230 return 0; 231 } 232 233 /** 234 * enum iwl_eeprom_channel_flags - channel flags in EEPROM 235 * @EEPROM_CHANNEL_VALID: channel is usable for this SKU/geo 236 * @EEPROM_CHANNEL_IBSS: usable as an IBSS channel 237 * @EEPROM_CHANNEL_ACTIVE: active scanning allowed 238 * @EEPROM_CHANNEL_RADAR: radar detection required 239 * @EEPROM_CHANNEL_WIDE: 20 MHz channel okay (?) 240 * @EEPROM_CHANNEL_DFS: dynamic freq selection candidate 241 */ 242 enum iwl_eeprom_channel_flags { 243 EEPROM_CHANNEL_VALID = BIT(0), 244 EEPROM_CHANNEL_IBSS = BIT(1), 245 EEPROM_CHANNEL_ACTIVE = BIT(3), 246 EEPROM_CHANNEL_RADAR = BIT(4), 247 EEPROM_CHANNEL_WIDE = BIT(5), 248 EEPROM_CHANNEL_DFS = BIT(7), 249 }; 250 251 /** 252 * struct iwl_eeprom_channel - EEPROM channel data 253 * @flags: %EEPROM_CHANNEL_* flags 254 * @max_power_avg: max power (in dBm) on this channel, at most 31 dBm 255 */ 256 struct iwl_eeprom_channel { 257 u8 flags; 258 s8 max_power_avg; 259 } __packed; 260 261 enum iwl_eeprom_enhanced_txpwr_flags { 262 IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0), 263 IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1), 264 IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2), 265 IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3), 266 IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4), 267 IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5), 268 IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6), 269 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7), 270 }; 271 272 /** 273 * struct iwl_eeprom_enhanced_txpwr - enhanced regulatory TX power limits 274 * @flags: entry flags 275 * @channel: channel number 276 * @chain_a_max: chain a max power in 1/2 dBm 277 * @chain_b_max: chain b max power in 1/2 dBm 278 * @chain_c_max: chain c max power in 1/2 dBm 279 * @delta_20_in_40: 20-in-40 deltas (hi/lo) 280 * @mimo2_max: mimo2 max power in 1/2 dBm 281 * @mimo3_max: mimo3 max power in 1/2 dBm 282 * 283 * This structure presents the enhanced regulatory tx power limit layout 284 * in an EEPROM image. 285 */ 286 struct iwl_eeprom_enhanced_txpwr { 287 u8 flags; 288 u8 channel; 289 s8 chain_a_max; 290 s8 chain_b_max; 291 s8 chain_c_max; 292 u8 delta_20_in_40; 293 s8 mimo2_max; 294 s8 mimo3_max; 295 } __packed; 296 297 static s8 iwl_get_max_txpwr_half_dbm(const struct iwl_nvm_data *data, 298 struct iwl_eeprom_enhanced_txpwr *txp) 299 { 300 s8 result = 0; /* (.5 dBm) */ 301 302 /* Take the highest tx power from any valid chains */ 303 if (data->valid_tx_ant & ANT_A && txp->chain_a_max > result) 304 result = txp->chain_a_max; 305 306 if (data->valid_tx_ant & ANT_B && txp->chain_b_max > result) 307 result = txp->chain_b_max; 308 309 if (data->valid_tx_ant & ANT_C && txp->chain_c_max > result) 310 result = txp->chain_c_max; 311 312 if ((data->valid_tx_ant == ANT_AB || 313 data->valid_tx_ant == ANT_BC || 314 data->valid_tx_ant == ANT_AC) && txp->mimo2_max > result) 315 result = txp->mimo2_max; 316 317 if (data->valid_tx_ant == ANT_ABC && txp->mimo3_max > result) 318 result = txp->mimo3_max; 319 320 return result; 321 } 322 323 #define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT) 324 #define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr) 325 #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE) 326 327 #define TXP_CHECK_AND_PRINT(x) \ 328 ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) ? # x " " : "") 329 330 static void 331 iwl_eeprom_enh_txp_read_element(struct iwl_nvm_data *data, 332 struct iwl_eeprom_enhanced_txpwr *txp, 333 int n_channels, s8 max_txpower_avg) 334 { 335 int ch_idx; 336 enum nl80211_band band; 337 338 band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ? 339 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ; 340 341 for (ch_idx = 0; ch_idx < n_channels; ch_idx++) { 342 struct ieee80211_channel *chan = &data->channels[ch_idx]; 343 344 /* update matching channel or from common data only */ 345 if (txp->channel != 0 && chan->hw_value != txp->channel) 346 continue; 347 348 /* update matching band only */ 349 if (band != chan->band) 350 continue; 351 352 if (chan->max_power < max_txpower_avg && 353 !(txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ)) 354 chan->max_power = max_txpower_avg; 355 } 356 } 357 358 static void iwl_eeprom_enhanced_txpower(struct device *dev, 359 struct iwl_nvm_data *data, 360 const u8 *eeprom, size_t eeprom_size, 361 int n_channels) 362 { 363 struct iwl_eeprom_enhanced_txpwr *txp_array, *txp; 364 int idx, entries; 365 __le16 *txp_len; 366 s8 max_txp_avg_halfdbm; 367 368 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8); 369 370 /* the length is in 16-bit words, but we want entries */ 371 txp_len = (__le16 *)iwl_eeprom_query_addr(eeprom, eeprom_size, 372 EEPROM_TXP_SZ_OFFS); 373 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN; 374 375 txp_array = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, 376 EEPROM_TXP_OFFS); 377 378 for (idx = 0; idx < entries; idx++) { 379 txp = &txp_array[idx]; 380 /* skip invalid entries */ 381 if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID)) 382 continue; 383 384 IWL_DEBUG_EEPROM(dev, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n", 385 (txp->channel && (txp->flags & 386 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ? 387 "Common " : (txp->channel) ? 388 "Channel" : "Common", 389 (txp->channel), 390 TXP_CHECK_AND_PRINT(VALID), 391 TXP_CHECK_AND_PRINT(BAND_52G), 392 TXP_CHECK_AND_PRINT(OFDM), 393 TXP_CHECK_AND_PRINT(40MHZ), 394 TXP_CHECK_AND_PRINT(HT_AP), 395 TXP_CHECK_AND_PRINT(RES1), 396 TXP_CHECK_AND_PRINT(RES2), 397 TXP_CHECK_AND_PRINT(COMMON_TYPE), 398 txp->flags); 399 IWL_DEBUG_EEPROM(dev, 400 "\t\t chain_A: %d chain_B: %d chain_C: %d\n", 401 txp->chain_a_max, txp->chain_b_max, 402 txp->chain_c_max); 403 IWL_DEBUG_EEPROM(dev, 404 "\t\t MIMO2: %d MIMO3: %d High 20_on_40: 0x%02x Low 20_on_40: 0x%02x\n", 405 txp->mimo2_max, txp->mimo3_max, 406 ((txp->delta_20_in_40 & 0xf0) >> 4), 407 (txp->delta_20_in_40 & 0x0f)); 408 409 max_txp_avg_halfdbm = iwl_get_max_txpwr_half_dbm(data, txp); 410 411 iwl_eeprom_enh_txp_read_element(data, txp, n_channels, 412 DIV_ROUND_UP(max_txp_avg_halfdbm, 2)); 413 414 if (max_txp_avg_halfdbm > data->max_tx_pwr_half_dbm) 415 data->max_tx_pwr_half_dbm = max_txp_avg_halfdbm; 416 } 417 } 418 419 static void iwl_init_band_reference(const struct iwl_cfg *cfg, 420 const u8 *eeprom, size_t eeprom_size, 421 int eeprom_band, int *eeprom_ch_count, 422 const struct iwl_eeprom_channel **ch_info, 423 const u8 **eeprom_ch_array) 424 { 425 u32 offset = cfg->eeprom_params->regulatory_bands[eeprom_band - 1]; 426 427 offset |= INDIRECT_ADDRESS | INDIRECT_REGULATORY; 428 429 *ch_info = (void *)iwl_eeprom_query_addr(eeprom, eeprom_size, offset); 430 431 switch (eeprom_band) { 432 case 1: /* 2.4GHz band */ 433 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1); 434 *eeprom_ch_array = iwl_eeprom_band_1; 435 break; 436 case 2: /* 4.9GHz band */ 437 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2); 438 *eeprom_ch_array = iwl_eeprom_band_2; 439 break; 440 case 3: /* 5.2GHz band */ 441 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3); 442 *eeprom_ch_array = iwl_eeprom_band_3; 443 break; 444 case 4: /* 5.5GHz band */ 445 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4); 446 *eeprom_ch_array = iwl_eeprom_band_4; 447 break; 448 case 5: /* 5.7GHz band */ 449 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5); 450 *eeprom_ch_array = iwl_eeprom_band_5; 451 break; 452 case 6: /* 2.4GHz ht40 channels */ 453 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6); 454 *eeprom_ch_array = iwl_eeprom_band_6; 455 break; 456 case 7: /* 5 GHz ht40 channels */ 457 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7); 458 *eeprom_ch_array = iwl_eeprom_band_7; 459 break; 460 default: 461 *eeprom_ch_count = 0; 462 *eeprom_ch_array = NULL; 463 WARN_ON(1); 464 } 465 } 466 467 #define CHECK_AND_PRINT(x) \ 468 ((eeprom_ch->flags & EEPROM_CHANNEL_##x) ? # x " " : "") 469 470 static void iwl_mod_ht40_chan_info(struct device *dev, 471 struct iwl_nvm_data *data, int n_channels, 472 enum nl80211_band band, u16 channel, 473 const struct iwl_eeprom_channel *eeprom_ch, 474 u8 clear_ht40_extension_channel) 475 { 476 struct ieee80211_channel *chan = NULL; 477 int i; 478 479 for (i = 0; i < n_channels; i++) { 480 if (data->channels[i].band != band) 481 continue; 482 if (data->channels[i].hw_value != channel) 483 continue; 484 chan = &data->channels[i]; 485 break; 486 } 487 488 if (!chan) 489 return; 490 491 IWL_DEBUG_EEPROM(dev, 492 "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", 493 channel, 494 band == NL80211_BAND_5GHZ ? "5.2" : "2.4", 495 CHECK_AND_PRINT(IBSS), 496 CHECK_AND_PRINT(ACTIVE), 497 CHECK_AND_PRINT(RADAR), 498 CHECK_AND_PRINT(WIDE), 499 CHECK_AND_PRINT(DFS), 500 eeprom_ch->flags, 501 eeprom_ch->max_power_avg, 502 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) && 503 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" 504 : "not "); 505 506 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID) 507 chan->flags &= ~clear_ht40_extension_channel; 508 } 509 510 #define CHECK_AND_PRINT_I(x) \ 511 ((eeprom_ch_info[ch_idx].flags & EEPROM_CHANNEL_##x) ? # x " " : "") 512 513 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg, 514 struct iwl_nvm_data *data, 515 const u8 *eeprom, size_t eeprom_size) 516 { 517 int band, ch_idx; 518 const struct iwl_eeprom_channel *eeprom_ch_info; 519 const u8 *eeprom_ch_array; 520 int eeprom_ch_count; 521 int n_channels = 0; 522 523 /* 524 * Loop through the 5 EEPROM bands and add them to the parse list 525 */ 526 for (band = 1; band <= 5; band++) { 527 struct ieee80211_channel *channel; 528 529 iwl_init_band_reference(cfg, eeprom, eeprom_size, band, 530 &eeprom_ch_count, &eeprom_ch_info, 531 &eeprom_ch_array); 532 533 /* Loop through each band adding each of the channels */ 534 for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) { 535 const struct iwl_eeprom_channel *eeprom_ch; 536 537 eeprom_ch = &eeprom_ch_info[ch_idx]; 538 539 if (!(eeprom_ch->flags & EEPROM_CHANNEL_VALID)) { 540 IWL_DEBUG_EEPROM(dev, 541 "Ch. %d Flags %x [%sGHz] - No traffic\n", 542 eeprom_ch_array[ch_idx], 543 eeprom_ch_info[ch_idx].flags, 544 (band != 1) ? "5.2" : "2.4"); 545 continue; 546 } 547 548 channel = &data->channels[n_channels]; 549 n_channels++; 550 551 channel->hw_value = eeprom_ch_array[ch_idx]; 552 channel->band = (band == 1) ? NL80211_BAND_2GHZ 553 : NL80211_BAND_5GHZ; 554 channel->center_freq = 555 ieee80211_channel_to_frequency( 556 channel->hw_value, channel->band); 557 558 /* set no-HT40, will enable as appropriate later */ 559 channel->flags = IEEE80211_CHAN_NO_HT40; 560 561 if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS)) 562 channel->flags |= IEEE80211_CHAN_NO_IR; 563 564 if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE)) 565 channel->flags |= IEEE80211_CHAN_NO_IR; 566 567 if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR) 568 channel->flags |= IEEE80211_CHAN_RADAR; 569 570 /* Initialize regulatory-based run-time data */ 571 channel->max_power = 572 eeprom_ch_info[ch_idx].max_power_avg; 573 IWL_DEBUG_EEPROM(dev, 574 "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", 575 channel->hw_value, 576 (band != 1) ? "5.2" : "2.4", 577 CHECK_AND_PRINT_I(VALID), 578 CHECK_AND_PRINT_I(IBSS), 579 CHECK_AND_PRINT_I(ACTIVE), 580 CHECK_AND_PRINT_I(RADAR), 581 CHECK_AND_PRINT_I(WIDE), 582 CHECK_AND_PRINT_I(DFS), 583 eeprom_ch_info[ch_idx].flags, 584 eeprom_ch_info[ch_idx].max_power_avg, 585 ((eeprom_ch_info[ch_idx].flags & 586 EEPROM_CHANNEL_IBSS) && 587 !(eeprom_ch_info[ch_idx].flags & 588 EEPROM_CHANNEL_RADAR)) 589 ? "" : "not "); 590 } 591 } 592 593 if (cfg->eeprom_params->enhanced_txpower) { 594 /* 595 * for newer device (6000 series and up) 596 * EEPROM contain enhanced tx power information 597 * driver need to process addition information 598 * to determine the max channel tx power limits 599 */ 600 iwl_eeprom_enhanced_txpower(dev, data, eeprom, eeprom_size, 601 n_channels); 602 } else { 603 /* All others use data from channel map */ 604 int i; 605 606 data->max_tx_pwr_half_dbm = -128; 607 608 for (i = 0; i < n_channels; i++) 609 data->max_tx_pwr_half_dbm = 610 max_t(s8, data->max_tx_pwr_half_dbm, 611 data->channels[i].max_power * 2); 612 } 613 614 /* Check if we do have HT40 channels */ 615 if (cfg->eeprom_params->regulatory_bands[5] == 616 EEPROM_REGULATORY_BAND_NO_HT40 && 617 cfg->eeprom_params->regulatory_bands[6] == 618 EEPROM_REGULATORY_BAND_NO_HT40) 619 return n_channels; 620 621 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */ 622 for (band = 6; band <= 7; band++) { 623 enum nl80211_band ieeeband; 624 625 iwl_init_band_reference(cfg, eeprom, eeprom_size, band, 626 &eeprom_ch_count, &eeprom_ch_info, 627 &eeprom_ch_array); 628 629 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */ 630 ieeeband = (band == 6) ? NL80211_BAND_2GHZ 631 : NL80211_BAND_5GHZ; 632 633 /* Loop through each band adding each of the channels */ 634 for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) { 635 /* Set up driver's info for lower half */ 636 iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband, 637 eeprom_ch_array[ch_idx], 638 &eeprom_ch_info[ch_idx], 639 IEEE80211_CHAN_NO_HT40PLUS); 640 641 /* Set up driver's info for upper half */ 642 iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband, 643 eeprom_ch_array[ch_idx] + 4, 644 &eeprom_ch_info[ch_idx], 645 IEEE80211_CHAN_NO_HT40MINUS); 646 } 647 } 648 649 return n_channels; 650 } 651 /* 652 * EEPROM access time values: 653 * 654 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. 655 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). 656 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. 657 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. 658 */ 659 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 660 661 /* 662 * The device's EEPROM semaphore prevents conflicts between driver and uCode 663 * when accessing the EEPROM; each access is a series of pulses to/from the 664 * EEPROM chip, not a single event, so even reads could conflict if they 665 * weren't arbitrated by the semaphore. 666 */ 667 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ 668 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 669 670 671 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans) 672 { 673 u16 count; 674 int ret; 675 676 for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) { 677 /* Request semaphore */ 678 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 679 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 680 681 /* See if we got it */ 682 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 683 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 684 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 685 IWL_EEPROM_SEM_TIMEOUT); 686 if (ret >= 0) { 687 IWL_DEBUG_EEPROM(trans->dev, 688 "Acquired semaphore after %d tries.\n", 689 count+1); 690 return ret; 691 } 692 } 693 694 return ret; 695 } 696 697 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans) 698 { 699 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG, 700 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 701 } 702 703 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp) 704 { 705 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; 706 707 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp); 708 709 switch (gp) { 710 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP: 711 if (!nvm_is_otp) { 712 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n", 713 gp); 714 return -ENOENT; 715 } 716 return 0; 717 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K: 718 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K: 719 if (nvm_is_otp) { 720 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); 721 return -ENOENT; 722 } 723 return 0; 724 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP: 725 default: 726 IWL_ERR(trans, 727 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", 728 nvm_is_otp ? "OTP" : "EEPROM", gp); 729 return -ENOENT; 730 } 731 } 732 733 /****************************************************************************** 734 * 735 * OTP related functions 736 * 737 ******************************************************************************/ 738 739 static void iwl_set_otp_access_absolute(struct iwl_trans *trans) 740 { 741 iwl_read32(trans, CSR_OTP_GP_REG); 742 743 iwl_clear_bit(trans, CSR_OTP_GP_REG, 744 CSR_OTP_GP_REG_OTP_ACCESS_MODE); 745 } 746 747 static int iwl_nvm_is_otp(struct iwl_trans *trans) 748 { 749 u32 otpgp; 750 751 /* OTP only valid for CP/PP and after */ 752 switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) { 753 case CSR_HW_REV_TYPE_NONE: 754 IWL_ERR(trans, "Unknown hardware type\n"); 755 return -EIO; 756 case CSR_HW_REV_TYPE_5300: 757 case CSR_HW_REV_TYPE_5350: 758 case CSR_HW_REV_TYPE_5100: 759 case CSR_HW_REV_TYPE_5150: 760 return 0; 761 default: 762 otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 763 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) 764 return 1; 765 return 0; 766 } 767 } 768 769 static int iwl_init_otp_access(struct iwl_trans *trans) 770 { 771 int ret; 772 773 ret = iwl_finish_nic_init(trans); 774 if (ret) 775 return ret; 776 777 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG, 778 APMG_PS_CTRL_VAL_RESET_REQ); 779 udelay(5); 780 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG, 781 APMG_PS_CTRL_VAL_RESET_REQ); 782 783 /* 784 * CSR auto clock gate disable bit - 785 * this is only applicable for HW with OTP shadow RAM 786 */ 787 if (trans->trans_cfg->base_params->shadow_ram_support) 788 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 789 CSR_RESET_LINK_PWR_MGMT_DISABLED); 790 791 return 0; 792 } 793 794 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr, 795 __le16 *eeprom_data) 796 { 797 int ret = 0; 798 u32 r; 799 u32 otpgp; 800 801 iwl_write32(trans, CSR_EEPROM_REG, 802 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 803 ret = iwl_poll_bit(trans, CSR_EEPROM_REG, 804 CSR_EEPROM_REG_READ_VALID_MSK, 805 CSR_EEPROM_REG_READ_VALID_MSK, 806 IWL_EEPROM_ACCESS_TIMEOUT); 807 if (ret < 0) { 808 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); 809 return ret; 810 } 811 r = iwl_read32(trans, CSR_EEPROM_REG); 812 /* check for ECC errors: */ 813 otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 814 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { 815 /* stop in this case */ 816 /* set the uncorrectable OTP ECC bit for acknowledgment */ 817 iwl_set_bit(trans, CSR_OTP_GP_REG, 818 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 819 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); 820 return -EINVAL; 821 } 822 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { 823 /* continue in this case */ 824 /* set the correctable OTP ECC bit for acknowledgment */ 825 iwl_set_bit(trans, CSR_OTP_GP_REG, 826 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); 827 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n"); 828 } 829 *eeprom_data = cpu_to_le16(r >> 16); 830 return 0; 831 } 832 833 /* 834 * iwl_is_otp_empty: check for empty OTP 835 */ 836 static bool iwl_is_otp_empty(struct iwl_trans *trans) 837 { 838 u16 next_link_addr = 0; 839 __le16 link_value; 840 bool is_empty = false; 841 842 /* locate the beginning of OTP link list */ 843 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) { 844 if (!link_value) { 845 IWL_ERR(trans, "OTP is empty\n"); 846 is_empty = true; 847 } 848 } else { 849 IWL_ERR(trans, "Unable to read first block of OTP list.\n"); 850 is_empty = true; 851 } 852 853 return is_empty; 854 } 855 856 857 /* 858 * iwl_find_otp_image: find EEPROM image in OTP 859 * finding the OTP block that contains the EEPROM image. 860 * the last valid block on the link list (the block _before_ the last block) 861 * is the block we should read and used to configure the device. 862 * If all the available OTP blocks are full, the last block will be the block 863 * we should read and used to configure the device. 864 * only perform this operation if shadow RAM is disabled 865 */ 866 static int iwl_find_otp_image(struct iwl_trans *trans, 867 u16 *validblockaddr) 868 { 869 u16 next_link_addr = 0, valid_addr; 870 __le16 link_value = 0; 871 int usedblocks = 0; 872 873 /* set addressing mode to absolute to traverse the link list */ 874 iwl_set_otp_access_absolute(trans); 875 876 /* checking for empty OTP or error */ 877 if (iwl_is_otp_empty(trans)) 878 return -EINVAL; 879 880 /* 881 * start traverse link list 882 * until reach the max number of OTP blocks 883 * different devices have different number of OTP blocks 884 */ 885 do { 886 /* save current valid block address 887 * check for more block on the link list 888 */ 889 valid_addr = next_link_addr; 890 next_link_addr = le16_to_cpu(link_value) * sizeof(u16); 891 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n", 892 usedblocks, next_link_addr); 893 if (iwl_read_otp_word(trans, next_link_addr, &link_value)) 894 return -EINVAL; 895 if (!link_value) { 896 /* 897 * reach the end of link list, return success and 898 * set address point to the starting address 899 * of the image 900 */ 901 *validblockaddr = valid_addr; 902 /* skip first 2 bytes (link list pointer) */ 903 *validblockaddr += 2; 904 return 0; 905 } 906 /* more in the link list, continue */ 907 usedblocks++; 908 } while (usedblocks <= trans->trans_cfg->base_params->max_ll_items); 909 910 /* OTP has no valid blocks */ 911 IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n"); 912 return -EINVAL; 913 } 914 915 /* 916 * iwl_read_eeprom - read EEPROM contents 917 * 918 * Load the EEPROM contents from adapter and return it 919 * and its size. 920 * 921 * NOTE: This routine uses the non-debug IO access functions. 922 */ 923 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size) 924 { 925 __le16 *e; 926 u32 gp = iwl_read32(trans, CSR_EEPROM_GP); 927 int sz; 928 int ret; 929 u16 addr; 930 u16 validblockaddr = 0; 931 u16 cache_addr = 0; 932 int nvm_is_otp; 933 934 if (!eeprom || !eeprom_size) 935 return -EINVAL; 936 937 nvm_is_otp = iwl_nvm_is_otp(trans); 938 if (nvm_is_otp < 0) 939 return nvm_is_otp; 940 941 sz = trans->trans_cfg->base_params->eeprom_size; 942 IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz); 943 944 e = kmalloc(sz, GFP_KERNEL); 945 if (!e) 946 return -ENOMEM; 947 948 ret = iwl_eeprom_verify_signature(trans, nvm_is_otp); 949 if (ret < 0) { 950 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp); 951 goto err_free; 952 } 953 954 /* Make sure driver (instead of uCode) is allowed to read EEPROM */ 955 ret = iwl_eeprom_acquire_semaphore(trans); 956 if (ret < 0) { 957 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n"); 958 goto err_free; 959 } 960 961 if (nvm_is_otp) { 962 ret = iwl_init_otp_access(trans); 963 if (ret) { 964 IWL_ERR(trans, "Failed to initialize OTP access.\n"); 965 goto err_unlock; 966 } 967 968 iwl_write32(trans, CSR_EEPROM_GP, 969 iwl_read32(trans, CSR_EEPROM_GP) & 970 ~CSR_EEPROM_GP_IF_OWNER_MSK); 971 972 iwl_set_bit(trans, CSR_OTP_GP_REG, 973 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK | 974 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 975 /* traversing the linked list if no shadow ram supported */ 976 if (!trans->trans_cfg->base_params->shadow_ram_support) { 977 ret = iwl_find_otp_image(trans, &validblockaddr); 978 if (ret) 979 goto err_unlock; 980 } 981 for (addr = validblockaddr; addr < validblockaddr + sz; 982 addr += sizeof(u16)) { 983 __le16 eeprom_data; 984 985 ret = iwl_read_otp_word(trans, addr, &eeprom_data); 986 if (ret) 987 goto err_unlock; 988 e[cache_addr / 2] = eeprom_data; 989 cache_addr += sizeof(u16); 990 } 991 } else { 992 /* eeprom is an array of 16bit values */ 993 for (addr = 0; addr < sz; addr += sizeof(u16)) { 994 u32 r; 995 996 iwl_write32(trans, CSR_EEPROM_REG, 997 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 998 999 ret = iwl_poll_bit(trans, CSR_EEPROM_REG, 1000 CSR_EEPROM_REG_READ_VALID_MSK, 1001 CSR_EEPROM_REG_READ_VALID_MSK, 1002 IWL_EEPROM_ACCESS_TIMEOUT); 1003 if (ret < 0) { 1004 IWL_ERR(trans, 1005 "Time out reading EEPROM[%d]\n", addr); 1006 goto err_unlock; 1007 } 1008 r = iwl_read32(trans, CSR_EEPROM_REG); 1009 e[addr / 2] = cpu_to_le16(r >> 16); 1010 } 1011 } 1012 1013 IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n", 1014 nvm_is_otp ? "OTP" : "EEPROM"); 1015 1016 iwl_eeprom_release_semaphore(trans); 1017 1018 *eeprom_size = sz; 1019 *eeprom = (u8 *)e; 1020 return 0; 1021 1022 err_unlock: 1023 iwl_eeprom_release_semaphore(trans); 1024 err_free: 1025 kfree(e); 1026 1027 return ret; 1028 } 1029 1030 static void iwl_init_sbands(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1031 struct iwl_nvm_data *data, 1032 const u8 *eeprom, size_t eeprom_size) 1033 { 1034 struct device *dev = trans->dev; 1035 int n_channels = iwl_init_channel_map(dev, cfg, data, 1036 eeprom, eeprom_size); 1037 int n_used = 0; 1038 struct ieee80211_supported_band *sband; 1039 1040 sband = &data->bands[NL80211_BAND_2GHZ]; 1041 sband->band = NL80211_BAND_2GHZ; 1042 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 1043 sband->n_bitrates = N_RATES_24; 1044 n_used += iwl_init_sband_channels(data, sband, n_channels, 1045 NL80211_BAND_2GHZ); 1046 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 1047 data->valid_tx_ant, data->valid_rx_ant); 1048 1049 sband = &data->bands[NL80211_BAND_5GHZ]; 1050 sband->band = NL80211_BAND_5GHZ; 1051 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 1052 sband->n_bitrates = N_RATES_52; 1053 n_used += iwl_init_sband_channels(data, sband, n_channels, 1054 NL80211_BAND_5GHZ); 1055 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 1056 data->valid_tx_ant, data->valid_rx_ant); 1057 1058 if (n_channels != n_used) 1059 IWL_ERR_DEV(dev, "EEPROM: used only %d of %d channels\n", 1060 n_used, n_channels); 1061 } 1062 1063 /* EEPROM data functions */ 1064 struct iwl_nvm_data * 1065 iwl_parse_eeprom_data(struct iwl_trans *trans, const struct iwl_cfg *cfg, 1066 const u8 *eeprom, size_t eeprom_size) 1067 { 1068 struct iwl_nvm_data *data; 1069 struct device *dev = trans->dev; 1070 const void *tmp; 1071 u16 radio_cfg, sku; 1072 1073 if (WARN_ON(!cfg || !cfg->eeprom_params)) 1074 return NULL; 1075 1076 data = kzalloc(struct_size(data, channels, IWL_NUM_CHANNELS), 1077 GFP_KERNEL); 1078 if (!data) 1079 return NULL; 1080 1081 /* get MAC address(es) */ 1082 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_MAC_ADDRESS); 1083 if (!tmp) 1084 goto err_free; 1085 memcpy(data->hw_addr, tmp, ETH_ALEN); 1086 data->n_hw_addrs = iwl_eeprom_query16(eeprom, eeprom_size, 1087 EEPROM_NUM_MAC_ADDRESS); 1088 1089 if (iwl_eeprom_read_calib(eeprom, eeprom_size, data)) 1090 goto err_free; 1091 1092 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_XTAL); 1093 if (!tmp) 1094 goto err_free; 1095 memcpy(data->xtal_calib, tmp, sizeof(data->xtal_calib)); 1096 1097 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, 1098 EEPROM_RAW_TEMPERATURE); 1099 if (!tmp) 1100 goto err_free; 1101 data->raw_temperature = *(__le16 *)tmp; 1102 1103 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, 1104 EEPROM_KELVIN_TEMPERATURE); 1105 if (!tmp) 1106 goto err_free; 1107 data->kelvin_temperature = *(__le16 *)tmp; 1108 data->kelvin_voltage = *((__le16 *)tmp + 1); 1109 1110 radio_cfg = 1111 iwl_eeprom_query16(eeprom, eeprom_size, EEPROM_RADIO_CONFIG); 1112 data->radio_cfg_dash = EEPROM_RF_CFG_DASH_MSK(radio_cfg); 1113 data->radio_cfg_pnum = EEPROM_RF_CFG_PNUM_MSK(radio_cfg); 1114 data->radio_cfg_step = EEPROM_RF_CFG_STEP_MSK(radio_cfg); 1115 data->radio_cfg_type = EEPROM_RF_CFG_TYPE_MSK(radio_cfg); 1116 data->valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg); 1117 data->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg); 1118 1119 sku = iwl_eeprom_query16(eeprom, eeprom_size, 1120 EEPROM_SKU_CAP); 1121 data->sku_cap_11n_enable = sku & EEPROM_SKU_CAP_11N_ENABLE; 1122 data->sku_cap_amt_enable = sku & EEPROM_SKU_CAP_AMT_ENABLE; 1123 data->sku_cap_band_24ghz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ; 1124 data->sku_cap_band_52ghz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ; 1125 data->sku_cap_ipan_enable = sku & EEPROM_SKU_CAP_IPAN_ENABLE; 1126 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1127 data->sku_cap_11n_enable = false; 1128 1129 data->nvm_version = iwl_eeprom_query16(eeprom, eeprom_size, 1130 EEPROM_VERSION); 1131 1132 /* check overrides (some devices have wrong EEPROM) */ 1133 if (cfg->valid_tx_ant) 1134 data->valid_tx_ant = cfg->valid_tx_ant; 1135 if (cfg->valid_rx_ant) 1136 data->valid_rx_ant = cfg->valid_rx_ant; 1137 1138 if (!data->valid_tx_ant || !data->valid_rx_ant) { 1139 IWL_ERR_DEV(dev, "invalid antennas (0x%x, 0x%x)\n", 1140 data->valid_tx_ant, data->valid_rx_ant); 1141 goto err_free; 1142 } 1143 1144 iwl_init_sbands(trans, cfg, data, eeprom, eeprom_size); 1145 1146 return data; 1147 err_free: 1148 kfree(data); 1149 return NULL; 1150 } 1151