1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2024 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_SC_UCODE_API_MAX 96 14 15 /* Lowest firmware API version supported */ 16 #define IWL_SC_UCODE_API_MIN 92 17 18 /* NVM versions */ 19 #define IWL_SC_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_SC_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_SC_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_SC_DCCM2_OFFSET 0x880000 25 #define IWL_SC_DCCM2_LEN 0x8000 26 #define IWL_SC_SMEM_OFFSET 0x400000 27 #define IWL_SC_SMEM_LEN 0xD0000 28 29 #define IWL_SC_A_FM_B_FW_PRE "iwlwifi-sc-a0-fm-b0" 30 #define IWL_SC_A_FM_C_FW_PRE "iwlwifi-sc-a0-fm-c0" 31 #define IWL_SC_A_HR_A_FW_PRE "iwlwifi-sc-a0-hr-b0" 32 #define IWL_SC_A_HR_B_FW_PRE "iwlwifi-sc-a0-hr-b0" 33 #define IWL_SC_A_GF_A_FW_PRE "iwlwifi-sc-a0-gf-a0" 34 #define IWL_SC_A_GF4_A_FW_PRE "iwlwifi-sc-a0-gf4-a0" 35 #define IWL_SC_A_WH_A_FW_PRE "iwlwifi-sc-a0-wh-a0" 36 #define IWL_SC2_A_FM_C_FW_PRE "iwlwifi-sc2-a0-fm-c0" 37 #define IWL_SC2_A_WH_A_FW_PRE "iwlwifi-sc2-a0-wh-a0" 38 #define IWL_SC2F_A_FM_C_FW_PRE "iwlwifi-sc2f-a0-fm-c0" 39 #define IWL_SC2F_A_WH_A_FW_PRE "iwlwifi-sc2f-a0-wh-a0" 40 41 #define IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(api) \ 42 IWL_SC_A_HR_A_FW_PRE "-" __stringify(api) ".ucode" 43 #define IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(api) \ 44 IWL_SC_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 45 46 static const struct iwl_base_params iwl_sc_base_params = { 47 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 48 .num_of_queues = 512, 49 .max_tfd_queue_size = 65536, 50 .shadow_ram_support = true, 51 .led_compensation = 57, 52 .wd_timeout = IWL_LONG_WD_TIMEOUT, 53 .max_event_log_size = 512, 54 .shadow_reg_enable = true, 55 .pcie_l1_allowed = true, 56 }; 57 58 #define IWL_DEVICE_BZ_COMMON \ 59 .ucode_api_max = IWL_SC_UCODE_API_MAX, \ 60 .ucode_api_min = IWL_SC_UCODE_API_MIN, \ 61 .led_mode = IWL_LED_RF_STATE, \ 62 .nvm_hw_section_num = 10, \ 63 .non_shared_ant = ANT_B, \ 64 .dccm_offset = IWL_SC_DCCM_OFFSET, \ 65 .dccm_len = IWL_SC_DCCM_LEN, \ 66 .dccm2_offset = IWL_SC_DCCM2_OFFSET, \ 67 .dccm2_len = IWL_SC_DCCM2_LEN, \ 68 .smem_offset = IWL_SC_SMEM_OFFSET, \ 69 .smem_len = IWL_SC_SMEM_LEN, \ 70 .apmg_not_supported = true, \ 71 .trans.mq_rx_supported = true, \ 72 .vht_mu_mimo_supported = true, \ 73 .mac_addr_from_csr = 0x30, \ 74 .nvm_ver = IWL_SC_NVM_VERSION, \ 75 .trans.rf_id = true, \ 76 .trans.gen2 = true, \ 77 .nvm_type = IWL_NVM_EXT, \ 78 .dbgc_supported = true, \ 79 .min_umac_error_event_table = 0xD0000, \ 80 .d3_debug_data_base_addr = 0x401000, \ 81 .d3_debug_data_length = 60 * 1024, \ 82 .mon_smem_regs = { \ 83 .write_ptr = { \ 84 .addr = LDBG_M2S_BUF_WPTR, \ 85 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 86 }, \ 87 .cycle_cnt = { \ 88 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 89 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 90 }, \ 91 }, \ 92 .trans.umac_prph_offset = 0x300000, \ 93 .trans.device_family = IWL_DEVICE_FAMILY_SC, \ 94 .trans.base_params = &iwl_sc_base_params, \ 95 .min_txq_size = 128, \ 96 .gp2_reg_addr = 0xd02c68, \ 97 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 98 .mon_dram_regs = { \ 99 .write_ptr = { \ 100 .addr = DBGC_CUR_DBGBUF_STATUS, \ 101 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 102 }, \ 103 .cycle_cnt = { \ 104 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 105 .mask = 0xffffffff, \ 106 }, \ 107 .cur_frag = { \ 108 .addr = DBGC_CUR_DBGBUF_STATUS, \ 109 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 110 }, \ 111 }, \ 112 .mon_dbgi_regs = { \ 113 .write_ptr = { \ 114 .addr = DBGI_SRAM_FIFO_POINTERS, \ 115 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 116 }, \ 117 } 118 119 #define IWL_DEVICE_SC \ 120 IWL_DEVICE_BZ_COMMON, \ 121 .uhb_supported = true, \ 122 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 123 .num_rbds = IWL_NUM_RBDS_SC_EHT, \ 124 .ht_params = &iwl_22000_ht_params 125 126 /* 127 * This size was picked according to 8 MSDUs inside 512 A-MSDUs in an 128 * A-MPDU, with additional overhead to account for processing time. 129 */ 130 #define IWL_NUM_RBDS_SC_EHT (512 * 16) 131 132 const struct iwl_cfg_trans_params iwl_sc_trans_cfg = { 133 .device_family = IWL_DEVICE_FAMILY_SC, 134 .base_params = &iwl_sc_base_params, 135 .mq_rx_supported = true, 136 .rf_id = true, 137 .gen2 = true, 138 .integrated = true, 139 .umac_prph_offset = 0x300000, 140 .xtal_latency = 12000, 141 .low_latency_xtal = true, 142 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 143 }; 144 145 const char iwl_sc_name[] = "Intel(R) TBD Sc device"; 146 147 const struct iwl_cfg iwl_cfg_sc = { 148 .fw_name_mac = "sc", 149 IWL_DEVICE_SC, 150 }; 151 152 const char iwl_sc2_name[] = "Intel(R) TBD Sc2 device"; 153 154 const struct iwl_cfg iwl_cfg_sc2 = { 155 .fw_name_mac = "sc2", 156 IWL_DEVICE_SC, 157 }; 158 159 const char iwl_sc2f_name[] = "Intel(R) TBD Sc2f device"; 160 161 const struct iwl_cfg iwl_cfg_sc2f = { 162 .fw_name_mac = "sc2f", 163 IWL_DEVICE_SC, 164 }; 165 166 IWL_FW_AND_PNVM(IWL_SC_A_FM_B_FW_PRE, IWL_SC_UCODE_API_MAX); 167 IWL_FW_AND_PNVM(IWL_SC_A_FM_C_FW_PRE, IWL_SC_UCODE_API_MAX); 168 MODULE_FIRMWARE(IWL_SC_A_HR_A_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 169 MODULE_FIRMWARE(IWL_SC_A_HR_B_FW_MODULE_FIRMWARE(IWL_SC_UCODE_API_MAX)); 170 IWL_FW_AND_PNVM(IWL_SC_A_GF_A_FW_PRE, IWL_SC_UCODE_API_MAX); 171 IWL_FW_AND_PNVM(IWL_SC_A_GF4_A_FW_PRE, IWL_SC_UCODE_API_MAX); 172 IWL_FW_AND_PNVM(IWL_SC_A_WH_A_FW_PRE, IWL_SC_UCODE_API_MAX); 173 IWL_FW_AND_PNVM(IWL_SC2_A_FM_C_FW_PRE, IWL_SC_UCODE_API_MAX); 174 IWL_FW_AND_PNVM(IWL_SC2_A_WH_A_FW_PRE, IWL_SC_UCODE_API_MAX); 175 IWL_FW_AND_PNVM(IWL_SC2F_A_FM_C_FW_PRE, IWL_SC_UCODE_API_MAX); 176 IWL_FW_AND_PNVM(IWL_SC2F_A_WH_A_FW_PRE, IWL_SC_UCODE_API_MAX); 177