1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2025 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_BZ_UCODE_API_MAX 98 14 15 /* Lowest firmware API version supported */ 16 #define IWL_BZ_UCODE_API_MIN 93 17 18 /* NVM versions */ 19 #define IWL_BZ_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_BZ_DCCM2_OFFSET 0x880000 25 #define IWL_BZ_DCCM2_LEN 0x8000 26 #define IWL_BZ_SMEM_OFFSET 0x400000 27 #define IWL_BZ_SMEM_LEN 0xD0000 28 29 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0" 30 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0" 31 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0" 32 #define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0" 33 #define IWL_BZ_A_FM_C_FW_PRE "iwlwifi-bz-a0-fm-c0" 34 #define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0" 35 #define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0" 36 #define IWL_GL_C_FM_C_FW_PRE "iwlwifi-gl-c0-fm-c0" 37 38 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 39 IWL_BZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 40 41 #if !IS_ENABLED(CONFIG_IWLMVM) 42 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 43 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 44 #endif 45 46 static const struct iwl_base_params iwl_bz_base_params = { 47 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 48 .num_of_queues = 512, 49 .max_tfd_queue_size = 65536, 50 .shadow_ram_support = true, 51 .led_compensation = 57, 52 .wd_timeout = IWL_LONG_WD_TIMEOUT, 53 .max_event_log_size = 512, 54 .shadow_reg_enable = true, 55 .pcie_l1_allowed = true, 56 }; 57 58 const struct iwl_ht_params iwl_bz_ht_params = { 59 .stbc = true, 60 .ldpc = true, 61 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 62 BIT(NL80211_BAND_6GHZ), 63 }; 64 65 #define IWL_DEVICE_BZ_COMMON \ 66 .ucode_api_max = IWL_BZ_UCODE_API_MAX, \ 67 .ucode_api_min = IWL_BZ_UCODE_API_MIN, \ 68 .led_mode = IWL_LED_RF_STATE, \ 69 .nvm_hw_section_num = 10, \ 70 .non_shared_ant = ANT_B, \ 71 .dccm_offset = IWL_BZ_DCCM_OFFSET, \ 72 .dccm_len = IWL_BZ_DCCM_LEN, \ 73 .dccm2_offset = IWL_BZ_DCCM2_OFFSET, \ 74 .dccm2_len = IWL_BZ_DCCM2_LEN, \ 75 .smem_offset = IWL_BZ_SMEM_OFFSET, \ 76 .smem_len = IWL_BZ_SMEM_LEN, \ 77 .apmg_not_supported = true, \ 78 .vht_mu_mimo_supported = true, \ 79 .mac_addr_from_csr = 0x30, \ 80 .nvm_ver = IWL_BZ_NVM_VERSION, \ 81 .nvm_type = IWL_NVM_EXT, \ 82 .dbgc_supported = true, \ 83 .min_umac_error_event_table = 0xD0000, \ 84 .d3_debug_data_base_addr = 0x401000, \ 85 .d3_debug_data_length = 60 * 1024, \ 86 .mon_smem_regs = { \ 87 .write_ptr = { \ 88 .addr = LDBG_M2S_BUF_WPTR, \ 89 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 90 }, \ 91 .cycle_cnt = { \ 92 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 93 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 94 }, \ 95 }, \ 96 .min_txq_size = 128, \ 97 .gp2_reg_addr = 0xd02c68, \ 98 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 99 .mon_dram_regs = { \ 100 .write_ptr = { \ 101 .addr = DBGC_CUR_DBGBUF_STATUS, \ 102 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 103 }, \ 104 .cycle_cnt = { \ 105 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 106 .mask = 0xffffffff, \ 107 }, \ 108 .cur_frag = { \ 109 .addr = DBGC_CUR_DBGBUF_STATUS, \ 110 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 111 }, \ 112 }, \ 113 .mon_dbgi_regs = { \ 114 .write_ptr = { \ 115 .addr = DBGI_SRAM_FIFO_POINTERS, \ 116 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 117 }, \ 118 } 119 120 #define IWL_DEVICE_BZ \ 121 IWL_DEVICE_BZ_COMMON, \ 122 .ht_params = &iwl_bz_ht_params 123 124 /* 125 * This size was picked according to 8 MSDUs inside 512 A-MSDUs in an 126 * A-MPDU, with additional overhead to account for processing time. 127 */ 128 #define IWL_NUM_RBDS_BZ_EHT (512 * 16) 129 130 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 131 .device_family = IWL_DEVICE_FAMILY_BZ, 132 .base_params = &iwl_bz_base_params, 133 .mq_rx_supported = true, 134 .rf_id = true, 135 .gen2 = true, 136 .integrated = true, 137 .umac_prph_offset = 0x300000, 138 .xtal_latency = 12000, 139 .low_latency_xtal = true, 140 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 141 }; 142 143 const struct iwl_cfg_trans_params iwl_gl_trans_cfg = { 144 .device_family = IWL_DEVICE_FAMILY_BZ, 145 .base_params = &iwl_bz_base_params, 146 .mq_rx_supported = true, 147 .rf_id = true, 148 .gen2 = true, 149 .umac_prph_offset = 0x300000, 150 .xtal_latency = 12000, 151 .low_latency_xtal = true, 152 }; 153 154 const char iwl_fm_name[] = "Intel(R) Wi-Fi 7 BE201 320MHz"; 155 const char iwl_wh_name[] = "Intel(R) Wi-Fi 7 BE211 320MHz"; 156 const char iwl_gl_name[] = "Intel(R) Wi-Fi 7 BE200 320MHz"; 157 const char iwl_mtp_name[] = "Intel(R) Wi-Fi 7 BE202 160MHz"; 158 159 const struct iwl_cfg iwl_cfg_bz = { 160 .uhb_supported = true, 161 IWL_DEVICE_BZ, 162 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 163 .num_rbds = IWL_NUM_RBDS_BZ_EHT, 164 }; 165 166 const struct iwl_cfg iwl_cfg_bz_160mhz = { 167 .uhb_supported = true, 168 IWL_DEVICE_BZ, 169 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 170 .num_rbds = IWL_NUM_RBDS_BZ_EHT, 171 .bw_limit = 160, 172 }; 173 174 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX)); 175 IWL_FW_AND_PNVM(IWL_BZ_A_GF_A_FW_PRE, IWL_BZ_UCODE_API_MAX); 176 IWL_FW_AND_PNVM(IWL_BZ_A_GF4_A_FW_PRE, IWL_BZ_UCODE_API_MAX); 177 IWL_FW_AND_PNVM(IWL_BZ_A_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 178 IWL_FW_AND_PNVM(IWL_BZ_A_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX); 179 IWL_FW_AND_PNVM(IWL_BZ_A_FM4_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 180 IWL_FW_AND_PNVM(IWL_GL_B_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX); 181 IWL_FW_AND_PNVM(IWL_GL_C_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX); 182