1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2025 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_AX210_UCODE_API_MAX 89 14 15 /* Lowest firmware API version supported */ 16 #define IWL_AX210_UCODE_API_MIN 77 17 18 /* Memory offsets and lengths */ 19 #define IWL_AX210_SMEM_OFFSET 0x400000 20 #define IWL_AX210_SMEM_LEN 0xD0000 21 22 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0" 23 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0" 24 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0" 25 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0" 26 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0" 27 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0" 28 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0" 29 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0" 30 #define IWL_MA_B_HR_B_FW_PRE "iwlwifi-ma-b0-hr-b0" 31 #define IWL_MA_B_GF_A_FW_PRE "iwlwifi-ma-b0-gf-a0" 32 #define IWL_MA_B_GF4_A_FW_PRE "iwlwifi-ma-b0-gf4-a0" 33 34 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 35 IWL_SO_A_JF_B_FW_PRE "-" __stringify(api) ".ucode" 36 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 37 IWL_SO_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 38 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 39 IWL_MA_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 40 #define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api) \ 41 IWL_MA_B_HR_B_FW_PRE "-" __stringify(api) ".ucode" 42 43 static const struct iwl_family_base_params iwl_ax210_base = { 44 .num_of_queues = 512, 45 .max_tfd_queue_size = 65536, 46 .shadow_ram_support = true, 47 .led_compensation = 57, 48 .wd_timeout = IWL_LONG_WD_TIMEOUT, 49 .max_event_log_size = 512, 50 .shadow_reg_enable = true, 51 .pcie_l1_allowed = true, 52 .smem_offset = IWL_AX210_SMEM_OFFSET, 53 .smem_len = IWL_AX210_SMEM_LEN, 54 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 55 .apmg_not_supported = true, 56 .mac_addr_from_csr = 0x380, 57 .min_umac_error_event_table = 0x400000, 58 .d3_debug_data_base_addr = 0x401000, 59 .d3_debug_data_length = 60 * 1024, 60 .mon_smem_regs = { 61 .write_ptr = { 62 .addr = LDBG_M2S_BUF_WPTR, 63 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, 64 }, 65 .cycle_cnt = { 66 .addr = LDBG_M2S_BUF_WRAP_CNT, 67 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, 68 }, 69 }, 70 .min_txq_size = 128, 71 .gp2_reg_addr = 0xd02c68, 72 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, 73 .mon_dram_regs = { 74 .write_ptr = { 75 .addr = DBGC_CUR_DBGBUF_STATUS, 76 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, 77 }, 78 .cycle_cnt = { 79 .addr = DBGC_DBGBUF_WRAP_AROUND, 80 .mask = 0xffffffff, 81 }, 82 .cur_frag = { 83 .addr = DBGC_CUR_DBGBUF_STATUS, 84 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, 85 }, 86 }, 87 .ucode_api_min = IWL_AX210_UCODE_API_MIN, 88 .ucode_api_max = IWL_AX210_UCODE_API_MAX, 89 }; 90 91 const struct iwl_mac_cfg iwl_ty_mac_cfg = { 92 .mq_rx_supported = true, 93 .gen2 = true, 94 .device_family = IWL_DEVICE_FAMILY_AX210, 95 .base = &iwl_ax210_base, 96 .umac_prph_offset = 0x300000, 97 /* TODO: the following values need to be checked */ 98 .xtal_latency = 500, 99 }; 100 101 const struct iwl_mac_cfg iwl_so_mac_cfg = { 102 .mq_rx_supported = true, 103 .gen2 = true, 104 .device_family = IWL_DEVICE_FAMILY_AX210, 105 .base = &iwl_ax210_base, 106 .umac_prph_offset = 0x300000, 107 .integrated = true, 108 /* TODO: the following values need to be checked */ 109 .xtal_latency = 500, 110 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 111 }; 112 113 const struct iwl_mac_cfg iwl_so_long_latency_mac_cfg = { 114 .mq_rx_supported = true, 115 .gen2 = true, 116 .device_family = IWL_DEVICE_FAMILY_AX210, 117 .base = &iwl_ax210_base, 118 .umac_prph_offset = 0x300000, 119 .integrated = true, 120 .low_latency_xtal = true, 121 .xtal_latency = 12000, 122 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 123 }; 124 125 const struct iwl_mac_cfg iwl_so_long_latency_imr_mac_cfg = { 126 .mq_rx_supported = true, 127 .gen2 = true, 128 .device_family = IWL_DEVICE_FAMILY_AX210, 129 .base = &iwl_ax210_base, 130 .umac_prph_offset = 0x300000, 131 .integrated = true, 132 .low_latency_xtal = true, 133 .xtal_latency = 12000, 134 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 135 .imr_enabled = true, 136 }; 137 138 const struct iwl_mac_cfg iwl_ma_mac_cfg = { 139 .device_family = IWL_DEVICE_FAMILY_AX210, 140 .base = &iwl_ax210_base, 141 .mq_rx_supported = true, 142 .gen2 = true, 143 .integrated = true, 144 .umac_prph_offset = 0x300000 145 }; 146 147 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 148 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 149 IWL_FW_AND_PNVM(IWL_SO_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 150 IWL_FW_AND_PNVM(IWL_TY_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 151 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 152 IWL_FW_AND_PNVM(IWL_MA_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 153 IWL_FW_AND_PNVM(IWL_MA_A_GF4_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 154 MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 155 IWL_FW_AND_PNVM(IWL_MA_B_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 156 IWL_FW_AND_PNVM(IWL_MA_B_GF4_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 157