1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2025 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_AX210_UCODE_API_MAX 89 14 15 /* Lowest firmware API version supported */ 16 #define IWL_AX210_UCODE_API_MIN 89 17 18 /* Memory offsets and lengths */ 19 #define IWL_AX210_SMEM_OFFSET 0x400000 20 #define IWL_AX210_SMEM_LEN 0xD0000 21 22 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0" 23 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0" 24 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0" 25 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0" 26 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0" 27 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0" 28 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0" 29 #define IWL_MA_B_HR_B_FW_PRE "iwlwifi-ma-b0-hr-b0" 30 #define IWL_MA_B_GF_A_FW_PRE "iwlwifi-ma-b0-gf-a0" 31 #define IWL_MA_B_GF4_A_FW_PRE "iwlwifi-ma-b0-gf4-a0" 32 33 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 34 IWL_SO_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 35 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 36 IWL_MA_A_HR_B_FW_PRE "-" __stringify(api) ".ucode" 37 #define IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(api) \ 38 IWL_MA_B_HR_B_FW_PRE "-" __stringify(api) ".ucode" 39 40 static const struct iwl_family_base_params iwl_ax210_base = { 41 .num_of_queues = 512, 42 .max_tfd_queue_size = 65536, 43 .shadow_ram_support = true, 44 .led_compensation = 57, 45 .wd_timeout = IWL_LONG_WD_TIMEOUT, 46 .max_event_log_size = 512, 47 .shadow_reg_enable = true, 48 .pcie_l1_allowed = true, 49 .smem_offset = IWL_AX210_SMEM_OFFSET, 50 .smem_len = IWL_AX210_SMEM_LEN, 51 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 52 .apmg_not_supported = true, 53 .mac_addr_from_csr = 0x380, 54 .min_umac_error_event_table = 0x400000, 55 .d3_debug_data_base_addr = 0x401000, 56 .d3_debug_data_length = 60 * 1024, 57 .mon_smem_regs = { 58 .write_ptr = { 59 .addr = LDBG_M2S_BUF_WPTR, 60 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, 61 }, 62 .cycle_cnt = { 63 .addr = LDBG_M2S_BUF_WRAP_CNT, 64 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, 65 }, 66 }, 67 .min_txq_size = 128, 68 .gp2_reg_addr = 0xd02c68, 69 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, 70 .mon_dram_regs = { 71 .write_ptr = { 72 .addr = DBGC_CUR_DBGBUF_STATUS, 73 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, 74 }, 75 .cycle_cnt = { 76 .addr = DBGC_DBGBUF_WRAP_AROUND, 77 .mask = 0xffffffff, 78 }, 79 .cur_frag = { 80 .addr = DBGC_CUR_DBGBUF_STATUS, 81 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, 82 }, 83 }, 84 .ucode_api_min = IWL_AX210_UCODE_API_MIN, 85 .ucode_api_max = IWL_AX210_UCODE_API_MAX, 86 }; 87 88 const struct iwl_mac_cfg iwl_ty_mac_cfg = { 89 .mq_rx_supported = true, 90 .gen2 = true, 91 .device_family = IWL_DEVICE_FAMILY_AX210, 92 .base = &iwl_ax210_base, 93 .umac_prph_offset = 0x300000, 94 /* TODO: the following values need to be checked */ 95 .xtal_latency = 500, 96 }; 97 98 const struct iwl_mac_cfg iwl_so_mac_cfg = { 99 .mq_rx_supported = true, 100 .gen2 = true, 101 .device_family = IWL_DEVICE_FAMILY_AX210, 102 .base = &iwl_ax210_base, 103 .umac_prph_offset = 0x300000, 104 .integrated = true, 105 /* TODO: the following values need to be checked */ 106 .xtal_latency = 500, 107 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 108 }; 109 110 const struct iwl_mac_cfg iwl_so_long_latency_mac_cfg = { 111 .mq_rx_supported = true, 112 .gen2 = true, 113 .device_family = IWL_DEVICE_FAMILY_AX210, 114 .base = &iwl_ax210_base, 115 .umac_prph_offset = 0x300000, 116 .integrated = true, 117 .low_latency_xtal = true, 118 .xtal_latency = 12000, 119 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 120 }; 121 122 const struct iwl_mac_cfg iwl_so_long_latency_imr_mac_cfg = { 123 .mq_rx_supported = true, 124 .gen2 = true, 125 .device_family = IWL_DEVICE_FAMILY_AX210, 126 .base = &iwl_ax210_base, 127 .umac_prph_offset = 0x300000, 128 .integrated = true, 129 .low_latency_xtal = true, 130 .xtal_latency = 12000, 131 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 132 .imr_enabled = true, 133 }; 134 135 const struct iwl_mac_cfg iwl_ma_mac_cfg = { 136 .device_family = IWL_DEVICE_FAMILY_AX210, 137 .base = &iwl_ax210_base, 138 .mq_rx_supported = true, 139 .gen2 = true, 140 .integrated = true, 141 .umac_prph_offset = 0x300000 142 }; 143 144 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 145 IWL_FW_AND_PNVM(IWL_SO_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 146 IWL_FW_AND_PNVM(IWL_TY_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 147 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 148 IWL_FW_AND_PNVM(IWL_MA_A_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 149 IWL_FW_AND_PNVM(IWL_MA_A_GF4_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 150 MODULE_FIRMWARE(IWL_MA_B_HR_B_FW_MODULE_FIRMWARE(IWL_AX210_UCODE_API_MAX)); 151 IWL_FW_AND_PNVM(IWL_MA_B_GF_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 152 IWL_FW_AND_PNVM(IWL_MA_B_GF4_A_FW_PRE, IWL_AX210_UCODE_API_MAX); 153