1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 5 * 6 * Contact Information: 7 * Intel Linux Wireless <ilw@linux.intel.com> 8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 9 * 10 *****************************************************************************/ 11 #ifndef __il_core_h__ 12 #define __il_core_h__ 13 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> /* for struct pci_device_id */ 16 #include <linux/kernel.h> 17 #include <linux/leds.h> 18 #include <linux/wait.h> 19 #include <linux/io.h> 20 #include <net/mac80211.h> 21 #include <net/ieee80211_radiotap.h> 22 23 #include "commands.h" 24 #include "csr.h" 25 #include "prph.h" 26 27 struct il_host_cmd; 28 struct il_cmd; 29 struct il_tx_queue; 30 31 #define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a) 32 #define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a) 33 #define IL_WARN_ONCE(f, a...) dev_warn_once(&il->pci_dev->dev, f, ## a) 34 #define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a) 35 36 #define RX_QUEUE_SIZE 256 37 #define RX_QUEUE_MASK 255 38 #define RX_QUEUE_SIZE_LOG 8 39 40 /* 41 * RX related structures and functions 42 */ 43 #define RX_FREE_BUFFERS 64 44 #define RX_LOW_WATERMARK 8 45 46 #define U32_PAD(n) ((4-(n))&0x3) 47 48 /* CT-KILL constants */ 49 #define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */ 50 51 /* Default noise level to report when noise measurement is not available. 52 * This may be because we're: 53 * 1) Not associated (4965, no beacon stats being sent to driver) 54 * 2) Scanning (noise measurement does not apply to associated channel) 55 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) 56 * Use default noise value of -127 ... this is below the range of measurable 57 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. 58 * Also, -127 works better than 0 when averaging frames with/without 59 * noise info (e.g. averaging might be done in app); measured dBm values are 60 * always negative ... using a negative value as the default keeps all 61 * averages within an s8's (used in some apps) range of negative values. */ 62 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127) 63 64 /* 65 * RTS threshold here is total size [2347] minus 4 FCS bytes 66 * Per spec: 67 * a value of 0 means RTS on all data/management packets 68 * a value > max MSDU size means no RTS 69 * else RTS for data/management frames where MPDU is larger 70 * than RTS value. 71 */ 72 #define DEFAULT_RTS_THRESHOLD 2347U 73 #define MIN_RTS_THRESHOLD 0U 74 #define MAX_RTS_THRESHOLD 2347U 75 #define MAX_MSDU_SIZE 2304U 76 #define MAX_MPDU_SIZE 2346U 77 #define DEFAULT_BEACON_INTERVAL 100U 78 #define DEFAULT_SHORT_RETRY_LIMIT 7U 79 #define DEFAULT_LONG_RETRY_LIMIT 4U 80 81 struct il_rx_buf { 82 dma_addr_t page_dma; 83 struct page *page; 84 struct list_head list; 85 }; 86 87 #define rxb_addr(r) page_address(r->page) 88 89 /* defined below */ 90 struct il_device_cmd; 91 92 struct il_cmd_meta { 93 /* only for SYNC commands, iff the reply skb is wanted */ 94 struct il_host_cmd *source; 95 /* 96 * only for ASYNC commands 97 * (which is somewhat stupid -- look at common.c for instance 98 * which duplicates a bunch of code because the callback isn't 99 * invoked for SYNC commands, if it were and its result passed 100 * through it would be simpler...) 101 */ 102 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd, 103 struct il_rx_pkt *pkt); 104 105 /* The CMD_SIZE_HUGE flag bit indicates that the command 106 * structure is stored at the end of the shared queue memory. */ 107 u32 flags; 108 109 DEFINE_DMA_UNMAP_ADDR(mapping); 110 DEFINE_DMA_UNMAP_LEN(len); 111 }; 112 113 /* 114 * Generic queue structure 115 * 116 * Contains common data for Rx and Tx queues 117 */ 118 struct il_queue { 119 int n_bd; /* number of BDs in this queue */ 120 int write_ptr; /* 1-st empty entry (idx) host_w */ 121 int read_ptr; /* last used entry (idx) host_r */ 122 /* use for monitoring and recovering the stuck queue */ 123 dma_addr_t dma_addr; /* physical addr for BD's */ 124 int n_win; /* safe queue win */ 125 u32 id; 126 int low_mark; /* low watermark, resume queue if free 127 * space more than this */ 128 int high_mark; /* high watermark, stop queue if free 129 * space less than this */ 130 }; 131 132 /** 133 * struct il_tx_queue - Tx Queue for DMA 134 * @q: generic Rx/Tx queue descriptor 135 * @bd: base of circular buffer of TFDs 136 * @cmd: array of command/TX buffer pointers 137 * @meta: array of meta data for each command/tx buffer 138 * @dma_addr_cmd: physical address of cmd/tx buffer array 139 * @skbs: array of per-TFD socket buffer pointers 140 * @time_stamp: time (in jiffies) of last read_ptr change 141 * @need_update: indicates need to update read/write idx 142 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled 143 * 144 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 145 * descriptors) and required locking structures. 146 */ 147 #define TFD_TX_CMD_SLOTS 256 148 #define TFD_CMD_SLOTS 32 149 150 struct il_tx_queue { 151 struct il_queue q; 152 void *tfds; 153 struct il_device_cmd **cmd; 154 struct il_cmd_meta *meta; 155 struct sk_buff **skbs; 156 unsigned long time_stamp; 157 u8 need_update; 158 u8 sched_retry; 159 u8 active; 160 u8 swq_id; 161 }; 162 163 /* 164 * EEPROM access time values: 165 * 166 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. 167 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). 168 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. 169 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. 170 */ 171 #define IL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 172 173 #define IL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ 174 #define IL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 175 176 /* 177 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags. 178 * 179 * IBSS and/or AP operation is allowed *only* on those channels with 180 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because 181 * RADAR detection is not supported by the 4965 driver, but is a 182 * requirement for establishing a new network for legal operation on channels 183 * requiring RADAR detection or restricting ACTIVE scanning. 184 * 185 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels. 186 * It only indicates that 20 MHz channel use is supported; HT40 channel 187 * usage is indicated by a separate set of regulatory flags for each 188 * HT40 channel pair. 189 * 190 * NOTE: Using a channel inappropriately will result in a uCode error! 191 */ 192 #define IL_NUM_TX_CALIB_GROUPS 5 193 enum { 194 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ 195 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ 196 /* Bit 2 Reserved */ 197 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ 198 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ 199 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ 200 /* Bit 6 Reserved (was Narrow Channel) */ 201 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ 202 }; 203 204 /* SKU Capabilities */ 205 /* 3945 only */ 206 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) 207 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) 208 209 /* *regulatory* channel data format in eeprom, one for each channel. 210 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */ 211 struct il_eeprom_channel { 212 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ 213 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ 214 } __packed; 215 216 /* 3945 Specific */ 217 #define EEPROM_3945_EEPROM_VERSION (0x2f) 218 219 /* 4965 has two radio transmitters (and 3 radio receivers) */ 220 #define EEPROM_TX_POWER_TX_CHAINS (2) 221 222 /* 4965 has room for up to 8 sets of txpower calibration data */ 223 #define EEPROM_TX_POWER_BANDS (8) 224 225 /* 4965 factory calibration measures txpower gain settings for 226 * each of 3 target output levels */ 227 #define EEPROM_TX_POWER_MEASUREMENTS (3) 228 229 /* 4965 Specific */ 230 /* 4965 driver does not work with txpower calibration version < 5 */ 231 #define EEPROM_4965_TX_POWER_VERSION (5) 232 #define EEPROM_4965_EEPROM_VERSION (0x2f) 233 #define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */ 234 #define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */ 235 #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */ 236 #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */ 237 238 /* 2.4 GHz */ 239 extern const u8 il_eeprom_band_1[14]; 240 241 /* 242 * factory calibration data for one txpower level, on one channel, 243 * measured on one of the 2 tx chains (radio transmitter and associated 244 * antenna). EEPROM contains: 245 * 246 * 1) Temperature (degrees Celsius) of device when measurement was made. 247 * 248 * 2) Gain table idx used to achieve the target measurement power. 249 * This refers to the "well-known" gain tables (see 4965.h). 250 * 251 * 3) Actual measured output power, in half-dBm ("34" = 17 dBm). 252 * 253 * 4) RF power amplifier detector level measurement (not used). 254 */ 255 struct il_eeprom_calib_measure { 256 u8 temperature; /* Device temperature (Celsius) */ 257 u8 gain_idx; /* Index into gain table */ 258 u8 actual_pow; /* Measured RF output power, half-dBm */ 259 s8 pa_det; /* Power amp detector level (not used) */ 260 } __packed; 261 262 /* 263 * measurement set for one channel. EEPROM contains: 264 * 265 * 1) Channel number measured 266 * 267 * 2) Measurements for each of 3 power levels for each of 2 radio transmitters 268 * (a.k.a. "tx chains") (6 measurements altogether) 269 */ 270 struct il_eeprom_calib_ch_info { 271 u8 ch_num; 272 struct il_eeprom_calib_measure 273 measurements[EEPROM_TX_POWER_TX_CHAINS] 274 [EEPROM_TX_POWER_MEASUREMENTS]; 275 } __packed; 276 277 /* 278 * txpower subband info. 279 * 280 * For each frequency subband, EEPROM contains the following: 281 * 282 * 1) First and last channels within range of the subband. "0" values 283 * indicate that this sample set is not being used. 284 * 285 * 2) Sample measurement sets for 2 channels close to the range endpoints. 286 */ 287 struct il_eeprom_calib_subband_info { 288 u8 ch_from; /* channel number of lowest channel in subband */ 289 u8 ch_to; /* channel number of highest channel in subband */ 290 struct il_eeprom_calib_ch_info ch1; 291 struct il_eeprom_calib_ch_info ch2; 292 } __packed; 293 294 /* 295 * txpower calibration info. EEPROM contains: 296 * 297 * 1) Factory-measured saturation power levels (maximum levels at which 298 * tx power amplifier can output a signal without too much distortion). 299 * There is one level for 2.4 GHz band and one for 5 GHz band. These 300 * values apply to all channels within each of the bands. 301 * 302 * 2) Factory-measured power supply voltage level. This is assumed to be 303 * constant (i.e. same value applies to all channels/bands) while the 304 * factory measurements are being made. 305 * 306 * 3) Up to 8 sets of factory-measured txpower calibration values. 307 * These are for different frequency ranges, since txpower gain 308 * characteristics of the analog radio circuitry vary with frequency. 309 * 310 * Not all sets need to be filled with data; 311 * struct il_eeprom_calib_subband_info contains range of channels 312 * (0 if unused) for each set of data. 313 */ 314 struct il_eeprom_calib_info { 315 u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */ 316 u8 saturation_power52; /* half-dBm */ 317 __le16 voltage; /* signed */ 318 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS]; 319 } __packed; 320 321 /* General */ 322 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ 323 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ 324 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ 325 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ 326 #define EEPROM_VERSION (2*0x44) /* 2 bytes */ 327 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ 328 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ 329 #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */ 330 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ 331 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ 332 333 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */ 334 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ 335 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 336 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 337 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 338 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 339 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 340 341 #define EEPROM_3945_RF_CFG_TYPE_MAX 0x0 342 #define EEPROM_4965_RF_CFG_TYPE_MAX 0x1 343 344 /* 345 * Per-channel regulatory data. 346 * 347 * Each channel that *might* be supported by iwl has a fixed location 348 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory 349 * txpower (MSB). 350 * 351 * Entries immediately below are for 20 MHz channel width. HT40 (40 MHz) 352 * channels (only for 4965, not supported by 3945) appear later in the EEPROM. 353 * 354 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 355 */ 356 #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ 357 #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ 358 #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ 359 360 /* 361 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, 362 * 5.0 GHz channels 7, 8, 11, 12, 16 363 * (4915-5080MHz) (none of these is ever supported) 364 */ 365 #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ 366 #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ 367 368 /* 369 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 370 * (5170-5320MHz) 371 */ 372 #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ 373 #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ 374 375 /* 376 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 377 * (5500-5700MHz) 378 */ 379 #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ 380 #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ 381 382 /* 383 * 5.7 GHz channels 145, 149, 153, 157, 161, 165 384 * (5725-5825MHz) 385 */ 386 #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ 387 #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ 388 389 /* 390 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11) 391 * 392 * The channel listed is the center of the lower 20 MHz half of the channel. 393 * The overall center frequency is actually 2 channels (10 MHz) above that, 394 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away 395 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5, 396 * and the overall HT40 channel width centers on channel 3. 397 * 398 * NOTE: The RXON command uses 20 MHz channel numbers to specify the 399 * control channel to which to tune. RXON also specifies whether the 400 * control channel is the upper or lower half of a HT40 channel. 401 * 402 * NOTE: 4965 does not support HT40 channels on 2.4 GHz. 403 */ 404 #define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0) /* 14 bytes */ 405 406 /* 407 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64), 408 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161) 409 */ 410 #define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8) /* 22 bytes */ 411 412 #define EEPROM_REGULATORY_BAND_NO_HT40 (0) 413 414 int il_eeprom_init(struct il_priv *il); 415 void il_eeprom_free(struct il_priv *il); 416 const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset); 417 u16 il_eeprom_query16(const struct il_priv *il, size_t offset); 418 int il_init_channel_map(struct il_priv *il); 419 void il_free_channel_map(struct il_priv *il); 420 const struct il_channel_info *il_get_channel_info(const struct il_priv *il, 421 enum nl80211_band band, 422 u16 channel); 423 424 #define IL_NUM_SCAN_RATES (2) 425 426 struct il4965_channel_tgd_info { 427 u8 type; 428 s8 max_power; 429 }; 430 431 struct il4965_channel_tgh_info { 432 s64 last_radar_time; 433 }; 434 435 #define IL4965_MAX_RATE (33) 436 437 struct il3945_clip_group { 438 /* maximum power level to prevent clipping for each rate, derived by 439 * us from this band's saturation power in EEPROM */ 440 const s8 clip_powers[IL_MAX_RATES]; 441 }; 442 443 /* current Tx power values to use, one for each rate for each channel. 444 * requested power is limited by: 445 * -- regulatory EEPROM limits for this channel 446 * -- hardware capabilities (clip-powers) 447 * -- spectrum management 448 * -- user preference (e.g. iwconfig) 449 * when requested power is set, base power idx must also be set. */ 450 struct il3945_channel_power_info { 451 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */ 452 s8 power_table_idx; /* actual (compenst'd) idx into gain table */ 453 s8 base_power_idx; /* gain idx for power at factory temp. */ 454 s8 requested_power; /* power (dBm) requested for this chnl/rate */ 455 }; 456 457 /* current scan Tx power values to use, one for each scan rate for each 458 * channel. */ 459 struct il3945_scan_power_info { 460 struct il3945_tx_power tpc; /* actual radio and DSP gain settings */ 461 s8 power_table_idx; /* actual (compenst'd) idx into gain table */ 462 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */ 463 }; 464 465 /* 466 * One for each channel, holds all channel setup data 467 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant 468 * with one another! 469 */ 470 struct il_channel_info { 471 struct il4965_channel_tgd_info tgd; 472 struct il4965_channel_tgh_info tgh; 473 struct il_eeprom_channel eeprom; /* EEPROM regulatory limit */ 474 struct il_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for 475 * HT40 channel */ 476 477 u8 channel; /* channel number */ 478 u8 flags; /* flags copied from EEPROM */ 479 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ 480 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */ 481 s8 min_power; /* always 0 */ 482 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */ 483 484 u8 group_idx; /* 0-4, maps channel to group1/2/3/4/5 */ 485 u8 band_idx; /* 0-4, maps channel to band1/2/3/4/5 */ 486 enum nl80211_band band; 487 488 /* HT40 channel info */ 489 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */ 490 u8 ht40_flags; /* flags copied from EEPROM */ 491 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */ 492 493 /* Radio/DSP gain settings for each "normal" data Tx rate. 494 * These include, in addition to RF and DSP gain, a few fields for 495 * remembering/modifying gain settings (idxes). */ 496 struct il3945_channel_power_info power_info[IL4965_MAX_RATE]; 497 498 /* Radio/DSP gain settings for each scan rate, for directed scans. */ 499 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES]; 500 }; 501 502 #define IL_TX_FIFO_BK 0 /* shared */ 503 #define IL_TX_FIFO_BE 1 504 #define IL_TX_FIFO_VI 2 /* shared */ 505 #define IL_TX_FIFO_VO 3 506 #define IL_TX_FIFO_UNUSED -1 507 508 /* Minimum number of queues. MAX_NUM is defined in hw specific files. 509 * Set the minimum to accommodate the 4 standard TX queues, 1 command 510 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */ 511 #define IL_MIN_NUM_QUEUES 10 512 513 #define IL_DEFAULT_CMD_QUEUE_NUM 4 514 515 #define IEEE80211_DATA_LEN 2304 516 #define IEEE80211_4ADDR_LEN 30 517 #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) 518 #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) 519 520 struct il_frame { 521 union { 522 struct ieee80211_hdr frame; 523 struct il_tx_beacon_cmd beacon; 524 u8 raw[IEEE80211_FRAME_LEN]; 525 u8 cmd[360]; 526 } u; 527 struct list_head list; 528 }; 529 530 enum { 531 CMD_SYNC = 0, 532 CMD_SIZE_NORMAL = 0, 533 CMD_NO_SKB = 0, 534 CMD_SIZE_HUGE = (1 << 0), 535 CMD_ASYNC = (1 << 1), 536 CMD_WANT_SKB = (1 << 2), 537 CMD_MAPPED = (1 << 3), 538 }; 539 540 #define DEF_CMD_PAYLOAD_SIZE 320 541 542 /** 543 * struct il_device_cmd 544 * 545 * For allocation of the command and tx queues, this establishes the overall 546 * size of the largest command we send to uCode, except for a scan command 547 * (which is relatively huge; space is allocated separately). 548 */ 549 struct il_device_cmd { 550 struct il_cmd_header hdr; /* uCode API */ 551 union { 552 u32 flags; 553 u8 val8; 554 u16 val16; 555 u32 val32; 556 struct il_tx_cmd_hdr tx; 557 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 558 } __packed cmd; 559 } __packed; 560 561 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd)) 562 563 /** 564 * struct il_device_cmd_huge 565 * 566 * For use when sending huge commands. 567 */ 568 struct il_device_cmd_huge { 569 struct il_cmd_header hdr; /* uCode API */ 570 union { 571 u8 payload[IL_MAX_CMD_SIZE - sizeof(struct il_cmd_header)]; 572 } __packed cmd; 573 } __packed; 574 575 struct il_host_cmd { 576 const void *data; 577 unsigned long reply_page; 578 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd, 579 struct il_rx_pkt *pkt); 580 u32 flags; 581 u16 len; 582 u8 id; 583 }; 584 585 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 586 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 587 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 588 589 /** 590 * struct il_rx_queue - Rx queue 591 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) 592 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 593 * @read: Shared idx to newest available Rx buffer 594 * @write: Shared idx to oldest written Rx packet 595 * @free_count: Number of pre-allocated buffers in rx_free 596 * @rx_free: list of free SKBs for use 597 * @rx_used: List of Rx buffers with no SKB 598 * @need_update: flag to indicate we need to update read/write idx 599 * @rb_stts: driver's pointer to receive buffer status 600 * @rb_stts_dma: bus address of receive buffer status 601 * 602 * NOTE: rx_free and rx_used are used as a FIFO for il_rx_bufs 603 */ 604 struct il_rx_queue { 605 __le32 *bd; 606 dma_addr_t bd_dma; 607 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; 608 struct il_rx_buf *queue[RX_QUEUE_SIZE]; 609 u32 read; 610 u32 write; 611 u32 free_count; 612 u32 write_actual; 613 struct list_head rx_free; 614 struct list_head rx_used; 615 int need_update; 616 struct il_rb_status *rb_stts; 617 dma_addr_t rb_stts_dma; 618 spinlock_t lock; 619 }; 620 621 #define IL_SUPPORTED_RATES_IE_LEN 8 622 623 #define MAX_TID_COUNT 9 624 625 #define IL_INVALID_RATE 0xFF 626 #define IL_INVALID_VALUE -1 627 628 /** 629 * struct il_ht_agg -- aggregation status while waiting for block-ack 630 * @txq_id: Tx queue used for Tx attempt 631 * @frame_count: # frames attempted by Tx command 632 * @wait_for_ba: Expect block-ack before next Tx reply 633 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win 634 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win 635 * @bitmap1: High order, one bit for each frame pending ACK in Tx win 636 * @rate_n_flags: Rate at which Tx was attempted 637 * 638 * If C_TX indicates that aggregation was attempted, driver must wait 639 * for block ack (N_COMPRESSED_BA). This struct stores tx reply info 640 * until block ack arrives. 641 */ 642 struct il_ht_agg { 643 u16 txq_id; 644 u16 frame_count; 645 u16 wait_for_ba; 646 u16 start_idx; 647 u64 bitmap; 648 u32 rate_n_flags; 649 #define IL_AGG_OFF 0 650 #define IL_AGG_ON 1 651 #define IL_EMPTYING_HW_QUEUE_ADDBA 2 652 #define IL_EMPTYING_HW_QUEUE_DELBA 3 653 u8 state; 654 }; 655 656 struct il_tid_data { 657 u16 seq_number; /* 4965 only */ 658 u16 tfds_in_queue; 659 struct il_ht_agg agg; 660 }; 661 662 struct il_hw_key { 663 u32 cipher; 664 int keylen; 665 u8 keyidx; 666 u8 key[32]; 667 }; 668 669 union il_ht_rate_supp { 670 u16 rates; 671 struct { 672 u8 siso_rate; 673 u8 mimo_rate; 674 }; 675 }; 676 677 #define CFG_HT_RX_AMPDU_FACTOR_8K (0x0) 678 #define CFG_HT_RX_AMPDU_FACTOR_16K (0x1) 679 #define CFG_HT_RX_AMPDU_FACTOR_32K (0x2) 680 #define CFG_HT_RX_AMPDU_FACTOR_64K (0x3) 681 #define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K 682 #define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K 683 #define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K 684 685 /* 686 * Maximal MPDU density for TX aggregation 687 * 4 - 2us density 688 * 5 - 4us density 689 * 6 - 8us density 690 * 7 - 16us density 691 */ 692 #define CFG_HT_MPDU_DENSITY_2USEC (0x4) 693 #define CFG_HT_MPDU_DENSITY_4USEC (0x5) 694 #define CFG_HT_MPDU_DENSITY_8USEC (0x6) 695 #define CFG_HT_MPDU_DENSITY_16USEC (0x7) 696 #define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC 697 #define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC 698 #define CFG_HT_MPDU_DENSITY_MIN (0x1) 699 700 struct il_ht_config { 701 bool single_chain_sufficient; 702 enum ieee80211_smps_mode smps; /* current smps mode */ 703 }; 704 705 /* QoS structures */ 706 struct il_qos_info { 707 int qos_active; 708 struct il_qosparam_cmd def_qos_parm; 709 }; 710 711 /* 712 * Structure should be accessed with sta_lock held. When station addition 713 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only 714 * the commands (il_addsta_cmd and il_link_quality_cmd) without 715 * sta_lock held. 716 */ 717 struct il_station_entry { 718 struct il_addsta_cmd sta; 719 struct il_tid_data tid[MAX_TID_COUNT]; 720 u8 used; 721 struct il_hw_key keyinfo; 722 struct il_link_quality_cmd *lq; 723 }; 724 725 struct il_station_priv_common { 726 u8 sta_id; 727 }; 728 729 /** 730 * struct il_vif_priv - driver's ilate per-interface information 731 * 732 * When mac80211 allocates a virtual interface, it can allocate 733 * space for us to put data into. 734 */ 735 struct il_vif_priv { 736 u8 ibss_bssid_sta_id; 737 }; 738 739 /* one for each uCode image (inst/data, boot/init/runtime) */ 740 struct fw_desc { 741 void *v_addr; /* access by driver */ 742 dma_addr_t p_addr; /* access by card's busmaster DMA */ 743 u32 len; /* bytes */ 744 }; 745 746 /* uCode file layout */ 747 struct il_ucode_header { 748 __le32 ver; /* major/minor/API/serial */ 749 struct { 750 __le32 inst_size; /* bytes of runtime code */ 751 __le32 data_size; /* bytes of runtime data */ 752 __le32 init_size; /* bytes of init code */ 753 __le32 init_data_size; /* bytes of init data */ 754 __le32 boot_size; /* bytes of bootstrap code */ 755 u8 data[0]; /* in same order as sizes */ 756 } v1; 757 }; 758 759 struct il4965_ibss_seq { 760 u8 mac[ETH_ALEN]; 761 u16 seq_num; 762 u16 frag_num; 763 unsigned long packet_time; 764 struct list_head list; 765 }; 766 767 struct il_sensitivity_ranges { 768 u16 min_nrg_cck; 769 u16 max_nrg_cck; 770 771 u16 nrg_th_cck; 772 u16 nrg_th_ofdm; 773 774 u16 auto_corr_min_ofdm; 775 u16 auto_corr_min_ofdm_mrc; 776 u16 auto_corr_min_ofdm_x1; 777 u16 auto_corr_min_ofdm_mrc_x1; 778 779 u16 auto_corr_max_ofdm; 780 u16 auto_corr_max_ofdm_mrc; 781 u16 auto_corr_max_ofdm_x1; 782 u16 auto_corr_max_ofdm_mrc_x1; 783 784 u16 auto_corr_max_cck; 785 u16 auto_corr_max_cck_mrc; 786 u16 auto_corr_min_cck; 787 u16 auto_corr_min_cck_mrc; 788 789 u16 barker_corr_th_min; 790 u16 barker_corr_th_min_mrc; 791 u16 nrg_th_cca; 792 }; 793 794 /** 795 * struct il_hw_params 796 * @bcast_id: f/w broadcast station ID 797 * @max_txq_num: Max # Tx queues supported 798 * @dma_chnl_num: Number of Tx DMA/FIFO channels 799 * @scd_bc_tbls_size: size of scheduler byte count tables 800 * @tfd_size: TFD size 801 * @tx/rx_chains_num: Number of TX/RX chains 802 * @valid_tx/rx_ant: usable antennas 803 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2) 804 * @max_rxq_log: Log-base-2 of max_rxq_size 805 * @rx_page_order: Rx buffer page order 806 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR 807 * @max_stations: 808 * @ht40_channel: is 40MHz width possible in band 2.4 809 * BIT(NL80211_BAND_5GHZ) BIT(NL80211_BAND_5GHZ) 810 * @sw_crypto: 0 for hw, 1 for sw 811 * @max_xxx_size: for ucode uses 812 * @ct_kill_threshold: temperature threshold 813 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time 814 * @struct il_sensitivity_ranges: range of sensitivity values 815 */ 816 struct il_hw_params { 817 u8 bcast_id; 818 u8 max_txq_num; 819 u8 dma_chnl_num; 820 u16 scd_bc_tbls_size; 821 u32 tfd_size; 822 u8 tx_chains_num; 823 u8 rx_chains_num; 824 u8 valid_tx_ant; 825 u8 valid_rx_ant; 826 u16 max_rxq_size; 827 u16 max_rxq_log; 828 u32 rx_page_order; 829 u32 rx_wrt_ptr_reg; 830 u8 max_stations; 831 u8 ht40_channel; 832 u8 max_beacon_itrvl; /* in 1024 ms */ 833 u32 max_inst_size; 834 u32 max_data_size; 835 u32 max_bsm_size; 836 u32 ct_kill_threshold; /* value in hw-dependent units */ 837 u16 beacon_time_tsf_bits; 838 const struct il_sensitivity_ranges *sens; 839 }; 840 841 /****************************************************************************** 842 * 843 * Functions implemented in core module which are forward declared here 844 * for use by iwl-[4-5].c 845 * 846 * NOTE: The implementation of these functions are not hardware specific 847 * which is why they are in the core module files. 848 * 849 * Naming convention -- 850 * il_ <-- Is part of iwlwifi 851 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) 852 * il4965_bg_ <-- Called from work queue context 853 * il4965_mac_ <-- mac80211 callback 854 * 855 ****************************************************************************/ 856 void il4965_update_chain_flags(struct il_priv *il); 857 extern const u8 il_bcast_addr[ETH_ALEN]; 858 int il_queue_space(const struct il_queue *q); 859 static inline int 860 il_queue_used(const struct il_queue *q, int i) 861 { 862 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr && 863 i < q->write_ptr) : !(i < 864 q->read_ptr 865 && i >= 866 q-> 867 write_ptr); 868 } 869 870 static inline u8 871 il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge) 872 { 873 /* 874 * This is for init calibration result and scan command which 875 * required buffer > TFD_MAX_PAYLOAD_SIZE, 876 * the big buffer at end of command array 877 */ 878 if (is_huge) 879 return q->n_win; /* must be power of 2 */ 880 881 /* Otherwise, use normal size buffers */ 882 return idx & (q->n_win - 1); 883 } 884 885 struct il_dma_ptr { 886 dma_addr_t dma; 887 void *addr; 888 size_t size; 889 }; 890 891 #define IL_OPERATION_MODE_AUTO 0 892 #define IL_OPERATION_MODE_HT_ONLY 1 893 #define IL_OPERATION_MODE_MIXED 2 894 #define IL_OPERATION_MODE_20MHZ 3 895 896 #define IL_TX_CRC_SIZE 4 897 #define IL_TX_DELIMITER_SIZE 4 898 899 #define TX_POWER_IL_ILLEGAL_VOLTAGE -10000 900 901 /* Sensitivity and chain noise calibration */ 902 #define INITIALIZATION_VALUE 0xFFFF 903 #define IL4965_CAL_NUM_BEACONS 20 904 #define IL_CAL_NUM_BEACONS 16 905 #define MAXIMUM_ALLOWED_PATHLOSS 15 906 907 #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 908 909 #define MAX_FA_OFDM 50 910 #define MIN_FA_OFDM 5 911 #define MAX_FA_CCK 50 912 #define MIN_FA_CCK 5 913 914 #define AUTO_CORR_STEP_OFDM 1 915 916 #define AUTO_CORR_STEP_CCK 3 917 #define AUTO_CORR_MAX_TH_CCK 160 918 919 #define NRG_DIFF 2 920 #define NRG_STEP_CCK 2 921 #define NRG_MARGIN 8 922 #define MAX_NUMBER_CCK_NO_FA 100 923 924 #define AUTO_CORR_CCK_MIN_VAL_DEF (125) 925 926 #define CHAIN_A 0 927 #define CHAIN_B 1 928 #define CHAIN_C 2 929 #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 930 #define ALL_BAND_FILTER 0xFF00 931 #define IN_BAND_FILTER 0xFF 932 #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF 933 934 #define NRG_NUM_PREV_STAT_L 20 935 #define NUM_RX_CHAINS 3 936 937 enum il4965_false_alarm_state { 938 IL_FA_TOO_MANY = 0, 939 IL_FA_TOO_FEW = 1, 940 IL_FA_GOOD_RANGE = 2, 941 }; 942 943 enum il4965_chain_noise_state { 944 IL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ 945 IL_CHAIN_NOISE_ACCUMULATE, 946 IL_CHAIN_NOISE_CALIBRATED, 947 IL_CHAIN_NOISE_DONE, 948 }; 949 950 enum ucode_type { 951 UCODE_NONE = 0, 952 UCODE_INIT, 953 UCODE_RT 954 }; 955 956 /* Sensitivity calib data */ 957 struct il_sensitivity_data { 958 u32 auto_corr_ofdm; 959 u32 auto_corr_ofdm_mrc; 960 u32 auto_corr_ofdm_x1; 961 u32 auto_corr_ofdm_mrc_x1; 962 u32 auto_corr_cck; 963 u32 auto_corr_cck_mrc; 964 965 u32 last_bad_plcp_cnt_ofdm; 966 u32 last_fa_cnt_ofdm; 967 u32 last_bad_plcp_cnt_cck; 968 u32 last_fa_cnt_cck; 969 970 u32 nrg_curr_state; 971 u32 nrg_prev_state; 972 u32 nrg_value[10]; 973 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; 974 u32 nrg_silence_ref; 975 u32 nrg_energy_idx; 976 u32 nrg_silence_idx; 977 u32 nrg_th_cck; 978 s32 nrg_auto_corr_silence_diff; 979 u32 num_in_cck_no_fa; 980 u32 nrg_th_ofdm; 981 982 u16 barker_corr_th_min; 983 u16 barker_corr_th_min_mrc; 984 u16 nrg_th_cca; 985 }; 986 987 /* Chain noise (differential Rx gain) calib data */ 988 struct il_chain_noise_data { 989 u32 active_chains; 990 u32 chain_noise_a; 991 u32 chain_noise_b; 992 u32 chain_noise_c; 993 u32 chain_signal_a; 994 u32 chain_signal_b; 995 u32 chain_signal_c; 996 u16 beacon_count; 997 u8 disconn_array[NUM_RX_CHAINS]; 998 u8 delta_gain_code[NUM_RX_CHAINS]; 999 u8 radio_write; 1000 u8 state; 1001 }; 1002 1003 #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */ 1004 #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 1005 1006 #define IL_TRAFFIC_ENTRIES (256) 1007 #define IL_TRAFFIC_ENTRY_SIZE (64) 1008 1009 enum { 1010 MEASUREMENT_READY = (1 << 0), 1011 MEASUREMENT_ACTIVE = (1 << 1), 1012 }; 1013 1014 /* interrupt stats */ 1015 struct isr_stats { 1016 u32 hw; 1017 u32 sw; 1018 u32 err_code; 1019 u32 sch; 1020 u32 alive; 1021 u32 rfkill; 1022 u32 ctkill; 1023 u32 wakeup; 1024 u32 rx; 1025 u32 handlers[IL_CN_MAX]; 1026 u32 tx; 1027 u32 unhandled; 1028 }; 1029 1030 /* management stats */ 1031 enum il_mgmt_stats { 1032 MANAGEMENT_ASSOC_REQ = 0, 1033 MANAGEMENT_ASSOC_RESP, 1034 MANAGEMENT_REASSOC_REQ, 1035 MANAGEMENT_REASSOC_RESP, 1036 MANAGEMENT_PROBE_REQ, 1037 MANAGEMENT_PROBE_RESP, 1038 MANAGEMENT_BEACON, 1039 MANAGEMENT_ATIM, 1040 MANAGEMENT_DISASSOC, 1041 MANAGEMENT_AUTH, 1042 MANAGEMENT_DEAUTH, 1043 MANAGEMENT_ACTION, 1044 MANAGEMENT_MAX, 1045 }; 1046 /* control stats */ 1047 enum il_ctrl_stats { 1048 CONTROL_BACK_REQ = 0, 1049 CONTROL_BACK, 1050 CONTROL_PSPOLL, 1051 CONTROL_RTS, 1052 CONTROL_CTS, 1053 CONTROL_ACK, 1054 CONTROL_CFEND, 1055 CONTROL_CFENDACK, 1056 CONTROL_MAX, 1057 }; 1058 1059 struct traffic_stats { 1060 #ifdef CONFIG_IWLEGACY_DEBUGFS 1061 u32 mgmt[MANAGEMENT_MAX]; 1062 u32 ctrl[CONTROL_MAX]; 1063 u32 data_cnt; 1064 u64 data_bytes; 1065 #endif 1066 }; 1067 1068 /* 1069 * host interrupt timeout value 1070 * used with setting interrupt coalescing timer 1071 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 1072 * 1073 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 1074 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs 1075 */ 1076 #define IL_HOST_INT_TIMEOUT_MAX (0xFF) 1077 #define IL_HOST_INT_TIMEOUT_DEF (0x40) 1078 #define IL_HOST_INT_TIMEOUT_MIN (0x0) 1079 #define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) 1080 #define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) 1081 #define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) 1082 1083 #define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5) 1084 1085 /* TX queue watchdog timeouts in mSecs */ 1086 #define IL_DEF_WD_TIMEOUT (2000) 1087 #define IL_LONG_WD_TIMEOUT (10000) 1088 #define IL_MAX_WD_TIMEOUT (120000) 1089 1090 struct il_force_reset { 1091 int reset_request_count; 1092 int reset_success_count; 1093 int reset_reject_count; 1094 unsigned long reset_duration; 1095 unsigned long last_force_reset_jiffies; 1096 }; 1097 1098 /* extend beacon time format bit shifting */ 1099 /* 1100 * for _3945 devices 1101 * bits 31:24 - extended 1102 * bits 23:0 - interval 1103 */ 1104 #define IL3945_EXT_BEACON_TIME_POS 24 1105 /* 1106 * for _4965 devices 1107 * bits 31:22 - extended 1108 * bits 21:0 - interval 1109 */ 1110 #define IL4965_EXT_BEACON_TIME_POS 22 1111 1112 struct il_rxon_context { 1113 struct ieee80211_vif *vif; 1114 }; 1115 1116 struct il_power_mgr { 1117 struct il_powertable_cmd sleep_cmd; 1118 struct il_powertable_cmd sleep_cmd_next; 1119 int debug_sleep_level_override; 1120 bool pci_pm; 1121 bool ps_disabled; 1122 }; 1123 1124 struct il_priv { 1125 struct ieee80211_hw *hw; 1126 struct ieee80211_channel *ieee_channels; 1127 struct ieee80211_rate *ieee_rates; 1128 1129 struct il_cfg *cfg; 1130 const struct il_ops *ops; 1131 #ifdef CONFIG_IWLEGACY_DEBUGFS 1132 const struct il_debugfs_ops *debugfs_ops; 1133 #endif 1134 1135 /* temporary frame storage list */ 1136 struct list_head free_frames; 1137 int frames_count; 1138 1139 enum nl80211_band band; 1140 int alloc_rxb_page; 1141 1142 void (*handlers[IL_CN_MAX]) (struct il_priv *il, 1143 struct il_rx_buf *rxb); 1144 1145 struct ieee80211_supported_band bands[NUM_NL80211_BANDS]; 1146 1147 /* spectrum measurement report caching */ 1148 struct il_spectrum_notification measure_report; 1149 u8 measurement_status; 1150 1151 /* ucode beacon time */ 1152 u32 ucode_beacon_time; 1153 int missed_beacon_threshold; 1154 1155 /* track IBSS manager (last beacon) status */ 1156 u32 ibss_manager; 1157 1158 /* force reset */ 1159 struct il_force_reset force_reset; 1160 1161 /* we allocate array of il_channel_info for NIC's valid channels. 1162 * Access via channel # using indirect idx array */ 1163 struct il_channel_info *channel_info; /* channel info array */ 1164 u8 channel_count; /* # of channels */ 1165 1166 /* thermal calibration */ 1167 s32 temperature; /* degrees Kelvin */ 1168 s32 last_temperature; 1169 1170 /* Scan related variables */ 1171 unsigned long scan_start; 1172 unsigned long scan_start_tsf; 1173 void *scan_cmd; 1174 enum nl80211_band scan_band; 1175 struct cfg80211_scan_request *scan_request; 1176 struct ieee80211_vif *scan_vif; 1177 u8 scan_tx_ant[NUM_NL80211_BANDS]; 1178 u8 mgmt_tx_ant; 1179 1180 /* spinlock */ 1181 spinlock_t lock; /* protect general shared data */ 1182 spinlock_t hcmd_lock; /* protect hcmd */ 1183 spinlock_t reg_lock; /* protect hw register access */ 1184 struct mutex mutex; 1185 1186 /* basic pci-network driver stuff */ 1187 struct pci_dev *pci_dev; 1188 1189 /* pci hardware address support */ 1190 void __iomem *hw_base; 1191 u32 hw_rev; 1192 u32 hw_wa_rev; 1193 u8 rev_id; 1194 1195 /* command queue number */ 1196 u8 cmd_queue; 1197 1198 /* max number of station keys */ 1199 u8 sta_key_max_num; 1200 1201 /* EEPROM MAC addresses */ 1202 struct mac_address addresses[1]; 1203 1204 /* uCode images, save to reload in case of failure */ 1205 int fw_idx; /* firmware we're trying to load */ 1206 u32 ucode_ver; /* version of ucode, copy of 1207 il_ucode.ver */ 1208 struct fw_desc ucode_code; /* runtime inst */ 1209 struct fw_desc ucode_data; /* runtime data original */ 1210 struct fw_desc ucode_data_backup; /* runtime data save/restore */ 1211 struct fw_desc ucode_init; /* initialization inst */ 1212 struct fw_desc ucode_init_data; /* initialization data */ 1213 struct fw_desc ucode_boot; /* bootstrap inst */ 1214 enum ucode_type ucode_type; 1215 u8 ucode_write_complete; /* the image write is complete */ 1216 char firmware_name[25]; 1217 1218 struct ieee80211_vif *vif; 1219 1220 struct il_qos_info qos_data; 1221 1222 struct { 1223 bool enabled; 1224 bool is_40mhz; 1225 bool non_gf_sta_present; 1226 u8 protection; 1227 u8 extension_chan_offset; 1228 } ht; 1229 1230 /* 1231 * We declare this const so it can only be 1232 * changed via explicit cast within the 1233 * routines that actually update the physical 1234 * hardware. 1235 */ 1236 const struct il_rxon_cmd active; 1237 struct il_rxon_cmd staging; 1238 1239 struct il_rxon_time_cmd timing; 1240 1241 __le16 switch_channel; 1242 1243 /* 1st responses from initialize and runtime uCode images. 1244 * _4965's initialize alive response contains some calibration data. */ 1245 struct il_init_alive_resp card_alive_init; 1246 struct il_alive_resp card_alive; 1247 1248 u16 active_rate; 1249 1250 u8 start_calib; 1251 struct il_sensitivity_data sensitivity_data; 1252 struct il_chain_noise_data chain_noise_data; 1253 __le16 sensitivity_tbl[HD_TBL_SIZE]; 1254 1255 struct il_ht_config current_ht_config; 1256 1257 /* Rate scaling data */ 1258 u8 retry_rate; 1259 1260 wait_queue_head_t wait_command_queue; 1261 1262 int activity_timer_active; 1263 1264 /* Rx and Tx DMA processing queues */ 1265 struct il_rx_queue rxq; 1266 struct il_tx_queue *txq; 1267 unsigned long txq_ctx_active_msk; 1268 struct il_dma_ptr kw; /* keep warm address */ 1269 struct il_dma_ptr scd_bc_tbls; 1270 1271 u32 scd_base_addr; /* scheduler sram base address */ 1272 1273 unsigned long status; 1274 1275 /* counts mgmt, ctl, and data packets */ 1276 struct traffic_stats tx_stats; 1277 struct traffic_stats rx_stats; 1278 1279 /* counts interrupts */ 1280 struct isr_stats isr_stats; 1281 1282 struct il_power_mgr power_data; 1283 1284 /* context information */ 1285 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */ 1286 1287 /* station table variables */ 1288 1289 /* Note: if lock and sta_lock are needed, lock must be acquired first */ 1290 spinlock_t sta_lock; 1291 int num_stations; 1292 struct il_station_entry stations[IL_STATION_COUNT]; 1293 unsigned long ucode_key_table; 1294 1295 /* queue refcounts */ 1296 #define IL_MAX_HW_QUEUES 32 1297 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)]; 1298 #define IL_STOP_REASON_PASSIVE 0 1299 unsigned long stop_reason; 1300 /* for each AC */ 1301 atomic_t queue_stop_count[4]; 1302 1303 /* Indication if ieee80211_ops->open has been called */ 1304 u8 is_open; 1305 1306 u8 mac80211_registered; 1307 1308 /* eeprom -- this is in the card's little endian byte order */ 1309 u8 *eeprom; 1310 struct il_eeprom_calib_info *calib_info; 1311 1312 enum nl80211_iftype iw_mode; 1313 1314 /* Last Rx'd beacon timestamp */ 1315 u64 timestamp; 1316 1317 union { 1318 #if IS_ENABLED(CONFIG_IWL3945) 1319 struct { 1320 void *shared_virt; 1321 dma_addr_t shared_phys; 1322 1323 struct delayed_work thermal_periodic; 1324 struct delayed_work rfkill_poll; 1325 1326 struct il3945_notif_stats stats; 1327 #ifdef CONFIG_IWLEGACY_DEBUGFS 1328 struct il3945_notif_stats accum_stats; 1329 struct il3945_notif_stats delta_stats; 1330 struct il3945_notif_stats max_delta; 1331 #endif 1332 1333 u32 sta_supp_rates; 1334 int last_rx_rssi; /* From Rx packet stats */ 1335 1336 /* Rx'd packet timing information */ 1337 u32 last_beacon_time; 1338 u64 last_tsf; 1339 1340 /* 1341 * each calibration channel group in the 1342 * EEPROM has a derived clip setting for 1343 * each rate. 1344 */ 1345 const struct il3945_clip_group clip_groups[5]; 1346 1347 } _3945; 1348 #endif 1349 #if IS_ENABLED(CONFIG_IWL4965) 1350 struct { 1351 struct il_rx_phy_res last_phy_res; 1352 bool last_phy_res_valid; 1353 u32 ampdu_ref; 1354 1355 struct completion firmware_loading_complete; 1356 1357 /* 1358 * chain noise reset and gain commands are the 1359 * two extra calibration commands follows the standard 1360 * phy calibration commands 1361 */ 1362 u8 phy_calib_chain_noise_reset_cmd; 1363 u8 phy_calib_chain_noise_gain_cmd; 1364 1365 u8 key_mapping_keys; 1366 struct il_wep_key wep_keys[WEP_KEYS_MAX]; 1367 1368 struct il_notif_stats stats; 1369 #ifdef CONFIG_IWLEGACY_DEBUGFS 1370 struct il_notif_stats accum_stats; 1371 struct il_notif_stats delta_stats; 1372 struct il_notif_stats max_delta; 1373 #endif 1374 1375 } _4965; 1376 #endif 1377 }; 1378 1379 struct il_hw_params hw_params; 1380 1381 u32 inta_mask; 1382 1383 struct workqueue_struct *workqueue; 1384 1385 struct work_struct restart; 1386 struct work_struct scan_completed; 1387 struct work_struct rx_replenish; 1388 struct work_struct abort_scan; 1389 1390 bool beacon_enabled; 1391 struct sk_buff *beacon_skb; 1392 1393 struct work_struct tx_flush; 1394 1395 struct tasklet_struct irq_tasklet; 1396 1397 struct delayed_work init_alive_start; 1398 struct delayed_work alive_start; 1399 struct delayed_work scan_check; 1400 1401 /* TX Power */ 1402 s8 tx_power_user_lmt; 1403 s8 tx_power_device_lmt; 1404 s8 tx_power_next; 1405 1406 #ifdef CONFIG_IWLEGACY_DEBUG 1407 /* debugging info */ 1408 u32 debug_level; /* per device debugging will override global 1409 il_debug_level if set */ 1410 #endif /* CONFIG_IWLEGACY_DEBUG */ 1411 #ifdef CONFIG_IWLEGACY_DEBUGFS 1412 /* debugfs */ 1413 u16 tx_traffic_idx; 1414 u16 rx_traffic_idx; 1415 u8 *tx_traffic; 1416 u8 *rx_traffic; 1417 struct dentry *debugfs_dir; 1418 u32 dbgfs_sram_offset, dbgfs_sram_len; 1419 bool disable_ht40; 1420 #endif /* CONFIG_IWLEGACY_DEBUGFS */ 1421 1422 struct work_struct txpower_work; 1423 bool disable_sens_cal; 1424 bool disable_chain_noise_cal; 1425 bool disable_tx_power_cal; 1426 struct work_struct run_time_calib_work; 1427 struct timer_list stats_periodic; 1428 struct timer_list watchdog; 1429 bool hw_ready; 1430 1431 struct led_classdev led; 1432 unsigned long blink_on, blink_off; 1433 bool led_registered; 1434 }; /*il_priv */ 1435 1436 static inline void 1437 il_txq_ctx_activate(struct il_priv *il, int txq_id) 1438 { 1439 set_bit(txq_id, &il->txq_ctx_active_msk); 1440 } 1441 1442 static inline void 1443 il_txq_ctx_deactivate(struct il_priv *il, int txq_id) 1444 { 1445 clear_bit(txq_id, &il->txq_ctx_active_msk); 1446 } 1447 1448 static inline int 1449 il_is_associated(struct il_priv *il) 1450 { 1451 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0; 1452 } 1453 1454 static inline int 1455 il_is_any_associated(struct il_priv *il) 1456 { 1457 return il_is_associated(il); 1458 } 1459 1460 static inline int 1461 il_is_channel_valid(const struct il_channel_info *ch_info) 1462 { 1463 if (ch_info == NULL) 1464 return 0; 1465 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0; 1466 } 1467 1468 static inline int 1469 il_is_channel_radar(const struct il_channel_info *ch_info) 1470 { 1471 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0; 1472 } 1473 1474 static inline u8 1475 il_is_channel_a_band(const struct il_channel_info *ch_info) 1476 { 1477 return ch_info->band == NL80211_BAND_5GHZ; 1478 } 1479 1480 static inline int 1481 il_is_channel_passive(const struct il_channel_info *ch) 1482 { 1483 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0; 1484 } 1485 1486 static inline int 1487 il_is_channel_ibss(const struct il_channel_info *ch) 1488 { 1489 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0; 1490 } 1491 1492 static inline void 1493 __il_free_pages(struct il_priv *il, struct page *page) 1494 { 1495 __free_pages(page, il->hw_params.rx_page_order); 1496 il->alloc_rxb_page--; 1497 } 1498 1499 static inline void 1500 il_free_pages(struct il_priv *il, unsigned long page) 1501 { 1502 free_pages(page, il->hw_params.rx_page_order); 1503 il->alloc_rxb_page--; 1504 } 1505 1506 #define IWLWIFI_VERSION "in-tree:" 1507 #define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation" 1508 #define DRV_AUTHOR "<ilw@linux.intel.com>" 1509 1510 #define IL_PCI_DEVICE(dev, subdev, cfg) \ 1511 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ 1512 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \ 1513 .driver_data = (kernel_ulong_t)&(cfg) 1514 1515 #define TIME_UNIT 1024 1516 1517 #define IL_SKU_G 0x1 1518 #define IL_SKU_A 0x2 1519 #define IL_SKU_N 0x8 1520 1521 #define IL_CMD(x) case x: return #x 1522 1523 /* Size of one Rx buffer in host DRAM */ 1524 #define IL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */ 1525 #define IL_RX_BUF_SIZE_4K (4 * 1024) 1526 #define IL_RX_BUF_SIZE_8K (8 * 1024) 1527 1528 #ifdef CONFIG_IWLEGACY_DEBUGFS 1529 struct il_debugfs_ops { 1530 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf, 1531 size_t count, loff_t *ppos); 1532 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf, 1533 size_t count, loff_t *ppos); 1534 ssize_t(*general_stats_read) (struct file *file, 1535 char __user *user_buf, size_t count, 1536 loff_t *ppos); 1537 }; 1538 #endif 1539 1540 struct il_ops { 1541 /* Handling TX */ 1542 void (*txq_update_byte_cnt_tbl) (struct il_priv *il, 1543 struct il_tx_queue *txq, 1544 u16 byte_cnt); 1545 int (*txq_attach_buf_to_tfd) (struct il_priv *il, 1546 struct il_tx_queue *txq, dma_addr_t addr, 1547 u16 len, u8 reset, u8 pad); 1548 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq); 1549 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq); 1550 /* alive notification after init uCode load */ 1551 void (*init_alive_start) (struct il_priv *il); 1552 /* check validity of rtc data address */ 1553 int (*is_valid_rtc_data_addr) (u32 addr); 1554 /* 1st ucode load */ 1555 int (*load_ucode) (struct il_priv *il); 1556 1557 void (*dump_nic_error_log) (struct il_priv *il); 1558 int (*dump_fh) (struct il_priv *il, char **buf, bool display); 1559 int (*set_channel_switch) (struct il_priv *il, 1560 struct ieee80211_channel_switch *ch_switch); 1561 /* power management */ 1562 int (*apm_init) (struct il_priv *il); 1563 1564 /* tx power */ 1565 int (*send_tx_power) (struct il_priv *il); 1566 void (*update_chain_flags) (struct il_priv *il); 1567 1568 /* eeprom operations */ 1569 int (*eeprom_acquire_semaphore) (struct il_priv *il); 1570 void (*eeprom_release_semaphore) (struct il_priv *il); 1571 1572 int (*rxon_assoc) (struct il_priv *il); 1573 int (*commit_rxon) (struct il_priv *il); 1574 void (*set_rxon_chain) (struct il_priv *il); 1575 1576 u16(*get_hcmd_size) (u8 cmd_id, u16 len); 1577 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data); 1578 1579 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif); 1580 void (*post_scan) (struct il_priv *il); 1581 void (*post_associate) (struct il_priv *il); 1582 void (*config_ap) (struct il_priv *il); 1583 /* station management */ 1584 int (*update_bcast_stations) (struct il_priv *il); 1585 int (*manage_ibss_station) (struct il_priv *il, 1586 struct ieee80211_vif *vif, bool add); 1587 1588 int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd); 1589 }; 1590 1591 struct il_mod_params { 1592 int sw_crypto; /* def: 0 = using hardware encryption */ 1593 int disable_hw_scan; /* def: 0 = use h/w scan */ 1594 int num_of_queues; /* def: HW dependent */ 1595 int disable_11n; /* def: 0 = 11n capabilities enabled */ 1596 int amsdu_size_8K; /* def: 0 = disable 8K amsdu size */ 1597 int antenna; /* def: 0 = both antennas (use diversity) */ 1598 int restart_fw; /* def: 1 = restart firmware */ 1599 }; 1600 1601 #define IL_LED_SOLID 11 1602 #define IL_DEF_LED_INTRVL cpu_to_le32(1000) 1603 1604 #define IL_LED_ACTIVITY (0<<1) 1605 #define IL_LED_LINK (1<<1) 1606 1607 /* 1608 * LED mode 1609 * IL_LED_DEFAULT: use device default 1610 * IL_LED_RF_STATE: turn LED on/off based on RF state 1611 * LED ON = RF ON 1612 * LED OFF = RF OFF 1613 * IL_LED_BLINK: adjust led blink rate based on blink table 1614 */ 1615 enum il_led_mode { 1616 IL_LED_DEFAULT, 1617 IL_LED_RF_STATE, 1618 IL_LED_BLINK, 1619 }; 1620 1621 void il_leds_init(struct il_priv *il); 1622 void il_leds_exit(struct il_priv *il); 1623 1624 /** 1625 * struct il_cfg 1626 * @fw_name_pre: Firmware filename prefix. The api version and extension 1627 * (.ucode) will be added to filename before loading from disk. The 1628 * filename is constructed as fw_name_pre<api>.ucode. 1629 * @ucode_api_max: Highest version of uCode API supported by driver. 1630 * @ucode_api_min: Lowest version of uCode API supported by driver. 1631 * @scan_antennas: available antenna for scan operation 1632 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off) 1633 * 1634 * We enable the driver to be backward compatible wrt API version. The 1635 * driver specifies which APIs it supports (with @ucode_api_max being the 1636 * highest and @ucode_api_min the lowest). Firmware will only be loaded if 1637 * it has a supported API version. The firmware's API version will be 1638 * stored in @il_priv, enabling the driver to make runtime changes based 1639 * on firmware version used. 1640 * 1641 * For example, 1642 * if (IL_UCODE_API(il->ucode_ver) >= 2) { 1643 * Driver interacts with Firmware API version >= 2. 1644 * } else { 1645 * Driver interacts with Firmware API version 1. 1646 * } 1647 * 1648 * The ideal usage of this infrastructure is to treat a new ucode API 1649 * release as a new hardware revision. That is, through utilizing the 1650 * il_hcmd_utils_ops etc. we accommodate different command structures 1651 * and flows between hardware versions as well as their API 1652 * versions. 1653 * 1654 */ 1655 struct il_cfg { 1656 /* params specific to an individual device within a device family */ 1657 const char *name; 1658 const char *fw_name_pre; 1659 const unsigned int ucode_api_max; 1660 const unsigned int ucode_api_min; 1661 u8 valid_tx_ant; 1662 u8 valid_rx_ant; 1663 unsigned int sku; 1664 u16 eeprom_ver; 1665 u16 eeprom_calib_ver; 1666 /* module based parameters which can be set from modprobe cmd */ 1667 const struct il_mod_params *mod_params; 1668 /* params not likely to change within a device family */ 1669 struct il_base_params *base_params; 1670 /* params likely to change within a device family */ 1671 u8 scan_rx_antennas[NUM_NL80211_BANDS]; 1672 enum il_led_mode led_mode; 1673 1674 int eeprom_size; 1675 int num_of_queues; /* def: HW dependent */ 1676 int num_of_ampdu_queues; /* def: HW dependent */ 1677 /* for il_apm_init() */ 1678 u32 pll_cfg_val; 1679 bool set_l0s; 1680 bool use_bsm; 1681 1682 u16 led_compensation; 1683 int chain_noise_num_beacons; 1684 unsigned int wd_timeout; 1685 bool temperature_kelvin; 1686 const bool ucode_tracing; 1687 const bool sensitivity_calib_by_driver; 1688 const bool chain_noise_calib_by_driver; 1689 1690 const u32 regulatory_bands[7]; 1691 }; 1692 1693 /*************************** 1694 * L i b * 1695 ***************************/ 1696 1697 int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1698 unsigned int link_id, u16 queue, 1699 const struct ieee80211_tx_queue_params *params); 1700 int il_mac_tx_last_beacon(struct ieee80211_hw *hw); 1701 1702 void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt); 1703 int il_check_rxon_cmd(struct il_priv *il); 1704 int il_full_rxon_required(struct il_priv *il); 1705 int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch); 1706 void il_set_flags_for_band(struct il_priv *il, enum nl80211_band band, 1707 struct ieee80211_vif *vif); 1708 u8 il_get_single_channel_number(struct il_priv *il, enum nl80211_band band); 1709 void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf); 1710 bool il_is_ht40_tx_allowed(struct il_priv *il, 1711 struct ieee80211_sta_ht_cap *ht_cap); 1712 void il_connection_init_rx_config(struct il_priv *il); 1713 void il_set_rate(struct il_priv *il); 1714 int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr, 1715 u32 decrypt_res, struct ieee80211_rx_status *stats); 1716 void il_irq_handle_error(struct il_priv *il); 1717 int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1718 void il_mac_remove_interface(struct ieee80211_hw *hw, 1719 struct ieee80211_vif *vif); 1720 int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1721 enum nl80211_iftype newtype, bool newp2p); 1722 void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1723 u32 queues, bool drop); 1724 int il_alloc_txq_mem(struct il_priv *il); 1725 void il_free_txq_mem(struct il_priv *il); 1726 1727 #ifdef CONFIG_IWLEGACY_DEBUGFS 1728 void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len); 1729 #else 1730 static inline void 1731 il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len) 1732 { 1733 } 1734 #endif 1735 1736 /***************************************************** 1737 * Handlers 1738 ***************************************************/ 1739 void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb); 1740 void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb); 1741 void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb); 1742 void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb); 1743 1744 /***************************************************** 1745 * RX 1746 ******************************************************/ 1747 void il_cmd_queue_unmap(struct il_priv *il); 1748 void il_cmd_queue_free(struct il_priv *il); 1749 int il_rx_queue_alloc(struct il_priv *il); 1750 void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q); 1751 int il_rx_queue_space(const struct il_rx_queue *q); 1752 void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb); 1753 1754 void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb); 1755 void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt); 1756 void il_chswitch_done(struct il_priv *il, bool is_success); 1757 1758 /***************************************************** 1759 * TX 1760 ******************************************************/ 1761 void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq); 1762 int il_tx_queue_init(struct il_priv *il, u32 txq_id); 1763 void il_tx_queue_reset(struct il_priv *il, u32 txq_id); 1764 void il_tx_queue_unmap(struct il_priv *il, int txq_id); 1765 void il_tx_queue_free(struct il_priv *il, int txq_id); 1766 void il_setup_watchdog(struct il_priv *il); 1767 /***************************************************** 1768 * TX power 1769 ****************************************************/ 1770 int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force); 1771 1772 /******************************************************************************* 1773 * Rate 1774 ******************************************************************************/ 1775 1776 u8 il_get_lowest_plcp(struct il_priv *il); 1777 1778 /******************************************************************************* 1779 * Scanning 1780 ******************************************************************************/ 1781 void il_init_scan_params(struct il_priv *il); 1782 int il_scan_cancel(struct il_priv *il); 1783 int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms); 1784 void il_force_scan_end(struct il_priv *il); 1785 int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1786 struct ieee80211_scan_request *hw_req); 1787 void il_internal_short_hw_scan(struct il_priv *il); 1788 int il_force_reset(struct il_priv *il, bool external); 1789 u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame, 1790 const u8 *ta, const u8 *ie, int ie_len, int left); 1791 void il_setup_rx_scan_handlers(struct il_priv *il); 1792 u16 il_get_active_dwell_time(struct il_priv *il, enum nl80211_band band, 1793 u8 n_probes); 1794 u16 il_get_passive_dwell_time(struct il_priv *il, enum nl80211_band band, 1795 struct ieee80211_vif *vif); 1796 void il_setup_scan_deferred_work(struct il_priv *il); 1797 void il_cancel_scan_deferred_work(struct il_priv *il); 1798 1799 /* For faster active scanning, scan will move to the next channel if fewer than 1800 * PLCP_QUIET_THRESH packets are heard on this channel within 1801 * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell 1802 * time if it's a quiet channel (nothing responded to our probe, and there's 1803 * no other traffic). 1804 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */ 1805 #define IL_ACTIVE_QUIET_TIME cpu_to_le16(10) /* msec */ 1806 #define IL_PLCP_QUIET_THRESH cpu_to_le16(1) /* packets */ 1807 1808 #define IL_SCAN_CHECK_WATCHDOG (HZ * 7) 1809 1810 /***************************************************** 1811 * S e n d i n g H o s t C o m m a n d s * 1812 *****************************************************/ 1813 1814 const char *il_get_cmd_string(u8 cmd); 1815 int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd); 1816 int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd); 1817 int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, 1818 const void *data); 1819 int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data, 1820 void (*callback) (struct il_priv *il, 1821 struct il_device_cmd *cmd, 1822 struct il_rx_pkt *pkt)); 1823 1824 int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd); 1825 1826 /***************************************************** 1827 * PCI * 1828 *****************************************************/ 1829 1830 void il_bg_watchdog(struct timer_list *t); 1831 u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval); 1832 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, 1833 u32 beacon_interval); 1834 1835 #ifdef CONFIG_PM_SLEEP 1836 extern const struct dev_pm_ops il_pm_ops; 1837 1838 #define IL_LEGACY_PM_OPS (&il_pm_ops) 1839 1840 #else /* !CONFIG_PM_SLEEP */ 1841 1842 #define IL_LEGACY_PM_OPS NULL 1843 1844 #endif /* !CONFIG_PM_SLEEP */ 1845 1846 /***************************************************** 1847 * Error Handling Debugging 1848 ******************************************************/ 1849 void il4965_dump_nic_error_log(struct il_priv *il); 1850 #ifdef CONFIG_IWLEGACY_DEBUG 1851 void il_print_rx_config_cmd(struct il_priv *il); 1852 #else 1853 static inline void 1854 il_print_rx_config_cmd(struct il_priv *il) 1855 { 1856 } 1857 #endif 1858 1859 void il_clear_isr_stats(struct il_priv *il); 1860 1861 /***************************************************** 1862 * GEOS 1863 ******************************************************/ 1864 int il_init_geos(struct il_priv *il); 1865 void il_free_geos(struct il_priv *il); 1866 1867 /*************** DRIVER STATUS FUNCTIONS *****/ 1868 1869 #define S_HCMD_ACTIVE 0 /* host command in progress */ 1870 /* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */ 1871 #define S_INT_ENABLED 2 1872 #define S_RFKILL 3 1873 #define S_CT_KILL 4 1874 #define S_INIT 5 1875 #define S_ALIVE 6 1876 #define S_READY 7 1877 #define S_TEMPERATURE 8 1878 #define S_GEO_CONFIGURED 9 1879 #define S_EXIT_PENDING 10 1880 #define S_STATS 12 1881 #define S_SCANNING 13 1882 #define S_SCAN_ABORTING 14 1883 #define S_SCAN_HW 15 1884 #define S_POWER_PMI 16 1885 #define S_FW_ERROR 17 1886 #define S_CHANNEL_SWITCH_PENDING 18 1887 1888 static inline int 1889 il_is_ready(struct il_priv *il) 1890 { 1891 /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are 1892 * set but EXIT_PENDING is not */ 1893 return test_bit(S_READY, &il->status) && 1894 test_bit(S_GEO_CONFIGURED, &il->status) && 1895 !test_bit(S_EXIT_PENDING, &il->status); 1896 } 1897 1898 static inline int 1899 il_is_alive(struct il_priv *il) 1900 { 1901 return test_bit(S_ALIVE, &il->status); 1902 } 1903 1904 static inline int 1905 il_is_init(struct il_priv *il) 1906 { 1907 return test_bit(S_INIT, &il->status); 1908 } 1909 1910 static inline int 1911 il_is_rfkill(struct il_priv *il) 1912 { 1913 return test_bit(S_RFKILL, &il->status); 1914 } 1915 1916 static inline int 1917 il_is_ctkill(struct il_priv *il) 1918 { 1919 return test_bit(S_CT_KILL, &il->status); 1920 } 1921 1922 static inline int 1923 il_is_ready_rf(struct il_priv *il) 1924 { 1925 1926 if (il_is_rfkill(il)) 1927 return 0; 1928 1929 return il_is_ready(il); 1930 } 1931 1932 void il_send_bt_config(struct il_priv *il); 1933 int il_send_stats_request(struct il_priv *il, u8 flags, bool clear); 1934 void il_apm_stop(struct il_priv *il); 1935 void _il_apm_stop(struct il_priv *il); 1936 1937 int il_apm_init(struct il_priv *il); 1938 1939 int il_send_rxon_timing(struct il_priv *il); 1940 1941 static inline int 1942 il_send_rxon_assoc(struct il_priv *il) 1943 { 1944 return il->ops->rxon_assoc(il); 1945 } 1946 1947 static inline int 1948 il_commit_rxon(struct il_priv *il) 1949 { 1950 return il->ops->commit_rxon(il); 1951 } 1952 1953 static inline const struct ieee80211_supported_band * 1954 il_get_hw_mode(struct il_priv *il, enum nl80211_band band) 1955 { 1956 return il->hw->wiphy->bands[band]; 1957 } 1958 1959 /* mac80211 handlers */ 1960 int il_mac_config(struct ieee80211_hw *hw, u32 changed); 1961 void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1962 void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1963 struct ieee80211_bss_conf *bss_conf, u64 changes); 1964 void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info, 1965 __le16 fc, __le32 *tx_flags); 1966 1967 irqreturn_t il_isr(int irq, void *data); 1968 1969 void il_set_bit(struct il_priv *p, u32 r, u32 m); 1970 void il_clear_bit(struct il_priv *p, u32 r, u32 m); 1971 bool _il_grab_nic_access(struct il_priv *il); 1972 int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout); 1973 int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout); 1974 u32 il_rd_prph(struct il_priv *il, u32 reg); 1975 void il_wr_prph(struct il_priv *il, u32 addr, u32 val); 1976 u32 il_read_targ_mem(struct il_priv *il, u32 addr); 1977 void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val); 1978 1979 static inline bool il_need_reclaim(struct il_priv *il, struct il_rx_pkt *pkt) 1980 { 1981 /* Reclaim a command buffer only if this packet is a response 1982 * to a (driver-originated) command. If the packet (e.g. Rx frame) 1983 * originated from uCode, there is no command buffer to reclaim. 1984 * Ucode should set SEQ_RX_FRAME bit if ucode-originated, but 1985 * apparently a few don't get set; catch them here. 1986 */ 1987 return !(pkt->hdr.sequence & SEQ_RX_FRAME) && 1988 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX && 1989 pkt->hdr.cmd != N_RX_PHY && pkt->hdr.cmd != N_RX && 1990 pkt->hdr.cmd != N_RX_MPDU && pkt->hdr.cmd != N_COMPRESSED_BA; 1991 } 1992 1993 static inline void 1994 _il_write8(struct il_priv *il, u32 ofs, u8 val) 1995 { 1996 writeb(val, il->hw_base + ofs); 1997 } 1998 #define il_write8(il, ofs, val) _il_write8(il, ofs, val) 1999 2000 static inline void 2001 _il_wr(struct il_priv *il, u32 ofs, u32 val) 2002 { 2003 writel(val, il->hw_base + ofs); 2004 } 2005 2006 static inline u32 2007 _il_rd(struct il_priv *il, u32 ofs) 2008 { 2009 return readl(il->hw_base + ofs); 2010 } 2011 2012 static inline void 2013 _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) 2014 { 2015 _il_wr(il, reg, _il_rd(il, reg) & ~mask); 2016 } 2017 2018 static inline void 2019 _il_set_bit(struct il_priv *il, u32 reg, u32 mask) 2020 { 2021 _il_wr(il, reg, _il_rd(il, reg) | mask); 2022 } 2023 2024 static inline void 2025 _il_release_nic_access(struct il_priv *il) 2026 { 2027 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2028 } 2029 2030 static inline u32 2031 il_rd(struct il_priv *il, u32 reg) 2032 { 2033 u32 value; 2034 unsigned long reg_flags; 2035 2036 spin_lock_irqsave(&il->reg_lock, reg_flags); 2037 _il_grab_nic_access(il); 2038 value = _il_rd(il, reg); 2039 _il_release_nic_access(il); 2040 spin_unlock_irqrestore(&il->reg_lock, reg_flags); 2041 return value; 2042 } 2043 2044 static inline void 2045 il_wr(struct il_priv *il, u32 reg, u32 value) 2046 { 2047 unsigned long reg_flags; 2048 2049 spin_lock_irqsave(&il->reg_lock, reg_flags); 2050 if (likely(_il_grab_nic_access(il))) { 2051 _il_wr(il, reg, value); 2052 _il_release_nic_access(il); 2053 } 2054 spin_unlock_irqrestore(&il->reg_lock, reg_flags); 2055 } 2056 2057 static inline u32 2058 _il_rd_prph(struct il_priv *il, u32 reg) 2059 { 2060 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); 2061 return _il_rd(il, HBUS_TARG_PRPH_RDAT); 2062 } 2063 2064 static inline void 2065 _il_wr_prph(struct il_priv *il, u32 addr, u32 val) 2066 { 2067 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24))); 2068 _il_wr(il, HBUS_TARG_PRPH_WDAT, val); 2069 } 2070 2071 static inline void 2072 il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask) 2073 { 2074 unsigned long reg_flags; 2075 2076 spin_lock_irqsave(&il->reg_lock, reg_flags); 2077 if (likely(_il_grab_nic_access(il))) { 2078 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask)); 2079 _il_release_nic_access(il); 2080 } 2081 spin_unlock_irqrestore(&il->reg_lock, reg_flags); 2082 } 2083 2084 static inline void 2085 il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask) 2086 { 2087 unsigned long reg_flags; 2088 2089 spin_lock_irqsave(&il->reg_lock, reg_flags); 2090 if (likely(_il_grab_nic_access(il))) { 2091 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits)); 2092 _il_release_nic_access(il); 2093 } 2094 spin_unlock_irqrestore(&il->reg_lock, reg_flags); 2095 } 2096 2097 static inline void 2098 il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask) 2099 { 2100 unsigned long reg_flags; 2101 u32 val; 2102 2103 spin_lock_irqsave(&il->reg_lock, reg_flags); 2104 if (likely(_il_grab_nic_access(il))) { 2105 val = _il_rd_prph(il, reg); 2106 _il_wr_prph(il, reg, (val & ~mask)); 2107 _il_release_nic_access(il); 2108 } 2109 spin_unlock_irqrestore(&il->reg_lock, reg_flags); 2110 } 2111 2112 #define HW_KEY_DYNAMIC 0 2113 #define HW_KEY_DEFAULT 1 2114 2115 #define IL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */ 2116 #define IL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */ 2117 #define IL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of 2118 being activated */ 2119 #define IL_STA_LOCAL BIT(3) /* station state not directed by mac80211; 2120 (this is for the IBSS BSSID stations) */ 2121 #define IL_STA_BCAST BIT(4) /* this station is the special bcast station */ 2122 2123 void il_restore_stations(struct il_priv *il); 2124 void il_clear_ucode_stations(struct il_priv *il); 2125 void il_dealloc_bcast_stations(struct il_priv *il); 2126 int il_get_free_ucode_key_idx(struct il_priv *il); 2127 int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags); 2128 int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap, 2129 struct ieee80211_sta *sta, u8 *sta_id_r); 2130 int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr); 2131 int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2132 struct ieee80211_sta *sta); 2133 2134 u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap, 2135 struct ieee80211_sta *sta); 2136 2137 int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq, 2138 u8 flags, bool init); 2139 2140 /** 2141 * il_clear_driver_stations - clear knowledge of all stations from driver 2142 * @il: iwl il struct 2143 * 2144 * This is called during il_down() to make sure that in the case 2145 * we're coming there from a hardware restart mac80211 will be 2146 * able to reconfigure stations -- if we're getting there in the 2147 * normal down flow then the stations will already be cleared. 2148 */ 2149 static inline void 2150 il_clear_driver_stations(struct il_priv *il) 2151 { 2152 unsigned long flags; 2153 2154 spin_lock_irqsave(&il->sta_lock, flags); 2155 memset(il->stations, 0, sizeof(il->stations)); 2156 il->num_stations = 0; 2157 il->ucode_key_table = 0; 2158 spin_unlock_irqrestore(&il->sta_lock, flags); 2159 } 2160 2161 static inline int 2162 il_sta_id(struct ieee80211_sta *sta) 2163 { 2164 if (WARN_ON(!sta)) 2165 return IL_INVALID_STATION; 2166 2167 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id; 2168 } 2169 2170 /** 2171 * il_sta_id_or_broadcast - return sta_id or broadcast sta 2172 * @il: iwl il 2173 * @context: the current context 2174 * @sta: mac80211 station 2175 * 2176 * In certain circumstances mac80211 passes a station pointer 2177 * that may be %NULL, for example during TX or key setup. In 2178 * that case, we need to use the broadcast station, so this 2179 * inline wraps that pattern. 2180 */ 2181 static inline int 2182 il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta) 2183 { 2184 int sta_id; 2185 2186 if (!sta) 2187 return il->hw_params.bcast_id; 2188 2189 sta_id = il_sta_id(sta); 2190 2191 /* 2192 * mac80211 should not be passing a partially 2193 * initialised station! 2194 */ 2195 WARN_ON(sta_id == IL_INVALID_STATION); 2196 2197 return sta_id; 2198 } 2199 2200 /** 2201 * il_queue_inc_wrap - increment queue idx, wrap back to beginning 2202 * @idx -- current idx 2203 * @n_bd -- total number of entries in queue (must be power of 2) 2204 */ 2205 static inline int 2206 il_queue_inc_wrap(int idx, int n_bd) 2207 { 2208 return ++idx & (n_bd - 1); 2209 } 2210 2211 /** 2212 * il_queue_dec_wrap - decrement queue idx, wrap back to end 2213 * @idx -- current idx 2214 * @n_bd -- total number of entries in queue (must be power of 2) 2215 */ 2216 static inline int 2217 il_queue_dec_wrap(int idx, int n_bd) 2218 { 2219 return --idx & (n_bd - 1); 2220 } 2221 2222 /* TODO: Move fw_desc functions to iwl-pci.ko */ 2223 static inline void 2224 il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc) 2225 { 2226 if (desc->v_addr) 2227 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr, 2228 desc->p_addr); 2229 desc->v_addr = NULL; 2230 desc->len = 0; 2231 } 2232 2233 static inline int 2234 il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc) 2235 { 2236 if (!desc->len) { 2237 desc->v_addr = NULL; 2238 return -EINVAL; 2239 } 2240 2241 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len, 2242 &desc->p_addr, GFP_KERNEL); 2243 return (desc->v_addr != NULL) ? 0 : -ENOMEM; 2244 } 2245 2246 /* 2247 * we have 8 bits used like this: 2248 * 2249 * 7 6 5 4 3 2 1 0 2250 * | | | | | | | | 2251 * | | | | | | +-+-------- AC queue (0-3) 2252 * | | | | | | 2253 * | +-+-+-+-+------------ HW queue ID 2254 * | 2255 * +---------------------- unused 2256 */ 2257 static inline void 2258 il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq) 2259 { 2260 BUG_ON(ac > 3); /* only have 2 bits */ 2261 BUG_ON(hwq > 31); /* only use 5 bits */ 2262 2263 txq->swq_id = (hwq << 2) | ac; 2264 } 2265 2266 static inline void 2267 _il_wake_queue(struct il_priv *il, u8 ac) 2268 { 2269 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0) 2270 ieee80211_wake_queue(il->hw, ac); 2271 } 2272 2273 static inline void 2274 _il_stop_queue(struct il_priv *il, u8 ac) 2275 { 2276 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0) 2277 ieee80211_stop_queue(il->hw, ac); 2278 } 2279 static inline void 2280 il_wake_queue(struct il_priv *il, struct il_tx_queue *txq) 2281 { 2282 u8 queue = txq->swq_id; 2283 u8 ac = queue & 3; 2284 u8 hwq = (queue >> 2) & 0x1f; 2285 2286 if (test_and_clear_bit(hwq, il->queue_stopped)) 2287 _il_wake_queue(il, ac); 2288 } 2289 2290 static inline void 2291 il_stop_queue(struct il_priv *il, struct il_tx_queue *txq) 2292 { 2293 u8 queue = txq->swq_id; 2294 u8 ac = queue & 3; 2295 u8 hwq = (queue >> 2) & 0x1f; 2296 2297 if (!test_and_set_bit(hwq, il->queue_stopped)) 2298 _il_stop_queue(il, ac); 2299 } 2300 2301 static inline void 2302 il_wake_queues_by_reason(struct il_priv *il, int reason) 2303 { 2304 u8 ac; 2305 2306 if (test_and_clear_bit(reason, &il->stop_reason)) 2307 for (ac = 0; ac < 4; ac++) 2308 _il_wake_queue(il, ac); 2309 } 2310 2311 static inline void 2312 il_stop_queues_by_reason(struct il_priv *il, int reason) 2313 { 2314 u8 ac; 2315 2316 if (!test_and_set_bit(reason, &il->stop_reason)) 2317 for (ac = 0; ac < 4; ac++) 2318 _il_stop_queue(il, ac); 2319 } 2320 2321 #ifdef ieee80211_stop_queue 2322 #undef ieee80211_stop_queue 2323 #endif 2324 2325 #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue 2326 2327 #ifdef ieee80211_wake_queue 2328 #undef ieee80211_wake_queue 2329 #endif 2330 2331 #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue 2332 2333 static inline void 2334 il_disable_interrupts(struct il_priv *il) 2335 { 2336 clear_bit(S_INT_ENABLED, &il->status); 2337 2338 /* disable interrupts from uCode/NIC to host */ 2339 _il_wr(il, CSR_INT_MASK, 0x00000000); 2340 2341 /* acknowledge/clear/reset any interrupts still pending 2342 * from uCode or flow handler (Rx/Tx DMA) */ 2343 _il_wr(il, CSR_INT, 0xffffffff); 2344 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff); 2345 } 2346 2347 static inline void 2348 il_enable_rfkill_int(struct il_priv *il) 2349 { 2350 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); 2351 } 2352 2353 static inline void 2354 il_enable_interrupts(struct il_priv *il) 2355 { 2356 set_bit(S_INT_ENABLED, &il->status); 2357 _il_wr(il, CSR_INT_MASK, il->inta_mask); 2358 } 2359 2360 /** 2361 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time 2362 * @il -- pointer to il_priv data structure 2363 * @tsf_bits -- number of bits need to shift for masking) 2364 */ 2365 static inline u32 2366 il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits) 2367 { 2368 return (1 << tsf_bits) - 1; 2369 } 2370 2371 /** 2372 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time 2373 * @il -- pointer to il_priv data structure 2374 * @tsf_bits -- number of bits need to shift for masking) 2375 */ 2376 static inline u32 2377 il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits) 2378 { 2379 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits; 2380 } 2381 2382 /** 2383 * struct il_rb_status - reseve buffer status host memory mapped FH registers 2384 * 2385 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed 2386 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed 2387 * @finished_rb_num [0:11] - Indicates the idx of the current RB 2388 * in which the last frame was written to 2389 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame 2390 * which was transferred 2391 */ 2392 struct il_rb_status { 2393 __le16 closed_rb_num; 2394 __le16 closed_fr_num; 2395 __le16 finished_rb_num; 2396 __le16 finished_fr_nam; 2397 __le32 __unused; /* 3945 only */ 2398 } __packed; 2399 2400 #define TFD_QUEUE_SIZE_MAX 256 2401 #define TFD_QUEUE_SIZE_BC_DUP 64 2402 #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) 2403 #define IL_TX_DMA_MASK DMA_BIT_MASK(36) 2404 #define IL_NUM_OF_TBS 20 2405 2406 static inline u8 2407 il_get_dma_hi_addr(dma_addr_t addr) 2408 { 2409 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; 2410 } 2411 2412 /** 2413 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor 2414 * 2415 * This structure contains dma address and length of transmission address 2416 * 2417 * @lo: low [31:0] portion of the dma address of TX buffer every even is 2418 * unaligned on 16 bit boundary 2419 * @hi_n_len: 0-3 [35:32] portion of dma 2420 * 4-15 length of the tx buffer 2421 */ 2422 struct il_tfd_tb { 2423 __le32 lo; 2424 __le16 hi_n_len; 2425 } __packed; 2426 2427 /** 2428 * struct il_tfd 2429 * 2430 * Transmit Frame Descriptor (TFD) 2431 * 2432 * @ __reserved1[3] reserved 2433 * @ num_tbs 0-4 number of active tbs 2434 * 5 reserved 2435 * 6-7 padding (not used) 2436 * @ tbs[20] transmit frame buffer descriptors 2437 * @ __pad padding 2438 * 2439 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 2440 * Both driver and device share these circular buffers, each of which must be 2441 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 2442 * 2443 * Driver must indicate the physical address of the base of each 2444 * circular buffer via the FH49_MEM_CBBC_QUEUE registers. 2445 * 2446 * Each TFD contains pointer/size information for up to 20 data buffers 2447 * in host DRAM. These buffers collectively contain the (one) frame described 2448 * by the TFD. Each buffer must be a single contiguous block of memory within 2449 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 2450 * of (4K - 4). The concatenates all of a TFD's buffers into a single 2451 * Tx frame, up to 8 KBytes in size. 2452 * 2453 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 2454 */ 2455 struct il_tfd { 2456 u8 __reserved1[3]; 2457 u8 num_tbs; 2458 struct il_tfd_tb tbs[IL_NUM_OF_TBS]; 2459 __le32 __pad; 2460 } __packed; 2461 /* PCI registers */ 2462 #define PCI_CFG_RETRY_TIMEOUT 0x041 2463 2464 struct il_rate_info { 2465 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ 2466 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */ 2467 u8 plcp_mimo2; /* uCode API: RATE_MIMO2_6M_PLCP, etc. */ 2468 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */ 2469 u8 prev_ieee; /* previous rate in IEEE speeds */ 2470 u8 next_ieee; /* next rate in IEEE speeds */ 2471 u8 prev_rs; /* previous rate used in rs algo */ 2472 u8 next_rs; /* next rate used in rs algo */ 2473 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */ 2474 u8 next_rs_tgg; /* next rate used in TGG rs algo */ 2475 }; 2476 2477 struct il3945_rate_info { 2478 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ 2479 u8 ieee; /* MAC header: RATE_6M_IEEE, etc. */ 2480 u8 prev_ieee; /* previous rate in IEEE speeds */ 2481 u8 next_ieee; /* next rate in IEEE speeds */ 2482 u8 prev_rs; /* previous rate used in rs algo */ 2483 u8 next_rs; /* next rate used in rs algo */ 2484 u8 prev_rs_tgg; /* previous rate used in TGG rs algo */ 2485 u8 next_rs_tgg; /* next rate used in TGG rs algo */ 2486 u8 table_rs_idx; /* idx in rate scale table cmd */ 2487 u8 prev_table_rs; /* prev in rate table cmd */ 2488 }; 2489 2490 /* 2491 * These serve as idxes into 2492 * struct il_rate_info il_rates[RATE_COUNT]; 2493 */ 2494 enum { 2495 RATE_1M_IDX = 0, 2496 RATE_2M_IDX, 2497 RATE_5M_IDX, 2498 RATE_11M_IDX, 2499 RATE_6M_IDX, 2500 RATE_9M_IDX, 2501 RATE_12M_IDX, 2502 RATE_18M_IDX, 2503 RATE_24M_IDX, 2504 RATE_36M_IDX, 2505 RATE_48M_IDX, 2506 RATE_54M_IDX, 2507 RATE_60M_IDX, 2508 RATE_COUNT, 2509 RATE_COUNT_LEGACY = RATE_COUNT - 1, /* Excluding 60M */ 2510 RATE_COUNT_3945 = RATE_COUNT - 1, 2511 RATE_INVM_IDX = RATE_COUNT, 2512 RATE_INVALID = RATE_COUNT, 2513 }; 2514 2515 enum { 2516 RATE_6M_IDX_TBL = 0, 2517 RATE_9M_IDX_TBL, 2518 RATE_12M_IDX_TBL, 2519 RATE_18M_IDX_TBL, 2520 RATE_24M_IDX_TBL, 2521 RATE_36M_IDX_TBL, 2522 RATE_48M_IDX_TBL, 2523 RATE_54M_IDX_TBL, 2524 RATE_1M_IDX_TBL, 2525 RATE_2M_IDX_TBL, 2526 RATE_5M_IDX_TBL, 2527 RATE_11M_IDX_TBL, 2528 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1, 2529 }; 2530 2531 enum { 2532 IL_FIRST_OFDM_RATE = RATE_6M_IDX, 2533 IL39_LAST_OFDM_RATE = RATE_54M_IDX, 2534 IL_LAST_OFDM_RATE = RATE_60M_IDX, 2535 IL_FIRST_CCK_RATE = RATE_1M_IDX, 2536 IL_LAST_CCK_RATE = RATE_11M_IDX, 2537 }; 2538 2539 /* #define vs. enum to keep from defaulting to 'large integer' */ 2540 #define RATE_6M_MASK (1 << RATE_6M_IDX) 2541 #define RATE_9M_MASK (1 << RATE_9M_IDX) 2542 #define RATE_12M_MASK (1 << RATE_12M_IDX) 2543 #define RATE_18M_MASK (1 << RATE_18M_IDX) 2544 #define RATE_24M_MASK (1 << RATE_24M_IDX) 2545 #define RATE_36M_MASK (1 << RATE_36M_IDX) 2546 #define RATE_48M_MASK (1 << RATE_48M_IDX) 2547 #define RATE_54M_MASK (1 << RATE_54M_IDX) 2548 #define RATE_60M_MASK (1 << RATE_60M_IDX) 2549 #define RATE_1M_MASK (1 << RATE_1M_IDX) 2550 #define RATE_2M_MASK (1 << RATE_2M_IDX) 2551 #define RATE_5M_MASK (1 << RATE_5M_IDX) 2552 #define RATE_11M_MASK (1 << RATE_11M_IDX) 2553 2554 /* uCode API values for legacy bit rates, both OFDM and CCK */ 2555 enum { 2556 RATE_6M_PLCP = 13, 2557 RATE_9M_PLCP = 15, 2558 RATE_12M_PLCP = 5, 2559 RATE_18M_PLCP = 7, 2560 RATE_24M_PLCP = 9, 2561 RATE_36M_PLCP = 11, 2562 RATE_48M_PLCP = 1, 2563 RATE_54M_PLCP = 3, 2564 RATE_60M_PLCP = 3, /*FIXME:RS:should be removed */ 2565 RATE_1M_PLCP = 10, 2566 RATE_2M_PLCP = 20, 2567 RATE_5M_PLCP = 55, 2568 RATE_11M_PLCP = 110, 2569 /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */ 2570 }; 2571 2572 /* uCode API values for OFDM high-throughput (HT) bit rates */ 2573 enum { 2574 RATE_SISO_6M_PLCP = 0, 2575 RATE_SISO_12M_PLCP = 1, 2576 RATE_SISO_18M_PLCP = 2, 2577 RATE_SISO_24M_PLCP = 3, 2578 RATE_SISO_36M_PLCP = 4, 2579 RATE_SISO_48M_PLCP = 5, 2580 RATE_SISO_54M_PLCP = 6, 2581 RATE_SISO_60M_PLCP = 7, 2582 RATE_MIMO2_6M_PLCP = 0x8, 2583 RATE_MIMO2_12M_PLCP = 0x9, 2584 RATE_MIMO2_18M_PLCP = 0xa, 2585 RATE_MIMO2_24M_PLCP = 0xb, 2586 RATE_MIMO2_36M_PLCP = 0xc, 2587 RATE_MIMO2_48M_PLCP = 0xd, 2588 RATE_MIMO2_54M_PLCP = 0xe, 2589 RATE_MIMO2_60M_PLCP = 0xf, 2590 RATE_SISO_INVM_PLCP, 2591 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP, 2592 }; 2593 2594 /* MAC header values for bit rates */ 2595 enum { 2596 RATE_6M_IEEE = 12, 2597 RATE_9M_IEEE = 18, 2598 RATE_12M_IEEE = 24, 2599 RATE_18M_IEEE = 36, 2600 RATE_24M_IEEE = 48, 2601 RATE_36M_IEEE = 72, 2602 RATE_48M_IEEE = 96, 2603 RATE_54M_IEEE = 108, 2604 RATE_60M_IEEE = 120, 2605 RATE_1M_IEEE = 2, 2606 RATE_2M_IEEE = 4, 2607 RATE_5M_IEEE = 11, 2608 RATE_11M_IEEE = 22, 2609 }; 2610 2611 #define IL_CCK_BASIC_RATES_MASK \ 2612 (RATE_1M_MASK | \ 2613 RATE_2M_MASK) 2614 2615 #define IL_CCK_RATES_MASK \ 2616 (IL_CCK_BASIC_RATES_MASK | \ 2617 RATE_5M_MASK | \ 2618 RATE_11M_MASK) 2619 2620 #define IL_OFDM_BASIC_RATES_MASK \ 2621 (RATE_6M_MASK | \ 2622 RATE_12M_MASK | \ 2623 RATE_24M_MASK) 2624 2625 #define IL_OFDM_RATES_MASK \ 2626 (IL_OFDM_BASIC_RATES_MASK | \ 2627 RATE_9M_MASK | \ 2628 RATE_18M_MASK | \ 2629 RATE_36M_MASK | \ 2630 RATE_48M_MASK | \ 2631 RATE_54M_MASK) 2632 2633 #define IL_BASIC_RATES_MASK \ 2634 (IL_OFDM_BASIC_RATES_MASK | \ 2635 IL_CCK_BASIC_RATES_MASK) 2636 2637 #define RATES_MASK ((1 << RATE_COUNT) - 1) 2638 #define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1) 2639 2640 #define IL_INVALID_VALUE -1 2641 2642 #define IL_MIN_RSSI_VAL -100 2643 #define IL_MAX_RSSI_VAL 0 2644 2645 /* These values specify how many Tx frame attempts before 2646 * searching for a new modulation mode */ 2647 #define IL_LEGACY_FAILURE_LIMIT 160 2648 #define IL_LEGACY_SUCCESS_LIMIT 480 2649 #define IL_LEGACY_TBL_COUNT 160 2650 2651 #define IL_NONE_LEGACY_FAILURE_LIMIT 400 2652 #define IL_NONE_LEGACY_SUCCESS_LIMIT 4500 2653 #define IL_NONE_LEGACY_TBL_COUNT 1500 2654 2655 /* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */ 2656 #define IL_RS_GOOD_RATIO 12800 /* 100% */ 2657 #define RATE_SCALE_SWITCH 10880 /* 85% */ 2658 #define RATE_HIGH_TH 10880 /* 85% */ 2659 #define RATE_INCREASE_TH 6400 /* 50% */ 2660 #define RATE_DECREASE_TH 1920 /* 15% */ 2661 2662 /* possible actions when in legacy mode */ 2663 #define IL_LEGACY_SWITCH_ANTENNA1 0 2664 #define IL_LEGACY_SWITCH_ANTENNA2 1 2665 #define IL_LEGACY_SWITCH_SISO 2 2666 #define IL_LEGACY_SWITCH_MIMO2_AB 3 2667 #define IL_LEGACY_SWITCH_MIMO2_AC 4 2668 #define IL_LEGACY_SWITCH_MIMO2_BC 5 2669 2670 /* possible actions when in siso mode */ 2671 #define IL_SISO_SWITCH_ANTENNA1 0 2672 #define IL_SISO_SWITCH_ANTENNA2 1 2673 #define IL_SISO_SWITCH_MIMO2_AB 2 2674 #define IL_SISO_SWITCH_MIMO2_AC 3 2675 #define IL_SISO_SWITCH_MIMO2_BC 4 2676 #define IL_SISO_SWITCH_GI 5 2677 2678 /* possible actions when in mimo mode */ 2679 #define IL_MIMO2_SWITCH_ANTENNA1 0 2680 #define IL_MIMO2_SWITCH_ANTENNA2 1 2681 #define IL_MIMO2_SWITCH_SISO_A 2 2682 #define IL_MIMO2_SWITCH_SISO_B 3 2683 #define IL_MIMO2_SWITCH_SISO_C 4 2684 #define IL_MIMO2_SWITCH_GI 5 2685 2686 #define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI 2687 2688 #define IL_ACTION_LIMIT 3 /* # possible actions */ 2689 2690 #define LQ_SIZE 2 /* 2 mode tables: "Active" and "Search" */ 2691 2692 /* load per tid defines for A-MPDU activation */ 2693 #define IL_AGG_TPT_THREHOLD 0 2694 #define IL_AGG_LOAD_THRESHOLD 10 2695 #define IL_AGG_ALL_TID 0xff 2696 #define TID_QUEUE_CELL_SPACING 50 /*mS */ 2697 #define TID_QUEUE_MAX_SIZE 20 2698 #define TID_ROUND_VALUE 5 /* mS */ 2699 #define TID_MAX_LOAD_COUNT 8 2700 2701 #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING) 2702 #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y)) 2703 2704 extern const struct il_rate_info il_rates[RATE_COUNT]; 2705 2706 enum il_table_type { 2707 LQ_NONE, 2708 LQ_G, /* legacy types */ 2709 LQ_A, 2710 LQ_SISO, /* high-throughput types */ 2711 LQ_MIMO2, 2712 LQ_MAX, 2713 }; 2714 2715 #define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A) 2716 #define is_siso(tbl) ((tbl) == LQ_SISO) 2717 #define is_mimo2(tbl) ((tbl) == LQ_MIMO2) 2718 #define is_mimo(tbl) (is_mimo2(tbl)) 2719 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) 2720 #define is_a_band(tbl) ((tbl) == LQ_A) 2721 #define is_g_and(tbl) ((tbl) == LQ_G) 2722 2723 #define ANT_NONE 0x0 2724 #define ANT_A BIT(0) 2725 #define ANT_B BIT(1) 2726 #define ANT_AB (ANT_A | ANT_B) 2727 #define ANT_C BIT(2) 2728 #define ANT_AC (ANT_A | ANT_C) 2729 #define ANT_BC (ANT_B | ANT_C) 2730 #define ANT_ABC (ANT_AB | ANT_C) 2731 2732 #define IL_MAX_MCS_DISPLAY_SIZE 12 2733 2734 struct il_rate_mcs_info { 2735 char mbps[IL_MAX_MCS_DISPLAY_SIZE]; 2736 char mcs[IL_MAX_MCS_DISPLAY_SIZE]; 2737 }; 2738 2739 /** 2740 * struct il_rate_scale_data -- tx success history for one rate 2741 */ 2742 struct il_rate_scale_data { 2743 u64 data; /* bitmap of successful frames */ 2744 s32 success_counter; /* number of frames successful */ 2745 s32 success_ratio; /* per-cent * 128 */ 2746 s32 counter; /* number of frames attempted */ 2747 s32 average_tpt; /* success ratio * expected throughput */ 2748 unsigned long stamp; 2749 }; 2750 2751 /** 2752 * struct il_scale_tbl_info -- tx params and success history for all rates 2753 * 2754 * There are two of these in struct il_lq_sta, 2755 * one for "active", and one for "search". 2756 */ 2757 struct il_scale_tbl_info { 2758 enum il_table_type lq_type; 2759 u8 ant_type; 2760 u8 is_SGI; /* 1 = short guard interval */ 2761 u8 is_ht40; /* 1 = 40 MHz channel width */ 2762 u8 is_dup; /* 1 = duplicated data streams */ 2763 u8 action; /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */ 2764 u8 max_search; /* maximun number of tables we can search */ 2765 s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */ 2766 u32 current_rate; /* rate_n_flags, uCode API format */ 2767 struct il_rate_scale_data win[RATE_COUNT]; /* rate histories */ 2768 }; 2769 2770 struct il_traffic_load { 2771 unsigned long time_stamp; /* age of the oldest stats */ 2772 u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time 2773 * slice */ 2774 u32 total; /* total num of packets during the 2775 * last TID_MAX_TIME_DIFF */ 2776 u8 queue_count; /* number of queues that has 2777 * been used since the last cleanup */ 2778 u8 head; /* start of the circular buffer */ 2779 }; 2780 2781 /** 2782 * struct il_lq_sta -- driver's rate scaling ilate structure 2783 * 2784 * Pointer to this gets passed back and forth between driver and mac80211. 2785 */ 2786 struct il_lq_sta { 2787 u8 active_tbl; /* idx of active table, range 0-1 */ 2788 u8 enable_counter; /* indicates HT mode */ 2789 u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */ 2790 u8 search_better_tbl; /* 1: currently trying alternate mode */ 2791 s32 last_tpt; 2792 2793 /* The following determine when to search for a new mode */ 2794 u32 table_count_limit; 2795 u32 max_failure_limit; /* # failed frames before new search */ 2796 u32 max_success_limit; /* # successful frames before new search */ 2797 u32 table_count; 2798 u32 total_failed; /* total failed frames, any/all rates */ 2799 u32 total_success; /* total successful frames, any/all rates */ 2800 u64 flush_timer; /* time staying in mode before new search */ 2801 2802 u8 action_counter; /* # mode-switch actions tried */ 2803 u8 is_green; 2804 u8 is_dup; 2805 enum nl80211_band band; 2806 2807 /* The following are bitmaps of rates; RATE_6M_MASK, etc. */ 2808 u32 supp_rates; 2809 u16 active_legacy_rate; 2810 u16 active_siso_rate; 2811 u16 active_mimo2_rate; 2812 s8 max_rate_idx; /* Max rate set by user */ 2813 u8 missed_rate_counter; 2814 2815 struct il_link_quality_cmd lq; 2816 struct il_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */ 2817 struct il_traffic_load load[TID_MAX_LOAD_COUNT]; 2818 u8 tx_agg_tid_en; 2819 #ifdef CONFIG_MAC80211_DEBUGFS 2820 u32 dbg_fixed_rate; 2821 #endif 2822 struct il_priv *drv; 2823 2824 /* used to be in sta_info */ 2825 int last_txrate_idx; 2826 /* last tx rate_n_flags */ 2827 u32 last_rate_n_flags; 2828 /* packets destined for this STA are aggregated */ 2829 u8 is_agg; 2830 }; 2831 2832 /* 2833 * il_station_priv: Driver's ilate station information 2834 * 2835 * When mac80211 creates a station it reserves some space (hw->sta_data_size) 2836 * in the structure for use by driver. This structure is places in that 2837 * space. 2838 * 2839 * The common struct MUST be first because it is shared between 2840 * 3945 and 4965! 2841 */ 2842 struct il_station_priv { 2843 struct il_station_priv_common common; 2844 struct il_lq_sta lq_sta; 2845 atomic_t pending_frames; 2846 bool client; 2847 bool asleep; 2848 }; 2849 2850 static inline u8 2851 il4965_num_of_ant(u8 m) 2852 { 2853 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C); 2854 } 2855 2856 static inline u8 2857 il4965_first_antenna(u8 mask) 2858 { 2859 if (mask & ANT_A) 2860 return ANT_A; 2861 if (mask & ANT_B) 2862 return ANT_B; 2863 return ANT_C; 2864 } 2865 2866 /** 2867 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info 2868 * 2869 * The specific throughput table used is based on the type of network 2870 * the associated with, including A, B, G, and G w/ TGG protection 2871 */ 2872 void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id); 2873 2874 /* Initialize station's rate scaling information after adding station */ 2875 void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta, 2876 u8 sta_id); 2877 void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta, 2878 u8 sta_id); 2879 2880 /** 2881 * il_rate_control_register - Register the rate control algorithm callbacks 2882 * 2883 * Since the rate control algorithm is hardware specific, there is no need 2884 * or reason to place it as a stand alone module. The driver can call 2885 * il_rate_control_register in order to register the rate control callbacks 2886 * with the mac80211 subsystem. This should be performed prior to calling 2887 * ieee80211_register_hw 2888 * 2889 */ 2890 int il4965_rate_control_register(void); 2891 int il3945_rate_control_register(void); 2892 2893 /** 2894 * il_rate_control_unregister - Unregister the rate control callbacks 2895 * 2896 * This should be called after calling ieee80211_unregister_hw, but before 2897 * the driver is unloaded. 2898 */ 2899 void il4965_rate_control_unregister(void); 2900 void il3945_rate_control_unregister(void); 2901 2902 int il_power_update_mode(struct il_priv *il, bool force); 2903 void il_power_initialize(struct il_priv *il); 2904 2905 extern u32 il_debug_level; 2906 2907 #ifdef CONFIG_IWLEGACY_DEBUG 2908 /* 2909 * il_get_debug_level: Return active debug level for device 2910 * 2911 * Using sysfs it is possible to set per device debug level. This debug 2912 * level will be used if set, otherwise the global debug level which can be 2913 * set via module parameter is used. 2914 */ 2915 static inline u32 2916 il_get_debug_level(struct il_priv *il) 2917 { 2918 if (il->debug_level) 2919 return il->debug_level; 2920 else 2921 return il_debug_level; 2922 } 2923 #else 2924 static inline u32 2925 il_get_debug_level(struct il_priv *il) 2926 { 2927 return il_debug_level; 2928 } 2929 #endif 2930 2931 #define il_print_hex_error(il, p, len) \ 2932 do { \ 2933 print_hex_dump(KERN_ERR, "iwl data: ", \ 2934 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \ 2935 } while (0) 2936 2937 #ifdef CONFIG_IWLEGACY_DEBUG 2938 #define IL_DBG(level, fmt, args...) \ 2939 do { \ 2940 if (il_get_debug_level(il) & level) \ 2941 dev_err(&il->hw->wiphy->dev, "%s " fmt, __func__, \ 2942 ##args); \ 2943 } while (0) 2944 2945 #define il_print_hex_dump(il, level, p, len) \ 2946 do { \ 2947 if (il_get_debug_level(il) & level) \ 2948 print_hex_dump(KERN_DEBUG, "iwl data: ", \ 2949 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \ 2950 } while (0) 2951 2952 #else 2953 #define IL_DBG(level, fmt, args...) no_printk(fmt, ##args) 2954 static inline void 2955 il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len) 2956 { 2957 } 2958 #endif /* CONFIG_IWLEGACY_DEBUG */ 2959 2960 #ifdef CONFIG_IWLEGACY_DEBUGFS 2961 void il_dbgfs_register(struct il_priv *il, const char *name); 2962 void il_dbgfs_unregister(struct il_priv *il); 2963 #else 2964 static inline void il_dbgfs_register(struct il_priv *il, const char *name) 2965 { 2966 } 2967 2968 static inline void 2969 il_dbgfs_unregister(struct il_priv *il) 2970 { 2971 } 2972 #endif /* CONFIG_IWLEGACY_DEBUGFS */ 2973 2974 /* 2975 * To use the debug system: 2976 * 2977 * If you are defining a new debug classification, simply add it to the #define 2978 * list here in the form of 2979 * 2980 * #define IL_DL_xxxx VALUE 2981 * 2982 * where xxxx should be the name of the classification (for example, WEP). 2983 * 2984 * You then need to either add a IL_xxxx_DEBUG() macro definition for your 2985 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want 2986 * to send output to that classification. 2987 * 2988 * The active debug levels can be accessed via files 2989 * 2990 * /sys/module/iwl4965/parameters/debug 2991 * /sys/module/iwl3945/parameters/debug 2992 * /sys/class/net/wlan0/device/debug_level 2993 * 2994 * when CONFIG_IWLEGACY_DEBUG=y. 2995 */ 2996 2997 /* 0x0000000F - 0x00000001 */ 2998 #define IL_DL_INFO (1 << 0) 2999 #define IL_DL_MAC80211 (1 << 1) 3000 #define IL_DL_HCMD (1 << 2) 3001 #define IL_DL_STATE (1 << 3) 3002 /* 0x000000F0 - 0x00000010 */ 3003 #define IL_DL_MACDUMP (1 << 4) 3004 #define IL_DL_HCMD_DUMP (1 << 5) 3005 #define IL_DL_EEPROM (1 << 6) 3006 #define IL_DL_RADIO (1 << 7) 3007 /* 0x00000F00 - 0x00000100 */ 3008 #define IL_DL_POWER (1 << 8) 3009 #define IL_DL_TEMP (1 << 9) 3010 #define IL_DL_NOTIF (1 << 10) 3011 #define IL_DL_SCAN (1 << 11) 3012 /* 0x0000F000 - 0x00001000 */ 3013 #define IL_DL_ASSOC (1 << 12) 3014 #define IL_DL_DROP (1 << 13) 3015 #define IL_DL_TXPOWER (1 << 14) 3016 #define IL_DL_AP (1 << 15) 3017 /* 0x000F0000 - 0x00010000 */ 3018 #define IL_DL_FW (1 << 16) 3019 #define IL_DL_RF_KILL (1 << 17) 3020 #define IL_DL_FW_ERRORS (1 << 18) 3021 #define IL_DL_LED (1 << 19) 3022 /* 0x00F00000 - 0x00100000 */ 3023 #define IL_DL_RATE (1 << 20) 3024 #define IL_DL_CALIB (1 << 21) 3025 #define IL_DL_WEP (1 << 22) 3026 #define IL_DL_TX (1 << 23) 3027 /* 0x0F000000 - 0x01000000 */ 3028 #define IL_DL_RX (1 << 24) 3029 #define IL_DL_ISR (1 << 25) 3030 #define IL_DL_HT (1 << 26) 3031 /* 0xF0000000 - 0x10000000 */ 3032 #define IL_DL_11H (1 << 28) 3033 #define IL_DL_STATS (1 << 29) 3034 #define IL_DL_TX_REPLY (1 << 30) 3035 #define IL_DL_QOS (1 << 31) 3036 3037 #define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a) 3038 #define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a) 3039 #define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a) 3040 #define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a) 3041 #define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a) 3042 #define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a) 3043 #define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a) 3044 #define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a) 3045 #define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a) 3046 #define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a) 3047 #define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a) 3048 #define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a) 3049 #define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a) 3050 #define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a) 3051 #define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a) 3052 #define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a) 3053 #define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a) 3054 #define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a) 3055 #define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a) 3056 #define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a) 3057 #define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a) 3058 #define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a) 3059 #define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a) 3060 #define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a) 3061 #define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a) 3062 #define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a) 3063 #define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a) 3064 #define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a) 3065 #define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a) 3066 3067 #endif /* __il_core_h__ */ 3068