1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 5 * 6 * Contact Information: 7 * Intel Linux Wireless <ilw@linux.intel.com> 8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 9 * 10 *****************************************************************************/ 11 12 #ifndef __il_3945_h__ 13 #define __il_3945_h__ 14 15 #include <linux/pci.h> /* for struct pci_device_id */ 16 #include <linux/kernel.h> 17 #include <net/ieee80211_radiotap.h> 18 19 /* Hardware specific file defines the PCI IDs table for that hardware module */ 20 extern const struct pci_device_id il3945_hw_card_ids[]; 21 22 #include "common.h" 23 24 extern const struct il_ops il3945_ops; 25 26 /* Highest firmware API version supported */ 27 #define IL3945_UCODE_API_MAX 2 28 29 /* Lowest firmware API version supported */ 30 #define IL3945_UCODE_API_MIN 1 31 32 #define IL3945_FW_PRE "iwlwifi-3945-" 33 #define _IL3945_MODULE_FIRMWARE(api) IL3945_FW_PRE #api ".ucode" 34 #define IL3945_MODULE_FIRMWARE(api) _IL3945_MODULE_FIRMWARE(api) 35 36 /* Default noise level to report when noise measurement is not available. 37 * This may be because we're: 38 * 1) Not associated (4965, no beacon stats being sent to driver) 39 * 2) Scanning (noise measurement does not apply to associated channel) 40 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames) 41 * Use default noise value of -127 ... this is below the range of measurable 42 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user. 43 * Also, -127 works better than 0 when averaging frames with/without 44 * noise info (e.g. averaging might be done in app); measured dBm values are 45 * always negative ... using a negative value as the default keeps all 46 * averages within an s8's (used in some apps) range of negative values. */ 47 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127) 48 49 /* Module parameters accessible from iwl-*.c */ 50 extern struct il_mod_params il3945_mod_params; 51 52 struct il3945_rate_scale_data { 53 u64 data; 54 s32 success_counter; 55 s32 success_ratio; 56 s32 counter; 57 s32 average_tpt; 58 unsigned long stamp; 59 }; 60 61 struct il3945_rs_sta { 62 spinlock_t lock; 63 struct il_priv *il; 64 s32 *expected_tpt; 65 unsigned long last_partial_flush; 66 unsigned long last_flush; 67 u32 flush_time; 68 u32 last_tx_packets; 69 u32 tx_packets; 70 u8 tgg; 71 u8 flush_pending; 72 u8 start_rate; 73 struct timer_list rate_scale_flush; 74 struct il3945_rate_scale_data win[RATE_COUNT_3945]; 75 76 /* used to be in sta_info */ 77 int last_txrate_idx; 78 }; 79 80 /* 81 * The common struct MUST be first because it is shared between 82 * 3945 and 4965! 83 */ 84 struct il3945_sta_priv { 85 struct il_station_priv_common common; 86 struct il3945_rs_sta rs_sta; 87 }; 88 89 enum il3945_antenna { 90 IL_ANTENNA_DIVERSITY, 91 IL_ANTENNA_MAIN, 92 IL_ANTENNA_AUX 93 }; 94 95 /* 96 * RTS threshold here is total size [2347] minus 4 FCS bytes 97 * Per spec: 98 * a value of 0 means RTS on all data/management packets 99 * a value > max MSDU size means no RTS 100 * else RTS for data/management frames where MPDU is larger 101 * than RTS value. 102 */ 103 #define DEFAULT_RTS_THRESHOLD 2347U 104 #define MIN_RTS_THRESHOLD 0U 105 #define MAX_RTS_THRESHOLD 2347U 106 #define MAX_MSDU_SIZE 2304U 107 #define MAX_MPDU_SIZE 2346U 108 #define DEFAULT_BEACON_INTERVAL 100U 109 #define DEFAULT_SHORT_RETRY_LIMIT 7U 110 #define DEFAULT_LONG_RETRY_LIMIT 4U 111 112 #define IL_TX_FIFO_AC0 0 113 #define IL_TX_FIFO_AC1 1 114 #define IL_TX_FIFO_AC2 2 115 #define IL_TX_FIFO_AC3 3 116 #define IL_TX_FIFO_HCCA_1 5 117 #define IL_TX_FIFO_HCCA_2 6 118 #define IL_TX_FIFO_NONE 7 119 120 #define IEEE80211_DATA_LEN 2304 121 #define IEEE80211_4ADDR_LEN 30 122 #define IEEE80211_HLEN (IEEE80211_4ADDR_LEN) 123 #define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) 124 125 struct il3945_frame { 126 union { 127 struct ieee80211_hdr frame; 128 struct il3945_tx_beacon_cmd beacon; 129 u8 raw[IEEE80211_FRAME_LEN]; 130 u8 cmd[360]; 131 } u; 132 struct list_head list; 133 }; 134 135 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8 136 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4 137 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12 138 139 #define IL_SUPPORTED_RATES_IE_LEN 8 140 141 #define SCAN_INTERVAL 100 142 143 #define MAX_TID_COUNT 9 144 145 #define IL_INVALID_RATE 0xFF 146 #define IL_INVALID_VALUE -1 147 148 #define STA_PS_STATUS_WAKE 0 149 #define STA_PS_STATUS_SLEEP 1 150 151 struct il3945_ibss_seq { 152 u8 mac[ETH_ALEN]; 153 u16 seq_num; 154 u16 frag_num; 155 unsigned long packet_time; 156 struct list_head list; 157 }; 158 159 #define IL_RX_HDR(x) ((struct il3945_rx_frame_hdr *)(\ 160 container_of(&x->u.rx_frame.stats, \ 161 struct il3945_rx_frame_stats, \ 162 hdr)->payload + \ 163 x->u.rx_frame.stats.phy_count)) 164 #define IL_RX_END(x) ((struct il3945_rx_frame_end *)(\ 165 IL_RX_HDR(x)->payload + \ 166 le16_to_cpu(IL_RX_HDR(x)->len))) 167 #define IL_RX_STATS(x) (&x->u.rx_frame.stats) 168 #define IL_RX_DATA(x) (IL_RX_HDR(x)->payload) 169 170 /****************************************************************************** 171 * 172 * Functions implemented in iwl3945-base.c which are forward declared here 173 * for use by iwl-*.c 174 * 175 *****************************************************************************/ 176 void il3945_rx_replenish(void *data); 177 void il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq); 178 unsigned int il3945_fill_beacon_frame(struct il_priv *il, 179 struct ieee80211_hdr *hdr, int left); 180 int il3945_dump_nic_event_log(struct il_priv *il, bool full_log, char **buf, 181 bool display); 182 void il3945_dump_nic_error_log(struct il_priv *il); 183 184 /****************************************************************************** 185 * 186 * Functions implemented in iwl-[34]*.c which are forward declared here 187 * for use by iwl3945-base.c 188 * 189 * NOTE: The implementation of these functions are hardware specific 190 * which is why they are in the hardware specific files (vs. iwl-base.c) 191 * 192 * Naming convention -- 193 * il3945_ <-- Its part of iwlwifi (should be changed to il3945_) 194 * il3945_hw_ <-- Hardware specific (implemented in iwl-XXXX.c by all HW) 195 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX) 196 * il3945_bg_ <-- Called from work queue context 197 * il3945_mac_ <-- mac80211 callback 198 * 199 ****************************************************************************/ 200 void il3945_hw_handler_setup(struct il_priv *il); 201 void il3945_hw_setup_deferred_work(struct il_priv *il); 202 void il3945_hw_cancel_deferred_work(struct il_priv *il); 203 int il3945_hw_rxq_stop(struct il_priv *il); 204 int il3945_hw_set_hw_params(struct il_priv *il); 205 int il3945_hw_nic_init(struct il_priv *il); 206 int il3945_hw_nic_stop_master(struct il_priv *il); 207 void il3945_hw_txq_ctx_free(struct il_priv *il); 208 void il3945_hw_txq_ctx_stop(struct il_priv *il); 209 int il3945_hw_nic_reset(struct il_priv *il); 210 int il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, 211 dma_addr_t addr, u16 len, u8 reset, u8 pad); 212 void il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq); 213 int il3945_hw_get_temperature(struct il_priv *il); 214 int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq); 215 unsigned int il3945_hw_get_beacon_cmd(struct il_priv *il, 216 struct il3945_frame *frame, u8 rate); 217 void il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd, 218 struct ieee80211_tx_info *info, 219 struct ieee80211_hdr *hdr, int sta_id); 220 int il3945_hw_reg_send_txpower(struct il_priv *il); 221 int il3945_hw_reg_set_txpower(struct il_priv *il, s8 power); 222 void il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb); 223 void il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb); 224 void il3945_disable_events(struct il_priv *il); 225 int il4965_get_temperature(const struct il_priv *il); 226 void il3945_post_associate(struct il_priv *il); 227 void il3945_config_ap(struct il_priv *il); 228 229 int il3945_commit_rxon(struct il_priv *il); 230 231 /** 232 * il3945_hw_find_station - Find station id for a given BSSID 233 * @bssid: MAC address of station ID to find 234 * 235 * NOTE: This should not be hardware specific but the code has 236 * not yet been merged into a single common layer for managing the 237 * station tables. 238 */ 239 u8 il3945_hw_find_station(struct il_priv *il, const u8 *bssid); 240 241 __le32 il3945_get_antenna_flags(const struct il_priv *il); 242 int il3945_init_hw_rate_table(struct il_priv *il); 243 void il3945_reg_txpower_periodic(struct il_priv *il); 244 int il3945_txpower_set_from_eeprom(struct il_priv *il); 245 246 int il3945_rs_next_rate(struct il_priv *il, int rate); 247 248 /* scanning */ 249 int il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif); 250 void il3945_post_scan(struct il_priv *il); 251 252 /* rates */ 253 extern const struct il3945_rate_info il3945_rates[RATE_COUNT_3945]; 254 255 /* RSSI to dBm */ 256 #define IL39_RSSI_OFFSET 95 257 258 /* 259 * EEPROM related constants, enums, and structures. 260 */ 261 #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) 262 263 /* 264 * Mapping of a Tx power level, at factory calibration temperature, 265 * to a radio/DSP gain table idx. 266 * One for each of 5 "sample" power levels in each band. 267 * v_det is measured at the factory, using the 3945's built-in power amplifier 268 * (PA) output voltage detector. This same detector is used during Tx of 269 * long packets in normal operation to provide feedback as to proper output 270 * level. 271 * Data copied from EEPROM. 272 * DO NOT ALTER THIS STRUCTURE!!! 273 */ 274 struct il3945_eeprom_txpower_sample { 275 u8 gain_idx; /* idx into power (gain) setup table ... */ 276 s8 power; /* ... for this pwr level for this chnl group */ 277 u16 v_det; /* PA output voltage */ 278 } __packed; 279 280 /* 281 * Mappings of Tx power levels -> nominal radio/DSP gain table idxes. 282 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). 283 * Tx power setup code interpolates between the 5 "sample" power levels 284 * to determine the nominal setup for a requested power level. 285 * Data copied from EEPROM. 286 * DO NOT ALTER THIS STRUCTURE!!! 287 */ 288 struct il3945_eeprom_txpower_group { 289 struct il3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ 290 s32 a, b, c, d, e; /* coefficients for voltage->power 291 * formula (signed) */ 292 s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on 293 * frequency (signed) */ 294 s8 saturation_power; /* highest power possible by h/w in this 295 * band */ 296 u8 group_channel; /* "representative" channel # in this band */ 297 s16 temperature; /* h/w temperature at factory calib this band 298 * (signed) */ 299 } __packed; 300 301 /* 302 * Temperature-based Tx-power compensation data, not band-specific. 303 * These coefficients are use to modify a/b/c/d/e coeffs based on 304 * difference between current temperature and factory calib temperature. 305 * Data copied from EEPROM. 306 */ 307 struct il3945_eeprom_temperature_corr { 308 u32 Ta; 309 u32 Tb; 310 u32 Tc; 311 u32 Td; 312 u32 Te; 313 } __packed; 314 315 /* 316 * EEPROM map 317 */ 318 struct il3945_eeprom { 319 u8 reserved0[16]; 320 u16 device_id; /* abs.ofs: 16 */ 321 u8 reserved1[2]; 322 u16 pmc; /* abs.ofs: 20 */ 323 u8 reserved2[20]; 324 u8 mac_address[6]; /* abs.ofs: 42 */ 325 u8 reserved3[58]; 326 u16 board_revision; /* abs.ofs: 106 */ 327 u8 reserved4[11]; 328 u8 board_pba_number[9]; /* abs.ofs: 119 */ 329 u8 reserved5[8]; 330 u16 version; /* abs.ofs: 136 */ 331 u8 sku_cap; /* abs.ofs: 138 */ 332 u8 leds_mode; /* abs.ofs: 139 */ 333 u16 oem_mode; 334 u16 wowlan_mode; /* abs.ofs: 142 */ 335 u16 leds_time_interval; /* abs.ofs: 144 */ 336 u8 leds_off_time; /* abs.ofs: 146 */ 337 u8 leds_on_time; /* abs.ofs: 147 */ 338 u8 almgor_m_version; /* abs.ofs: 148 */ 339 u8 antenna_switch_type; /* abs.ofs: 149 */ 340 u8 reserved6[42]; 341 u8 sku_id[4]; /* abs.ofs: 192 */ 342 343 /* 344 * Per-channel regulatory data. 345 * 346 * Each channel that *might* be supported by 3945 has a fixed location 347 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory 348 * txpower (MSB). 349 * 350 * Entries immediately below are for 20 MHz channel width. 351 * 352 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 353 */ 354 u16 band_1_count; /* abs.ofs: 196 */ 355 struct il_eeprom_channel band_1_channels[14]; /* abs.ofs: 198 */ 356 357 /* 358 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, 359 * 5.0 GHz channels 7, 8, 11, 12, 16 360 * (4915-5080MHz) (none of these is ever supported) 361 */ 362 u16 band_2_count; /* abs.ofs: 226 */ 363 struct il_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ 364 365 /* 366 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 367 * (5170-5320MHz) 368 */ 369 u16 band_3_count; /* abs.ofs: 254 */ 370 struct il_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ 371 372 /* 373 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 374 * (5500-5700MHz) 375 */ 376 u16 band_4_count; /* abs.ofs: 280 */ 377 struct il_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ 378 379 /* 380 * 5.7 GHz channels 145, 149, 153, 157, 161, 165 381 * (5725-5825MHz) 382 */ 383 u16 band_5_count; /* abs.ofs: 304 */ 384 struct il_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ 385 386 u8 reserved9[194]; 387 388 /* 389 * 3945 Txpower calibration data. 390 */ 391 #define IL_NUM_TX_CALIB_GROUPS 5 392 struct il3945_eeprom_txpower_group groups[IL_NUM_TX_CALIB_GROUPS]; 393 /* abs.ofs: 512 */ 394 struct il3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ 395 u8 reserved16[172]; /* fill out to full 1024 byte block */ 396 } __packed; 397 398 #define IL3945_EEPROM_IMG_SIZE 1024 399 400 /* End of EEPROM */ 401 402 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ 403 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ 404 405 /* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */ 406 #define IL39_NUM_QUEUES 5 407 #define IL39_CMD_QUEUE_NUM 4 408 409 #define IL_DEFAULT_TX_RETRY 15 410 411 /*********************************************/ 412 413 #define RFD_SIZE 4 414 #define NUM_TFD_CHUNKS 4 415 416 #define TFD_CTL_COUNT_SET(n) (n << 24) 417 #define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7) 418 #define TFD_CTL_PAD_SET(n) (n << 28) 419 #define TFD_CTL_PAD_GET(ctl) (ctl >> 28) 420 421 /* Sizes and addresses for instruction and data memory (SRAM) in 422 * 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ 423 #define IL39_RTC_INST_LOWER_BOUND (0x000000) 424 #define IL39_RTC_INST_UPPER_BOUND (0x014000) 425 426 #define IL39_RTC_DATA_LOWER_BOUND (0x800000) 427 #define IL39_RTC_DATA_UPPER_BOUND (0x808000) 428 429 #define IL39_RTC_INST_SIZE (IL39_RTC_INST_UPPER_BOUND - \ 430 IL39_RTC_INST_LOWER_BOUND) 431 #define IL39_RTC_DATA_SIZE (IL39_RTC_DATA_UPPER_BOUND - \ 432 IL39_RTC_DATA_LOWER_BOUND) 433 434 #define IL39_MAX_INST_SIZE IL39_RTC_INST_SIZE 435 #define IL39_MAX_DATA_SIZE IL39_RTC_DATA_SIZE 436 437 /* Size of uCode instruction memory in bootstrap state machine */ 438 #define IL39_MAX_BSM_SIZE IL39_RTC_INST_SIZE 439 440 static inline int 441 il3945_hw_valid_rtc_data_addr(u32 addr) 442 { 443 return (addr >= IL39_RTC_DATA_LOWER_BOUND && 444 addr < IL39_RTC_DATA_UPPER_BOUND); 445 } 446 447 /* Base physical address of il3945_shared is provided to FH39_TSSR_CBB_BASE 448 * and &il3945_shared.rx_read_ptr[0] is provided to FH39_RCSR_RPTR_ADDR(0) */ 449 struct il3945_shared { 450 __le32 tx_base_ptr[8]; 451 } __packed; 452 453 /************************************/ 454 /* iwl3945 Flow Handler Definitions */ 455 /************************************/ 456 457 /** 458 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 459 * Addresses are offsets from device's PCI hardware base address. 460 */ 461 #define FH39_MEM_LOWER_BOUND (0x0800) 462 #define FH39_MEM_UPPER_BOUND (0x1000) 463 464 #define FH39_CBCC_TBL (FH39_MEM_LOWER_BOUND + 0x140) 465 #define FH39_TFDB_TBL (FH39_MEM_LOWER_BOUND + 0x180) 466 #define FH39_RCSR_TBL (FH39_MEM_LOWER_BOUND + 0x400) 467 #define FH39_RSSR_TBL (FH39_MEM_LOWER_BOUND + 0x4c0) 468 #define FH39_TCSR_TBL (FH39_MEM_LOWER_BOUND + 0x500) 469 #define FH39_TSSR_TBL (FH39_MEM_LOWER_BOUND + 0x680) 470 471 /* TFDB (Transmit Frame Buffer Descriptor) */ 472 #define FH39_TFDB(_ch, buf) (FH39_TFDB_TBL + \ 473 ((_ch) * 2 + (buf)) * 0x28) 474 #define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TBL + 0x50 * (_ch)) 475 476 /* CBCC channel is [0,2] */ 477 #define FH39_CBCC(_ch) (FH39_CBCC_TBL + (_ch) * 0x8) 478 #define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00) 479 #define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04) 480 481 /* RCSR channel is [0,2] */ 482 #define FH39_RCSR(_ch) (FH39_RCSR_TBL + (_ch) * 0x40) 483 #define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00) 484 #define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04) 485 #define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20) 486 #define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24) 487 488 #define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0)) 489 490 /* RSSR */ 491 #define FH39_RSSR_CTRL (FH39_RSSR_TBL + 0x000) 492 #define FH39_RSSR_STATUS (FH39_RSSR_TBL + 0x004) 493 494 /* TCSR */ 495 #define FH39_TCSR(_ch) (FH39_TCSR_TBL + (_ch) * 0x20) 496 #define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00) 497 #define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04) 498 #define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08) 499 500 /* TSSR */ 501 #define FH39_TSSR_CBB_BASE (FH39_TSSR_TBL + 0x000) 502 #define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TBL + 0x008) 503 #define FH39_TSSR_TX_STATUS (FH39_TSSR_TBL + 0x010) 504 505 /* DBM */ 506 507 #define FH39_SRVC_CHNL (6) 508 509 #define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) 510 #define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) 511 512 #define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) 513 514 #define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) 515 516 #define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) 517 518 #define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) 519 520 #define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) 521 522 #define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) 523 524 #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 525 #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) 526 527 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) 528 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) 529 530 #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 531 532 #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 533 534 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 535 #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 536 537 #define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) 538 539 #define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) 540 541 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) 542 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) 543 544 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) 545 546 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) 547 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) 548 549 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) 550 #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) 551 552 #define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24) 553 #define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16) 554 555 #define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \ 556 (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \ 557 FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch)) 558 559 #define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 560 561 struct il3945_tfd_tb { 562 __le32 addr; 563 __le32 len; 564 } __packed; 565 566 struct il3945_tfd { 567 __le32 control_flags; 568 struct il3945_tfd_tb tbs[4]; 569 u8 __pad[28]; 570 } __packed; 571 572 #ifdef CONFIG_IWLEGACY_DEBUGFS 573 extern const struct il_debugfs_ops il3945_debugfs_ops; 574 #endif 575 576 #endif 577