xref: /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c (revision ea518afc992032f7570c0a89ac9240b387dc0faf)
1 /*
2  * Copyright (c) 2010 Broadcom Corporation
3  * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
12  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
14  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
15  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
17 
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 
20 #include <linux/pci_ids.h>
21 #include <linux/if_ether.h>
22 #include <net/cfg80211.h>
23 #include <net/mac80211.h>
24 #include <brcm_hw_ids.h>
25 #include <aiutils.h>
26 #include <chipcommon.h>
27 #include "rate.h"
28 #include "scb.h"
29 #include "phy/phy_hal.h"
30 #include "channel.h"
31 #include "antsel.h"
32 #include "stf.h"
33 #include "ampdu.h"
34 #include "mac80211_if.h"
35 #include "ucode_loader.h"
36 #include "main.h"
37 #include "soc.h"
38 #include "dma.h"
39 #include "debug.h"
40 #include "brcms_trace_events.h"
41 
42 /* watchdog timer, in unit of ms */
43 #define TIMER_INTERVAL_WATCHDOG		1000
44 /* radio monitor timer, in unit of ms */
45 #define TIMER_INTERVAL_RADIOCHK		800
46 
47 /* beacon interval, in unit of 1024TU */
48 #define BEACON_INTERVAL_DEFAULT		100
49 
50 /* n-mode support capability */
51 /* 2x2 includes both 1x1 & 2x2 devices
52  * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
53  * control it independently
54  */
55 #define WL_11N_2x2			1
56 #define WL_11N_3x3			3
57 #define WL_11N_4x4			4
58 
59 #define EDCF_ACI_MASK			0x60
60 #define EDCF_ACI_SHIFT			5
61 #define EDCF_ECWMIN_MASK		0x0f
62 #define EDCF_ECWMAX_SHIFT		4
63 #define EDCF_AIFSN_MASK			0x0f
64 #define EDCF_AIFSN_MAX			15
65 #define EDCF_ECWMAX_MASK		0xf0
66 
67 #define EDCF_AC_BE_TXOP_STA		0x0000
68 #define EDCF_AC_BK_TXOP_STA		0x0000
69 #define EDCF_AC_VO_ACI_STA		0x62
70 #define EDCF_AC_VO_ECW_STA		0x32
71 #define EDCF_AC_VI_ACI_STA		0x42
72 #define EDCF_AC_VI_ECW_STA		0x43
73 #define EDCF_AC_BK_ECW_STA		0xA4
74 #define EDCF_AC_VI_TXOP_STA		0x005e
75 #define EDCF_AC_VO_TXOP_STA		0x002f
76 #define EDCF_AC_BE_ACI_STA		0x03
77 #define EDCF_AC_BE_ECW_STA		0xA4
78 #define EDCF_AC_BK_ACI_STA		0x27
79 #define EDCF_AC_VO_TXOP_AP		0x002f
80 
81 #define EDCF_TXOP2USEC(txop)		((txop) << 5)
82 #define EDCF_ECW2CW(exp)		((1 << (exp)) - 1)
83 
84 #define APHY_SYMBOL_TIME		4
85 #define APHY_PREAMBLE_TIME		16
86 #define APHY_SIGNAL_TIME		4
87 #define APHY_SIFS_TIME			16
88 #define APHY_SERVICE_NBITS		16
89 #define APHY_TAIL_NBITS			6
90 #define BPHY_SIFS_TIME			10
91 #define BPHY_PLCP_SHORT_TIME		96
92 
93 #define PREN_PREAMBLE			24
94 #define PREN_MM_EXT			12
95 #define PREN_PREAMBLE_EXT		4
96 
97 #define DOT11_MAC_HDR_LEN		24
98 #define DOT11_ACK_LEN			10
99 #define DOT11_BA_LEN			4
100 #define DOT11_OFDM_SIGNAL_EXTENSION	6
101 #define DOT11_MIN_FRAG_LEN		256
102 #define DOT11_RTS_LEN			16
103 #define DOT11_CTS_LEN			10
104 #define DOT11_BA_BITMAP_LEN		128
105 #define DOT11_MAXNUMFRAGS		16
106 #define DOT11_MAX_FRAG_LEN		2346
107 
108 #define BPHY_PLCP_TIME			192
109 #define RIFS_11N_TIME			2
110 
111 /* length of the BCN template area */
112 #define BCN_TMPL_LEN			512
113 
114 /* brcms_bss_info flag bit values */
115 #define BRCMS_BSS_HT			0x0020	/* BSS is HT (MIMO) capable */
116 
117 /* chip rx buffer offset */
118 #define BRCMS_HWRXOFF			38
119 
120 /* rfdisable delay timer 500 ms, runs of ALP clock */
121 #define RFDISABLE_DEFAULT		10000000
122 
123 #define BRCMS_TEMPSENSE_PERIOD		10	/* 10 second timeout */
124 
125 /* synthpu_dly times in us */
126 #define SYNTHPU_DLY_APHY_US		3700
127 #define SYNTHPU_DLY_BPHY_US		1050
128 #define SYNTHPU_DLY_NPHY_US		2048
129 #define SYNTHPU_DLY_LPPHY_US		300
130 
131 #define ANTCNT				10	/* vanilla M_MAX_ANTCNT val */
132 
133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
134 #define EDCF_SHORT_S			0
135 #define EDCF_SFB_S			4
136 #define EDCF_LONG_S			8
137 #define EDCF_LFB_S			12
138 #define EDCF_SHORT_M			BITFIELD_MASK(4)
139 #define EDCF_SFB_M			BITFIELD_MASK(4)
140 #define EDCF_LONG_M			BITFIELD_MASK(4)
141 #define EDCF_LFB_M			BITFIELD_MASK(4)
142 
143 #define RETRY_SHORT_DEF			7	/* Default Short retry Limit */
144 #define RETRY_SHORT_MAX			255	/* Maximum Short retry Limit */
145 #define RETRY_LONG_DEF			4	/* Default Long retry count */
146 #define RETRY_SHORT_FB			3	/* Short count for fb rate */
147 #define RETRY_LONG_FB			2	/* Long count for fb rate */
148 
149 #define APHY_CWMIN			15
150 #define PHY_CWMAX			1023
151 
152 #define EDCF_AIFSN_MIN			1
153 
154 #define FRAGNUM_MASK			0xF
155 
156 #define APHY_SLOT_TIME			9
157 #define BPHY_SLOT_TIME			20
158 
159 #define WL_SPURAVOID_OFF		0
160 #define WL_SPURAVOID_ON1		1
161 #define WL_SPURAVOID_ON2		2
162 
163 /* invalid core flags, use the saved coreflags */
164 #define BRCMS_USE_COREFLAGS		0xffffffff
165 
166 /* values for PLCPHdr_override */
167 #define BRCMS_PLCP_AUTO			-1
168 #define BRCMS_PLCP_SHORT		0
169 #define BRCMS_PLCP_LONG			1
170 
171 /* values for g_protection_override and n_protection_override */
172 #define BRCMS_PROTECTION_AUTO		-1
173 #define BRCMS_PROTECTION_OFF		0
174 #define BRCMS_PROTECTION_ON		1
175 #define BRCMS_PROTECTION_MMHDR_ONLY	2
176 #define BRCMS_PROTECTION_CTS_ONLY	3
177 
178 /* values for g_protection_control and n_protection_control */
179 #define BRCMS_PROTECTION_CTL_OFF	0
180 #define BRCMS_PROTECTION_CTL_LOCAL	1
181 #define BRCMS_PROTECTION_CTL_OVERLAP	2
182 
183 /* values for n_protection */
184 #define BRCMS_N_PROTECTION_OFF		0
185 #define BRCMS_N_PROTECTION_OPTIONAL	1
186 #define BRCMS_N_PROTECTION_20IN40	2
187 #define BRCMS_N_PROTECTION_MIXEDMODE	3
188 
189 /* values for band specific 40MHz capabilities */
190 #define BRCMS_N_BW_20ALL		0
191 #define BRCMS_N_BW_40ALL		1
192 #define BRCMS_N_BW_20IN2G_40IN5G	2
193 
194 /* bitflags for SGI support (sgi_rx iovar) */
195 #define BRCMS_N_SGI_20			0x01
196 #define BRCMS_N_SGI_40			0x02
197 
198 /* defines used by the nrate iovar */
199 /* MSC in use,indicates b0-6 holds an mcs */
200 #define NRATE_MCS_INUSE			0x00000080
201 /* rate/mcs value */
202 #define NRATE_RATE_MASK			0x0000007f
203 /* stf mode mask: siso, cdd, stbc, sdm */
204 #define NRATE_STF_MASK			0x0000ff00
205 /* stf mode shift */
206 #define NRATE_STF_SHIFT			8
207 /* bit indicate to override mcs only */
208 #define NRATE_OVERRIDE_MCS_ONLY		0x40000000
209 #define NRATE_SGI_MASK			0x00800000	/* sgi mode */
210 #define NRATE_SGI_SHIFT			23		/* sgi mode */
211 #define NRATE_LDPC_CODING		0x00400000	/* adv coding in use */
212 #define NRATE_LDPC_SHIFT		22		/* ldpc shift */
213 
214 #define NRATE_STF_SISO			0		/* stf mode SISO */
215 #define NRATE_STF_CDD			1		/* stf mode CDD */
216 #define NRATE_STF_STBC			2		/* stf mode STBC */
217 #define NRATE_STF_SDM			3		/* stf mode SDM */
218 
219 #define MAX_DMA_SEGS			4
220 
221 /* # of entries in Tx FIFO */
222 #define NTXD				64
223 /* Max # of entries in Rx FIFO based on 4kb page size */
224 #define NRXD				256
225 
226 /* Amount of headroom to leave in Tx FIFO */
227 #define TX_HEADROOM			4
228 
229 /* try to keep this # rbufs posted to the chip */
230 #define NRXBUFPOST			32
231 
232 /* max # frames to process in brcms_c_recv() */
233 #define RXBND				8
234 /* max # tx status to process in wlc_txstatus() */
235 #define TXSBND				8
236 
237 /* brcmu_format_flags() bit description structure */
238 struct brcms_c_bit_desc {
239 	u32 bit;
240 	const char *name;
241 };
242 
243 /*
244  * The following table lists the buffer memory allocated to xmt fifos in HW.
245  * the size is in units of 256bytes(one block), total size is HW dependent
246  * ucode has default fifo partition, sw can overwrite if necessary
247  *
248  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
249  * the twiki is updated before making changes.
250  */
251 
252 /* Starting corerev for the fifo size table */
253 #define XMTFIFOTBL_STARTREV	17
254 
255 struct d11init {
256 	__le16 addr;
257 	__le16 size;
258 	__le32 value;
259 };
260 
261 struct edcf_acparam {
262 	u8 ACI;
263 	u8 ECW;
264 	u16 TXOP;
265 } __packed;
266 
267 /* debug/trace */
268 uint brcm_msg_level;
269 
270 /* TX FIFO number to WME/802.1E Access Category */
271 static const u8 wme_fifo2ac[] = {
272 	IEEE80211_AC_BK,
273 	IEEE80211_AC_BE,
274 	IEEE80211_AC_VI,
275 	IEEE80211_AC_VO,
276 	IEEE80211_AC_BE,
277 	IEEE80211_AC_BE
278 };
279 
280 /* ieee80211 Access Category to TX FIFO number */
281 static const u8 wme_ac2fifo[] = {
282 	TX_AC_VO_FIFO,
283 	TX_AC_VI_FIFO,
284 	TX_AC_BE_FIFO,
285 	TX_AC_BK_FIFO
286 };
287 
288 static const u16 xmtfifo_sz[][NFIFO] = {
289 	/* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
290 	{20, 192, 192, 21, 17, 5},
291 	/* corerev 18: */
292 	{0, 0, 0, 0, 0, 0},
293 	/* corerev 19: */
294 	{0, 0, 0, 0, 0, 0},
295 	/* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
296 	{20, 192, 192, 21, 17, 5},
297 	/* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
298 	{9, 58, 22, 14, 14, 5},
299 	/* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
300 	{20, 192, 192, 21, 17, 5},
301 	/* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
302 	{20, 192, 192, 21, 17, 5},
303 	/* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
304 	{9, 58, 22, 14, 14, 5},
305 	/* corerev 25: */
306 	{0, 0, 0, 0, 0, 0},
307 	/* corerev 26: */
308 	{0, 0, 0, 0, 0, 0},
309 	/* corerev 27: */
310 	{0, 0, 0, 0, 0, 0},
311 	/* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
312 	{9, 58, 22, 14, 14, 5},
313 };
314 
315 #ifdef DEBUG
316 static const char * const fifo_names[] = {
317 	"AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
318 #else
319 static const char fifo_names[6][1];
320 #endif
321 
322 #ifdef DEBUG
323 /* pointer to most recently allocated wl/wlc */
324 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
325 #endif
326 
327 /* Mapping of ieee80211 AC numbers to tx fifos */
328 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
329 	[IEEE80211_AC_VO]	= TX_AC_VO_FIFO,
330 	[IEEE80211_AC_VI]	= TX_AC_VI_FIFO,
331 	[IEEE80211_AC_BE]	= TX_AC_BE_FIFO,
332 	[IEEE80211_AC_BK]	= TX_AC_BK_FIFO,
333 };
334 
335 /* Mapping of tx fifos to ieee80211 AC numbers */
336 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
337 	[TX_AC_BK_FIFO]	= IEEE80211_AC_BK,
338 	[TX_AC_BE_FIFO]	= IEEE80211_AC_BE,
339 	[TX_AC_VI_FIFO]	= IEEE80211_AC_VI,
340 	[TX_AC_VO_FIFO]	= IEEE80211_AC_VO,
341 };
342 
343 static u8 brcms_ac_to_fifo(u8 ac)
344 {
345 	if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
346 		return TX_AC_BE_FIFO;
347 	return ac_to_fifo_mapping[ac];
348 }
349 
350 static u8 brcms_fifo_to_ac(u8 fifo)
351 {
352 	if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
353 		return IEEE80211_AC_BE;
354 	return fifo_to_ac_mapping[fifo];
355 }
356 
357 /* Find basic rate for a given rate */
358 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
359 {
360 	if (is_mcs_rate(rspec))
361 		return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
362 		       .leg_ofdm];
363 	return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
364 }
365 
366 static u16 frametype(u32 rspec, u8 mimoframe)
367 {
368 	if (is_mcs_rate(rspec))
369 		return mimoframe;
370 	return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
371 }
372 
373 /* currently the best mechanism for determining SIFS is the band in use */
374 static u16 get_sifs(struct brcms_band *band)
375 {
376 	return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
377 				 BPHY_SIFS_TIME;
378 }
379 
380 /*
381  * Detect Card removed.
382  * Even checking an sbconfig register read will not false trigger when the core
383  * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
384  * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
385  * reg with fixed 0/1 pattern (some platforms return all 0).
386  * If clocks are present, call the sb routine which will figure out if the
387  * device is removed.
388  */
389 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
390 {
391 	u32 macctrl;
392 
393 	if (!wlc->hw->clk)
394 		return ai_deviceremoved(wlc->hw->sih);
395 	macctrl = bcma_read32(wlc->hw->d11core,
396 			      D11REGOFFS(maccontrol));
397 	return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
398 }
399 
400 /* sum the individual fifo tx pending packet counts */
401 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
402 {
403 	int i;
404 	int pending = 0;
405 
406 	for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
407 		if (wlc->hw->di[i])
408 			pending += dma_txpending(wlc->hw->di[i]);
409 	return pending;
410 }
411 
412 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
413 {
414 	return wlc->pub->_nbands > 1 && !wlc->bandlocked;
415 }
416 
417 static int brcms_chspec_bw(u16 chanspec)
418 {
419 	if (CHSPEC_IS40(chanspec))
420 		return BRCMS_40_MHZ;
421 	if (CHSPEC_IS20(chanspec))
422 		return BRCMS_20_MHZ;
423 
424 	return BRCMS_10_MHZ;
425 }
426 
427 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
428 {
429 	if (cfg == NULL)
430 		return;
431 
432 	kfree(cfg->current_bss);
433 	kfree(cfg);
434 }
435 
436 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
437 {
438 	if (wlc == NULL)
439 		return;
440 
441 	brcms_c_bsscfg_mfree(wlc->bsscfg);
442 	kfree(wlc->pub);
443 	kfree(wlc->modulecb);
444 	kfree(wlc->default_bss);
445 	kfree(wlc->protection);
446 	kfree(wlc->stf);
447 	kfree(wlc->bandstate[0]);
448 	if (wlc->corestate)
449 		kfree(wlc->corestate->macstat_snapshot);
450 	kfree(wlc->corestate);
451 	if (wlc->hw)
452 		kfree(wlc->hw->bandstate[0]);
453 	kfree(wlc->hw);
454 	if (wlc->beacon)
455 		dev_kfree_skb_any(wlc->beacon);
456 	if (wlc->probe_resp)
457 		dev_kfree_skb_any(wlc->probe_resp);
458 
459 	kfree(wlc);
460 }
461 
462 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
463 {
464 	struct brcms_bss_cfg *cfg;
465 
466 	cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
467 	if (cfg == NULL)
468 		goto fail;
469 
470 	cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
471 	if (cfg->current_bss == NULL)
472 		goto fail;
473 
474 	return cfg;
475 
476  fail:
477 	brcms_c_bsscfg_mfree(cfg);
478 	return NULL;
479 }
480 
481 static struct brcms_c_info *
482 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
483 {
484 	struct brcms_c_info *wlc;
485 
486 	wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
487 	if (wlc == NULL) {
488 		*err = 1002;
489 		goto fail;
490 	}
491 
492 	/* allocate struct brcms_c_pub state structure */
493 	wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
494 	if (wlc->pub == NULL) {
495 		*err = 1003;
496 		goto fail;
497 	}
498 	wlc->pub->wlc = wlc;
499 
500 	/* allocate struct brcms_hardware state structure */
501 
502 	wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
503 	if (wlc->hw == NULL) {
504 		*err = 1005;
505 		goto fail;
506 	}
507 	wlc->hw->wlc = wlc;
508 
509 	wlc->hw->bandstate[0] =
510 		kcalloc(MAXBANDS, sizeof(struct brcms_hw_band), GFP_ATOMIC);
511 	if (wlc->hw->bandstate[0] == NULL) {
512 		*err = 1006;
513 		goto fail;
514 	} else {
515 		int i;
516 
517 		for (i = 1; i < MAXBANDS; i++)
518 			wlc->hw->bandstate[i] = (struct brcms_hw_band *)
519 			    ((unsigned long)wlc->hw->bandstate[0] +
520 			     (sizeof(struct brcms_hw_band) * i));
521 	}
522 
523 	wlc->modulecb =
524 		kcalloc(BRCMS_MAXMODULES, sizeof(struct modulecb),
525 			GFP_ATOMIC);
526 	if (wlc->modulecb == NULL) {
527 		*err = 1009;
528 		goto fail;
529 	}
530 
531 	wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
532 	if (wlc->default_bss == NULL) {
533 		*err = 1010;
534 		goto fail;
535 	}
536 
537 	wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
538 	if (wlc->bsscfg == NULL) {
539 		*err = 1011;
540 		goto fail;
541 	}
542 
543 	wlc->protection = kzalloc(sizeof(struct brcms_protection),
544 				  GFP_ATOMIC);
545 	if (wlc->protection == NULL) {
546 		*err = 1016;
547 		goto fail;
548 	}
549 
550 	wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
551 	if (wlc->stf == NULL) {
552 		*err = 1017;
553 		goto fail;
554 	}
555 
556 	wlc->bandstate[0] =
557 		kcalloc(MAXBANDS, sizeof(struct brcms_band), GFP_ATOMIC);
558 	if (wlc->bandstate[0] == NULL) {
559 		*err = 1025;
560 		goto fail;
561 	} else {
562 		int i;
563 
564 		for (i = 1; i < MAXBANDS; i++)
565 			wlc->bandstate[i] = (struct brcms_band *)
566 				((unsigned long)wlc->bandstate[0]
567 				+ (sizeof(struct brcms_band)*i));
568 	}
569 
570 	wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
571 	if (wlc->corestate == NULL) {
572 		*err = 1026;
573 		goto fail;
574 	}
575 
576 	wlc->corestate->macstat_snapshot =
577 		kzalloc(sizeof(struct macstat), GFP_ATOMIC);
578 	if (wlc->corestate->macstat_snapshot == NULL) {
579 		*err = 1027;
580 		goto fail;
581 	}
582 
583 	return wlc;
584 
585  fail:
586 	brcms_c_detach_mfree(wlc);
587 	return NULL;
588 }
589 
590 /*
591  * Update the slot timing for standard 11b/g (20us slots)
592  * or shortslot 11g (9us slots)
593  * The PSM needs to be suspended for this call.
594  */
595 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
596 					bool shortslot)
597 {
598 	struct bcma_device *core = wlc_hw->d11core;
599 
600 	if (shortslot) {
601 		/* 11g short slot: 11a timing */
602 		bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
603 		brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
604 	} else {
605 		/* 11g long slot: 11b timing */
606 		bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
607 		brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
608 	}
609 }
610 
611 /*
612  * calculate frame duration of a given rate and length, return
613  * time in usec unit
614  */
615 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
616 				    u8 preamble_type, uint mac_len)
617 {
618 	uint nsyms, dur = 0, Ndps, kNdps;
619 	uint rate = rspec2rate(ratespec);
620 
621 	if (rate == 0) {
622 		brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
623 			  wlc->pub->unit);
624 		rate = BRCM_RATE_1M;
625 	}
626 
627 	if (is_mcs_rate(ratespec)) {
628 		uint mcs = ratespec & RSPEC_RATE_MASK;
629 		int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
630 
631 		dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
632 		if (preamble_type == BRCMS_MM_PREAMBLE)
633 			dur += PREN_MM_EXT;
634 		/* 1000Ndbps = kbps * 4 */
635 		kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
636 				   rspec_issgi(ratespec)) * 4;
637 
638 		if (rspec_stc(ratespec) == 0)
639 			nsyms =
640 			    CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
641 				  APHY_TAIL_NBITS) * 1000, kNdps);
642 		else
643 			/* STBC needs to have even number of symbols */
644 			nsyms =
645 			    2 *
646 			    CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
647 				  APHY_TAIL_NBITS) * 1000, 2 * kNdps);
648 
649 		dur += APHY_SYMBOL_TIME * nsyms;
650 		if (wlc->band->bandtype == BRCM_BAND_2G)
651 			dur += DOT11_OFDM_SIGNAL_EXTENSION;
652 	} else if (is_ofdm_rate(rate)) {
653 		dur = APHY_PREAMBLE_TIME;
654 		dur += APHY_SIGNAL_TIME;
655 		/* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
656 		Ndps = rate * 2;
657 		/* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
658 		nsyms =
659 		    CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
660 			 Ndps);
661 		dur += APHY_SYMBOL_TIME * nsyms;
662 		if (wlc->band->bandtype == BRCM_BAND_2G)
663 			dur += DOT11_OFDM_SIGNAL_EXTENSION;
664 	} else {
665 		/*
666 		 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
667 		 * will divide out
668 		 */
669 		mac_len = mac_len * 8 * 2;
670 		/* calc ceiling of bits/rate = microseconds of air time */
671 		dur = (mac_len + rate - 1) / rate;
672 		if (preamble_type & BRCMS_SHORT_PREAMBLE)
673 			dur += BPHY_PLCP_SHORT_TIME;
674 		else
675 			dur += BPHY_PLCP_TIME;
676 	}
677 	return dur;
678 }
679 
680 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
681 				const struct d11init *inits)
682 {
683 	struct bcma_device *core = wlc_hw->d11core;
684 	int i;
685 	uint offset;
686 	u16 size;
687 	u32 value;
688 
689 	brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
690 
691 	for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
692 		size = le16_to_cpu(inits[i].size);
693 		offset = le16_to_cpu(inits[i].addr);
694 		value = le32_to_cpu(inits[i].value);
695 		if (size == 2)
696 			bcma_write16(core, offset, value);
697 		else if (size == 4)
698 			bcma_write32(core, offset, value);
699 		else
700 			break;
701 	}
702 }
703 
704 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
705 {
706 	u8 idx;
707 	static const u16 addr[] = {
708 		M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
709 		M_HOST_FLAGS5
710 	};
711 
712 	for (idx = 0; idx < MHFMAX; idx++)
713 		brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
714 }
715 
716 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
717 {
718 	struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
719 
720 	/* init microcode host flags */
721 	brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
722 
723 	/* do band-specific ucode IHR, SHM, and SCR inits */
724 	if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
725 		if (BRCMS_ISNPHY(wlc_hw->band))
726 			brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
727 		else
728 			brcms_err(wlc_hw->d11core,
729 				  "%s: wl%d: unsupported phy in corerev %d\n",
730 				  __func__, wlc_hw->unit,
731 				  wlc_hw->corerev);
732 	} else {
733 		if (D11REV_IS(wlc_hw->corerev, 24)) {
734 			if (BRCMS_ISLCNPHY(wlc_hw->band))
735 				brcms_c_write_inits(wlc_hw,
736 						    ucode->d11lcn0bsinitvals24);
737 			else
738 				brcms_err(wlc_hw->d11core,
739 					  "%s: wl%d: unsupported phy in core rev %d\n",
740 					  __func__, wlc_hw->unit,
741 					  wlc_hw->corerev);
742 		} else {
743 			brcms_err(wlc_hw->d11core,
744 				  "%s: wl%d: unsupported corerev %d\n",
745 				  __func__, wlc_hw->unit, wlc_hw->corerev);
746 		}
747 	}
748 }
749 
750 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
751 {
752 	struct bcma_device *core = wlc_hw->d11core;
753 	u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
754 
755 	bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
756 }
757 
758 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
759 {
760 	brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
761 
762 	wlc_hw->phyclk = clk;
763 
764 	if (OFF == clk) {	/* clear gmode bit, put phy into reset */
765 
766 		brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
767 				   (SICF_PRST | SICF_FGC));
768 		udelay(1);
769 		brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
770 		udelay(1);
771 
772 	} else {		/* take phy out of reset */
773 
774 		brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
775 		udelay(1);
776 		brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
777 		udelay(1);
778 
779 	}
780 }
781 
782 /* low-level band switch utility routine */
783 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
784 {
785 	brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
786 			   bandunit);
787 
788 	wlc_hw->band = wlc_hw->bandstate[bandunit];
789 
790 	/*
791 	 * BMAC_NOTE:
792 	 *   until we eliminate need for wlc->band refs in low level code
793 	 */
794 	wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
795 
796 	/* set gmode core flag */
797 	if (wlc_hw->sbclk && !wlc_hw->noreset) {
798 		u32 gmode = 0;
799 
800 		if (bandunit == 0)
801 			gmode = SICF_GMODE;
802 
803 		brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
804 	}
805 }
806 
807 /* switch to new band but leave it inactive */
808 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
809 {
810 	struct brcms_hardware *wlc_hw = wlc->hw;
811 	u32 macintmask;
812 	u32 macctrl;
813 
814 	brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
815 	macctrl = bcma_read32(wlc_hw->d11core,
816 			      D11REGOFFS(maccontrol));
817 	WARN_ON((macctrl & MCTL_EN_MAC) != 0);
818 
819 	/* disable interrupts */
820 	macintmask = brcms_intrsoff(wlc->wl);
821 
822 	/* radio off */
823 	wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
824 
825 	brcms_b_core_phy_clk(wlc_hw, OFF);
826 
827 	brcms_c_setxband(wlc_hw, bandunit);
828 
829 	return macintmask;
830 }
831 
832 /* process an individual struct tx_status */
833 static bool
834 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
835 {
836 	struct sk_buff *p = NULL;
837 	uint queue = NFIFO;
838 	struct dma_pub *dma = NULL;
839 	struct d11txh *txh = NULL;
840 	struct scb *scb = NULL;
841 	int tx_frame_count;
842 	uint supr_status;
843 	bool lastframe;
844 	struct ieee80211_hdr *h;
845 	struct ieee80211_tx_info *tx_info;
846 	struct ieee80211_tx_rate *txrate;
847 	int i;
848 	bool fatal = true;
849 
850 	trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
851 			     txs->frameid, txs->status, txs->lasttxtime,
852 			     txs->sequence, txs->phyerr, txs->ackphyrxsh);
853 
854 	/* discard intermediate indications for ucode with one legitimate case:
855 	 *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
856 	 *   but the subsequent tx of DATA failed. so it will start rts/cts
857 	 *   from the beginning (resetting the rts transmission count)
858 	 */
859 	if (!(txs->status & TX_STATUS_AMPDU)
860 	    && (txs->status & TX_STATUS_INTERMEDIATE)) {
861 		brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
862 		fatal = false;
863 		goto out;
864 	}
865 
866 	queue = txs->frameid & TXFID_QUEUE_MASK;
867 	if (queue >= NFIFO) {
868 		brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
869 		goto out;
870 	}
871 
872 	dma = wlc->hw->di[queue];
873 
874 	p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
875 	if (p == NULL) {
876 		brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
877 		goto out;
878 	}
879 
880 	txh = (struct d11txh *) (p->data);
881 
882 	if (txs->phyerr)
883 		brcms_dbg_tx(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
884 			     txs->phyerr, txh->MainRates);
885 
886 	if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
887 		brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
888 		goto out;
889 	}
890 	tx_info = IEEE80211_SKB_CB(p);
891 	h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
892 
893 	if (tx_info->rate_driver_data[0])
894 		scb = &wlc->pri_scb;
895 
896 	if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
897 		brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
898 		fatal = false;
899 		goto out;
900 	}
901 
902 	/*
903 	 * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
904 	 * frames; this traces them for the rest.
905 	 */
906 	trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
907 
908 	supr_status = txs->status & TX_STATUS_SUPR_MASK;
909 	if (supr_status == TX_STATUS_SUPR_BADCH) {
910 		unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
911 		brcms_dbg_tx(wlc->hw->d11core,
912 			     "Pkt tx suppressed, dest chan %u, current %d\n",
913 			     (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
914 			     CHSPEC_CHANNEL(wlc->default_bss->chanspec));
915 	}
916 
917 	tx_frame_count =
918 	    (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
919 
920 	lastframe = !ieee80211_has_morefrags(h->frame_control);
921 
922 	if (!lastframe) {
923 		brcms_err(wlc->hw->d11core, "Not last frame!\n");
924 	} else {
925 		/*
926 		 * Set information to be consumed by Minstrel ht.
927 		 *
928 		 * The "fallback limit" is the number of tx attempts a given
929 		 * MPDU is sent at the "primary" rate. Tx attempts beyond that
930 		 * limit are sent at the "secondary" rate.
931 		 * A 'short frame' does not exceed RTS treshold.
932 		 */
933 		u16 sfbl,	/* Short Frame Rate Fallback Limit */
934 		    lfbl,	/* Long Frame Rate Fallback Limit */
935 		    fbl;
936 
937 		if (queue < IEEE80211_NUM_ACS) {
938 			sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
939 				      EDCF_SFB);
940 			lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
941 				      EDCF_LFB);
942 		} else {
943 			sfbl = wlc->SFBL;
944 			lfbl = wlc->LFBL;
945 		}
946 
947 		txrate = tx_info->status.rates;
948 		if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
949 			fbl = lfbl;
950 		else
951 			fbl = sfbl;
952 
953 		ieee80211_tx_info_clear_status(tx_info);
954 
955 		if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
956 			/*
957 			 * rate selection requested a fallback rate
958 			 * and we used it
959 			 */
960 			txrate[0].count = fbl;
961 			txrate[1].count = tx_frame_count - fbl;
962 		} else {
963 			/*
964 			 * rate selection did not request fallback rate, or
965 			 * we didn't need it
966 			 */
967 			txrate[0].count = tx_frame_count;
968 			/*
969 			 * rc80211_minstrel.c:minstrel_tx_status() expects
970 			 * unused rates to be marked with idx = -1
971 			 */
972 			txrate[1].idx = -1;
973 			txrate[1].count = 0;
974 		}
975 
976 		/* clear the rest of the rates */
977 		for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
978 			txrate[i].idx = -1;
979 			txrate[i].count = 0;
980 		}
981 
982 		if (txs->status & TX_STATUS_ACK_RCV)
983 			tx_info->flags |= IEEE80211_TX_STAT_ACK;
984 	}
985 
986 	if (lastframe) {
987 		/* remove PLCP & Broadcom tx descriptor header */
988 		skb_pull(p, D11_PHY_HDR_LEN);
989 		skb_pull(p, D11_TXH_LEN);
990 		ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
991 	} else {
992 		brcms_err(wlc->hw->d11core,
993 			  "%s: Not last frame => not calling tx_status\n",
994 			  __func__);
995 	}
996 
997 	fatal = false;
998 
999  out:
1000 	if (fatal) {
1001 		if (txh)
1002 			trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1003 					   sizeof(*txh));
1004 		brcmu_pkt_buf_free_skb(p);
1005 	}
1006 
1007 	if (dma && queue < NFIFO) {
1008 		u16 ac_queue = brcms_fifo_to_ac(queue);
1009 		if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1010 		    ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1011 			ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1012 		dma_kick_tx(dma);
1013 	}
1014 
1015 	return fatal;
1016 }
1017 
1018 /* process tx completion events in BMAC
1019  * Return true if more tx status need to be processed. false otherwise.
1020  */
1021 static bool
1022 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1023 {
1024 	struct bcma_device *core;
1025 	struct tx_status txstatus, *txs;
1026 	u32 s1, s2;
1027 	uint n = 0;
1028 	/*
1029 	 * Param 'max_tx_num' indicates max. # tx status to process before
1030 	 * break out.
1031 	 */
1032 	uint max_tx_num = bound ? TXSBND : -1;
1033 
1034 	txs = &txstatus;
1035 	core = wlc_hw->d11core;
1036 	*fatal = false;
1037 
1038 	while (n < max_tx_num) {
1039 		s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1040 		if (s1 == 0xffffffff) {
1041 			brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1042 				  __func__);
1043 			*fatal = true;
1044 			return false;
1045 		}
1046 		/* only process when valid */
1047 		if (!(s1 & TXS_V))
1048 			break;
1049 
1050 		s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1051 		txs->status = s1 & TXS_STATUS_MASK;
1052 		txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1053 		txs->sequence = s2 & TXS_SEQ_MASK;
1054 		txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1055 		txs->lasttxtime = 0;
1056 
1057 		*fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1058 		if (*fatal)
1059 			return false;
1060 		n++;
1061 	}
1062 
1063 	return n >= max_tx_num;
1064 }
1065 
1066 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1067 {
1068 	if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
1069 		/*
1070 		 * DirFrmQ is now valid...defer setting until end
1071 		 * of ATIM window
1072 		 */
1073 		wlc->qvalid |= MCMD_DIRFRMQVAL;
1074 }
1075 
1076 /* set initial host flags value */
1077 static void
1078 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1079 {
1080 	struct brcms_hardware *wlc_hw = wlc->hw;
1081 
1082 	memset(mhfs, 0, MHFMAX * sizeof(u16));
1083 
1084 	mhfs[MHF2] |= mhf2_init;
1085 
1086 	/* prohibit use of slowclock on multifunction boards */
1087 	if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1088 		mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1089 
1090 	if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1091 		mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1092 		mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1093 	}
1094 }
1095 
1096 static uint
1097 dmareg(uint direction, uint fifonum)
1098 {
1099 	if (direction == DMA_TX)
1100 		return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1101 	return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1102 }
1103 
1104 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1105 {
1106 	uint i;
1107 	char name[8];
1108 	/*
1109 	 * ucode host flag 2 needed for pio mode, independent of band and fifo
1110 	 */
1111 	u16 pio_mhf2 = 0;
1112 	struct brcms_hardware *wlc_hw = wlc->hw;
1113 	uint unit = wlc_hw->unit;
1114 
1115 	/* name and offsets for dma_attach */
1116 	snprintf(name, sizeof(name), "wl%d", unit);
1117 
1118 	if (wlc_hw->di[0] == NULL) {	/* Init FIFOs */
1119 		int dma_attach_err = 0;
1120 
1121 		/*
1122 		 * FIFO 0
1123 		 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1124 		 * RX: RX_FIFO (RX data packets)
1125 		 */
1126 		wlc_hw->di[0] = dma_attach(name, wlc,
1127 					   (wme ? dmareg(DMA_TX, 0) : 0),
1128 					   dmareg(DMA_RX, 0),
1129 					   (wme ? NTXD : 0), NRXD,
1130 					   RXBUFSZ, -1, NRXBUFPOST,
1131 					   BRCMS_HWRXOFF);
1132 		dma_attach_err |= (NULL == wlc_hw->di[0]);
1133 
1134 		/*
1135 		 * FIFO 1
1136 		 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1137 		 *   (legacy) TX_DATA_FIFO (TX data packets)
1138 		 * RX: UNUSED
1139 		 */
1140 		wlc_hw->di[1] = dma_attach(name, wlc,
1141 					   dmareg(DMA_TX, 1), 0,
1142 					   NTXD, 0, 0, -1, 0, 0);
1143 		dma_attach_err |= (NULL == wlc_hw->di[1]);
1144 
1145 		/*
1146 		 * FIFO 2
1147 		 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1148 		 * RX: UNUSED
1149 		 */
1150 		wlc_hw->di[2] = dma_attach(name, wlc,
1151 					   dmareg(DMA_TX, 2), 0,
1152 					   NTXD, 0, 0, -1, 0, 0);
1153 		dma_attach_err |= (NULL == wlc_hw->di[2]);
1154 		/*
1155 		 * FIFO 3
1156 		 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1157 		 *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1158 		 */
1159 		wlc_hw->di[3] = dma_attach(name, wlc,
1160 					   dmareg(DMA_TX, 3),
1161 					   0, NTXD, 0, 0, -1,
1162 					   0, 0);
1163 		dma_attach_err |= (NULL == wlc_hw->di[3]);
1164 /* Cleaner to leave this as if with AP defined */
1165 
1166 		if (dma_attach_err) {
1167 			brcms_err(wlc_hw->d11core,
1168 				  "wl%d: wlc_attach: dma_attach failed\n",
1169 				  unit);
1170 			return false;
1171 		}
1172 
1173 		/* get pointer to dma engine tx flow control variable */
1174 		for (i = 0; i < NFIFO; i++)
1175 			if (wlc_hw->di[i])
1176 				wlc_hw->txavail[i] =
1177 				    (uint *) dma_getvar(wlc_hw->di[i],
1178 							"&txavail");
1179 	}
1180 
1181 	/* initial ucode host flags */
1182 	brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1183 
1184 	return true;
1185 }
1186 
1187 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1188 {
1189 	uint j;
1190 
1191 	for (j = 0; j < NFIFO; j++) {
1192 		if (wlc_hw->di[j]) {
1193 			dma_detach(wlc_hw->di[j]);
1194 			wlc_hw->di[j] = NULL;
1195 		}
1196 	}
1197 }
1198 
1199 /*
1200  * Initialize brcms_c_info default values ...
1201  * may get overrides later in this function
1202  *  BMAC_NOTES, move low out and resolve the dangling ones
1203  */
1204 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1205 {
1206 	struct brcms_c_info *wlc = wlc_hw->wlc;
1207 
1208 	/* set default sw macintmask value */
1209 	wlc->defmacintmask = DEF_MACINTMASK;
1210 
1211 	/* various 802.11g modes */
1212 	wlc_hw->shortslot = false;
1213 
1214 	wlc_hw->SFBL = RETRY_SHORT_FB;
1215 	wlc_hw->LFBL = RETRY_LONG_FB;
1216 
1217 	/* default mac retry limits */
1218 	wlc_hw->SRL = RETRY_SHORT_DEF;
1219 	wlc_hw->LRL = RETRY_LONG_DEF;
1220 	wlc_hw->chanspec = ch20mhz_chspec(1);
1221 }
1222 
1223 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1224 {
1225 	/* delay before first read of ucode state */
1226 	udelay(40);
1227 
1228 	/* wait until ucode is no longer asleep */
1229 	SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1230 		  DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1231 }
1232 
1233 /* control chip clock to save power, enable dynamic clock or force fast clock */
1234 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1235 {
1236 	if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1237 		/* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1238 		 * on backplane, but mac core will still run on ALP(not HT) when
1239 		 * it enters powersave mode, which means the FCA bit may not be
1240 		 * set. Should wakeup mac if driver wants it to run on HT.
1241 		 */
1242 
1243 		if (wlc_hw->clk) {
1244 			if (mode == BCMA_CLKMODE_FAST) {
1245 				bcma_set32(wlc_hw->d11core,
1246 					   D11REGOFFS(clk_ctl_st),
1247 					   CCS_FORCEHT);
1248 
1249 				udelay(64);
1250 
1251 				SPINWAIT(
1252 				    ((bcma_read32(wlc_hw->d11core,
1253 				      D11REGOFFS(clk_ctl_st)) &
1254 				      CCS_HTAVAIL) == 0),
1255 				      PMU_MAX_TRANSITION_DLY);
1256 				WARN_ON(!(bcma_read32(wlc_hw->d11core,
1257 					D11REGOFFS(clk_ctl_st)) &
1258 					CCS_HTAVAIL));
1259 			} else {
1260 				if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1261 				    (bcma_read32(wlc_hw->d11core,
1262 					D11REGOFFS(clk_ctl_st)) &
1263 					(CCS_FORCEHT | CCS_HTAREQ)))
1264 					SPINWAIT(
1265 					    ((bcma_read32(wlc_hw->d11core,
1266 					      offsetof(struct d11regs,
1267 						       clk_ctl_st)) &
1268 					      CCS_HTAVAIL) == 0),
1269 					      PMU_MAX_TRANSITION_DLY);
1270 				bcma_mask32(wlc_hw->d11core,
1271 					D11REGOFFS(clk_ctl_st),
1272 					~CCS_FORCEHT);
1273 			}
1274 		}
1275 		wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1276 	} else {
1277 
1278 		/* old chips w/o PMU, force HT through cc,
1279 		 * then use FCA to verify mac is running fast clock
1280 		 */
1281 
1282 		wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1283 
1284 		/* check fast clock is available (if core is not in reset) */
1285 		if (wlc_hw->forcefastclk && wlc_hw->clk)
1286 			WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1287 				  SISF_FCLKA));
1288 
1289 		/*
1290 		 * keep the ucode wake bit on if forcefastclk is on since we
1291 		 * do not want ucode to put us back to slow clock when it dozes
1292 		 * for PM mode. Code below matches the wake override bit with
1293 		 * current forcefastclk state. Only setting bit in wake_override
1294 		 * instead of waking ucode immediately since old code had this
1295 		 * behavior. Older code set wlc->forcefastclk but only had the
1296 		 * wake happen if the wakup_ucode work (protected by an up
1297 		 * check) was executed just below.
1298 		 */
1299 		if (wlc_hw->forcefastclk)
1300 			mboolset(wlc_hw->wake_override,
1301 				 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1302 		else
1303 			mboolclr(wlc_hw->wake_override,
1304 				 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1305 	}
1306 }
1307 
1308 /* set or clear ucode host flag bits
1309  * it has an optimization for no-change write
1310  * it only writes through shared memory when the core has clock;
1311  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1312  *
1313  *
1314  * bands values are: BRCM_BAND_AUTO <--- Current band only
1315  *                   BRCM_BAND_5G   <--- 5G band only
1316  *                   BRCM_BAND_2G   <--- 2G band only
1317  *                   BRCM_BAND_ALL  <--- All bands
1318  */
1319 void
1320 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1321 	     int bands)
1322 {
1323 	u16 save;
1324 	u16 addr[MHFMAX] = {
1325 		M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1326 		M_HOST_FLAGS5
1327 	};
1328 	struct brcms_hw_band *band;
1329 
1330 	if ((val & ~mask) || idx >= MHFMAX)
1331 		return; /* error condition */
1332 
1333 	switch (bands) {
1334 		/* Current band only or all bands,
1335 		 * then set the band to current band
1336 		 */
1337 	case BRCM_BAND_AUTO:
1338 	case BRCM_BAND_ALL:
1339 		band = wlc_hw->band;
1340 		break;
1341 	case BRCM_BAND_5G:
1342 		band = wlc_hw->bandstate[BAND_5G_INDEX];
1343 		break;
1344 	case BRCM_BAND_2G:
1345 		band = wlc_hw->bandstate[BAND_2G_INDEX];
1346 		break;
1347 	default:
1348 		band = NULL;	/* error condition */
1349 	}
1350 
1351 	if (band) {
1352 		save = band->mhfs[idx];
1353 		band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1354 
1355 		/* optimization: only write through if changed, and
1356 		 * changed band is the current band
1357 		 */
1358 		if (wlc_hw->clk && (band->mhfs[idx] != save)
1359 		    && (band == wlc_hw->band))
1360 			brcms_b_write_shm(wlc_hw, addr[idx],
1361 					   (u16) band->mhfs[idx]);
1362 	}
1363 
1364 	if (bands == BRCM_BAND_ALL) {
1365 		wlc_hw->bandstate[0]->mhfs[idx] =
1366 		    (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1367 		wlc_hw->bandstate[1]->mhfs[idx] =
1368 		    (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1369 	}
1370 }
1371 
1372 /* set the maccontrol register to desired reset state and
1373  * initialize the sw cache of the register
1374  */
1375 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1376 {
1377 	/* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1378 	wlc_hw->maccontrol = 0;
1379 	wlc_hw->suspended_fifos = 0;
1380 	wlc_hw->wake_override = 0;
1381 	wlc_hw->mute_override = 0;
1382 	brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1383 }
1384 
1385 /*
1386  * write the software state of maccontrol and
1387  * overrides to the maccontrol register
1388  */
1389 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1390 {
1391 	u32 maccontrol = wlc_hw->maccontrol;
1392 
1393 	/* OR in the wake bit if overridden */
1394 	if (wlc_hw->wake_override)
1395 		maccontrol |= MCTL_WAKE;
1396 
1397 	/* set AP and INFRA bits for mute if needed */
1398 	if (wlc_hw->mute_override) {
1399 		maccontrol &= ~(MCTL_AP);
1400 		maccontrol |= MCTL_INFRA;
1401 	}
1402 
1403 	bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1404 		     maccontrol);
1405 }
1406 
1407 /* set or clear maccontrol bits */
1408 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1409 {
1410 	u32 maccontrol;
1411 	u32 new_maccontrol;
1412 
1413 	if (val & ~mask)
1414 		return; /* error condition */
1415 	maccontrol = wlc_hw->maccontrol;
1416 	new_maccontrol = (maccontrol & ~mask) | val;
1417 
1418 	/* if the new maccontrol value is the same as the old, nothing to do */
1419 	if (new_maccontrol == maccontrol)
1420 		return;
1421 
1422 	/* something changed, cache the new value */
1423 	wlc_hw->maccontrol = new_maccontrol;
1424 
1425 	/* write the new values with overrides applied */
1426 	brcms_c_mctrl_write(wlc_hw);
1427 }
1428 
1429 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1430 				 u32 override_bit)
1431 {
1432 	if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1433 		mboolset(wlc_hw->wake_override, override_bit);
1434 		return;
1435 	}
1436 
1437 	mboolset(wlc_hw->wake_override, override_bit);
1438 
1439 	brcms_c_mctrl_write(wlc_hw);
1440 	brcms_b_wait_for_wake(wlc_hw);
1441 }
1442 
1443 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1444 				   u32 override_bit)
1445 {
1446 	mboolclr(wlc_hw->wake_override, override_bit);
1447 
1448 	if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1449 		return;
1450 
1451 	brcms_c_mctrl_write(wlc_hw);
1452 }
1453 
1454 /* When driver needs ucode to stop beaconing, it has to make sure that
1455  * MCTL_AP is clear and MCTL_INFRA is set
1456  * Mode           MCTL_AP        MCTL_INFRA
1457  * AP                1              1
1458  * STA               0              1 <--- This will ensure no beacons
1459  * IBSS              0              0
1460  */
1461 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1462 {
1463 	wlc_hw->mute_override = 1;
1464 
1465 	/* if maccontrol already has AP == 0 and INFRA == 1 without this
1466 	 * override, then there is no change to write
1467 	 */
1468 	if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1469 		return;
1470 
1471 	brcms_c_mctrl_write(wlc_hw);
1472 }
1473 
1474 /* Clear the override on AP and INFRA bits */
1475 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1476 {
1477 	if (wlc_hw->mute_override == 0)
1478 		return;
1479 
1480 	wlc_hw->mute_override = 0;
1481 
1482 	/* if maccontrol already has AP == 0 and INFRA == 1 without this
1483 	 * override, then there is no change to write
1484 	 */
1485 	if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1486 		return;
1487 
1488 	brcms_c_mctrl_write(wlc_hw);
1489 }
1490 
1491 /*
1492  * Write a MAC address to the given match reg offset in the RXE match engine.
1493  */
1494 static void
1495 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1496 		       const u8 *addr)
1497 {
1498 	struct bcma_device *core = wlc_hw->d11core;
1499 	u16 mac_l;
1500 	u16 mac_m;
1501 	u16 mac_h;
1502 
1503 	brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1504 
1505 	mac_l = addr[0] | (addr[1] << 8);
1506 	mac_m = addr[2] | (addr[3] << 8);
1507 	mac_h = addr[4] | (addr[5] << 8);
1508 
1509 	/* enter the MAC addr into the RXE match registers */
1510 	bcma_write16(core, D11REGOFFS(rcm_ctl),
1511 		     RCM_INC_DATA | match_reg_offset);
1512 	bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1513 	bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1514 	bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1515 }
1516 
1517 void
1518 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1519 			    void *buf)
1520 {
1521 	struct bcma_device *core = wlc_hw->d11core;
1522 	u32 word;
1523 	__le32 word_le;
1524 	__be32 word_be;
1525 	bool be_bit;
1526 	brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1527 
1528 	bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1529 
1530 	/* if MCTL_BIGEND bit set in mac control register,
1531 	 * the chip swaps data in fifo, as well as data in
1532 	 * template ram
1533 	 */
1534 	be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1535 
1536 	while (len > 0) {
1537 		memcpy(&word, buf, sizeof(u32));
1538 
1539 		if (be_bit) {
1540 			word_be = cpu_to_be32(word);
1541 			word = *(u32 *)&word_be;
1542 		} else {
1543 			word_le = cpu_to_le32(word);
1544 			word = *(u32 *)&word_le;
1545 		}
1546 
1547 		bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1548 
1549 		buf = (u8 *) buf + sizeof(u32);
1550 		len -= sizeof(u32);
1551 	}
1552 }
1553 
1554 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1555 {
1556 	wlc_hw->band->CWmin = newmin;
1557 
1558 	bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1559 		     OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1560 	(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1561 	bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1562 }
1563 
1564 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1565 {
1566 	wlc_hw->band->CWmax = newmax;
1567 
1568 	bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1569 		     OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1570 	(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1571 	bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1572 }
1573 
1574 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1575 {
1576 	bool fastclk;
1577 
1578 	/* request FAST clock if not on */
1579 	fastclk = wlc_hw->forcefastclk;
1580 	if (!fastclk)
1581 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1582 
1583 	wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1584 
1585 	brcms_b_phy_reset(wlc_hw);
1586 	wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1587 
1588 	/* restore the clk */
1589 	if (!fastclk)
1590 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1591 }
1592 
1593 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1594 {
1595 	u16 v;
1596 	struct brcms_c_info *wlc = wlc_hw->wlc;
1597 	/* update SYNTHPU_DLY */
1598 
1599 	if (BRCMS_ISLCNPHY(wlc->band))
1600 		v = SYNTHPU_DLY_LPPHY_US;
1601 	else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1602 		v = SYNTHPU_DLY_NPHY_US;
1603 	else
1604 		v = SYNTHPU_DLY_BPHY_US;
1605 
1606 	brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1607 }
1608 
1609 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1610 {
1611 	u16 phyctl;
1612 	u16 phytxant = wlc_hw->bmac_phytxant;
1613 	u16 mask = PHY_TXC_ANT_MASK;
1614 
1615 	/* set the Probe Response frame phy control word */
1616 	phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1617 	phyctl = (phyctl & ~mask) | phytxant;
1618 	brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1619 
1620 	/* set the Response (ACK/CTS) frame phy control word */
1621 	phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1622 	phyctl = (phyctl & ~mask) | phytxant;
1623 	brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1624 }
1625 
1626 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1627 					 u8 rate)
1628 {
1629 	uint i;
1630 	u8 plcp_rate = 0;
1631 	struct plcp_signal_rate_lookup {
1632 		u8 rate;
1633 		u8 signal_rate;
1634 	};
1635 	/* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1636 	const struct plcp_signal_rate_lookup rate_lookup[] = {
1637 		{BRCM_RATE_6M, 0xB},
1638 		{BRCM_RATE_9M, 0xF},
1639 		{BRCM_RATE_12M, 0xA},
1640 		{BRCM_RATE_18M, 0xE},
1641 		{BRCM_RATE_24M, 0x9},
1642 		{BRCM_RATE_36M, 0xD},
1643 		{BRCM_RATE_48M, 0x8},
1644 		{BRCM_RATE_54M, 0xC}
1645 	};
1646 
1647 	for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1648 		if (rate == rate_lookup[i].rate) {
1649 			plcp_rate = rate_lookup[i].signal_rate;
1650 			break;
1651 		}
1652 	}
1653 
1654 	/* Find the SHM pointer to the rate table entry by looking in the
1655 	 * Direct-map Table
1656 	 */
1657 	return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1658 }
1659 
1660 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1661 {
1662 	u8 rate;
1663 	u8 rates[8] = {
1664 		BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1665 		BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1666 	};
1667 	u16 entry_ptr;
1668 	u16 pctl1;
1669 	uint i;
1670 
1671 	if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1672 		return;
1673 
1674 	/* walk the phy rate table and update the entries */
1675 	for (i = 0; i < ARRAY_SIZE(rates); i++) {
1676 		rate = rates[i];
1677 
1678 		entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1679 
1680 		/* read the SHM Rate Table entry OFDM PCTL1 values */
1681 		pctl1 =
1682 		    brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1683 
1684 		/* modify the value */
1685 		pctl1 &= ~PHY_TXC1_MODE_MASK;
1686 		pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1687 
1688 		/* Update the SHM Rate Table entry OFDM PCTL1 values */
1689 		brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1690 				   pctl1);
1691 	}
1692 }
1693 
1694 /* band-specific init */
1695 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1696 {
1697 	struct brcms_hardware *wlc_hw = wlc->hw;
1698 
1699 	brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1700 			   wlc_hw->band->bandunit);
1701 
1702 	brcms_c_ucode_bsinit(wlc_hw);
1703 
1704 	wlc_phy_init(wlc_hw->band->pi, chanspec);
1705 
1706 	brcms_c_ucode_txant_set(wlc_hw);
1707 
1708 	/*
1709 	 * cwmin is band-specific, update hardware
1710 	 * with value for current band
1711 	 */
1712 	brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1713 	brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1714 
1715 	brcms_b_update_slot_timing(wlc_hw,
1716 				   wlc_hw->band->bandtype == BRCM_BAND_5G ?
1717 				   true : wlc_hw->shortslot);
1718 
1719 	/* write phytype and phyvers */
1720 	brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1721 	brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1722 
1723 	/*
1724 	 * initialize the txphyctl1 rate table since
1725 	 * shmem is shared between bands
1726 	 */
1727 	brcms_upd_ofdm_pctl1_table(wlc_hw);
1728 
1729 	brcms_b_upd_synthpu(wlc_hw);
1730 }
1731 
1732 /* Perform a soft reset of the PHY PLL */
1733 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1734 {
1735 	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1736 		  ~0, 0);
1737 	udelay(1);
1738 	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1739 		  0x4, 0);
1740 	udelay(1);
1741 	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1742 		  0x4, 4);
1743 	udelay(1);
1744 	ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1745 		  0x4, 0);
1746 	udelay(1);
1747 }
1748 
1749 /* light way to turn on phy clock without reset for NPHY only
1750  *  refer to brcms_b_core_phy_clk for full version
1751  */
1752 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1753 {
1754 	/* support(necessary for NPHY and HYPHY) only */
1755 	if (!BRCMS_ISNPHY(wlc_hw->band))
1756 		return;
1757 
1758 	if (ON == clk)
1759 		brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1760 	else
1761 		brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1762 
1763 }
1764 
1765 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1766 {
1767 	if (ON == clk)
1768 		brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1769 	else
1770 		brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1771 }
1772 
1773 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1774 {
1775 	struct brcms_phy_pub *pih = wlc_hw->band->pi;
1776 	u32 phy_bw_clkbits;
1777 
1778 	brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1779 
1780 	if (pih == NULL)
1781 		return;
1782 
1783 	phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1784 
1785 	/* Specific reset sequence required for NPHY rev 3 and 4 */
1786 	if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1787 	    NREV_LE(wlc_hw->band->phyrev, 4)) {
1788 		/* Set the PHY bandwidth */
1789 		brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1790 
1791 		udelay(1);
1792 
1793 		/* Perform a soft reset of the PHY PLL */
1794 		brcms_b_core_phypll_reset(wlc_hw);
1795 
1796 		/* reset the PHY */
1797 		brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1798 				   (SICF_PRST | SICF_PCLKE));
1799 	} else {
1800 		brcms_b_core_ioctl(wlc_hw,
1801 				   (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1802 				   (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1803 	}
1804 
1805 	udelay(2);
1806 	brcms_b_core_phy_clk(wlc_hw, ON);
1807 
1808 	wlc_phy_anacore(pih, ON);
1809 }
1810 
1811 /* switch to and initialize new band */
1812 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1813 			    u16 chanspec) {
1814 	struct brcms_c_info *wlc = wlc_hw->wlc;
1815 	u32 macintmask;
1816 
1817 	/* Enable the d11 core before accessing it */
1818 	if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1819 		bcma_core_enable(wlc_hw->d11core, 0);
1820 		brcms_c_mctrl_reset(wlc_hw);
1821 	}
1822 
1823 	macintmask = brcms_c_setband_inact(wlc, bandunit);
1824 
1825 	if (!wlc_hw->up)
1826 		return;
1827 
1828 	brcms_b_core_phy_clk(wlc_hw, ON);
1829 
1830 	/* band-specific initializations */
1831 	brcms_b_bsinit(wlc, chanspec);
1832 
1833 	/*
1834 	 * If there are any pending software interrupt bits,
1835 	 * then replace these with a harmless nonzero value
1836 	 * so brcms_c_dpc() will re-enable interrupts when done.
1837 	 */
1838 	if (wlc->macintstatus)
1839 		wlc->macintstatus = MI_DMAINT;
1840 
1841 	/* restore macintmask */
1842 	brcms_intrsrestore(wlc->wl, macintmask);
1843 
1844 	/* ucode should still be suspended.. */
1845 	WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1846 		 MCTL_EN_MAC) != 0);
1847 }
1848 
1849 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1850 {
1851 
1852 	/* reject unsupported corerev */
1853 	if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1854 		wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1855 			  wlc_hw->corerev);
1856 		return false;
1857 	}
1858 
1859 	return true;
1860 }
1861 
1862 /* Validate some board info parameters */
1863 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1864 {
1865 	uint boardrev = wlc_hw->boardrev;
1866 
1867 	/* 4 bits each for board type, major, minor, and tiny version */
1868 	uint brt = (boardrev & 0xf000) >> 12;
1869 	uint b0 = (boardrev & 0xf00) >> 8;
1870 	uint b1 = (boardrev & 0xf0) >> 4;
1871 	uint b2 = boardrev & 0xf;
1872 
1873 	/* voards from other vendors are always considered valid */
1874 	if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1875 		return true;
1876 
1877 	/* do some boardrev sanity checks when boardvendor is Broadcom */
1878 	if (boardrev == 0)
1879 		return false;
1880 
1881 	if (boardrev <= 0xff)
1882 		return true;
1883 
1884 	if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1885 		|| (b2 > 9))
1886 		return false;
1887 
1888 	return true;
1889 }
1890 
1891 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1892 {
1893 	struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1894 
1895 	/* If macaddr exists, use it (Sromrev4, CIS, ...). */
1896 	if (!is_zero_ether_addr(sprom->il0mac)) {
1897 		memcpy(etheraddr, sprom->il0mac, ETH_ALEN);
1898 		return;
1899 	}
1900 
1901 	if (wlc_hw->_nbands > 1)
1902 		memcpy(etheraddr, sprom->et1mac, ETH_ALEN);
1903 	else
1904 		memcpy(etheraddr, sprom->il0mac, ETH_ALEN);
1905 }
1906 
1907 /* power both the pll and external oscillator on/off */
1908 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1909 {
1910 	brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1911 
1912 	/*
1913 	 * dont power down if plldown is false or
1914 	 * we must poll hw radio disable
1915 	 */
1916 	if (!want && wlc_hw->pllreq)
1917 		return;
1918 
1919 	wlc_hw->sbclk = want;
1920 	if (!wlc_hw->sbclk) {
1921 		wlc_hw->clk = false;
1922 		if (wlc_hw->band && wlc_hw->band->pi)
1923 			wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1924 	}
1925 }
1926 
1927 /*
1928  * Return true if radio is disabled, otherwise false.
1929  * hw radio disable signal is an external pin, users activate it asynchronously
1930  * this function could be called when driver is down and w/o clock
1931  * it operates on different registers depending on corerev and boardflag.
1932  */
1933 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1934 {
1935 	bool v, clk, xtal;
1936 	u32 flags = 0;
1937 
1938 	xtal = wlc_hw->sbclk;
1939 	if (!xtal)
1940 		brcms_b_xtal(wlc_hw, ON);
1941 
1942 	/* may need to take core out of reset first */
1943 	clk = wlc_hw->clk;
1944 	if (!clk) {
1945 		/*
1946 		 * mac no longer enables phyclk automatically when driver
1947 		 * accesses phyreg throughput mac. This can be skipped since
1948 		 * only mac reg is accessed below
1949 		 */
1950 		if (D11REV_GE(wlc_hw->corerev, 18))
1951 			flags |= SICF_PCLKE;
1952 
1953 		/*
1954 		 * TODO: test suspend/resume
1955 		 *
1956 		 * AI chip doesn't restore bar0win2 on
1957 		 * hibernation/resume, need sw fixup
1958 		 */
1959 
1960 		bcma_core_enable(wlc_hw->d11core, flags);
1961 		brcms_c_mctrl_reset(wlc_hw);
1962 	}
1963 
1964 	v = ((bcma_read32(wlc_hw->d11core,
1965 			  D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1966 
1967 	/* put core back into reset */
1968 	if (!clk)
1969 		bcma_core_disable(wlc_hw->d11core, 0);
1970 
1971 	if (!xtal)
1972 		brcms_b_xtal(wlc_hw, OFF);
1973 
1974 	return v;
1975 }
1976 
1977 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1978 {
1979 	struct dma_pub *di = wlc_hw->di[fifo];
1980 	return dma_rxreset(di);
1981 }
1982 
1983 /* d11 core reset
1984  *   ensure fask clock during reset
1985  *   reset dma
1986  *   reset d11(out of reset)
1987  *   reset phy(out of reset)
1988  *   clear software macintstatus for fresh new start
1989  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1990  */
1991 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1992 {
1993 	uint i;
1994 	bool fastclk;
1995 
1996 	if (flags == BRCMS_USE_COREFLAGS)
1997 		flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
1998 
1999 	brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2000 
2001 	/* request FAST clock if not on  */
2002 	fastclk = wlc_hw->forcefastclk;
2003 	if (!fastclk)
2004 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2005 
2006 	/* reset the dma engines except first time thru */
2007 	if (bcma_core_is_enabled(wlc_hw->d11core)) {
2008 		for (i = 0; i < NFIFO; i++)
2009 			if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2010 				brcms_err(wlc_hw->d11core, "wl%d: %s: "
2011 					  "dma_txreset[%d]: cannot stop dma\n",
2012 					   wlc_hw->unit, __func__, i);
2013 
2014 		if ((wlc_hw->di[RX_FIFO])
2015 		    && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2016 			brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2017 				  "[%d]: cannot stop dma\n",
2018 				  wlc_hw->unit, __func__, RX_FIFO);
2019 	}
2020 	/* if noreset, just stop the psm and return */
2021 	if (wlc_hw->noreset) {
2022 		wlc_hw->wlc->macintstatus = 0;	/* skip wl_dpc after down */
2023 		brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2024 		return;
2025 	}
2026 
2027 	/*
2028 	 * mac no longer enables phyclk automatically when driver accesses
2029 	 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2030 	 * band->pi is invalid. need to enable PHY CLK
2031 	 */
2032 	if (D11REV_GE(wlc_hw->corerev, 18))
2033 		flags |= SICF_PCLKE;
2034 
2035 	/*
2036 	 * reset the core
2037 	 * In chips with PMU, the fastclk request goes through d11 core
2038 	 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2039 	 *
2040 	 * This adds some delay and we can optimize it by also requesting
2041 	 * fastclk through chipcommon during this period if necessary. But
2042 	 * that has to work coordinate with other driver like mips/arm since
2043 	 * they may touch chipcommon as well.
2044 	 */
2045 	wlc_hw->clk = false;
2046 	bcma_core_enable(wlc_hw->d11core, flags);
2047 	wlc_hw->clk = true;
2048 	if (wlc_hw->band && wlc_hw->band->pi)
2049 		wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2050 
2051 	brcms_c_mctrl_reset(wlc_hw);
2052 
2053 	if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2054 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2055 
2056 	brcms_b_phy_reset(wlc_hw);
2057 
2058 	/* turn on PHY_PLL */
2059 	brcms_b_core_phypll_ctl(wlc_hw, true);
2060 
2061 	/* clear sw intstatus */
2062 	wlc_hw->wlc->macintstatus = 0;
2063 
2064 	/* restore the clk setting */
2065 	if (!fastclk)
2066 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2067 }
2068 
2069 /* txfifo sizes needs to be modified(increased) since the newer cores
2070  * have more memory.
2071  */
2072 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2073 {
2074 	struct bcma_device *core = wlc_hw->d11core;
2075 	u16 fifo_nu;
2076 	u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2077 	u16 txfifo_def, txfifo_def1;
2078 	u16 txfifo_cmd;
2079 
2080 	/* tx fifos start at TXFIFO_START_BLK from the Base address */
2081 	txfifo_startblk = TXFIFO_START_BLK;
2082 
2083 	/* sequence of operations:  reset fifo, set fifo size, reset fifo */
2084 	for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2085 
2086 		txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2087 		txfifo_def = (txfifo_startblk & 0xff) |
2088 		    (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2089 		txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2090 		    ((((txfifo_endblk -
2091 			1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2092 		txfifo_cmd =
2093 		    TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2094 
2095 		bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2096 		bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2097 		bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2098 
2099 		bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2100 
2101 		txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2102 	}
2103 	/*
2104 	 * need to propagate to shm location to be in sync since ucode/hw won't
2105 	 * do this
2106 	 */
2107 	brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2108 			   wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2109 	brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2110 			   wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2111 	brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2112 			   ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2113 			    xmtfifo_sz[TX_AC_BK_FIFO]));
2114 	brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2115 			   ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2116 			    xmtfifo_sz[TX_BCMC_FIFO]));
2117 }
2118 
2119 /* This function is used for changing the tsf frac register
2120  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2121  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2122  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2123  * HTPHY Formula is 2^26/freq(MHz) e.g.
2124  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2125  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2126  * For spuron: 123MHz -> 2^26/123    = 545600.5
2127  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2128  * For spur off: 120MHz -> 2^26/120    = 559240.5
2129  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2130  */
2131 
2132 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2133 {
2134 	struct bcma_device *core = wlc_hw->d11core;
2135 
2136 	if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2137 	    (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2138 		if (spurmode == WL_SPURAVOID_ON2) {	/* 126Mhz */
2139 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2140 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2141 		} else if (spurmode == WL_SPURAVOID_ON1) {	/* 123Mhz */
2142 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2143 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2144 		} else {	/* 120Mhz */
2145 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2146 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2147 		}
2148 	} else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2149 		if (spurmode == WL_SPURAVOID_ON1) {	/* 82Mhz */
2150 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2151 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2152 		} else {	/* 80Mhz */
2153 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2154 			bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2155 		}
2156 	}
2157 }
2158 
2159 void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr)
2160 {
2161 	memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2162 	wlc->bsscfg->type = BRCMS_TYPE_STATION;
2163 }
2164 
2165 void brcms_c_start_ap(struct brcms_c_info *wlc, u8 *addr, const u8 *bssid,
2166 		      u8 *ssid, size_t ssid_len)
2167 {
2168 	brcms_c_set_ssid(wlc, ssid, ssid_len);
2169 
2170 	memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2171 	memcpy(wlc->bsscfg->BSSID, bssid, sizeof(wlc->bsscfg->BSSID));
2172 	wlc->bsscfg->type = BRCMS_TYPE_AP;
2173 
2174 	brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, MCTL_AP | MCTL_INFRA);
2175 }
2176 
2177 void brcms_c_start_adhoc(struct brcms_c_info *wlc, u8 *addr)
2178 {
2179 	memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2180 	wlc->bsscfg->type = BRCMS_TYPE_ADHOC;
2181 
2182 	brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, 0);
2183 }
2184 
2185 /* Initialize GPIOs that are controlled by D11 core */
2186 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2187 {
2188 	struct brcms_hardware *wlc_hw = wlc->hw;
2189 	u32 gc, gm;
2190 
2191 	/* use GPIO select 0 to get all gpio signals from the gpio out reg */
2192 	brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2193 
2194 	/*
2195 	 * Common GPIO setup:
2196 	 *      G0 = LED 0 = WLAN Activity
2197 	 *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2198 	 *      G2 = LED 2 = WLAN 5 GHz Radio State
2199 	 *      G4 = radio disable input (HI enabled, LO disabled)
2200 	 */
2201 
2202 	gc = gm = 0;
2203 
2204 	/* Allocate GPIOs for mimo antenna diversity feature */
2205 	if (wlc_hw->antsel_type == ANTSEL_2x3) {
2206 		/* Enable antenna diversity, use 2x3 mode */
2207 		brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2208 			     MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2209 		brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2210 			     MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2211 
2212 		/* init superswitch control */
2213 		wlc_phy_antsel_init(wlc_hw->band->pi, false);
2214 
2215 	} else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2216 		gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2217 		/*
2218 		 * The board itself is powered by these GPIOs
2219 		 * (when not sending pattern) so set them high
2220 		 */
2221 		bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2222 			   (BOARD_GPIO_12 | BOARD_GPIO_13));
2223 		bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2224 			   (BOARD_GPIO_12 | BOARD_GPIO_13));
2225 
2226 		/* Enable antenna diversity, use 2x4 mode */
2227 		brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2228 			     MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2229 		brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2230 			     BRCM_BAND_ALL);
2231 
2232 		/* Configure the desired clock to be 4Mhz */
2233 		brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2234 				   ANTSEL_CLKDIV_4MHZ);
2235 	}
2236 
2237 	/*
2238 	 * gpio 9 controls the PA. ucode is responsible
2239 	 * for wiggling out and oe
2240 	 */
2241 	if (wlc_hw->boardflags & BFL_PACTRL)
2242 		gm |= gc |= BOARD_GPIO_PACTRL;
2243 
2244 	/* apply to gpiocontrol register */
2245 	bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2246 }
2247 
2248 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2249 			      const __le32 ucode[], const size_t nbytes)
2250 {
2251 	struct bcma_device *core = wlc_hw->d11core;
2252 	uint i;
2253 	uint count;
2254 
2255 	brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2256 
2257 	count = (nbytes / sizeof(u32));
2258 
2259 	bcma_write32(core, D11REGOFFS(objaddr),
2260 		     OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2261 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2262 	for (i = 0; i < count; i++)
2263 		bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2264 
2265 }
2266 
2267 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2268 {
2269 	struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2270 
2271 	if (wlc_hw->ucode_loaded)
2272 		return;
2273 
2274 	if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2275 		if (BRCMS_ISNPHY(wlc_hw->band)) {
2276 			brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2277 					  ucode->bcm43xx_16_mimosz);
2278 			wlc_hw->ucode_loaded = true;
2279 		} else
2280 			brcms_err(wlc_hw->d11core,
2281 				  "%s: wl%d: unsupported phy in corerev %d\n",
2282 				  __func__, wlc_hw->unit, wlc_hw->corerev);
2283 	} else if (D11REV_IS(wlc_hw->corerev, 24)) {
2284 		if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2285 			brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2286 					  ucode->bcm43xx_24_lcnsz);
2287 			wlc_hw->ucode_loaded = true;
2288 		} else {
2289 			brcms_err(wlc_hw->d11core,
2290 				  "%s: wl%d: unsupported phy in corerev %d\n",
2291 				  __func__, wlc_hw->unit, wlc_hw->corerev);
2292 		}
2293 	}
2294 }
2295 
2296 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2297 {
2298 	/* update sw state */
2299 	wlc_hw->bmac_phytxant = phytxant;
2300 
2301 	/* push to ucode if up */
2302 	if (!wlc_hw->up)
2303 		return;
2304 	brcms_c_ucode_txant_set(wlc_hw);
2305 
2306 }
2307 
2308 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2309 {
2310 	return (u16) wlc_hw->wlc->stf->txant;
2311 }
2312 
2313 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2314 {
2315 	wlc_hw->antsel_type = antsel_type;
2316 
2317 	/* Update the antsel type for phy module to use */
2318 	wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2319 }
2320 
2321 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2322 {
2323 	bool fatal = false;
2324 	uint unit;
2325 	uint intstatus, idx;
2326 	struct bcma_device *core = wlc_hw->d11core;
2327 
2328 	unit = wlc_hw->unit;
2329 
2330 	for (idx = 0; idx < NFIFO; idx++) {
2331 		/* read intstatus register and ignore any non-error bits */
2332 		intstatus =
2333 			bcma_read32(core,
2334 				    D11REGOFFS(intctrlregs[idx].intstatus)) &
2335 			I_ERRORS;
2336 		if (!intstatus)
2337 			continue;
2338 
2339 		brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2340 			      unit, idx, intstatus);
2341 
2342 		if (intstatus & I_RO) {
2343 			brcms_err(core, "wl%d: fifo %d: receive fifo "
2344 				  "overflow\n", unit, idx);
2345 			fatal = true;
2346 		}
2347 
2348 		if (intstatus & I_PC) {
2349 			brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2350 				  unit, idx);
2351 			fatal = true;
2352 		}
2353 
2354 		if (intstatus & I_PD) {
2355 			brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2356 				  idx);
2357 			fatal = true;
2358 		}
2359 
2360 		if (intstatus & I_DE) {
2361 			brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2362 				  "error\n", unit, idx);
2363 			fatal = true;
2364 		}
2365 
2366 		if (intstatus & I_RU)
2367 			brcms_err(core, "wl%d: fifo %d: receive descriptor "
2368 				  "underflow\n", idx, unit);
2369 
2370 		if (intstatus & I_XU) {
2371 			brcms_err(core, "wl%d: fifo %d: transmit fifo "
2372 				  "underflow\n", idx, unit);
2373 			fatal = true;
2374 		}
2375 
2376 		if (fatal) {
2377 			brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2378 			break;
2379 		} else
2380 			bcma_write32(core,
2381 				     D11REGOFFS(intctrlregs[idx].intstatus),
2382 				     intstatus);
2383 	}
2384 }
2385 
2386 void brcms_c_intrson(struct brcms_c_info *wlc)
2387 {
2388 	struct brcms_hardware *wlc_hw = wlc->hw;
2389 	wlc->macintmask = wlc->defmacintmask;
2390 	bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2391 }
2392 
2393 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2394 {
2395 	struct brcms_hardware *wlc_hw = wlc->hw;
2396 	u32 macintmask;
2397 
2398 	if (!wlc_hw->clk)
2399 		return 0;
2400 
2401 	macintmask = wlc->macintmask;	/* isr can still happen */
2402 
2403 	bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2404 	(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2405 	udelay(1);		/* ensure int line is no longer driven */
2406 	wlc->macintmask = 0;
2407 
2408 	/* return previous macintmask; resolve race between us and our isr */
2409 	return wlc->macintstatus ? 0 : macintmask;
2410 }
2411 
2412 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2413 {
2414 	struct brcms_hardware *wlc_hw = wlc->hw;
2415 	if (!wlc_hw->clk)
2416 		return;
2417 
2418 	wlc->macintmask = macintmask;
2419 	bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2420 }
2421 
2422 /* assumes that the d11 MAC is enabled */
2423 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2424 				    uint tx_fifo)
2425 {
2426 	u8 fifo = 1 << tx_fifo;
2427 
2428 	/* Two clients of this code, 11h Quiet period and scanning. */
2429 
2430 	/* only suspend if not already suspended */
2431 	if ((wlc_hw->suspended_fifos & fifo) == fifo)
2432 		return;
2433 
2434 	/* force the core awake only if not already */
2435 	if (wlc_hw->suspended_fifos == 0)
2436 		brcms_c_ucode_wake_override_set(wlc_hw,
2437 						BRCMS_WAKE_OVERRIDE_TXFIFO);
2438 
2439 	wlc_hw->suspended_fifos |= fifo;
2440 
2441 	if (wlc_hw->di[tx_fifo]) {
2442 		/*
2443 		 * Suspending AMPDU transmissions in the middle can cause
2444 		 * underflow which may result in mismatch between ucode and
2445 		 * driver so suspend the mac before suspending the FIFO
2446 		 */
2447 		if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2448 			brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2449 
2450 		dma_txsuspend(wlc_hw->di[tx_fifo]);
2451 
2452 		if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2453 			brcms_c_enable_mac(wlc_hw->wlc);
2454 	}
2455 }
2456 
2457 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2458 				   uint tx_fifo)
2459 {
2460 	/* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2461 	 * but need to be done here for PIO otherwise the watchdog will catch
2462 	 * the inconsistency and fire
2463 	 */
2464 	/* Two clients of this code, 11h Quiet period and scanning. */
2465 	if (wlc_hw->di[tx_fifo])
2466 		dma_txresume(wlc_hw->di[tx_fifo]);
2467 
2468 	/* allow core to sleep again */
2469 	if (wlc_hw->suspended_fifos == 0)
2470 		return;
2471 	else {
2472 		wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2473 		if (wlc_hw->suspended_fifos == 0)
2474 			brcms_c_ucode_wake_override_clear(wlc_hw,
2475 						BRCMS_WAKE_OVERRIDE_TXFIFO);
2476 	}
2477 }
2478 
2479 /* precondition: requires the mac core to be enabled */
2480 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2481 {
2482 	static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2483 	u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2484 
2485 	if (mute_tx) {
2486 		/* suspend tx fifos */
2487 		brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2488 		brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2489 		brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2490 		brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2491 
2492 		/* zero the address match register so we do not send ACKs */
2493 		brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2494 	} else {
2495 		/* resume tx fifos */
2496 		brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2497 		brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2498 		brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2499 		brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2500 
2501 		/* Restore address */
2502 		brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2503 	}
2504 
2505 	wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2506 
2507 	if (mute_tx)
2508 		brcms_c_ucode_mute_override_set(wlc_hw);
2509 	else
2510 		brcms_c_ucode_mute_override_clear(wlc_hw);
2511 }
2512 
2513 void
2514 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2515 {
2516 	brcms_b_mute(wlc->hw, mute_tx);
2517 }
2518 
2519 /*
2520  * Read and clear macintmask and macintstatus and intstatus registers.
2521  * This routine should be called with interrupts off
2522  * Return:
2523  *   -1 if brcms_deviceremoved(wlc) evaluates to true;
2524  *   0 if the interrupt is not for us, or we are in some special cases;
2525  *   device interrupt status bits otherwise.
2526  */
2527 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2528 {
2529 	struct brcms_hardware *wlc_hw = wlc->hw;
2530 	struct bcma_device *core = wlc_hw->d11core;
2531 	u32 macintstatus, mask;
2532 
2533 	/* macintstatus includes a DMA interrupt summary bit */
2534 	macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2535 	mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2536 
2537 	trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2538 
2539 	/* detect cardbus removed, in power down(suspend) and in reset */
2540 	if (brcms_deviceremoved(wlc))
2541 		return -1;
2542 
2543 	/* brcms_deviceremoved() succeeds even when the core is still resetting,
2544 	 * handle that case here.
2545 	 */
2546 	if (macintstatus == 0xffffffff)
2547 		return 0;
2548 
2549 	/* defer unsolicited interrupts */
2550 	macintstatus &= mask;
2551 
2552 	/* if not for us */
2553 	if (macintstatus == 0)
2554 		return 0;
2555 
2556 	/* turn off the interrupts */
2557 	bcma_write32(core, D11REGOFFS(macintmask), 0);
2558 	(void)bcma_read32(core, D11REGOFFS(macintmask));
2559 	wlc->macintmask = 0;
2560 
2561 	/* clear device interrupts */
2562 	bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2563 
2564 	/* MI_DMAINT is indication of non-zero intstatus */
2565 	if (macintstatus & MI_DMAINT)
2566 		/*
2567 		 * only fifo interrupt enabled is I_RI in
2568 		 * RX_FIFO. If MI_DMAINT is set, assume it
2569 		 * is set and clear the interrupt.
2570 		 */
2571 		bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2572 			     DEF_RXINTMASK);
2573 
2574 	return macintstatus;
2575 }
2576 
2577 /* Update wlc->macintstatus and wlc->intstatus[]. */
2578 /* Return true if they are updated successfully. false otherwise */
2579 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2580 {
2581 	u32 macintstatus;
2582 
2583 	/* read and clear macintstatus and intstatus registers */
2584 	macintstatus = wlc_intstatus(wlc, false);
2585 
2586 	/* device is removed */
2587 	if (macintstatus == 0xffffffff)
2588 		return false;
2589 
2590 	/* update interrupt status in software */
2591 	wlc->macintstatus |= macintstatus;
2592 
2593 	return true;
2594 }
2595 
2596 /*
2597  * First-level interrupt processing.
2598  * Return true if this was our interrupt
2599  * and if further brcms_c_dpc() processing is required,
2600  * false otherwise.
2601  */
2602 bool brcms_c_isr(struct brcms_c_info *wlc)
2603 {
2604 	struct brcms_hardware *wlc_hw = wlc->hw;
2605 	u32 macintstatus;
2606 
2607 	if (!wlc_hw->up || !wlc->macintmask)
2608 		return false;
2609 
2610 	/* read and clear macintstatus and intstatus registers */
2611 	macintstatus = wlc_intstatus(wlc, true);
2612 
2613 	if (macintstatus == 0xffffffff) {
2614 		brcms_err(wlc_hw->d11core,
2615 			  "DEVICEREMOVED detected in the ISR code path\n");
2616 		return false;
2617 	}
2618 
2619 	/* it is not for us */
2620 	if (macintstatus == 0)
2621 		return false;
2622 
2623 	/* save interrupt status bits */
2624 	wlc->macintstatus = macintstatus;
2625 
2626 	return true;
2627 
2628 }
2629 
2630 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2631 {
2632 	struct brcms_hardware *wlc_hw = wlc->hw;
2633 	struct bcma_device *core = wlc_hw->d11core;
2634 	u32 mc, mi;
2635 
2636 	brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2637 			   wlc_hw->band->bandunit);
2638 
2639 	/*
2640 	 * Track overlapping suspend requests
2641 	 */
2642 	wlc_hw->mac_suspend_depth++;
2643 	if (wlc_hw->mac_suspend_depth > 1)
2644 		return;
2645 
2646 	/* force the core awake */
2647 	brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2648 
2649 	mc = bcma_read32(core, D11REGOFFS(maccontrol));
2650 
2651 	if (mc == 0xffffffff) {
2652 		brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2653 			  __func__);
2654 		brcms_down(wlc->wl);
2655 		return;
2656 	}
2657 	WARN_ON(mc & MCTL_PSM_JMP_0);
2658 	WARN_ON(!(mc & MCTL_PSM_RUN));
2659 	WARN_ON(!(mc & MCTL_EN_MAC));
2660 
2661 	mi = bcma_read32(core, D11REGOFFS(macintstatus));
2662 	if (mi == 0xffffffff) {
2663 		brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2664 			  __func__);
2665 		brcms_down(wlc->wl);
2666 		return;
2667 	}
2668 	WARN_ON(mi & MI_MACSSPNDD);
2669 
2670 	brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2671 
2672 	SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2673 		 BRCMS_MAX_MAC_SUSPEND);
2674 
2675 	if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2676 		brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2677 			  " and MI_MACSSPNDD is still not on.\n",
2678 			  wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2679 		brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2680 			  "psm_brc 0x%04x\n", wlc_hw->unit,
2681 			  bcma_read32(core, D11REGOFFS(psmdebug)),
2682 			  bcma_read32(core, D11REGOFFS(phydebug)),
2683 			  bcma_read16(core, D11REGOFFS(psm_brc)));
2684 	}
2685 
2686 	mc = bcma_read32(core, D11REGOFFS(maccontrol));
2687 	if (mc == 0xffffffff) {
2688 		brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2689 			  __func__);
2690 		brcms_down(wlc->wl);
2691 		return;
2692 	}
2693 	WARN_ON(mc & MCTL_PSM_JMP_0);
2694 	WARN_ON(!(mc & MCTL_PSM_RUN));
2695 	WARN_ON(mc & MCTL_EN_MAC);
2696 }
2697 
2698 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2699 {
2700 	struct brcms_hardware *wlc_hw = wlc->hw;
2701 	struct bcma_device *core = wlc_hw->d11core;
2702 	u32 mc, mi;
2703 
2704 	brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2705 			   wlc->band->bandunit);
2706 
2707 	/*
2708 	 * Track overlapping suspend requests
2709 	 */
2710 	wlc_hw->mac_suspend_depth--;
2711 	if (wlc_hw->mac_suspend_depth > 0)
2712 		return;
2713 
2714 	mc = bcma_read32(core, D11REGOFFS(maccontrol));
2715 	WARN_ON(mc & MCTL_PSM_JMP_0);
2716 	WARN_ON(mc & MCTL_EN_MAC);
2717 	WARN_ON(!(mc & MCTL_PSM_RUN));
2718 
2719 	brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2720 	bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2721 
2722 	mc = bcma_read32(core, D11REGOFFS(maccontrol));
2723 	WARN_ON(mc & MCTL_PSM_JMP_0);
2724 	WARN_ON(!(mc & MCTL_EN_MAC));
2725 	WARN_ON(!(mc & MCTL_PSM_RUN));
2726 
2727 	mi = bcma_read32(core, D11REGOFFS(macintstatus));
2728 	WARN_ON(mi & MI_MACSSPNDD);
2729 
2730 	brcms_c_ucode_wake_override_clear(wlc_hw,
2731 					  BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2732 }
2733 
2734 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2735 {
2736 	wlc_hw->hw_stf_ss_opmode = stf_mode;
2737 
2738 	if (wlc_hw->clk)
2739 		brcms_upd_ofdm_pctl1_table(wlc_hw);
2740 }
2741 
2742 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2743 {
2744 	struct bcma_device *core = wlc_hw->d11core;
2745 	u32 w, val;
2746 	struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2747 
2748 	/* Validate dchip register access */
2749 
2750 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2751 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2752 	w = bcma_read32(core, D11REGOFFS(objdata));
2753 
2754 	/* Can we write and read back a 32bit register? */
2755 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2756 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2757 	bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2758 
2759 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2760 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2761 	val = bcma_read32(core, D11REGOFFS(objdata));
2762 	if (val != (u32) 0xaa5555aa) {
2763 		wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2764 			  "expected 0xaa5555aa\n", wlc_hw->unit, val);
2765 		return false;
2766 	}
2767 
2768 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2769 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2770 	bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2771 
2772 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2773 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2774 	val = bcma_read32(core, D11REGOFFS(objdata));
2775 	if (val != (u32) 0x55aaaa55) {
2776 		wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2777 			  "expected 0x55aaaa55\n", wlc_hw->unit, val);
2778 		return false;
2779 	}
2780 
2781 	bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2782 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2783 	bcma_write32(core, D11REGOFFS(objdata), w);
2784 
2785 	/* clear CFPStart */
2786 	bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2787 
2788 	w = bcma_read32(core, D11REGOFFS(maccontrol));
2789 	if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2790 	    (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2791 		wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2792 			  "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2793 			  (MCTL_IHR_EN | MCTL_WAKE),
2794 			  (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2795 		return false;
2796 	}
2797 
2798 	return true;
2799 }
2800 
2801 #define PHYPLL_WAIT_US	100000
2802 
2803 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2804 {
2805 	struct bcma_device *core = wlc_hw->d11core;
2806 	u32 tmp;
2807 
2808 	brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2809 
2810 	tmp = 0;
2811 
2812 	if (on) {
2813 		if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2814 			bcma_set32(core, D11REGOFFS(clk_ctl_st),
2815 				   CCS_ERSRC_REQ_HT |
2816 				   CCS_ERSRC_REQ_D11PLL |
2817 				   CCS_ERSRC_REQ_PHYPLL);
2818 			SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2819 				  CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2820 				 PHYPLL_WAIT_US);
2821 
2822 			tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2823 			if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2824 				brcms_err(core, "%s: turn on PHY PLL failed\n",
2825 					  __func__);
2826 		} else {
2827 			bcma_set32(core, D11REGOFFS(clk_ctl_st),
2828 				   tmp | CCS_ERSRC_REQ_D11PLL |
2829 				   CCS_ERSRC_REQ_PHYPLL);
2830 			SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2831 				  (CCS_ERSRC_AVAIL_D11PLL |
2832 				   CCS_ERSRC_AVAIL_PHYPLL)) !=
2833 				 (CCS_ERSRC_AVAIL_D11PLL |
2834 				  CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2835 
2836 			tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2837 			if ((tmp &
2838 			     (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2839 			    !=
2840 			    (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2841 				brcms_err(core, "%s: turn on PHY PLL failed\n",
2842 					  __func__);
2843 		}
2844 	} else {
2845 		/*
2846 		 * Since the PLL may be shared, other cores can still
2847 		 * be requesting it; so we'll deassert the request but
2848 		 * not wait for status to comply.
2849 		 */
2850 		bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2851 			    ~CCS_ERSRC_REQ_PHYPLL);
2852 		(void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2853 	}
2854 }
2855 
2856 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2857 {
2858 	bool dev_gone;
2859 
2860 	brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2861 
2862 	dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2863 
2864 	if (dev_gone)
2865 		return;
2866 
2867 	if (wlc_hw->noreset)
2868 		return;
2869 
2870 	/* radio off */
2871 	wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2872 
2873 	/* turn off analog core */
2874 	wlc_phy_anacore(wlc_hw->band->pi, OFF);
2875 
2876 	/* turn off PHYPLL to save power */
2877 	brcms_b_core_phypll_ctl(wlc_hw, false);
2878 
2879 	wlc_hw->clk = false;
2880 	bcma_core_disable(wlc_hw->d11core, 0);
2881 	wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2882 }
2883 
2884 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2885 {
2886 	struct brcms_hardware *wlc_hw = wlc->hw;
2887 	uint i;
2888 
2889 	/* free any posted tx packets */
2890 	for (i = 0; i < NFIFO; i++) {
2891 		if (wlc_hw->di[i]) {
2892 			dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2893 			if (i < TX_BCMC_FIFO)
2894 				ieee80211_wake_queue(wlc->pub->ieee_hw,
2895 						     brcms_fifo_to_ac(i));
2896 		}
2897 	}
2898 
2899 	/* free any posted rx packets */
2900 	dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2901 }
2902 
2903 static u16
2904 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2905 {
2906 	struct bcma_device *core = wlc_hw->d11core;
2907 	u16 objoff = D11REGOFFS(objdata);
2908 
2909 	bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2910 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2911 	if (offset & 2)
2912 		objoff += 2;
2913 
2914 	return bcma_read16(core, objoff);
2915 }
2916 
2917 static void
2918 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2919 		     u32 sel)
2920 {
2921 	struct bcma_device *core = wlc_hw->d11core;
2922 	u16 objoff = D11REGOFFS(objdata);
2923 
2924 	bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2925 	(void)bcma_read32(core, D11REGOFFS(objaddr));
2926 	if (offset & 2)
2927 		objoff += 2;
2928 
2929 	bcma_wflush16(core, objoff, v);
2930 }
2931 
2932 /*
2933  * Read a single u16 from shared memory.
2934  * SHM 'offset' needs to be an even address
2935  */
2936 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2937 {
2938 	return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2939 }
2940 
2941 /*
2942  * Write a single u16 to shared memory.
2943  * SHM 'offset' needs to be an even address
2944  */
2945 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2946 {
2947 	brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2948 }
2949 
2950 /*
2951  * Copy a buffer to shared memory of specified type .
2952  * SHM 'offset' needs to be an even address and
2953  * Buffer length 'len' must be an even number of bytes
2954  * 'sel' selects the type of memory
2955  */
2956 void
2957 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2958 		      const void *buf, int len, u32 sel)
2959 {
2960 	u16 v;
2961 	const u8 *p = (const u8 *)buf;
2962 	int i;
2963 
2964 	if (len <= 0 || (offset & 1) || (len & 1))
2965 		return;
2966 
2967 	for (i = 0; i < len; i += 2) {
2968 		v = p[i] | (p[i + 1] << 8);
2969 		brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2970 	}
2971 }
2972 
2973 /*
2974  * Copy a piece of shared memory of specified type to a buffer .
2975  * SHM 'offset' needs to be an even address and
2976  * Buffer length 'len' must be an even number of bytes
2977  * 'sel' selects the type of memory
2978  */
2979 void
2980 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2981 			 int len, u32 sel)
2982 {
2983 	u16 v;
2984 	u8 *p = (u8 *) buf;
2985 	int i;
2986 
2987 	if (len <= 0 || (offset & 1) || (len & 1))
2988 		return;
2989 
2990 	for (i = 0; i < len; i += 2) {
2991 		v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2992 		p[i] = v & 0xFF;
2993 		p[i + 1] = (v >> 8) & 0xFF;
2994 	}
2995 }
2996 
2997 /* Copy a buffer to shared memory.
2998  * SHM 'offset' needs to be an even address and
2999  * Buffer length 'len' must be an even number of bytes
3000  */
3001 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
3002 			const void *buf, int len)
3003 {
3004 	brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
3005 }
3006 
3007 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3008 				   u16 SRL, u16 LRL)
3009 {
3010 	wlc_hw->SRL = SRL;
3011 	wlc_hw->LRL = LRL;
3012 
3013 	/* write retry limit to SCR, shouldn't need to suspend */
3014 	if (wlc_hw->up) {
3015 		bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3016 			     OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3017 		(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3018 		bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3019 		bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3020 			     OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3021 		(void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3022 		bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3023 	}
3024 }
3025 
3026 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3027 {
3028 	if (set) {
3029 		if (mboolisset(wlc_hw->pllreq, req_bit))
3030 			return;
3031 
3032 		mboolset(wlc_hw->pllreq, req_bit);
3033 
3034 		if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3035 			if (!wlc_hw->sbclk)
3036 				brcms_b_xtal(wlc_hw, ON);
3037 		}
3038 	} else {
3039 		if (!mboolisset(wlc_hw->pllreq, req_bit))
3040 			return;
3041 
3042 		mboolclr(wlc_hw->pllreq, req_bit);
3043 
3044 		if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3045 			if (wlc_hw->sbclk)
3046 				brcms_b_xtal(wlc_hw, OFF);
3047 		}
3048 	}
3049 }
3050 
3051 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3052 {
3053 	wlc_hw->antsel_avail = antsel_avail;
3054 }
3055 
3056 /*
3057  * conditions under which the PM bit should be set in outgoing frames
3058  * and STAY_AWAKE is meaningful
3059  */
3060 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3061 {
3062 	/* not supporting PS so always return false for now */
3063 	return false;
3064 }
3065 
3066 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3067 {
3068 	int i;
3069 	struct macstat *macstats;
3070 #ifdef DEBUG
3071 	u16 delta;
3072 	u16 rxf0ovfl;
3073 	u16 txfunfl[NFIFO];
3074 #endif				/* DEBUG */
3075 
3076 	/* if driver down, make no sense to update stats */
3077 	if (!wlc->pub->up)
3078 		return;
3079 
3080 	macstats = wlc->core->macstat_snapshot;
3081 
3082 #ifdef DEBUG
3083 	/* save last rx fifo 0 overflow count */
3084 	rxf0ovfl = macstats->rxf0ovfl;
3085 
3086 	/* save last tx fifo  underflow count */
3087 	for (i = 0; i < NFIFO; i++)
3088 		txfunfl[i] = macstats->txfunfl[i];
3089 #endif				/* DEBUG */
3090 
3091 	/* Read mac stats from contiguous shared memory */
3092 	brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, macstats,
3093 				sizeof(*macstats), OBJADDR_SHM_SEL);
3094 
3095 #ifdef DEBUG
3096 	/* check for rx fifo 0 overflow */
3097 	delta = (u16)(macstats->rxf0ovfl - rxf0ovfl);
3098 	if (delta)
3099 		brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3100 			  wlc->pub->unit, delta);
3101 
3102 	/* check for tx fifo underflows */
3103 	for (i = 0; i < NFIFO; i++) {
3104 		delta = macstats->txfunfl[i] - txfunfl[i];
3105 		if (delta)
3106 			brcms_err(wlc->hw->d11core,
3107 				  "wl%d: %u tx fifo %d underflows!\n",
3108 				  wlc->pub->unit, delta, i);
3109 	}
3110 #endif				/* DEBUG */
3111 
3112 	/* merge counters from dma module */
3113 	for (i = 0; i < NFIFO; i++) {
3114 		if (wlc->hw->di[i])
3115 			dma_counterreset(wlc->hw->di[i]);
3116 	}
3117 }
3118 
3119 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3120 {
3121 	/* reset the core */
3122 	if (!brcms_deviceremoved(wlc_hw->wlc))
3123 		brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3124 
3125 	/* purge the dma rings */
3126 	brcms_c_flushqueues(wlc_hw->wlc);
3127 }
3128 
3129 void brcms_c_reset(struct brcms_c_info *wlc)
3130 {
3131 	brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3132 
3133 	/* slurp up hw mac counters before core reset */
3134 	brcms_c_statsupd(wlc);
3135 
3136 	/* reset our snapshot of macstat counters */
3137 	memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
3138 
3139 	brcms_b_reset(wlc->hw);
3140 }
3141 
3142 void brcms_c_init_scb(struct scb *scb)
3143 {
3144 	int i;
3145 
3146 	memset(scb, 0, sizeof(struct scb));
3147 	scb->flags = SCB_WMECAP | SCB_HTCAP;
3148 	for (i = 0; i < NUMPRIO; i++) {
3149 		scb->seqnum[i] = 0;
3150 	}
3151 
3152 	scb->magic = SCB_MAGIC;
3153 }
3154 
3155 /* d11 core init
3156  *   reset PSM
3157  *   download ucode/PCM
3158  *   let ucode run to suspended
3159  *   download ucode inits
3160  *   config other core registers
3161  *   init dma
3162  */
3163 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3164 {
3165 	struct brcms_hardware *wlc_hw = wlc->hw;
3166 	struct bcma_device *core = wlc_hw->d11core;
3167 	u32 bcnint_us;
3168 	uint i = 0;
3169 	bool fifosz_fixup = false;
3170 	int err = 0;
3171 	u16 buf[NFIFO];
3172 	struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3173 
3174 	brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3175 
3176 	/* reset PSM */
3177 	brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3178 
3179 	brcms_ucode_download(wlc_hw);
3180 	/*
3181 	 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3182 	 */
3183 	fifosz_fixup = true;
3184 
3185 	/* let the PSM run to the suspended state, set mode to BSS STA */
3186 	bcma_write32(core, D11REGOFFS(macintstatus), -1);
3187 	brcms_b_mctrl(wlc_hw, ~0,
3188 		       (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3189 
3190 	/* wait for ucode to self-suspend after auto-init */
3191 	SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3192 		   MI_MACSSPNDD) == 0), 1000 * 1000);
3193 	if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3194 		brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3195 			  "suspend!\n", wlc_hw->unit);
3196 
3197 	brcms_c_gpio_init(wlc);
3198 
3199 	bcma_aread32(core, BCMA_IOST);
3200 
3201 	if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3202 		if (BRCMS_ISNPHY(wlc_hw->band))
3203 			brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3204 		else
3205 			brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3206 				  " %d\n", __func__, wlc_hw->unit,
3207 				  wlc_hw->corerev);
3208 	} else if (D11REV_IS(wlc_hw->corerev, 24)) {
3209 		if (BRCMS_ISLCNPHY(wlc_hw->band))
3210 			brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3211 		else
3212 			brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3213 				  " %d\n", __func__, wlc_hw->unit,
3214 				  wlc_hw->corerev);
3215 	} else {
3216 		brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3217 			  __func__, wlc_hw->unit, wlc_hw->corerev);
3218 	}
3219 
3220 	/* For old ucode, txfifo sizes needs to be modified(increased) */
3221 	if (fifosz_fixup)
3222 		brcms_b_corerev_fifofixup(wlc_hw);
3223 
3224 	/* check txfifo allocations match between ucode and driver */
3225 	buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3226 	if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3227 		i = TX_AC_BE_FIFO;
3228 		err = -1;
3229 	}
3230 	buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3231 	if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3232 		i = TX_AC_VI_FIFO;
3233 		err = -1;
3234 	}
3235 	buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3236 	buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3237 	buf[TX_AC_BK_FIFO] &= 0xff;
3238 	if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3239 		i = TX_AC_BK_FIFO;
3240 		err = -1;
3241 	}
3242 	if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3243 		i = TX_AC_VO_FIFO;
3244 		err = -1;
3245 	}
3246 	buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3247 	buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3248 	buf[TX_BCMC_FIFO] &= 0xff;
3249 	if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3250 		i = TX_BCMC_FIFO;
3251 		err = -1;
3252 	}
3253 	if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3254 		i = TX_ATIM_FIFO;
3255 		err = -1;
3256 	}
3257 	if (err != 0)
3258 		brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3259 			  " driver size %d index %d\n", buf[i],
3260 			  wlc_hw->xmtfifo_sz[i], i);
3261 
3262 	/* make sure we can still talk to the mac */
3263 	WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3264 
3265 	/* band-specific inits done by wlc_bsinit() */
3266 
3267 	/* Set up frame burst size and antenna swap threshold init values */
3268 	brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3269 	brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3270 
3271 	/* enable one rx interrupt per received frame */
3272 	bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3273 
3274 	/* set the station mode (BSS STA) */
3275 	brcms_b_mctrl(wlc_hw,
3276 		       (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3277 		       (MCTL_INFRA | MCTL_DISCARD_PMQ));
3278 
3279 	/* set up Beacon interval */
3280 	bcnint_us = 0x8000 << 10;
3281 	bcma_write32(core, D11REGOFFS(tsf_cfprep),
3282 		     (bcnint_us << CFPREP_CBI_SHIFT));
3283 	bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3284 	bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3285 
3286 	/* write interrupt mask */
3287 	bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3288 		     DEF_RXINTMASK);
3289 
3290 	/* allow the MAC to control the PHY clock (dynamic on/off) */
3291 	brcms_b_macphyclk_set(wlc_hw, ON);
3292 
3293 	/* program dynamic clock control fast powerup delay register */
3294 	wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3295 	bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3296 
3297 	/* tell the ucode the corerev */
3298 	brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3299 
3300 	/* tell the ucode MAC capabilities */
3301 	brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3302 			   (u16) (wlc_hw->machwcap & 0xffff));
3303 	brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3304 			   (u16) ((wlc_hw->
3305 				      machwcap >> 16) & 0xffff));
3306 
3307 	/* write retry limits to SCR, this done after PSM init */
3308 	bcma_write32(core, D11REGOFFS(objaddr),
3309 		     OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3310 	(void)bcma_read32(core, D11REGOFFS(objaddr));
3311 	bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3312 	bcma_write32(core, D11REGOFFS(objaddr),
3313 		     OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3314 	(void)bcma_read32(core, D11REGOFFS(objaddr));
3315 	bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3316 
3317 	/* write rate fallback retry limits */
3318 	brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3319 	brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3320 
3321 	bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3322 	bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3323 
3324 	/* init the tx dma engines */
3325 	for (i = 0; i < NFIFO; i++) {
3326 		if (wlc_hw->di[i])
3327 			dma_txinit(wlc_hw->di[i]);
3328 	}
3329 
3330 	/* init the rx dma engine(s) and post receive buffers */
3331 	dma_rxinit(wlc_hw->di[RX_FIFO]);
3332 	dma_rxfill(wlc_hw->di[RX_FIFO]);
3333 }
3334 
3335 static void brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec)
3336 {
3337 	u32 macintmask;
3338 	bool fastclk;
3339 	struct brcms_c_info *wlc = wlc_hw->wlc;
3340 
3341 	/* request FAST clock if not on */
3342 	fastclk = wlc_hw->forcefastclk;
3343 	if (!fastclk)
3344 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3345 
3346 	/* disable interrupts */
3347 	macintmask = brcms_intrsoff(wlc->wl);
3348 
3349 	/* set up the specified band and chanspec */
3350 	brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3351 	wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3352 
3353 	/* do one-time phy inits and calibration */
3354 	wlc_phy_cal_init(wlc_hw->band->pi);
3355 
3356 	/* core-specific initialization */
3357 	brcms_b_coreinit(wlc);
3358 
3359 	/* band-specific inits */
3360 	brcms_b_bsinit(wlc, chanspec);
3361 
3362 	/* restore macintmask */
3363 	brcms_intrsrestore(wlc->wl, macintmask);
3364 
3365 	/* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3366 	 * is suspended and brcms_c_enable_mac() will clear this override bit.
3367 	 */
3368 	mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3369 
3370 	/*
3371 	 * initialize mac_suspend_depth to 1 to match ucode
3372 	 * initial suspended state
3373 	 */
3374 	wlc_hw->mac_suspend_depth = 1;
3375 
3376 	/* restore the clk */
3377 	if (!fastclk)
3378 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3379 }
3380 
3381 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3382 				     u16 chanspec)
3383 {
3384 	/* Save our copy of the chanspec */
3385 	wlc->chanspec = chanspec;
3386 
3387 	/* Set the chanspec and power limits for this locale */
3388 	brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3389 
3390 	if (wlc->stf->ss_algosel_auto)
3391 		brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3392 					    chanspec);
3393 
3394 	brcms_c_stf_ss_update(wlc, wlc->band);
3395 }
3396 
3397 static void
3398 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3399 {
3400 	brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3401 		wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3402 		(bool) (wlc->pub->_n_enab & SUPPORT_11N),
3403 		brcms_chspec_bw(wlc->default_bss->chanspec),
3404 		wlc->stf->txstreams);
3405 }
3406 
3407 /* derive wlc->band->basic_rate[] table from 'rateset' */
3408 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3409 			      struct brcms_c_rateset *rateset)
3410 {
3411 	u8 rate;
3412 	u8 mandatory;
3413 	u8 cck_basic = 0;
3414 	u8 ofdm_basic = 0;
3415 	u8 *br = wlc->band->basic_rate;
3416 	uint i;
3417 
3418 	/* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3419 	memset(br, 0, BRCM_MAXRATE + 1);
3420 
3421 	/* For each basic rate in the rates list, make an entry in the
3422 	 * best basic lookup.
3423 	 */
3424 	for (i = 0; i < rateset->count; i++) {
3425 		/* only make an entry for a basic rate */
3426 		if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3427 			continue;
3428 
3429 		/* mask off basic bit */
3430 		rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3431 
3432 		if (rate > BRCM_MAXRATE) {
3433 			brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3434 				  "invalid rate 0x%X in rate set\n",
3435 				  rateset->rates[i]);
3436 			continue;
3437 		}
3438 
3439 		br[rate] = rate;
3440 	}
3441 
3442 	/* The rate lookup table now has non-zero entries for each
3443 	 * basic rate, equal to the basic rate: br[basicN] = basicN
3444 	 *
3445 	 * To look up the best basic rate corresponding to any
3446 	 * particular rate, code can use the basic_rate table
3447 	 * like this
3448 	 *
3449 	 * basic_rate = wlc->band->basic_rate[tx_rate]
3450 	 *
3451 	 * Make sure there is a best basic rate entry for
3452 	 * every rate by walking up the table from low rates
3453 	 * to high, filling in holes in the lookup table
3454 	 */
3455 
3456 	for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3457 		rate = wlc->band->hw_rateset.rates[i];
3458 
3459 		if (br[rate] != 0) {
3460 			/* This rate is a basic rate.
3461 			 * Keep track of the best basic rate so far by
3462 			 * modulation type.
3463 			 */
3464 			if (is_ofdm_rate(rate))
3465 				ofdm_basic = rate;
3466 			else
3467 				cck_basic = rate;
3468 
3469 			continue;
3470 		}
3471 
3472 		/* This rate is not a basic rate so figure out the
3473 		 * best basic rate less than this rate and fill in
3474 		 * the hole in the table
3475 		 */
3476 
3477 		br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3478 
3479 		if (br[rate] != 0)
3480 			continue;
3481 
3482 		if (is_ofdm_rate(rate)) {
3483 			/*
3484 			 * In 11g and 11a, the OFDM mandatory rates
3485 			 * are 6, 12, and 24 Mbps
3486 			 */
3487 			if (rate >= BRCM_RATE_24M)
3488 				mandatory = BRCM_RATE_24M;
3489 			else if (rate >= BRCM_RATE_12M)
3490 				mandatory = BRCM_RATE_12M;
3491 			else
3492 				mandatory = BRCM_RATE_6M;
3493 		} else {
3494 			/* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3495 			mandatory = rate;
3496 		}
3497 
3498 		br[rate] = mandatory;
3499 	}
3500 }
3501 
3502 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3503 				     u16 chanspec)
3504 {
3505 	struct brcms_c_rateset default_rateset;
3506 	uint parkband;
3507 	uint i, band_order[2];
3508 
3509 	/*
3510 	 * We might have been bandlocked during down and the chip
3511 	 * power-cycled (hibernate). Figure out the right band to park on
3512 	 */
3513 	if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3514 		/* updated in brcms_c_bandlock() */
3515 		parkband = wlc->band->bandunit;
3516 		band_order[0] = band_order[1] = parkband;
3517 	} else {
3518 		/* park on the band of the specified chanspec */
3519 		parkband = chspec_bandunit(chanspec);
3520 
3521 		/* order so that parkband initialize last */
3522 		band_order[0] = parkband ^ 1;
3523 		band_order[1] = parkband;
3524 	}
3525 
3526 	/* make each band operational, software state init */
3527 	for (i = 0; i < wlc->pub->_nbands; i++) {
3528 		uint j = band_order[i];
3529 
3530 		wlc->band = wlc->bandstate[j];
3531 
3532 		brcms_default_rateset(wlc, &default_rateset);
3533 
3534 		/* fill in hw_rate */
3535 		brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3536 				   false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3537 				   (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3538 
3539 		/* init basic rate lookup */
3540 		brcms_c_rate_lookup_init(wlc, &default_rateset);
3541 	}
3542 
3543 	/* sync up phy/radio chanspec */
3544 	brcms_c_set_phy_chanspec(wlc, chanspec);
3545 }
3546 
3547 /*
3548  * Set or clear filtering related maccontrol bits based on
3549  * specified filter flags
3550  */
3551 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3552 {
3553 	u32 promisc_bits = 0;
3554 
3555 	wlc->filter_flags = filter_flags;
3556 
3557 	if (filter_flags & FIF_OTHER_BSS)
3558 		promisc_bits |= MCTL_PROMISC;
3559 
3560 	if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3561 		promisc_bits |= MCTL_BCNS_PROMISC;
3562 
3563 	if (filter_flags & FIF_FCSFAIL)
3564 		promisc_bits |= MCTL_KEEPBADFCS;
3565 
3566 	if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3567 		promisc_bits |= MCTL_KEEPCONTROL;
3568 
3569 	brcms_b_mctrl(wlc->hw,
3570 		MCTL_PROMISC | MCTL_BCNS_PROMISC |
3571 		MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3572 		promisc_bits);
3573 }
3574 
3575 /*
3576  * ucode, hwmac update
3577  *    Channel dependent updates for ucode and hw
3578  */
3579 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3580 {
3581 	/* enable or disable any active IBSSs depending on whether or not
3582 	 * we are on the home channel
3583 	 */
3584 	if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3585 		if (wlc->pub->associated) {
3586 			/*
3587 			 * BMAC_NOTE: This is something that should be fixed
3588 			 * in ucode inits. I think that the ucode inits set
3589 			 * up the bcn templates and shm values with a bogus
3590 			 * beacon. This should not be done in the inits. If
3591 			 * ucode needs to set up a beacon for testing, the
3592 			 * test routines should write it down, not expect the
3593 			 * inits to populate a bogus beacon.
3594 			 */
3595 			if (BRCMS_PHY_11N_CAP(wlc->band))
3596 				brcms_b_write_shm(wlc->hw,
3597 						M_BCN_TXTSF_OFFSET, 0);
3598 		}
3599 	} else {
3600 		/* disable an active IBSS if we are not on the home channel */
3601 	}
3602 }
3603 
3604 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3605 				   u8 basic_rate)
3606 {
3607 	u8 phy_rate, index;
3608 	u8 basic_phy_rate, basic_index;
3609 	u16 dir_table, basic_table;
3610 	u16 basic_ptr;
3611 
3612 	/* Shared memory address for the table we are reading */
3613 	dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3614 
3615 	/* Shared memory address for the table we are writing */
3616 	basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3617 
3618 	/*
3619 	 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3620 	 * the index into the rate table.
3621 	 */
3622 	phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3623 	basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3624 	index = phy_rate & 0xf;
3625 	basic_index = basic_phy_rate & 0xf;
3626 
3627 	/* Find the SHM pointer to the ACK rate entry by looking in the
3628 	 * Direct-map Table
3629 	 */
3630 	basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3631 
3632 	/* Update the SHM BSS-basic-rate-set mapping table with the pointer
3633 	 * to the correct basic rate for the given incoming rate
3634 	 */
3635 	brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3636 }
3637 
3638 static const struct brcms_c_rateset *
3639 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3640 {
3641 	const struct brcms_c_rateset *rs_dflt;
3642 
3643 	if (BRCMS_PHY_11N_CAP(wlc->band)) {
3644 		if (wlc->band->bandtype == BRCM_BAND_5G)
3645 			rs_dflt = &ofdm_mimo_rates;
3646 		else
3647 			rs_dflt = &cck_ofdm_mimo_rates;
3648 	} else if (wlc->band->gmode)
3649 		rs_dflt = &cck_ofdm_rates;
3650 	else
3651 		rs_dflt = &cck_rates;
3652 
3653 	return rs_dflt;
3654 }
3655 
3656 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3657 {
3658 	const struct brcms_c_rateset *rs_dflt;
3659 	struct brcms_c_rateset rs;
3660 	u8 rate, basic_rate;
3661 	uint i;
3662 
3663 	rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3664 
3665 	brcms_c_rateset_copy(rs_dflt, &rs);
3666 	brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3667 
3668 	/* walk the phy rate table and update SHM basic rate lookup table */
3669 	for (i = 0; i < rs.count; i++) {
3670 		rate = rs.rates[i] & BRCMS_RATE_MASK;
3671 
3672 		/* for a given rate brcms_basic_rate returns the rate at
3673 		 * which a response ACK/CTS should be sent.
3674 		 */
3675 		basic_rate = brcms_basic_rate(wlc, rate);
3676 		if (basic_rate == 0)
3677 			/* This should only happen if we are using a
3678 			 * restricted rateset.
3679 			 */
3680 			basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3681 
3682 		brcms_c_write_rate_shm(wlc, rate, basic_rate);
3683 	}
3684 }
3685 
3686 /* band-specific init */
3687 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3688 {
3689 	brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3690 		       wlc->pub->unit, wlc->band->bandunit);
3691 
3692 	/* write ucode ACK/CTS rate table */
3693 	brcms_c_set_ratetable(wlc);
3694 
3695 	/* update some band specific mac configuration */
3696 	brcms_c_ucode_mac_upd(wlc);
3697 
3698 	/* init antenna selection */
3699 	brcms_c_antsel_init(wlc->asi);
3700 
3701 }
3702 
3703 /* formula:  IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3704 static int
3705 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3706 		   bool writeToShm)
3707 {
3708 	int idle_busy_ratio_x_16 = 0;
3709 	uint offset =
3710 	    isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3711 	    M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3712 	if (duty_cycle > 100 || duty_cycle < 0) {
3713 		brcms_err(wlc->hw->d11core,
3714 			  "wl%d:  duty cycle value off limit\n",
3715 			  wlc->pub->unit);
3716 		return -EINVAL;
3717 	}
3718 	if (duty_cycle)
3719 		idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3720 	/* Only write to shared memory  when wl is up */
3721 	if (writeToShm)
3722 		brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3723 
3724 	if (isOFDM)
3725 		wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3726 	else
3727 		wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3728 
3729 	return 0;
3730 }
3731 
3732 /* push sw hps and wake state through hardware */
3733 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3734 {
3735 	u32 v1, v2;
3736 	bool hps;
3737 	bool awake_before;
3738 
3739 	hps = brcms_c_ps_allowed(wlc);
3740 
3741 	brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3742 			   hps);
3743 
3744 	v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3745 	v2 = MCTL_WAKE;
3746 	if (hps)
3747 		v2 |= MCTL_HPS;
3748 
3749 	brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3750 
3751 	awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3752 
3753 	if (!awake_before)
3754 		brcms_b_wait_for_wake(wlc->hw);
3755 }
3756 
3757 /*
3758  * Write this BSS config's MAC address to core.
3759  * Updates RXE match engine.
3760  */
3761 static void brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3762 {
3763 	struct brcms_c_info *wlc = bsscfg->wlc;
3764 
3765 	/* enter the MAC addr into the RXE match registers */
3766 	brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, wlc->pub->cur_etheraddr);
3767 
3768 	brcms_c_ampdu_macaddr_upd(wlc);
3769 }
3770 
3771 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3772  * Updates RXE match engine.
3773  */
3774 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3775 {
3776 	/* we need to update BSSID in RXE match registers */
3777 	brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3778 }
3779 
3780 void brcms_c_set_ssid(struct brcms_c_info *wlc, u8 *ssid, size_t ssid_len)
3781 {
3782 	u8 len = min_t(u8, sizeof(wlc->bsscfg->SSID), ssid_len);
3783 	memset(wlc->bsscfg->SSID, 0, sizeof(wlc->bsscfg->SSID));
3784 
3785 	memcpy(wlc->bsscfg->SSID, ssid, len);
3786 	wlc->bsscfg->SSID_len = len;
3787 }
3788 
3789 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3790 {
3791 	wlc_hw->shortslot = shortslot;
3792 
3793 	if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3794 		brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3795 		brcms_b_update_slot_timing(wlc_hw, shortslot);
3796 		brcms_c_enable_mac(wlc_hw->wlc);
3797 	}
3798 }
3799 
3800 /*
3801  * Suspend the MAC and update the slot timing
3802  * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3803  */
3804 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3805 {
3806 	/* use the override if it is set */
3807 	if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3808 		shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3809 
3810 	if (wlc->shortslot == shortslot)
3811 		return;
3812 
3813 	wlc->shortslot = shortslot;
3814 
3815 	brcms_b_set_shortslot(wlc->hw, shortslot);
3816 }
3817 
3818 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3819 {
3820 	if (wlc->home_chanspec != chanspec) {
3821 		wlc->home_chanspec = chanspec;
3822 
3823 		if (wlc->pub->associated)
3824 			wlc->bsscfg->current_bss->chanspec = chanspec;
3825 	}
3826 }
3827 
3828 void
3829 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3830 		      bool mute_tx, struct txpwr_limits *txpwr)
3831 {
3832 	uint bandunit;
3833 
3834 	brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3835 			   chanspec);
3836 
3837 	wlc_hw->chanspec = chanspec;
3838 
3839 	/* Switch bands if necessary */
3840 	if (wlc_hw->_nbands > 1) {
3841 		bandunit = chspec_bandunit(chanspec);
3842 		if (wlc_hw->band->bandunit != bandunit) {
3843 			/* brcms_b_setband disables other bandunit,
3844 			 *  use light band switch if not up yet
3845 			 */
3846 			if (wlc_hw->up) {
3847 				wlc_phy_chanspec_radio_set(wlc_hw->
3848 							   bandstate[bandunit]->
3849 							   pi, chanspec);
3850 				brcms_b_setband(wlc_hw, bandunit, chanspec);
3851 			} else {
3852 				brcms_c_setxband(wlc_hw, bandunit);
3853 			}
3854 		}
3855 	}
3856 
3857 	wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3858 
3859 	if (!wlc_hw->up) {
3860 		if (wlc_hw->clk)
3861 			wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3862 						  chanspec);
3863 		wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3864 	} else {
3865 		wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3866 		wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3867 
3868 		/* Update muting of the channel */
3869 		brcms_b_mute(wlc_hw, mute_tx);
3870 	}
3871 }
3872 
3873 /* switch to and initialize new band */
3874 static void brcms_c_setband(struct brcms_c_info *wlc,
3875 					   uint bandunit)
3876 {
3877 	wlc->band = wlc->bandstate[bandunit];
3878 
3879 	if (!wlc->pub->up)
3880 		return;
3881 
3882 	/* wait for at least one beacon before entering sleeping state */
3883 	brcms_c_set_ps_ctrl(wlc);
3884 
3885 	/* band-specific initializations */
3886 	brcms_c_bsinit(wlc);
3887 }
3888 
3889 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3890 {
3891 	uint bandunit;
3892 	u16 old_chanspec = wlc->chanspec;
3893 
3894 	if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3895 		brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3896 			  wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3897 		return;
3898 	}
3899 
3900 	/* Switch bands if necessary */
3901 	if (wlc->pub->_nbands > 1) {
3902 		bandunit = chspec_bandunit(chanspec);
3903 		if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3904 			if (wlc->bandlocked) {
3905 				brcms_err(wlc->hw->d11core,
3906 					  "wl%d: %s: chspec %d band is locked!\n",
3907 					  wlc->pub->unit, __func__,
3908 					  CHSPEC_CHANNEL(chanspec));
3909 				return;
3910 			}
3911 			/*
3912 			 * should the setband call come after the
3913 			 * brcms_b_chanspec() ? if the setband updates
3914 			 * (brcms_c_bsinit) use low level calls to inspect and
3915 			 * set state, the state inspected may be from the wrong
3916 			 * band, or the following brcms_b_set_chanspec() may
3917 			 * undo the work.
3918 			 */
3919 			brcms_c_setband(wlc, bandunit);
3920 		}
3921 	}
3922 
3923 	/* sync up phy/radio chanspec */
3924 	brcms_c_set_phy_chanspec(wlc, chanspec);
3925 
3926 	/* init antenna selection */
3927 	if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3928 		brcms_c_antsel_init(wlc->asi);
3929 
3930 		/* Fix the hardware rateset based on bw.
3931 		 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3932 		 */
3933 		brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3934 			wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3935 	}
3936 
3937 	/* update some mac configuration since chanspec changed */
3938 	brcms_c_ucode_mac_upd(wlc);
3939 }
3940 
3941 /*
3942  * This function changes the phytxctl for beacon based on current
3943  * beacon ratespec AND txant setting as per this table:
3944  *  ratespec     CCK		ant = wlc->stf->txant
3945  *		OFDM		ant = 3
3946  */
3947 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3948 				       u32 bcn_rspec)
3949 {
3950 	u16 phyctl;
3951 	u16 phytxant = wlc->stf->phytxant;
3952 	u16 mask = PHY_TXC_ANT_MASK;
3953 
3954 	/* for non-siso rates or default setting, use the available chains */
3955 	if (BRCMS_PHY_11N_CAP(wlc->band))
3956 		phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3957 
3958 	phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3959 	phyctl = (phyctl & ~mask) | phytxant;
3960 	brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3961 }
3962 
3963 /*
3964  * centralized protection config change function to simplify debugging, no
3965  * consistency checking this should be called only on changes to avoid overhead
3966  * in periodic function
3967  */
3968 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3969 {
3970 	/*
3971 	 * Cannot use brcms_dbg_* here because this function is called
3972 	 * before wlc is sufficiently initialized.
3973 	 */
3974 	BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3975 
3976 	switch (idx) {
3977 	case BRCMS_PROT_G_SPEC:
3978 		wlc->protection->_g = (bool) val;
3979 		break;
3980 	case BRCMS_PROT_G_OVR:
3981 		wlc->protection->g_override = (s8) val;
3982 		break;
3983 	case BRCMS_PROT_G_USER:
3984 		wlc->protection->gmode_user = (u8) val;
3985 		break;
3986 	case BRCMS_PROT_OVERLAP:
3987 		wlc->protection->overlap = (s8) val;
3988 		break;
3989 	case BRCMS_PROT_N_USER:
3990 		wlc->protection->nmode_user = (s8) val;
3991 		break;
3992 	case BRCMS_PROT_N_CFG:
3993 		wlc->protection->n_cfg = (s8) val;
3994 		break;
3995 	case BRCMS_PROT_N_CFG_OVR:
3996 		wlc->protection->n_cfg_override = (s8) val;
3997 		break;
3998 	case BRCMS_PROT_N_NONGF:
3999 		wlc->protection->nongf = (bool) val;
4000 		break;
4001 	case BRCMS_PROT_N_NONGF_OVR:
4002 		wlc->protection->nongf_override = (s8) val;
4003 		break;
4004 	case BRCMS_PROT_N_PAM_OVR:
4005 		wlc->protection->n_pam_override = (s8) val;
4006 		break;
4007 	case BRCMS_PROT_N_OBSS:
4008 		wlc->protection->n_obss = (bool) val;
4009 		break;
4010 
4011 	default:
4012 		break;
4013 	}
4014 
4015 }
4016 
4017 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4018 {
4019 	if (wlc->pub->up) {
4020 		brcms_c_update_beacon(wlc);
4021 		brcms_c_update_probe_resp(wlc, true);
4022 	}
4023 }
4024 
4025 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4026 {
4027 	wlc->stf->ldpc = val;
4028 
4029 	if (wlc->pub->up) {
4030 		brcms_c_update_beacon(wlc);
4031 		brcms_c_update_probe_resp(wlc, true);
4032 		wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4033 	}
4034 }
4035 
4036 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4037 		       const struct ieee80211_tx_queue_params *params,
4038 		       bool suspend)
4039 {
4040 	int i;
4041 	struct shm_acparams acp_shm;
4042 	u16 *shm_entry;
4043 
4044 	/* Only apply params if the core is out of reset and has clocks */
4045 	if (!wlc->clk) {
4046 		brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4047 			  wlc->pub->unit, __func__);
4048 		return;
4049 	}
4050 
4051 	memset(&acp_shm, 0, sizeof(struct shm_acparams));
4052 	/* fill in shm ac params struct */
4053 	acp_shm.txop = params->txop;
4054 	/* convert from units of 32us to us for ucode */
4055 	wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4056 	    EDCF_TXOP2USEC(acp_shm.txop);
4057 	acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4058 
4059 	if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4060 	    && acp_shm.aifs < EDCF_AIFSN_MAX)
4061 		acp_shm.aifs++;
4062 
4063 	if (acp_shm.aifs < EDCF_AIFSN_MIN
4064 	    || acp_shm.aifs > EDCF_AIFSN_MAX) {
4065 		brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4066 			  "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4067 	} else {
4068 		acp_shm.cwmin = params->cw_min;
4069 		acp_shm.cwmax = params->cw_max;
4070 		acp_shm.cwcur = acp_shm.cwmin;
4071 		acp_shm.bslots =
4072 			bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4073 			acp_shm.cwcur;
4074 		acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4075 		/* Indicate the new params to the ucode */
4076 		acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4077 						  wme_ac2fifo[aci] *
4078 						  M_EDCF_QLEN +
4079 						  M_EDCF_STATUS_OFF));
4080 		acp_shm.status |= WME_STATUS_NEWAC;
4081 
4082 		/* Fill in shm acparam table */
4083 		shm_entry = (u16 *) &acp_shm;
4084 		for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4085 			brcms_b_write_shm(wlc->hw,
4086 					  M_EDCF_QINFO +
4087 					  wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4088 					  *shm_entry++);
4089 	}
4090 
4091 	if (suspend)
4092 		brcms_c_suspend_mac_and_wait(wlc);
4093 
4094 	brcms_c_update_beacon(wlc);
4095 	brcms_c_update_probe_resp(wlc, false);
4096 
4097 	if (suspend)
4098 		brcms_c_enable_mac(wlc);
4099 }
4100 
4101 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4102 {
4103 	u16 aci;
4104 	int i_ac;
4105 	struct ieee80211_tx_queue_params txq_pars;
4106 	static const struct edcf_acparam default_edcf_acparams[] = {
4107 		 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4108 		 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4109 		 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4110 		 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4111 	}; /* ucode needs these parameters during its initialization */
4112 	const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4113 
4114 	for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4115 		/* find out which ac this set of params applies to */
4116 		aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4117 
4118 		/* fill in shm ac params struct */
4119 		txq_pars.txop = edcf_acp->TXOP;
4120 		txq_pars.aifs = edcf_acp->ACI;
4121 
4122 		/* CWmin = 2^(ECWmin) - 1 */
4123 		txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4124 		/* CWmax = 2^(ECWmax) - 1 */
4125 		txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4126 					    >> EDCF_ECWMAX_SHIFT);
4127 		brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4128 	}
4129 
4130 	if (suspend) {
4131 		brcms_c_suspend_mac_and_wait(wlc);
4132 		brcms_c_enable_mac(wlc);
4133 	}
4134 }
4135 
4136 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4137 {
4138 	/* Don't start the timer if HWRADIO feature is disabled */
4139 	if (wlc->radio_monitor)
4140 		return;
4141 
4142 	wlc->radio_monitor = true;
4143 	brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4144 	brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4145 }
4146 
4147 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4148 {
4149 	if (!wlc->radio_monitor)
4150 		return true;
4151 
4152 	wlc->radio_monitor = false;
4153 	brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4154 	return brcms_del_timer(wlc->radio_timer);
4155 }
4156 
4157 /* read hwdisable state and propagate to wlc flag */
4158 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4159 {
4160 	if (wlc->pub->hw_off)
4161 		return;
4162 
4163 	if (brcms_b_radio_read_hwdisabled(wlc->hw))
4164 		mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4165 	else
4166 		mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4167 }
4168 
4169 /* update hwradio status and return it */
4170 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4171 {
4172 	brcms_c_radio_hwdisable_upd(wlc);
4173 
4174 	return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4175 			true : false;
4176 }
4177 
4178 /* periodical query hw radio button while driver is "down" */
4179 static void brcms_c_radio_timer(void *arg)
4180 {
4181 	struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4182 
4183 	if (brcms_deviceremoved(wlc)) {
4184 		brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4185 			  wlc->pub->unit, __func__);
4186 		brcms_down(wlc->wl);
4187 		return;
4188 	}
4189 
4190 	brcms_c_radio_hwdisable_upd(wlc);
4191 }
4192 
4193 /* common low-level watchdog code */
4194 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4195 {
4196 	struct brcms_hardware *wlc_hw = wlc->hw;
4197 
4198 	if (!wlc_hw->up)
4199 		return;
4200 
4201 	/* increment second count */
4202 	wlc_hw->now++;
4203 
4204 	/* Check for FIFO error interrupts */
4205 	brcms_b_fifoerrors(wlc_hw);
4206 
4207 	/* make sure RX dma has buffers */
4208 	dma_rxfill(wlc->hw->di[RX_FIFO]);
4209 
4210 	wlc_phy_watchdog(wlc_hw->band->pi);
4211 }
4212 
4213 /* common watchdog code */
4214 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4215 {
4216 	brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4217 
4218 	if (!wlc->pub->up)
4219 		return;
4220 
4221 	if (brcms_deviceremoved(wlc)) {
4222 		brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4223 			  wlc->pub->unit, __func__);
4224 		brcms_down(wlc->wl);
4225 		return;
4226 	}
4227 
4228 	/* increment second count */
4229 	wlc->pub->now++;
4230 
4231 	brcms_c_radio_hwdisable_upd(wlc);
4232 	/* if radio is disable, driver may be down, quit here */
4233 	if (wlc->pub->radio_disabled)
4234 		return;
4235 
4236 	brcms_b_watchdog(wlc);
4237 
4238 	/*
4239 	 * occasionally sample mac stat counters to
4240 	 * detect 16-bit counter wrap
4241 	 */
4242 	if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4243 		brcms_c_statsupd(wlc);
4244 
4245 	if (BRCMS_ISNPHY(wlc->band) &&
4246 	    ((wlc->pub->now - wlc->tempsense_lasttime) >=
4247 	     BRCMS_TEMPSENSE_PERIOD)) {
4248 		wlc->tempsense_lasttime = wlc->pub->now;
4249 		brcms_c_tempsense_upd(wlc);
4250 	}
4251 }
4252 
4253 static void brcms_c_watchdog_by_timer(void *arg)
4254 {
4255 	struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4256 
4257 	brcms_c_watchdog(wlc);
4258 }
4259 
4260 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4261 {
4262 	wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4263 		wlc, "watchdog");
4264 	if (!wlc->wdtimer) {
4265 		wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for wdtimer "
4266 			  "failed\n", unit);
4267 		goto fail;
4268 	}
4269 
4270 	wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4271 		wlc, "radio");
4272 	if (!wlc->radio_timer) {
4273 		wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for radio_timer "
4274 			  "failed\n", unit);
4275 		goto fail;
4276 	}
4277 
4278 	return true;
4279 
4280  fail:
4281 	return false;
4282 }
4283 
4284 /*
4285  * Initialize brcms_c_info default values ...
4286  * may get overrides later in this function
4287  */
4288 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4289 {
4290 	int i;
4291 
4292 	/* Save our copy of the chanspec */
4293 	wlc->chanspec = ch20mhz_chspec(1);
4294 
4295 	/* various 802.11g modes */
4296 	wlc->shortslot = false;
4297 	wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4298 
4299 	brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4300 	brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4301 
4302 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4303 			       BRCMS_PROTECTION_AUTO);
4304 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4305 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4306 			       BRCMS_PROTECTION_AUTO);
4307 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4308 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4309 
4310 	brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4311 			       BRCMS_PROTECTION_CTL_OVERLAP);
4312 
4313 	/* 802.11g draft 4.0 NonERP elt advertisement */
4314 	wlc->include_legacy_erp = true;
4315 
4316 	wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4317 	wlc->stf->txant = ANT_TX_DEF;
4318 
4319 	wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4320 
4321 	wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4322 	for (i = 0; i < NFIFO; i++)
4323 		wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4324 	wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4325 
4326 	/* default rate fallback retry limits */
4327 	wlc->SFBL = RETRY_SHORT_FB;
4328 	wlc->LFBL = RETRY_LONG_FB;
4329 
4330 	/* default mac retry limits */
4331 	wlc->SRL = RETRY_SHORT_DEF;
4332 	wlc->LRL = RETRY_LONG_DEF;
4333 
4334 	/* WME QoS mode is Auto by default */
4335 	wlc->pub->_ampdu = AMPDU_AGG_HOST;
4336 }
4337 
4338 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4339 {
4340 	uint err = 0;
4341 	uint unit;
4342 	unit = wlc->pub->unit;
4343 
4344 	wlc->asi = brcms_c_antsel_attach(wlc);
4345 	if (wlc->asi == NULL) {
4346 		wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4347 			  "failed\n", unit);
4348 		err = 44;
4349 		goto fail;
4350 	}
4351 
4352 	wlc->ampdu = brcms_c_ampdu_attach(wlc);
4353 	if (wlc->ampdu == NULL) {
4354 		wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4355 			  "failed\n", unit);
4356 		err = 50;
4357 		goto fail;
4358 	}
4359 
4360 	if ((brcms_c_stf_attach(wlc) != 0)) {
4361 		wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4362 			  "failed\n", unit);
4363 		err = 68;
4364 		goto fail;
4365 	}
4366  fail:
4367 	return err;
4368 }
4369 
4370 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4371 {
4372 	return wlc->pub;
4373 }
4374 
4375 /* low level attach
4376  *    run backplane attach, init nvram
4377  *    run phy attach
4378  *    initialize software state for each core and band
4379  *    put the whole chip in reset(driver down state), no clock
4380  */
4381 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4382 			  uint unit, bool piomode)
4383 {
4384 	struct brcms_hardware *wlc_hw;
4385 	uint err = 0;
4386 	uint j;
4387 	bool wme = false;
4388 	struct shared_phy_params sha_params;
4389 	struct wiphy *wiphy = wlc->wiphy;
4390 	struct pci_dev *pcidev = core->bus->host_pci;
4391 	struct ssb_sprom *sprom = &core->bus->sprom;
4392 
4393 	if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4394 		brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4395 			       pcidev->vendor,
4396 			       pcidev->device);
4397 	else
4398 		brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4399 			       core->bus->boardinfo.vendor,
4400 			       core->bus->boardinfo.type);
4401 
4402 	wme = true;
4403 
4404 	wlc_hw = wlc->hw;
4405 	wlc_hw->wlc = wlc;
4406 	wlc_hw->unit = unit;
4407 	wlc_hw->band = wlc_hw->bandstate[0];
4408 	wlc_hw->_piomode = piomode;
4409 
4410 	/* populate struct brcms_hardware with default values  */
4411 	brcms_b_info_init(wlc_hw);
4412 
4413 	/*
4414 	 * Do the hardware portion of the attach. Also initialize software
4415 	 * state that depends on the particular hardware we are running.
4416 	 */
4417 	wlc_hw->sih = ai_attach(core->bus);
4418 	if (wlc_hw->sih == NULL) {
4419 		wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4420 			  unit);
4421 		err = 11;
4422 		goto fail;
4423 	}
4424 
4425 	/* verify again the device is supported */
4426 	if (!brcms_c_chipmatch(core)) {
4427 		wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4428 			 unit);
4429 		err = 12;
4430 		goto fail;
4431 	}
4432 
4433 	if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4434 		wlc_hw->vendorid = pcidev->vendor;
4435 		wlc_hw->deviceid = pcidev->device;
4436 	} else {
4437 		wlc_hw->vendorid = core->bus->boardinfo.vendor;
4438 		wlc_hw->deviceid = core->bus->boardinfo.type;
4439 	}
4440 
4441 	wlc_hw->d11core = core;
4442 	wlc_hw->corerev = core->id.rev;
4443 
4444 	/* validate chip, chiprev and corerev */
4445 	if (!brcms_c_isgoodchip(wlc_hw)) {
4446 		err = 13;
4447 		goto fail;
4448 	}
4449 
4450 	/* initialize power control registers */
4451 	ai_clkctl_init(wlc_hw->sih);
4452 
4453 	/* request fastclock and force fastclock for the rest of attach
4454 	 * bring the d11 core out of reset.
4455 	 *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4456 	 *   is still false; But it will be called again inside wlc_corereset,
4457 	 *   after d11 is out of reset.
4458 	 */
4459 	brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4460 	brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4461 
4462 	if (!brcms_b_validate_chip_access(wlc_hw)) {
4463 		wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4464 			"failed\n", unit);
4465 		err = 14;
4466 		goto fail;
4467 	}
4468 
4469 	/* get the board rev, used just below */
4470 	j = sprom->board_rev;
4471 	/* promote srom boardrev of 0xFF to 1 */
4472 	if (j == BOARDREV_PROMOTABLE)
4473 		j = BOARDREV_PROMOTED;
4474 	wlc_hw->boardrev = (u16) j;
4475 	if (!brcms_c_validboardtype(wlc_hw)) {
4476 		wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4477 			  "board type (0x%x)" " or revision level (0x%x)\n",
4478 			  unit, ai_get_boardtype(wlc_hw->sih),
4479 			  wlc_hw->boardrev);
4480 		err = 15;
4481 		goto fail;
4482 	}
4483 	wlc_hw->sromrev = sprom->revision;
4484 	wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4485 	wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4486 
4487 	if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4488 		brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4489 
4490 	/* check device id(srom, nvram etc.) to set bands */
4491 	if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4492 	    wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4493 	    wlc_hw->deviceid == BCM43224_CHIP_ID)
4494 		/* Dualband boards */
4495 		wlc_hw->_nbands = 2;
4496 	else
4497 		wlc_hw->_nbands = 1;
4498 
4499 	if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4500 		wlc_hw->_nbands = 1;
4501 
4502 	/* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4503 	 * unconditionally does the init of these values
4504 	 */
4505 	wlc->vendorid = wlc_hw->vendorid;
4506 	wlc->deviceid = wlc_hw->deviceid;
4507 	wlc->pub->sih = wlc_hw->sih;
4508 	wlc->pub->corerev = wlc_hw->corerev;
4509 	wlc->pub->sromrev = wlc_hw->sromrev;
4510 	wlc->pub->boardrev = wlc_hw->boardrev;
4511 	wlc->pub->boardflags = wlc_hw->boardflags;
4512 	wlc->pub->boardflags2 = wlc_hw->boardflags2;
4513 	wlc->pub->_nbands = wlc_hw->_nbands;
4514 
4515 	wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4516 
4517 	if (wlc_hw->physhim == NULL) {
4518 		wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4519 			"failed\n", unit);
4520 		err = 25;
4521 		goto fail;
4522 	}
4523 
4524 	/* pass all the parameters to wlc_phy_shared_attach in one struct */
4525 	sha_params.sih = wlc_hw->sih;
4526 	sha_params.physhim = wlc_hw->physhim;
4527 	sha_params.unit = unit;
4528 	sha_params.corerev = wlc_hw->corerev;
4529 	sha_params.vid = wlc_hw->vendorid;
4530 	sha_params.did = wlc_hw->deviceid;
4531 	sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4532 	sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4533 	sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4534 	sha_params.sromrev = wlc_hw->sromrev;
4535 	sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4536 	sha_params.boardrev = wlc_hw->boardrev;
4537 	sha_params.boardflags = wlc_hw->boardflags;
4538 	sha_params.boardflags2 = wlc_hw->boardflags2;
4539 
4540 	/* alloc and save pointer to shared phy state area */
4541 	wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4542 	if (!wlc_hw->phy_sh) {
4543 		err = 16;
4544 		goto fail;
4545 	}
4546 
4547 	/* initialize software state for each core and band */
4548 	for (j = 0; j < wlc_hw->_nbands; j++) {
4549 		/*
4550 		 * band0 is always 2.4Ghz
4551 		 * band1, if present, is 5Ghz
4552 		 */
4553 
4554 		brcms_c_setxband(wlc_hw, j);
4555 
4556 		wlc_hw->band->bandunit = j;
4557 		wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4558 		wlc->band->bandunit = j;
4559 		wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4560 		wlc->core->coreidx = core->core_index;
4561 
4562 		wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4563 		wlc_hw->machwcap_backup = wlc_hw->machwcap;
4564 
4565 		/* init tx fifo size */
4566 		WARN_ON(wlc_hw->corerev < XMTFIFOTBL_STARTREV ||
4567 			(wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4568 				ARRAY_SIZE(xmtfifo_sz));
4569 		wlc_hw->xmtfifo_sz =
4570 		    xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4571 		WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4572 
4573 		/* Get a phy for this band */
4574 		wlc_hw->band->pi =
4575 			wlc_phy_attach(wlc_hw->phy_sh, core,
4576 				       wlc_hw->band->bandtype,
4577 				       wlc->wiphy);
4578 		if (wlc_hw->band->pi == NULL) {
4579 			wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4580 				  "attach failed\n", unit);
4581 			err = 17;
4582 			goto fail;
4583 		}
4584 
4585 		wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4586 
4587 		wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4588 				       &wlc_hw->band->phyrev,
4589 				       &wlc_hw->band->radioid,
4590 				       &wlc_hw->band->radiorev);
4591 		wlc_hw->band->abgphy_encore =
4592 		    wlc_phy_get_encore(wlc_hw->band->pi);
4593 		wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4594 		wlc_hw->band->core_flags =
4595 		    wlc_phy_get_coreflags(wlc_hw->band->pi);
4596 
4597 		/* verify good phy_type & supported phy revision */
4598 		if (BRCMS_ISNPHY(wlc_hw->band)) {
4599 			if (NCONF_HAS(wlc_hw->band->phyrev))
4600 				goto good_phy;
4601 			else
4602 				goto bad_phy;
4603 		} else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4604 			if (LCNCONF_HAS(wlc_hw->band->phyrev))
4605 				goto good_phy;
4606 			else
4607 				goto bad_phy;
4608 		} else {
4609  bad_phy:
4610 			wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4611 				  "phy type/rev (%d/%d)\n", unit,
4612 				  wlc_hw->band->phytype, wlc_hw->band->phyrev);
4613 			err = 18;
4614 			goto fail;
4615 		}
4616 
4617  good_phy:
4618 		/*
4619 		 * BMAC_NOTE: wlc->band->pi should not be set below and should
4620 		 * be done in the high level attach. However we can not make
4621 		 * that change until all low level access is changed to
4622 		 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4623 		 * keeping wlc_hw->band->pi as well for incremental update of
4624 		 * low level fns, and cut over low only init when all fns
4625 		 * updated.
4626 		 */
4627 		wlc->band->pi = wlc_hw->band->pi;
4628 		wlc->band->phytype = wlc_hw->band->phytype;
4629 		wlc->band->phyrev = wlc_hw->band->phyrev;
4630 		wlc->band->radioid = wlc_hw->band->radioid;
4631 		wlc->band->radiorev = wlc_hw->band->radiorev;
4632 		brcms_dbg_info(core, "wl%d: phy %u/%u radio %x/%u\n", unit,
4633 			       wlc->band->phytype, wlc->band->phyrev,
4634 			       wlc->band->radioid, wlc->band->radiorev);
4635 		/* default contention windows size limits */
4636 		wlc_hw->band->CWmin = APHY_CWMIN;
4637 		wlc_hw->band->CWmax = PHY_CWMAX;
4638 
4639 		if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4640 			err = 19;
4641 			goto fail;
4642 		}
4643 	}
4644 
4645 	/* disable core to match driver "down" state */
4646 	brcms_c_coredisable(wlc_hw);
4647 
4648 	/* Match driver "down" state */
4649 	bcma_host_pci_down(wlc_hw->d11core->bus);
4650 
4651 	/* turn off pll and xtal to match driver "down" state */
4652 	brcms_b_xtal(wlc_hw, OFF);
4653 
4654 	/* *******************************************************************
4655 	 * The hardware is in the DOWN state at this point. D11 core
4656 	 * or cores are in reset with clocks off, and the board PLLs
4657 	 * are off if possible.
4658 	 *
4659 	 * Beyond this point, wlc->sbclk == false and chip registers
4660 	 * should not be touched.
4661 	 *********************************************************************
4662 	 */
4663 
4664 	/* init etheraddr state variables */
4665 	brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4666 
4667 	if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4668 	    is_zero_ether_addr(wlc_hw->etheraddr)) {
4669 		wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4670 			  unit);
4671 		err = 22;
4672 		goto fail;
4673 	}
4674 
4675 	brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4676 		       wlc_hw->deviceid, wlc_hw->_nbands,
4677 		       ai_get_boardtype(wlc_hw->sih));
4678 
4679 	return err;
4680 
4681  fail:
4682 	wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4683 		  err);
4684 	return err;
4685 }
4686 
4687 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4688 {
4689 	int aa;
4690 	uint unit;
4691 	int bandtype;
4692 	struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4693 
4694 	unit = wlc->pub->unit;
4695 	bandtype = wlc->band->bandtype;
4696 
4697 	/* get antennas available */
4698 	if (bandtype == BRCM_BAND_5G)
4699 		aa = sprom->ant_available_a;
4700 	else
4701 		aa = sprom->ant_available_bg;
4702 
4703 	if ((aa < 1) || (aa > 15)) {
4704 		wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4705 			  " srom (0x%x), using 3\n", unit, __func__, aa);
4706 		aa = 3;
4707 	}
4708 
4709 	/* reset the defaults if we have a single antenna */
4710 	if (aa == 1) {
4711 		wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4712 		wlc->stf->txant = ANT_TX_FORCE_0;
4713 	} else if (aa == 2) {
4714 		wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4715 		wlc->stf->txant = ANT_TX_FORCE_1;
4716 	} else {
4717 	}
4718 
4719 	/* Compute Antenna Gain */
4720 	if (bandtype == BRCM_BAND_5G)
4721 		wlc->band->antgain = sprom->antenna_gain.a1;
4722 	else
4723 		wlc->band->antgain = sprom->antenna_gain.a0;
4724 
4725 	return true;
4726 }
4727 
4728 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4729 {
4730 	u16 chanspec;
4731 	struct brcms_band *band;
4732 	struct brcms_bss_info *bi = wlc->default_bss;
4733 
4734 	/* init default and target BSS with some sane initial values */
4735 	memset(bi, 0, sizeof(*bi));
4736 	bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4737 
4738 	/* fill the default channel as the first valid channel
4739 	 * starting from the 2G channels
4740 	 */
4741 	chanspec = ch20mhz_chspec(1);
4742 	wlc->home_chanspec = bi->chanspec = chanspec;
4743 
4744 	/* find the band of our default channel */
4745 	band = wlc->band;
4746 	if (wlc->pub->_nbands > 1 &&
4747 	    band->bandunit != chspec_bandunit(chanspec))
4748 		band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4749 
4750 	/* init bss rates to the band specific default rate set */
4751 	brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4752 		band->bandtype, false, BRCMS_RATE_MASK_FULL,
4753 		(bool) (wlc->pub->_n_enab & SUPPORT_11N),
4754 		brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4755 
4756 	if (wlc->pub->_n_enab & SUPPORT_11N)
4757 		bi->flags |= BRCMS_BSS_HT;
4758 }
4759 
4760 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4761 {
4762 	uint i;
4763 	struct brcms_band *band;
4764 
4765 	for (i = 0; i < wlc->pub->_nbands; i++) {
4766 		band = wlc->bandstate[i];
4767 		if (band->bandtype == BRCM_BAND_5G) {
4768 			if ((bwcap == BRCMS_N_BW_40ALL)
4769 			    || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4770 				band->mimo_cap_40 = true;
4771 			else
4772 				band->mimo_cap_40 = false;
4773 		} else {
4774 			if (bwcap == BRCMS_N_BW_40ALL)
4775 				band->mimo_cap_40 = true;
4776 			else
4777 				band->mimo_cap_40 = false;
4778 		}
4779 	}
4780 }
4781 
4782 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4783 {
4784 	/* free timer state */
4785 	if (wlc->wdtimer) {
4786 		brcms_free_timer(wlc->wdtimer);
4787 		wlc->wdtimer = NULL;
4788 	}
4789 	if (wlc->radio_timer) {
4790 		brcms_free_timer(wlc->radio_timer);
4791 		wlc->radio_timer = NULL;
4792 	}
4793 }
4794 
4795 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4796 {
4797 	if (wlc->asi) {
4798 		brcms_c_antsel_detach(wlc->asi);
4799 		wlc->asi = NULL;
4800 	}
4801 
4802 	if (wlc->ampdu) {
4803 		brcms_c_ampdu_detach(wlc->ampdu);
4804 		wlc->ampdu = NULL;
4805 	}
4806 
4807 	brcms_c_stf_detach(wlc);
4808 }
4809 
4810 /*
4811  * low level detach
4812  */
4813 static void brcms_b_detach(struct brcms_c_info *wlc)
4814 {
4815 	uint i;
4816 	struct brcms_hw_band *band;
4817 	struct brcms_hardware *wlc_hw = wlc->hw;
4818 
4819 	brcms_b_detach_dmapio(wlc_hw);
4820 
4821 	band = wlc_hw->band;
4822 	for (i = 0; i < wlc_hw->_nbands; i++) {
4823 		if (band->pi) {
4824 			/* Detach this band's phy */
4825 			wlc_phy_detach(band->pi);
4826 			band->pi = NULL;
4827 		}
4828 		band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4829 	}
4830 
4831 	/* Free shared phy state */
4832 	kfree(wlc_hw->phy_sh);
4833 
4834 	wlc_phy_shim_detach(wlc_hw->physhim);
4835 
4836 	if (wlc_hw->sih) {
4837 		ai_detach(wlc_hw->sih);
4838 		wlc_hw->sih = NULL;
4839 	}
4840 }
4841 
4842 /*
4843  * Return a count of the number of driver callbacks still pending.
4844  *
4845  * General policy is that brcms_c_detach can only dealloc/free software states.
4846  * It can NOT touch hardware registers since the d11core may be in reset and
4847  * clock may not be available.
4848  * One exception is sb register access, which is possible if crystal is turned
4849  * on after "down" state, driver should avoid software timer with the exception
4850  * of radio_monitor.
4851  */
4852 uint brcms_c_detach(struct brcms_c_info *wlc)
4853 {
4854 	uint callbacks;
4855 
4856 	if (wlc == NULL)
4857 		return 0;
4858 
4859 	brcms_b_detach(wlc);
4860 
4861 	/* delete software timers */
4862 	callbacks = 0;
4863 	if (!brcms_c_radio_monitor_stop(wlc))
4864 		callbacks++;
4865 
4866 	brcms_c_channel_mgr_detach(wlc->cmi);
4867 
4868 	brcms_c_timers_deinit(wlc);
4869 
4870 	brcms_c_detach_module(wlc);
4871 
4872 	brcms_c_detach_mfree(wlc);
4873 	return callbacks;
4874 }
4875 
4876 /* update state that depends on the current value of "ap" */
4877 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4878 {
4879 	/* STA-BSS; short capable */
4880 	wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4881 }
4882 
4883 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4884 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4885 {
4886 	if (wlc_hw->wlc->pub->hw_up)
4887 		return;
4888 
4889 	brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4890 
4891 	/*
4892 	 * Enable pll and xtal, initialize the power control registers,
4893 	 * and force fastclock for the remainder of brcms_c_up().
4894 	 */
4895 	brcms_b_xtal(wlc_hw, ON);
4896 	ai_clkctl_init(wlc_hw->sih);
4897 	brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4898 
4899 	/*
4900 	 * TODO: test suspend/resume
4901 	 *
4902 	 * AI chip doesn't restore bar0win2 on
4903 	 * hibernation/resume, need sw fixup
4904 	 */
4905 
4906 	/*
4907 	 * Inform phy that a POR reset has occurred so
4908 	 * it does a complete phy init
4909 	 */
4910 	wlc_phy_por_inform(wlc_hw->band->pi);
4911 
4912 	wlc_hw->ucode_loaded = false;
4913 	wlc_hw->wlc->pub->hw_up = true;
4914 
4915 	if ((wlc_hw->boardflags & BFL_FEM)
4916 	    && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4917 		if (!
4918 		    (wlc_hw->boardrev >= 0x1250
4919 		     && (wlc_hw->boardflags & BFL_FEM_BT)))
4920 			ai_epa_4313war(wlc_hw->sih);
4921 	}
4922 }
4923 
4924 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4925 {
4926 	brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4927 
4928 	/*
4929 	 * Enable pll and xtal, initialize the power control registers,
4930 	 * and force fastclock for the remainder of brcms_c_up().
4931 	 */
4932 	brcms_b_xtal(wlc_hw, ON);
4933 	ai_clkctl_init(wlc_hw->sih);
4934 	brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4935 
4936 	/*
4937 	 * Configure pci/pcmcia here instead of in brcms_c_attach()
4938 	 * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
4939 	 */
4940 	bcma_host_pci_irq_ctl(wlc_hw->d11core->bus, wlc_hw->d11core,
4941 			      true);
4942 
4943 	/*
4944 	 * Need to read the hwradio status here to cover the case where the
4945 	 * system is loaded with the hw radio disabled. We do not want to
4946 	 * bring the driver up in this case.
4947 	 */
4948 	if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
4949 		/* put SB PCI in down state again */
4950 		bcma_host_pci_down(wlc_hw->d11core->bus);
4951 		brcms_b_xtal(wlc_hw, OFF);
4952 		return -ENOMEDIUM;
4953 	}
4954 
4955 	bcma_host_pci_up(wlc_hw->d11core->bus);
4956 
4957 	/* reset the d11 core */
4958 	brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4959 
4960 	return 0;
4961 }
4962 
4963 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
4964 {
4965 	wlc_hw->up = true;
4966 	wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
4967 
4968 	/* FULLY enable dynamic power control and d11 core interrupt */
4969 	brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
4970 	brcms_intrson(wlc_hw->wlc->wl);
4971 	return 0;
4972 }
4973 
4974 /*
4975  * Write WME tunable parameters for retransmit/max rate
4976  * from wlc struct to ucode
4977  */
4978 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
4979 {
4980 	int ac;
4981 
4982 	/* Need clock to do this */
4983 	if (!wlc->clk)
4984 		return;
4985 
4986 	for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
4987 		brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
4988 				  wlc->wme_retries[ac]);
4989 }
4990 
4991 /* make interface operational */
4992 int brcms_c_up(struct brcms_c_info *wlc)
4993 {
4994 	struct ieee80211_channel *ch;
4995 
4996 	brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4997 
4998 	/* HW is turned off so don't try to access it */
4999 	if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5000 		return -ENOMEDIUM;
5001 
5002 	if (!wlc->pub->hw_up) {
5003 		brcms_b_hw_up(wlc->hw);
5004 		wlc->pub->hw_up = true;
5005 	}
5006 
5007 	if ((wlc->pub->boardflags & BFL_FEM)
5008 	    && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5009 		if (wlc->pub->boardrev >= 0x1250
5010 		    && (wlc->pub->boardflags & BFL_FEM_BT))
5011 			brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5012 				MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5013 		else
5014 			brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5015 				    MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5016 	}
5017 
5018 	/*
5019 	 * Need to read the hwradio status here to cover the case where the
5020 	 * system is loaded with the hw radio disabled. We do not want to bring
5021 	 * the driver up in this case. If radio is disabled, abort up, lower
5022 	 * power, start radio timer and return 0(for NDIS) don't call
5023 	 * radio_update to avoid looping brcms_c_up.
5024 	 *
5025 	 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5026 	 */
5027 	if (!wlc->pub->radio_disabled) {
5028 		int status = brcms_b_up_prep(wlc->hw);
5029 		if (status == -ENOMEDIUM) {
5030 			if (!mboolisset
5031 			    (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5032 				struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5033 				mboolset(wlc->pub->radio_disabled,
5034 					 WL_RADIO_HW_DISABLE);
5035 				if (bsscfg->type == BRCMS_TYPE_STATION ||
5036 				    bsscfg->type == BRCMS_TYPE_ADHOC)
5037 					brcms_err(wlc->hw->d11core,
5038 						  "wl%d: up: rfdisable -> "
5039 						  "bsscfg_disable()\n",
5040 						   wlc->pub->unit);
5041 			}
5042 		}
5043 	}
5044 
5045 	if (wlc->pub->radio_disabled) {
5046 		brcms_c_radio_monitor_start(wlc);
5047 		return 0;
5048 	}
5049 
5050 	/* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5051 	wlc->clk = true;
5052 
5053 	brcms_c_radio_monitor_stop(wlc);
5054 
5055 	/* Set EDCF hostflags */
5056 	brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5057 
5058 	brcms_init(wlc->wl);
5059 	wlc->pub->up = true;
5060 
5061 	if (wlc->bandinit_pending) {
5062 		ch = wlc->pub->ieee_hw->conf.chandef.chan;
5063 		brcms_c_suspend_mac_and_wait(wlc);
5064 		brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5065 		wlc->bandinit_pending = false;
5066 		brcms_c_enable_mac(wlc);
5067 	}
5068 
5069 	brcms_b_up_finish(wlc->hw);
5070 
5071 	/* Program the TX wme params with the current settings */
5072 	brcms_c_wme_retries_write(wlc);
5073 
5074 	/* start one second watchdog timer */
5075 	brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5076 	wlc->WDarmed = true;
5077 
5078 	/* ensure antenna config is up to date */
5079 	brcms_c_stf_phy_txant_upd(wlc);
5080 	/* ensure LDPC config is in sync */
5081 	brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5082 
5083 	return 0;
5084 }
5085 
5086 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5087 {
5088 	bool dev_gone;
5089 	uint callbacks = 0;
5090 
5091 	if (!wlc_hw->up)
5092 		return callbacks;
5093 
5094 	dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5095 
5096 	/* disable interrupts */
5097 	if (dev_gone)
5098 		wlc_hw->wlc->macintmask = 0;
5099 	else {
5100 		/* now disable interrupts */
5101 		brcms_intrsoff(wlc_hw->wlc->wl);
5102 
5103 		/* ensure we're running on the pll clock again */
5104 		brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5105 	}
5106 	/* down phy at the last of this stage */
5107 	callbacks += wlc_phy_down(wlc_hw->band->pi);
5108 
5109 	return callbacks;
5110 }
5111 
5112 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5113 {
5114 	uint callbacks = 0;
5115 	bool dev_gone;
5116 
5117 	if (!wlc_hw->up)
5118 		return callbacks;
5119 
5120 	wlc_hw->up = false;
5121 	wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5122 
5123 	dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5124 
5125 	if (dev_gone) {
5126 		wlc_hw->sbclk = false;
5127 		wlc_hw->clk = false;
5128 		wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5129 
5130 		/* reclaim any posted packets */
5131 		brcms_c_flushqueues(wlc_hw->wlc);
5132 	} else {
5133 
5134 		/* Reset and disable the core */
5135 		if (bcma_core_is_enabled(wlc_hw->d11core)) {
5136 			if (bcma_read32(wlc_hw->d11core,
5137 					D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5138 				brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5139 			callbacks += brcms_reset(wlc_hw->wlc->wl);
5140 			brcms_c_coredisable(wlc_hw);
5141 		}
5142 
5143 		/* turn off primary xtal and pll */
5144 		if (!wlc_hw->noreset) {
5145 			bcma_host_pci_down(wlc_hw->d11core->bus);
5146 			brcms_b_xtal(wlc_hw, OFF);
5147 		}
5148 	}
5149 
5150 	return callbacks;
5151 }
5152 
5153 /*
5154  * Mark the interface nonoperational, stop the software mechanisms,
5155  * disable the hardware, free any transient buffer state.
5156  * Return a count of the number of driver callbacks still pending.
5157  */
5158 uint brcms_c_down(struct brcms_c_info *wlc)
5159 {
5160 
5161 	uint callbacks = 0;
5162 	int i;
5163 
5164 	brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5165 
5166 	/* check if we are already in the going down path */
5167 	if (wlc->going_down) {
5168 		brcms_err(wlc->hw->d11core,
5169 			  "wl%d: %s: Driver going down so return\n",
5170 			  wlc->pub->unit, __func__);
5171 		return 0;
5172 	}
5173 	if (!wlc->pub->up)
5174 		return callbacks;
5175 
5176 	wlc->going_down = true;
5177 
5178 	callbacks += brcms_b_bmac_down_prep(wlc->hw);
5179 
5180 	brcms_deviceremoved(wlc);
5181 
5182 	/* Call any registered down handlers */
5183 	for (i = 0; i < BRCMS_MAXMODULES; i++) {
5184 		if (wlc->modulecb[i].down_fn)
5185 			callbacks +=
5186 			    wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5187 	}
5188 
5189 	/* cancel the watchdog timer */
5190 	if (wlc->WDarmed) {
5191 		if (!brcms_del_timer(wlc->wdtimer))
5192 			callbacks++;
5193 		wlc->WDarmed = false;
5194 	}
5195 
5196 	wlc->pub->up = false;
5197 
5198 	wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5199 
5200 	callbacks += brcms_b_down_finish(wlc->hw);
5201 
5202 	/* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5203 	wlc->clk = false;
5204 
5205 	wlc->going_down = false;
5206 	return callbacks;
5207 }
5208 
5209 /* Set the current gmode configuration */
5210 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5211 {
5212 	int ret = 0;
5213 	uint i;
5214 	struct brcms_c_rateset rs;
5215 	/* Default to 54g Auto */
5216 	/* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5217 	s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5218 	bool ofdm_basic = false;	/* Make 6, 12, and 24 basic rates */
5219 	struct brcms_band *band;
5220 
5221 	/* if N-support is enabled, allow Gmode set as long as requested
5222 	 * Gmode is not GMODE_LEGACY_B
5223 	 */
5224 	if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5225 		return -ENOTSUPP;
5226 
5227 	/* verify that we are dealing with 2G band and grab the band pointer */
5228 	if (wlc->band->bandtype == BRCM_BAND_2G)
5229 		band = wlc->band;
5230 	else if ((wlc->pub->_nbands > 1) &&
5231 		 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5232 		band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5233 	else
5234 		return -EINVAL;
5235 
5236 	/* update configuration value */
5237 	if (config)
5238 		brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5239 
5240 	/* Clear rateset override */
5241 	memset(&rs, 0, sizeof(rs));
5242 
5243 	switch (gmode) {
5244 	case GMODE_LEGACY_B:
5245 		shortslot = BRCMS_SHORTSLOT_OFF;
5246 		brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5247 
5248 		break;
5249 
5250 	case GMODE_LRS:
5251 		break;
5252 
5253 	case GMODE_AUTO:
5254 		/* Accept defaults */
5255 		break;
5256 
5257 	case GMODE_ONLY:
5258 		ofdm_basic = true;
5259 		break;
5260 
5261 	case GMODE_PERFORMANCE:
5262 		shortslot = BRCMS_SHORTSLOT_ON;
5263 		ofdm_basic = true;
5264 		break;
5265 
5266 	default:
5267 		/* Error */
5268 		brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5269 			  wlc->pub->unit, __func__, gmode);
5270 		return -ENOTSUPP;
5271 	}
5272 
5273 	band->gmode = gmode;
5274 
5275 	wlc->shortslot_override = shortslot;
5276 
5277 	/* Use the default 11g rateset */
5278 	if (!rs.count)
5279 		brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5280 
5281 	if (ofdm_basic) {
5282 		for (i = 0; i < rs.count; i++) {
5283 			if (rs.rates[i] == BRCM_RATE_6M
5284 			    || rs.rates[i] == BRCM_RATE_12M
5285 			    || rs.rates[i] == BRCM_RATE_24M)
5286 				rs.rates[i] |= BRCMS_RATE_FLAG;
5287 		}
5288 	}
5289 
5290 	/* Set default bss rateset */
5291 	wlc->default_bss->rateset.count = rs.count;
5292 	memcpy(wlc->default_bss->rateset.rates, rs.rates,
5293 	       sizeof(wlc->default_bss->rateset.rates));
5294 
5295 	return ret;
5296 }
5297 
5298 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5299 {
5300 	uint i;
5301 	s32 nmode = AUTO;
5302 
5303 	if (wlc->stf->txstreams == WL_11N_3x3)
5304 		nmode = WL_11N_3x3;
5305 	else
5306 		nmode = WL_11N_2x2;
5307 
5308 	/* force GMODE_AUTO if NMODE is ON */
5309 	brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5310 	if (nmode == WL_11N_3x3)
5311 		wlc->pub->_n_enab = SUPPORT_HT;
5312 	else
5313 		wlc->pub->_n_enab = SUPPORT_11N;
5314 	wlc->default_bss->flags |= BRCMS_BSS_HT;
5315 	/* add the mcs rates to the default and hw ratesets */
5316 	brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5317 			      wlc->stf->txstreams);
5318 	for (i = 0; i < wlc->pub->_nbands; i++)
5319 		memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5320 		       wlc->default_bss->rateset.mcs, MCSSET_LEN);
5321 
5322 	return 0;
5323 }
5324 
5325 static int
5326 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5327 			     struct brcms_c_rateset *rs_arg)
5328 {
5329 	struct brcms_c_rateset rs, new;
5330 	uint bandunit;
5331 
5332 	memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5333 
5334 	/* check for bad count value */
5335 	if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5336 		return -EINVAL;
5337 
5338 	/* try the current band */
5339 	bandunit = wlc->band->bandunit;
5340 	memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5341 	if (brcms_c_rate_hwrs_filter_sort_validate
5342 	    (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5343 	     wlc->stf->txstreams))
5344 		goto good;
5345 
5346 	/* try the other band */
5347 	if (brcms_is_mband_unlocked(wlc)) {
5348 		bandunit = OTHERBANDUNIT(wlc);
5349 		memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5350 		if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5351 						       &wlc->
5352 						       bandstate[bandunit]->
5353 						       hw_rateset, true,
5354 						       wlc->stf->txstreams))
5355 			goto good;
5356 	}
5357 
5358 	return -EBADE;
5359 
5360  good:
5361 	/* apply new rateset */
5362 	memcpy(&wlc->default_bss->rateset, &new,
5363 	       sizeof(struct brcms_c_rateset));
5364 	memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5365 	       sizeof(struct brcms_c_rateset));
5366 	return 0;
5367 }
5368 
5369 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5370 {
5371 	wlc_phy_ofdm_rateset_war(wlc->band->pi, false);
5372 }
5373 
5374 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5375 {
5376 	u16 chspec = ch20mhz_chspec(channel);
5377 
5378 	if (channel > MAXCHANNEL)
5379 		return -EINVAL;
5380 
5381 	if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5382 		return -EINVAL;
5383 
5384 
5385 	if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5386 		if (wlc->band->bandunit != chspec_bandunit(chspec))
5387 			wlc->bandinit_pending = true;
5388 		else
5389 			wlc->bandinit_pending = false;
5390 	}
5391 
5392 	wlc->default_bss->chanspec = chspec;
5393 	/* brcms_c_BSSinit() will sanitize the rateset before
5394 	 * using it.. */
5395 	if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5396 		brcms_c_set_home_chanspec(wlc, chspec);
5397 		brcms_c_suspend_mac_and_wait(wlc);
5398 		brcms_c_set_chanspec(wlc, chspec);
5399 		brcms_c_enable_mac(wlc);
5400 	}
5401 	return 0;
5402 }
5403 
5404 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5405 {
5406 	int ac;
5407 
5408 	if (srl < 1 || srl > RETRY_SHORT_MAX ||
5409 	    lrl < 1 || lrl > RETRY_SHORT_MAX)
5410 		return -EINVAL;
5411 
5412 	wlc->SRL = srl;
5413 	wlc->LRL = lrl;
5414 
5415 	brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5416 
5417 	for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5418 		wlc->wme_retries[ac] =	SFIELD(wlc->wme_retries[ac],
5419 					       EDCF_SHORT,  wlc->SRL);
5420 		wlc->wme_retries[ac] =	SFIELD(wlc->wme_retries[ac],
5421 					       EDCF_LONG, wlc->LRL);
5422 	}
5423 	brcms_c_wme_retries_write(wlc);
5424 
5425 	return 0;
5426 }
5427 
5428 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5429 				 struct brcm_rateset *currs)
5430 {
5431 	struct brcms_c_rateset *rs;
5432 
5433 	if (wlc->pub->associated)
5434 		rs = &wlc->bsscfg->current_bss->rateset;
5435 	else
5436 		rs = &wlc->default_bss->rateset;
5437 
5438 	/* Copy only legacy rateset section */
5439 	currs->count = rs->count;
5440 	memcpy(&currs->rates, &rs->rates, rs->count);
5441 }
5442 
5443 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5444 {
5445 	struct brcms_c_rateset internal_rs;
5446 	int bcmerror;
5447 
5448 	if (rs->count > BRCMS_NUMRATES)
5449 		return -ENOBUFS;
5450 
5451 	memset(&internal_rs, 0, sizeof(internal_rs));
5452 
5453 	/* Copy only legacy rateset section */
5454 	internal_rs.count = rs->count;
5455 	memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5456 
5457 	/* merge rateset coming in with the current mcsset */
5458 	if (wlc->pub->_n_enab & SUPPORT_11N) {
5459 		struct brcms_bss_info *mcsset_bss;
5460 		if (wlc->pub->associated)
5461 			mcsset_bss = wlc->bsscfg->current_bss;
5462 		else
5463 			mcsset_bss = wlc->default_bss;
5464 		memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5465 		       MCSSET_LEN);
5466 	}
5467 
5468 	bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5469 	if (!bcmerror)
5470 		brcms_c_ofdm_rateset_war(wlc);
5471 
5472 	return bcmerror;
5473 }
5474 
5475 static void brcms_c_time_lock(struct brcms_c_info *wlc)
5476 {
5477 	bcma_set32(wlc->hw->d11core, D11REGOFFS(maccontrol), MCTL_TBTTHOLD);
5478 	/* Commit the write */
5479 	bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5480 }
5481 
5482 static void brcms_c_time_unlock(struct brcms_c_info *wlc)
5483 {
5484 	bcma_mask32(wlc->hw->d11core, D11REGOFFS(maccontrol), ~MCTL_TBTTHOLD);
5485 	/* Commit the write */
5486 	bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5487 }
5488 
5489 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5490 {
5491 	u32 bcnint_us;
5492 
5493 	if (period == 0)
5494 		return -EINVAL;
5495 
5496 	wlc->default_bss->beacon_period = period;
5497 
5498 	bcnint_us = period << 10;
5499 	brcms_c_time_lock(wlc);
5500 	bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfprep),
5501 		     (bcnint_us << CFPREP_CBI_SHIFT));
5502 	bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfpstart), bcnint_us);
5503 	brcms_c_time_unlock(wlc);
5504 
5505 	return 0;
5506 }
5507 
5508 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5509 {
5510 	return wlc->band->phytype;
5511 }
5512 
5513 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5514 {
5515 	wlc->shortslot_override = sslot_override;
5516 
5517 	/*
5518 	 * shortslot is an 11g feature, so no more work if we are
5519 	 * currently on the 5G band
5520 	 */
5521 	if (wlc->band->bandtype == BRCM_BAND_5G)
5522 		return;
5523 
5524 	if (wlc->pub->up && wlc->pub->associated) {
5525 		/* let watchdog or beacon processing update shortslot */
5526 	} else if (wlc->pub->up) {
5527 		/* unassociated shortslot is off */
5528 		brcms_c_switch_shortslot(wlc, false);
5529 	} else {
5530 		/* driver is down, so just update the brcms_c_info
5531 		 * value */
5532 		if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5533 			wlc->shortslot = false;
5534 		else
5535 			wlc->shortslot =
5536 			    (wlc->shortslot_override ==
5537 			     BRCMS_SHORTSLOT_ON);
5538 	}
5539 }
5540 
5541 /*
5542  * register watchdog and down handlers.
5543  */
5544 int brcms_c_module_register(struct brcms_pub *pub,
5545 			    const char *name, struct brcms_info *hdl,
5546 			    int (*d_fn)(void *handle))
5547 {
5548 	struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5549 	int i;
5550 
5551 	/* find an empty entry and just add, no duplication check! */
5552 	for (i = 0; i < BRCMS_MAXMODULES; i++) {
5553 		if (wlc->modulecb[i].name[0] == '\0') {
5554 			strscpy(wlc->modulecb[i].name, name,
5555 				sizeof(wlc->modulecb[i].name));
5556 			wlc->modulecb[i].hdl = hdl;
5557 			wlc->modulecb[i].down_fn = d_fn;
5558 			return 0;
5559 		}
5560 	}
5561 
5562 	return -ENOSR;
5563 }
5564 
5565 /* unregister module callbacks */
5566 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5567 			      struct brcms_info *hdl)
5568 {
5569 	struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5570 	int i;
5571 
5572 	if (wlc == NULL)
5573 		return -ENODATA;
5574 
5575 	for (i = 0; i < BRCMS_MAXMODULES; i++) {
5576 		if (!strcmp(wlc->modulecb[i].name, name) &&
5577 		    (wlc->modulecb[i].hdl == hdl)) {
5578 			memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i]));
5579 			return 0;
5580 		}
5581 	}
5582 
5583 	/* table not found! */
5584 	return -ENODATA;
5585 }
5586 
5587 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5588 {
5589 	struct pci_dev *pcidev = core->bus->host_pci;
5590 	u16 vendor = pcidev->vendor;
5591 	u16 device = pcidev->device;
5592 
5593 	if (vendor != PCI_VENDOR_ID_BROADCOM) {
5594 		pr_err("unknown vendor id %04x\n", vendor);
5595 		return false;
5596 	}
5597 
5598 	if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
5599 		return true;
5600 	if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5601 		return true;
5602 	if (device == BCM4313_D11N2G_ID || device == BCM4313_CHIP_ID)
5603 		return true;
5604 	if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5605 		return true;
5606 
5607 	pr_err("unknown device id %04x\n", device);
5608 	return false;
5609 }
5610 
5611 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5612 {
5613 	struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5614 
5615 	if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5616 		return true;
5617 
5618 	pr_err("unknown chip id %04x\n", chipinfo->id);
5619 	return false;
5620 }
5621 
5622 bool brcms_c_chipmatch(struct bcma_device *core)
5623 {
5624 	switch (core->bus->hosttype) {
5625 	case BCMA_HOSTTYPE_PCI:
5626 		return brcms_c_chipmatch_pci(core);
5627 	case BCMA_HOSTTYPE_SOC:
5628 		return brcms_c_chipmatch_soc(core);
5629 	default:
5630 		pr_err("unknown host type: %i\n", core->bus->hosttype);
5631 		return false;
5632 	}
5633 }
5634 
5635 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5636 {
5637 	u16 table_ptr;
5638 	u8 phy_rate, index;
5639 
5640 	/* get the phy specific rate encoding for the PLCP SIGNAL field */
5641 	if (is_ofdm_rate(rate))
5642 		table_ptr = M_RT_DIRMAP_A;
5643 	else
5644 		table_ptr = M_RT_DIRMAP_B;
5645 
5646 	/* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5647 	 * the index into the rate table.
5648 	 */
5649 	phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5650 	index = phy_rate & 0xf;
5651 
5652 	/* Find the SHM pointer to the rate table entry by looking in the
5653 	 * Direct-map Table
5654 	 */
5655 	return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5656 }
5657 
5658 /*
5659  * bcmc_fid_generate:
5660  * Generate frame ID for a BCMC packet.  The frag field is not used
5661  * for MC frames so is used as part of the sequence number.
5662  */
5663 static inline u16
5664 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5665 		  struct d11txh *txh)
5666 {
5667 	u16 frameid;
5668 
5669 	frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5670 						  TXFID_QUEUE_MASK);
5671 	frameid |=
5672 	    (((wlc->
5673 	       mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5674 	    TX_BCMC_FIFO;
5675 
5676 	return frameid;
5677 }
5678 
5679 static uint
5680 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5681 		      u8 preamble_type)
5682 {
5683 	uint dur = 0;
5684 
5685 	/*
5686 	 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5687 	 * is less than or equal to the rate of the immediately previous
5688 	 * frame in the FES
5689 	 */
5690 	rspec = brcms_basic_rate(wlc, rspec);
5691 	/* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5692 	dur =
5693 	    brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5694 				(DOT11_ACK_LEN + FCS_LEN));
5695 	return dur;
5696 }
5697 
5698 static uint
5699 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5700 		      u8 preamble_type)
5701 {
5702 	return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5703 }
5704 
5705 static uint
5706 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5707 		     u8 preamble_type)
5708 {
5709 	/*
5710 	 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5711 	 * is less than or equal to the rate of the immediately previous
5712 	 * frame in the FES
5713 	 */
5714 	rspec = brcms_basic_rate(wlc, rspec);
5715 	/* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5716 	return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5717 				   (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5718 				    FCS_LEN));
5719 }
5720 
5721 /* brcms_c_compute_frame_dur()
5722  *
5723  * Calculate the 802.11 MAC header DUR field for MPDU
5724  * DUR for a single frame = 1 SIFS + 1 ACK
5725  * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5726  *
5727  * rate			MPDU rate in unit of 500kbps
5728  * next_frag_len	next MPDU length in bytes
5729  * preamble_type	use short/GF or long/MM PLCP header
5730  */
5731 static u16
5732 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5733 		      u8 preamble_type, uint next_frag_len)
5734 {
5735 	u16 dur, sifs;
5736 
5737 	sifs = get_sifs(wlc->band);
5738 
5739 	dur = sifs;
5740 	dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5741 
5742 	if (next_frag_len) {
5743 		/* Double the current DUR to get 2 SIFS + 2 ACKs */
5744 		dur *= 2;
5745 		/* add another SIFS and the frag time */
5746 		dur += sifs;
5747 		dur +=
5748 		    (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5749 						 next_frag_len);
5750 	}
5751 	return dur;
5752 }
5753 
5754 /* The opposite of brcms_c_calc_frame_time */
5755 static uint
5756 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5757 		   u8 preamble_type, uint dur)
5758 {
5759 	uint nsyms, mac_len, Ndps, kNdps;
5760 	uint rate = rspec2rate(ratespec);
5761 
5762 	if (is_mcs_rate(ratespec)) {
5763 		uint mcs = ratespec & RSPEC_RATE_MASK;
5764 		int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5765 		dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5766 		/* payload calculation matches that of regular ofdm */
5767 		if (wlc->band->bandtype == BRCM_BAND_2G)
5768 			dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5769 		/* kNdbps = kbps * 4 */
5770 		kNdps =	mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5771 				   rspec_issgi(ratespec)) * 4;
5772 		nsyms = dur / APHY_SYMBOL_TIME;
5773 		mac_len =
5774 		    ((nsyms * kNdps) -
5775 		     ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5776 	} else if (is_ofdm_rate(ratespec)) {
5777 		dur -= APHY_PREAMBLE_TIME;
5778 		dur -= APHY_SIGNAL_TIME;
5779 		/* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5780 		Ndps = rate * 2;
5781 		nsyms = dur / APHY_SYMBOL_TIME;
5782 		mac_len =
5783 		    ((nsyms * Ndps) -
5784 		     (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5785 	} else {
5786 		if (preamble_type & BRCMS_SHORT_PREAMBLE)
5787 			dur -= BPHY_PLCP_SHORT_TIME;
5788 		else
5789 			dur -= BPHY_PLCP_TIME;
5790 		mac_len = dur * rate;
5791 		/* divide out factor of 2 in rate (1/2 mbps) */
5792 		mac_len = mac_len / 8 / 2;
5793 	}
5794 	return mac_len;
5795 }
5796 
5797 /*
5798  * Return true if the specified rate is supported by the specified band.
5799  * BRCM_BAND_AUTO indicates the current band.
5800  */
5801 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5802 		    bool verbose)
5803 {
5804 	struct brcms_c_rateset *hw_rateset;
5805 	uint i;
5806 
5807 	if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5808 		hw_rateset = &wlc->band->hw_rateset;
5809 	else if (wlc->pub->_nbands > 1)
5810 		hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5811 	else
5812 		/* other band specified and we are a single band device */
5813 		return false;
5814 
5815 	/* check if this is a mimo rate */
5816 	if (is_mcs_rate(rspec)) {
5817 		if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5818 			goto error;
5819 
5820 		return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5821 	}
5822 
5823 	for (i = 0; i < hw_rateset->count; i++)
5824 		if (hw_rateset->rates[i] == rspec2rate(rspec))
5825 			return true;
5826  error:
5827 	if (verbose)
5828 		brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5829 			  "not in hw_rateset\n", wlc->pub->unit, rspec);
5830 
5831 	return false;
5832 }
5833 
5834 static u32
5835 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5836 		       u32 int_val)
5837 {
5838 	struct bcma_device *core = wlc->hw->d11core;
5839 	u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5840 	u8 rate = int_val & NRATE_RATE_MASK;
5841 	u32 rspec;
5842 	bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5843 	bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5844 	bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5845 				  == NRATE_OVERRIDE_MCS_ONLY);
5846 
5847 	if (!ismcs)
5848 		return (u32) rate;
5849 
5850 	/* validate the combination of rate/mcs/stf is allowed */
5851 	if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5852 		/* mcs only allowed when nmode */
5853 		if (stf > PHY_TXC1_MODE_SDM) {
5854 			brcms_err(core, "wl%d: %s: Invalid stf\n",
5855 				  wlc->pub->unit, __func__);
5856 			goto done;
5857 		}
5858 
5859 		/* mcs 32 is a special case, DUP mode 40 only */
5860 		if (rate == 32) {
5861 			if (!CHSPEC_IS40(wlc->home_chanspec) ||
5862 			    ((stf != PHY_TXC1_MODE_SISO)
5863 			     && (stf != PHY_TXC1_MODE_CDD))) {
5864 				brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5865 					  wlc->pub->unit, __func__);
5866 				goto done;
5867 			}
5868 			/* mcs > 7 must use stf SDM */
5869 		} else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5870 			/* mcs > 7 must use stf SDM */
5871 			if (stf != PHY_TXC1_MODE_SDM) {
5872 				brcms_dbg_mac80211(core, "wl%d: enabling "
5873 						   "SDM mode for mcs %d\n",
5874 						   wlc->pub->unit, rate);
5875 				stf = PHY_TXC1_MODE_SDM;
5876 			}
5877 		} else {
5878 			/*
5879 			 * MCS 0-7 may use SISO, CDD, and for
5880 			 * phy_rev >= 3 STBC
5881 			 */
5882 			if ((stf > PHY_TXC1_MODE_STBC) ||
5883 			    (!BRCMS_STBC_CAP_PHY(wlc)
5884 			     && (stf == PHY_TXC1_MODE_STBC))) {
5885 				brcms_err(core, "wl%d: %s: Invalid STBC\n",
5886 					  wlc->pub->unit, __func__);
5887 				goto done;
5888 			}
5889 		}
5890 	} else if (is_ofdm_rate(rate)) {
5891 		if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
5892 			brcms_err(core, "wl%d: %s: Invalid OFDM\n",
5893 				  wlc->pub->unit, __func__);
5894 			goto done;
5895 		}
5896 	} else if (is_cck_rate(rate)) {
5897 		if ((cur_band->bandtype != BRCM_BAND_2G)
5898 		    || (stf != PHY_TXC1_MODE_SISO)) {
5899 			brcms_err(core, "wl%d: %s: Invalid CCK\n",
5900 				  wlc->pub->unit, __func__);
5901 			goto done;
5902 		}
5903 	} else {
5904 		brcms_err(core, "wl%d: %s: Unknown rate type\n",
5905 			  wlc->pub->unit, __func__);
5906 		goto done;
5907 	}
5908 	/* make sure multiple antennae are available for non-siso rates */
5909 	if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
5910 		brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
5911 			  "request\n", wlc->pub->unit, __func__);
5912 		goto done;
5913 	}
5914 
5915 	rspec = rate;
5916 	if (ismcs) {
5917 		rspec |= RSPEC_MIMORATE;
5918 		/* For STBC populate the STC field of the ratespec */
5919 		if (stf == PHY_TXC1_MODE_STBC) {
5920 			u8 stc;
5921 			stc = 1;	/* Nss for single stream is always 1 */
5922 			rspec |= (stc << RSPEC_STC_SHIFT);
5923 		}
5924 	}
5925 
5926 	rspec |= (stf << RSPEC_STF_SHIFT);
5927 
5928 	if (override_mcs_only)
5929 		rspec |= RSPEC_OVERRIDE_MCS_ONLY;
5930 
5931 	if (issgi)
5932 		rspec |= RSPEC_SHORT_GI;
5933 
5934 	if ((rate != 0)
5935 	    && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
5936 		return rate;
5937 
5938 	return rspec;
5939 done:
5940 	return rate;
5941 }
5942 
5943 /*
5944  * Compute PLCP, but only requires actual rate and length of pkt.
5945  * Rate is given in the driver standard multiple of 500 kbps.
5946  * le is set for 11 Mbps rate if necessary.
5947  * Broken out for PRQ.
5948  */
5949 
5950 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
5951 			     uint length, u8 *plcp)
5952 {
5953 	u16 usec = 0;
5954 	u8 le = 0;
5955 
5956 	switch (rate_500) {
5957 	case BRCM_RATE_1M:
5958 		usec = length << 3;
5959 		break;
5960 	case BRCM_RATE_2M:
5961 		usec = length << 2;
5962 		break;
5963 	case BRCM_RATE_5M5:
5964 		usec = (length << 4) / 11;
5965 		if ((length << 4) - (usec * 11) > 0)
5966 			usec++;
5967 		break;
5968 	case BRCM_RATE_11M:
5969 		usec = (length << 3) / 11;
5970 		if ((length << 3) - (usec * 11) > 0) {
5971 			usec++;
5972 			if ((usec * 11) - (length << 3) >= 8)
5973 				le = D11B_PLCP_SIGNAL_LE;
5974 		}
5975 		break;
5976 
5977 	default:
5978 		brcms_err(wlc->hw->d11core,
5979 			  "brcms_c_cck_plcp_set: unsupported rate %d\n",
5980 			  rate_500);
5981 		rate_500 = BRCM_RATE_1M;
5982 		usec = length << 3;
5983 		break;
5984 	}
5985 	/* PLCP signal byte */
5986 	plcp[0] = rate_500 * 5;	/* r (500kbps) * 5 == r (100kbps) */
5987 	/* PLCP service byte */
5988 	plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
5989 	/* PLCP length u16, little endian */
5990 	plcp[2] = usec & 0xff;
5991 	plcp[3] = (usec >> 8) & 0xff;
5992 	/* PLCP CRC16 */
5993 	plcp[4] = 0;
5994 	plcp[5] = 0;
5995 }
5996 
5997 /* Rate: 802.11 rate code, length: PSDU length in octets */
5998 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
5999 {
6000 	u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6001 	plcp[0] = mcs;
6002 	if (rspec_is40mhz(rspec) || (mcs == 32))
6003 		plcp[0] |= MIMO_PLCP_40MHZ;
6004 	BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6005 	plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6006 	plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6007 	plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6008 	plcp[5] = 0;
6009 }
6010 
6011 /* Rate: 802.11 rate code, length: PSDU length in octets */
6012 static void
6013 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6014 {
6015 	u8 rate_signal;
6016 	u32 tmp = 0;
6017 	int rate = rspec2rate(rspec);
6018 
6019 	/*
6020 	 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6021 	 * transmitted first
6022 	 */
6023 	rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6024 	memset(plcp, 0, D11_PHY_HDR_LEN);
6025 	D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6026 
6027 	tmp = (length & 0xfff) << 5;
6028 	plcp[2] |= (tmp >> 16) & 0xff;
6029 	plcp[1] |= (tmp >> 8) & 0xff;
6030 	plcp[0] |= tmp & 0xff;
6031 }
6032 
6033 /* Rate: 802.11 rate code, length: PSDU length in octets */
6034 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6035 				 uint length, u8 *plcp)
6036 {
6037 	int rate = rspec2rate(rspec);
6038 
6039 	brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6040 }
6041 
6042 static void
6043 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6044 		     uint length, u8 *plcp)
6045 {
6046 	if (is_mcs_rate(rspec))
6047 		brcms_c_compute_mimo_plcp(rspec, length, plcp);
6048 	else if (is_ofdm_rate(rspec))
6049 		brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6050 	else
6051 		brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6052 }
6053 
6054 /* brcms_c_compute_rtscts_dur()
6055  *
6056  * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6057  * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6058  * DUR for CTS-TO-SELF w/ frame    = 2 SIFS         + next frame time + 1 ACK
6059  *
6060  * cts			cts-to-self or rts/cts
6061  * rts_rate		rts or cts rate in unit of 500kbps
6062  * rate			next MPDU rate in unit of 500kbps
6063  * frame_len		next MPDU frame length in bytes
6064  */
6065 u16
6066 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6067 			   u32 rts_rate,
6068 			   u32 frame_rate, u8 rts_preamble_type,
6069 			   u8 frame_preamble_type, uint frame_len, bool ba)
6070 {
6071 	u16 dur, sifs;
6072 
6073 	sifs = get_sifs(wlc->band);
6074 
6075 	if (!cts_only) {
6076 		/* RTS/CTS */
6077 		dur = 3 * sifs;
6078 		dur +=
6079 		    (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6080 					       rts_preamble_type);
6081 	} else {
6082 		/* CTS-TO-SELF */
6083 		dur = 2 * sifs;
6084 	}
6085 
6086 	dur +=
6087 	    (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6088 					 frame_len);
6089 	if (ba)
6090 		dur +=
6091 		    (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6092 					      BRCMS_SHORT_PREAMBLE);
6093 	else
6094 		dur +=
6095 		    (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6096 					       frame_preamble_type);
6097 	return dur;
6098 }
6099 
6100 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6101 {
6102 	u16 phyctl1 = 0;
6103 	u16 bw;
6104 
6105 	if (BRCMS_ISLCNPHY(wlc->band)) {
6106 		bw = PHY_TXC1_BW_20MHZ;
6107 	} else {
6108 		bw = rspec_get_bw(rspec);
6109 		/* 10Mhz is not supported yet */
6110 		if (bw < PHY_TXC1_BW_20MHZ) {
6111 			brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
6112 				  "not supported yet, set to 20L\n", bw);
6113 			bw = PHY_TXC1_BW_20MHZ;
6114 		}
6115 	}
6116 
6117 	if (is_mcs_rate(rspec)) {
6118 		uint mcs = rspec & RSPEC_RATE_MASK;
6119 
6120 		/* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6121 		phyctl1 = rspec_phytxbyte2(rspec);
6122 		/* set the upper byte of phyctl1 */
6123 		phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6124 	} else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6125 		   && !BRCMS_ISSSLPNPHY(wlc->band)) {
6126 		/*
6127 		 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6128 		 * Data Rate. Eventually MIMOPHY would also be converted to
6129 		 * this format
6130 		 */
6131 		/* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6132 		phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6133 	} else {		/* legacy OFDM/CCK */
6134 		s16 phycfg;
6135 		/* get the phyctl byte from rate phycfg table */
6136 		phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6137 		if (phycfg == -1) {
6138 			brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
6139 				  "legacy OFDM/CCK rate\n");
6140 			phycfg = 0;
6141 		}
6142 		/* set the upper byte of phyctl1 */
6143 		phyctl1 =
6144 		    (bw | (phycfg << 8) |
6145 		     (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6146 	}
6147 	return phyctl1;
6148 }
6149 
6150 /*
6151  * Add struct d11txh, struct cck_phy_hdr.
6152  *
6153  * 'p' data must start with 802.11 MAC header
6154  * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6155  *
6156  * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6157  *
6158  */
6159 static u16
6160 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6161 		     struct sk_buff *p, struct scb *scb, uint frag,
6162 		     uint nfrags, uint queue, uint next_frag_len)
6163 {
6164 	struct ieee80211_hdr *h;
6165 	struct d11txh *txh;
6166 	u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6167 	int len, phylen, rts_phylen;
6168 	u16 mch, phyctl, xfts, mainrates;
6169 	u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6170 	u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6171 	u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6172 	bool use_rts = false;
6173 	bool use_cts = false;
6174 	bool use_rifs = false;
6175 	u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6176 	u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6177 	u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6178 	struct ieee80211_rts *rts = NULL;
6179 	bool qos;
6180 	uint ac;
6181 	bool hwtkmic = false;
6182 	u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6183 #define ANTCFG_NONE 0xFF
6184 	u8 antcfg = ANTCFG_NONE;
6185 	u8 fbantcfg = ANTCFG_NONE;
6186 	uint phyctl1_stf = 0;
6187 	u16 durid = 0;
6188 	struct ieee80211_tx_rate *txrate[2];
6189 	int k;
6190 	struct ieee80211_tx_info *tx_info;
6191 	bool is_mcs;
6192 	u16 mimo_txbw;
6193 	u8 mimo_preamble_type;
6194 
6195 	/* locate 802.11 MAC header */
6196 	h = (struct ieee80211_hdr *)(p->data);
6197 	qos = ieee80211_is_data_qos(h->frame_control);
6198 
6199 	/* compute length of frame in bytes for use in PLCP computations */
6200 	len = p->len;
6201 	phylen = len + FCS_LEN;
6202 
6203 	/* Get tx_info */
6204 	tx_info = IEEE80211_SKB_CB(p);
6205 
6206 	/* add PLCP */
6207 	plcp = skb_push(p, D11_PHY_HDR_LEN);
6208 
6209 	/* add Broadcom tx descriptor header */
6210 	txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6211 	memset(txh, 0, D11_TXH_LEN);
6212 
6213 	/* setup frameid */
6214 	if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6215 		/* non-AP STA should never use BCMC queue */
6216 		if (queue == TX_BCMC_FIFO) {
6217 			brcms_err(wlc->hw->d11core,
6218 				  "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6219 				  wlc->pub->unit, __func__);
6220 			frameid = bcmc_fid_generate(wlc, NULL, txh);
6221 		} else {
6222 			/* Increment the counter for first fragment */
6223 			if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6224 				scb->seqnum[p->priority]++;
6225 
6226 			/* extract fragment number from frame first */
6227 			seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6228 			seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6229 			h->seq_ctrl = cpu_to_le16(seq);
6230 
6231 			frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6232 			    (queue & TXFID_QUEUE_MASK);
6233 		}
6234 	}
6235 	frameid |= queue & TXFID_QUEUE_MASK;
6236 
6237 	/* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6238 	if (ieee80211_is_beacon(h->frame_control))
6239 		mcl |= TXC_IGNOREPMQ;
6240 
6241 	txrate[0] = tx_info->control.rates;
6242 	txrate[1] = txrate[0] + 1;
6243 
6244 	/*
6245 	 * if rate control algorithm didn't give us a fallback
6246 	 * rate, use the primary rate
6247 	 */
6248 	if (txrate[1]->idx < 0)
6249 		txrate[1] = txrate[0];
6250 
6251 	for (k = 0; k < hw->max_rates; k++) {
6252 		is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6253 		if (!is_mcs) {
6254 			if ((txrate[k]->idx >= 0)
6255 			    && (txrate[k]->idx <
6256 				hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6257 				rspec[k] =
6258 				    hw->wiphy->bands[tx_info->band]->
6259 				    bitrates[txrate[k]->idx].hw_value;
6260 			} else {
6261 				rspec[k] = BRCM_RATE_1M;
6262 			}
6263 		} else {
6264 			rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6265 					NRATE_MCS_INUSE | txrate[k]->idx);
6266 		}
6267 
6268 		/*
6269 		 * Currently only support same setting for primay and
6270 		 * fallback rates. Unify flags for each rate into a
6271 		 * single value for the frame
6272 		 */
6273 		use_rts |=
6274 		    txrate[k]->
6275 		    flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6276 		use_cts |=
6277 		    txrate[k]->
6278 		    flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6279 
6280 
6281 		/*
6282 		 * (1) RATE:
6283 		 *   determine and validate primary rate
6284 		 *   and fallback rates
6285 		 */
6286 		if (!rspec_active(rspec[k])) {
6287 			rspec[k] = BRCM_RATE_1M;
6288 		} else {
6289 			if (!is_multicast_ether_addr(h->addr1)) {
6290 				/* set tx antenna config */
6291 				brcms_c_antsel_antcfg_get(wlc->asi, false,
6292 					false, 0, 0, &antcfg, &fbantcfg);
6293 			}
6294 		}
6295 	}
6296 
6297 	phyctl1_stf = wlc->stf->ss_opmode;
6298 
6299 	if (wlc->pub->_n_enab & SUPPORT_11N) {
6300 		for (k = 0; k < hw->max_rates; k++) {
6301 			/*
6302 			 * apply siso/cdd to single stream mcs's or ofdm
6303 			 * if rspec is auto selected
6304 			 */
6305 			if (((is_mcs_rate(rspec[k]) &&
6306 			      is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6307 			     is_ofdm_rate(rspec[k]))
6308 			    && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6309 				|| !(rspec[k] & RSPEC_OVERRIDE))) {
6310 				rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6311 
6312 				/* For SISO MCS use STBC if possible */
6313 				if (is_mcs_rate(rspec[k])
6314 				    && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6315 					u8 stc;
6316 
6317 					/* Nss for single stream is always 1 */
6318 					stc = 1;
6319 					rspec[k] |= (PHY_TXC1_MODE_STBC <<
6320 							RSPEC_STF_SHIFT) |
6321 						    (stc << RSPEC_STC_SHIFT);
6322 				} else
6323 					rspec[k] |=
6324 					    (phyctl1_stf << RSPEC_STF_SHIFT);
6325 			}
6326 
6327 			/*
6328 			 * Is the phy configured to use 40MHZ frames? If
6329 			 * so then pick the desired txbw
6330 			 */
6331 			if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6332 				/* default txbw is 20in40 SB */
6333 				mimo_ctlchbw = mimo_txbw =
6334 				   CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6335 								 wlc->band->pi))
6336 				   ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6337 
6338 				if (is_mcs_rate(rspec[k])) {
6339 					/* mcs 32 must be 40b/w DUP */
6340 					if ((rspec[k] & RSPEC_RATE_MASK)
6341 					    == 32) {
6342 						mimo_txbw =
6343 						    PHY_TXC1_BW_40MHZ_DUP;
6344 						/* use override */
6345 					} else if (wlc->mimo_40txbw != AUTO)
6346 						mimo_txbw = wlc->mimo_40txbw;
6347 					/* else check if dst is using 40 Mhz */
6348 					else if (scb->flags & SCB_IS40)
6349 						mimo_txbw = PHY_TXC1_BW_40MHZ;
6350 				} else if (is_ofdm_rate(rspec[k])) {
6351 					if (wlc->ofdm_40txbw != AUTO)
6352 						mimo_txbw = wlc->ofdm_40txbw;
6353 				} else if (wlc->cck_40txbw != AUTO) {
6354 					mimo_txbw = wlc->cck_40txbw;
6355 				}
6356 			} else {
6357 				/*
6358 				 * mcs32 is 40 b/w only.
6359 				 * This is possible for probe packets on
6360 				 * a STA during SCAN
6361 				 */
6362 				if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6363 					/* mcs 0 */
6364 					rspec[k] = RSPEC_MIMORATE;
6365 
6366 				mimo_txbw = PHY_TXC1_BW_20MHZ;
6367 			}
6368 
6369 			/* Set channel width */
6370 			rspec[k] &= ~RSPEC_BW_MASK;
6371 			if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6372 				rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6373 			else
6374 				rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6375 
6376 			/* Disable short GI, not supported yet */
6377 			rspec[k] &= ~RSPEC_SHORT_GI;
6378 
6379 			mimo_preamble_type = BRCMS_MM_PREAMBLE;
6380 			if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6381 				mimo_preamble_type = BRCMS_GF_PREAMBLE;
6382 
6383 			if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6384 			    && (!is_mcs_rate(rspec[k]))) {
6385 				brcms_warn(wlc->hw->d11core,
6386 					   "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n",
6387 					   wlc->pub->unit, __func__);
6388 			}
6389 
6390 			if (is_mcs_rate(rspec[k])) {
6391 				preamble_type[k] = mimo_preamble_type;
6392 
6393 				/*
6394 				 * if SGI is selected, then forced mm
6395 				 * for single stream
6396 				 */
6397 				if ((rspec[k] & RSPEC_SHORT_GI)
6398 				    && is_single_stream(rspec[k] &
6399 							RSPEC_RATE_MASK))
6400 					preamble_type[k] = BRCMS_MM_PREAMBLE;
6401 			}
6402 
6403 			/* should be better conditionalized */
6404 			if (!is_mcs_rate(rspec[0])
6405 			    && (tx_info->control.rates[0].
6406 				flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6407 				preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6408 		}
6409 	} else {
6410 		for (k = 0; k < hw->max_rates; k++) {
6411 			/* Set ctrlchbw as 20Mhz */
6412 			rspec[k] &= ~RSPEC_BW_MASK;
6413 			rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6414 
6415 			/* for nphy, stf of ofdm frames must follow policies */
6416 			if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6417 				rspec[k] &= ~RSPEC_STF_MASK;
6418 				rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6419 			}
6420 		}
6421 	}
6422 
6423 	/* Reset these for use with AMPDU's */
6424 	txrate[0]->count = 0;
6425 	txrate[1]->count = 0;
6426 
6427 	/* (2) PROTECTION, may change rspec */
6428 	if ((ieee80211_is_data(h->frame_control) ||
6429 	    ieee80211_is_mgmt(h->frame_control)) &&
6430 	    (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6431 		use_rts = true;
6432 
6433 	/* (3) PLCP: determine PLCP header and MAC duration,
6434 	 * fill struct d11txh */
6435 	brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6436 	brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6437 	memcpy(&txh->FragPLCPFallback,
6438 	       plcp_fallback, sizeof(txh->FragPLCPFallback));
6439 
6440 	/* Length field now put in CCK FBR CRC field */
6441 	if (is_cck_rate(rspec[1])) {
6442 		txh->FragPLCPFallback[4] = phylen & 0xff;
6443 		txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6444 	}
6445 
6446 	/* MIMO-RATE: need validation ?? */
6447 	mainrates = is_ofdm_rate(rspec[0]) ?
6448 			D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6449 			plcp[0];
6450 
6451 	/* DUR field for main rate */
6452 	if (!ieee80211_is_pspoll(h->frame_control) &&
6453 	    !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6454 		durid =
6455 		    brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6456 					  next_frag_len);
6457 		h->duration_id = cpu_to_le16(durid);
6458 	} else if (use_rifs) {
6459 		/* NAV protect to end of next max packet size */
6460 		durid =
6461 		    (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6462 						 preamble_type[0],
6463 						 DOT11_MAX_FRAG_LEN);
6464 		durid += RIFS_11N_TIME;
6465 		h->duration_id = cpu_to_le16(durid);
6466 	}
6467 
6468 	/* DUR field for fallback rate */
6469 	if (ieee80211_is_pspoll(h->frame_control))
6470 		txh->FragDurFallback = h->duration_id;
6471 	else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6472 		txh->FragDurFallback = 0;
6473 	else {
6474 		durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6475 					      preamble_type[1], next_frag_len);
6476 		txh->FragDurFallback = cpu_to_le16(durid);
6477 	}
6478 
6479 	/* (4) MAC-HDR: MacTxControlLow */
6480 	if (frag == 0)
6481 		mcl |= TXC_STARTMSDU;
6482 
6483 	if (!is_multicast_ether_addr(h->addr1))
6484 		mcl |= TXC_IMMEDACK;
6485 
6486 	if (wlc->band->bandtype == BRCM_BAND_5G)
6487 		mcl |= TXC_FREQBAND_5G;
6488 
6489 	if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6490 		mcl |= TXC_BW_40;
6491 
6492 	/* set AMIC bit if using hardware TKIP MIC */
6493 	if (hwtkmic)
6494 		mcl |= TXC_AMIC;
6495 
6496 	txh->MacTxControlLow = cpu_to_le16(mcl);
6497 
6498 	/* MacTxControlHigh */
6499 	mch = 0;
6500 
6501 	/* Set fallback rate preamble type */
6502 	if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6503 	    (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6504 		if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6505 			mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6506 	}
6507 
6508 	/* MacFrameControl */
6509 	memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6510 	txh->TxFesTimeNormal = cpu_to_le16(0);
6511 
6512 	txh->TxFesTimeFallback = cpu_to_le16(0);
6513 
6514 	/* TxFrameRA */
6515 	memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6516 
6517 	/* TxFrameID */
6518 	txh->TxFrameID = cpu_to_le16(frameid);
6519 
6520 	/*
6521 	 * TxStatus, Note the case of recreating the first frag of a suppressed
6522 	 * frame then we may need to reset the retry cnt's via the status reg
6523 	 */
6524 	txh->TxStatus = cpu_to_le16(status);
6525 
6526 	/*
6527 	 * extra fields for ucode AMPDU aggregation, the new fields are added to
6528 	 * the END of previous structure so that it's compatible in driver.
6529 	 */
6530 	txh->MaxNMpdus = cpu_to_le16(0);
6531 	txh->MaxABytes_MRT = cpu_to_le16(0);
6532 	txh->MaxABytes_FBR = cpu_to_le16(0);
6533 	txh->MinMBytes = cpu_to_le16(0);
6534 
6535 	/* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6536 	 * furnish struct d11txh */
6537 	/* RTS PLCP header and RTS frame */
6538 	if (use_rts || use_cts) {
6539 		if (use_rts && use_cts)
6540 			use_cts = false;
6541 
6542 		for (k = 0; k < 2; k++) {
6543 			rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6544 							      false,
6545 							      mimo_ctlchbw);
6546 		}
6547 
6548 		if (!is_ofdm_rate(rts_rspec[0]) &&
6549 		    !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6550 		      (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6551 			rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6552 			mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6553 		}
6554 
6555 		if (!is_ofdm_rate(rts_rspec[1]) &&
6556 		    !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6557 		      (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6558 			rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6559 			mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6560 		}
6561 
6562 		/* RTS/CTS additions to MacTxControlLow */
6563 		if (use_cts) {
6564 			txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6565 		} else {
6566 			txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6567 			txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6568 		}
6569 
6570 		/* RTS PLCP header */
6571 		rts_plcp = txh->RTSPhyHeader;
6572 		if (use_cts)
6573 			rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6574 		else
6575 			rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6576 
6577 		brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6578 
6579 		/* fallback rate version of RTS PLCP header */
6580 		brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6581 				 rts_plcp_fallback);
6582 		memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6583 		       sizeof(txh->RTSPLCPFallback));
6584 
6585 		/* RTS frame fields... */
6586 		rts = (struct ieee80211_rts *)&txh->rts_frame;
6587 
6588 		durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6589 					       rspec[0], rts_preamble_type[0],
6590 					       preamble_type[0], phylen, false);
6591 		rts->duration = cpu_to_le16(durid);
6592 		/* fallback rate version of RTS DUR field */
6593 		durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6594 					       rts_rspec[1], rspec[1],
6595 					       rts_preamble_type[1],
6596 					       preamble_type[1], phylen, false);
6597 		txh->RTSDurFallback = cpu_to_le16(durid);
6598 
6599 		if (use_cts) {
6600 			rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6601 							 IEEE80211_STYPE_CTS);
6602 
6603 			memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6604 		} else {
6605 			rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6606 							 IEEE80211_STYPE_RTS);
6607 
6608 			memcpy(&rts->ra, &h->addr1, ETH_ALEN);
6609 			memcpy(&rts->ta, &h->addr2, ETH_ALEN);
6610 		}
6611 
6612 		/* mainrate
6613 		 *    low 8 bits: main frag rate/mcs,
6614 		 *    high 8 bits: rts/cts rate/mcs
6615 		 */
6616 		mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6617 				D11A_PHY_HDR_GRATE(
6618 					(struct ofdm_phy_hdr *) rts_plcp) :
6619 				rts_plcp[0]) << 8;
6620 	} else {
6621 		memset(txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6622 		memset(&txh->rts_frame, 0, sizeof(struct ieee80211_rts));
6623 		memset(txh->RTSPLCPFallback, 0, sizeof(txh->RTSPLCPFallback));
6624 		txh->RTSDurFallback = 0;
6625 	}
6626 
6627 #ifdef SUPPORT_40MHZ
6628 	/* add null delimiter count */
6629 	if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6630 		txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6631 		   brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6632 
6633 #endif
6634 
6635 	/*
6636 	 * Now that RTS/RTS FB preamble types are updated, write
6637 	 * the final value
6638 	 */
6639 	txh->MacTxControlHigh = cpu_to_le16(mch);
6640 
6641 	/*
6642 	 * MainRates (both the rts and frag plcp rates have
6643 	 * been calculated now)
6644 	 */
6645 	txh->MainRates = cpu_to_le16(mainrates);
6646 
6647 	/* XtraFrameTypes */
6648 	xfts = frametype(rspec[1], wlc->mimoft);
6649 	xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6650 	xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6651 	xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6652 							     XFTS_CHANNEL_SHIFT;
6653 	txh->XtraFrameTypes = cpu_to_le16(xfts);
6654 
6655 	/* PhyTxControlWord */
6656 	phyctl = frametype(rspec[0], wlc->mimoft);
6657 	if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6658 	    (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6659 		if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6660 			phyctl |= PHY_TXC_SHORT_HDR;
6661 	}
6662 
6663 	/* phytxant is properly bit shifted */
6664 	phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6665 	txh->PhyTxControlWord = cpu_to_le16(phyctl);
6666 
6667 	/* PhyTxControlWord_1 */
6668 	if (BRCMS_PHY_11N_CAP(wlc->band)) {
6669 		u16 phyctl1 = 0;
6670 
6671 		phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
6672 		txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
6673 		phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
6674 		txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
6675 
6676 		if (use_rts || use_cts) {
6677 			phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
6678 			txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
6679 			phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
6680 			txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
6681 		}
6682 
6683 		/*
6684 		 * For mcs frames, if mixedmode(overloaded with long preamble)
6685 		 * is going to be set, fill in non-zero MModeLen and/or
6686 		 * MModeFbrLen it will be unnecessary if they are separated
6687 		 */
6688 		if (is_mcs_rate(rspec[0]) &&
6689 		    (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
6690 			u16 mmodelen =
6691 			    brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
6692 			txh->MModeLen = cpu_to_le16(mmodelen);
6693 		}
6694 
6695 		if (is_mcs_rate(rspec[1]) &&
6696 		    (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
6697 			u16 mmodefbrlen =
6698 			    brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
6699 			txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
6700 		}
6701 	}
6702 
6703 	ac = skb_get_queue_mapping(p);
6704 	if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
6705 		uint frag_dur, dur, dur_fallback;
6706 
6707 		/* WME: Update TXOP threshold */
6708 		if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
6709 			frag_dur =
6710 			    brcms_c_calc_frame_time(wlc, rspec[0],
6711 					preamble_type[0], phylen);
6712 
6713 			if (rts) {
6714 				/* 1 RTS or CTS-to-self frame */
6715 				dur =
6716 				    brcms_c_calc_cts_time(wlc, rts_rspec[0],
6717 						      rts_preamble_type[0]);
6718 				dur_fallback =
6719 				    brcms_c_calc_cts_time(wlc, rts_rspec[1],
6720 						      rts_preamble_type[1]);
6721 				/* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6722 				dur += le16_to_cpu(rts->duration);
6723 				dur_fallback +=
6724 					le16_to_cpu(txh->RTSDurFallback);
6725 			} else if (use_rifs) {
6726 				dur = frag_dur;
6727 				dur_fallback = 0;
6728 			} else {
6729 				/* frame + SIFS + ACK */
6730 				dur = frag_dur;
6731 				dur +=
6732 				    brcms_c_compute_frame_dur(wlc, rspec[0],
6733 							  preamble_type[0], 0);
6734 
6735 				dur_fallback =
6736 				    brcms_c_calc_frame_time(wlc, rspec[1],
6737 							preamble_type[1],
6738 							phylen);
6739 				dur_fallback +=
6740 				    brcms_c_compute_frame_dur(wlc, rspec[1],
6741 							  preamble_type[1], 0);
6742 			}
6743 			/* NEED to set TxFesTimeNormal (hard) */
6744 			txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
6745 			/*
6746 			 * NEED to set fallback rate version of
6747 			 * TxFesTimeNormal (hard)
6748 			 */
6749 			txh->TxFesTimeFallback =
6750 				cpu_to_le16((u16) dur_fallback);
6751 
6752 			/*
6753 			 * update txop byte threshold (txop minus intraframe
6754 			 * overhead)
6755 			 */
6756 			if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
6757 				uint newfragthresh;
6758 
6759 				newfragthresh =
6760 				    brcms_c_calc_frame_len(wlc,
6761 					rspec[0], preamble_type[0],
6762 					(wlc->edcf_txop[ac] -
6763 						(dur - frag_dur)));
6764 				/* range bound the fragthreshold */
6765 				if (newfragthresh < DOT11_MIN_FRAG_LEN)
6766 					newfragthresh =
6767 					    DOT11_MIN_FRAG_LEN;
6768 				else if (newfragthresh >
6769 					 wlc->usr_fragthresh)
6770 					newfragthresh =
6771 					    wlc->usr_fragthresh;
6772 				/* update the fragthresh and do txc update */
6773 				if (wlc->fragthresh[queue] !=
6774 				    (u16) newfragthresh)
6775 					wlc->fragthresh[queue] =
6776 					    (u16) newfragthresh;
6777 			} else {
6778 				brcms_warn(wlc->hw->d11core,
6779 					   "wl%d: %s txop invalid for rate %d\n",
6780 					   wlc->pub->unit, fifo_names[queue],
6781 					   rspec2rate(rspec[0]));
6782 			}
6783 
6784 			if (dur > wlc->edcf_txop[ac])
6785 				brcms_warn(wlc->hw->d11core,
6786 					   "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n",
6787 					   wlc->pub->unit, __func__,
6788 					   fifo_names[queue],
6789 					   phylen, wlc->fragthresh[queue],
6790 					   dur, wlc->edcf_txop[ac]);
6791 		}
6792 	}
6793 
6794 	return 0;
6795 }
6796 
6797 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
6798 {
6799 	struct dma_pub *dma;
6800 	int fifo, ret = -ENOSPC;
6801 	struct d11txh *txh;
6802 	u16 frameid = INVALIDFID;
6803 
6804 	fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
6805 	dma = wlc->hw->di[fifo];
6806 	txh = (struct d11txh *)(skb->data);
6807 
6808 	if (dma->txavail == 0) {
6809 		/*
6810 		 * We sometimes get a frame from mac80211 after stopping
6811 		 * the queues. This only ever seems to be a single frame
6812 		 * and is seems likely to be a race. TX_HEADROOM should
6813 		 * ensure that we have enough space to handle these stray
6814 		 * packets, so warn if there isn't. If we're out of space
6815 		 * in the tx ring and the tx queue isn't stopped then
6816 		 * we've really got a bug; warn loudly if that happens.
6817 		 */
6818 		brcms_warn(wlc->hw->d11core,
6819 			   "Received frame for tx with no space in DMA ring\n");
6820 		WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
6821 						 skb_get_queue_mapping(skb)));
6822 		return -ENOSPC;
6823 	}
6824 
6825 	/* When a BC/MC frame is being committed to the BCMC fifo
6826 	 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6827 	 */
6828 	if (fifo == TX_BCMC_FIFO)
6829 		frameid = le16_to_cpu(txh->TxFrameID);
6830 
6831 	/* Commit BCMC sequence number in the SHM frame ID location */
6832 	if (frameid != INVALIDFID) {
6833 		/*
6834 		 * To inform the ucode of the last mcast frame posted
6835 		 * so that it can clear moredata bit
6836 		 */
6837 		brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
6838 	}
6839 
6840 	ret = brcms_c_txfifo(wlc, fifo, skb);
6841 	/*
6842 	 * The only reason for brcms_c_txfifo to fail is because
6843 	 * there weren't any DMA descriptors, but we've already
6844 	 * checked for that. So if it does fail yell loudly.
6845 	 */
6846 	WARN_ON_ONCE(ret);
6847 
6848 	return ret;
6849 }
6850 
6851 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
6852 			      struct ieee80211_hw *hw)
6853 {
6854 	uint fifo;
6855 	struct scb *scb = &wlc->pri_scb;
6856 
6857 	fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6858 	brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
6859 	if (!brcms_c_tx(wlc, sdu))
6860 		return true;
6861 
6862 	/* packet discarded */
6863 	dev_kfree_skb_any(sdu);
6864 	return false;
6865 }
6866 
6867 int
6868 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
6869 {
6870 	struct dma_pub *dma = wlc->hw->di[fifo];
6871 	int ret;
6872 	u16 queue;
6873 
6874 	ret = dma_txfast(wlc, dma, p);
6875 	if (ret	< 0)
6876 		wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
6877 
6878 	/*
6879 	 * Stop queue if DMA ring is full. Reserve some free descriptors,
6880 	 * as we sometimes receive a frame from mac80211 after the queues
6881 	 * are stopped.
6882 	 */
6883 	queue = skb_get_queue_mapping(p);
6884 	if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
6885 	    !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
6886 		ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
6887 
6888 	return ret;
6889 }
6890 
6891 u32
6892 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
6893 			   bool use_rspec, u16 mimo_ctlchbw)
6894 {
6895 	u32 rts_rspec = 0;
6896 
6897 	if (use_rspec)
6898 		/* use frame rate as rts rate */
6899 		rts_rspec = rspec;
6900 	else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
6901 		/* Use 11Mbps as the g protection RTS target rate and fallback.
6902 		 * Use the brcms_basic_rate() lookup to find the best basic rate
6903 		 * under the target in case 11 Mbps is not Basic.
6904 		 * 6 and 9 Mbps are not usually selected by rate selection, but
6905 		 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
6906 		 * is more robust.
6907 		 */
6908 		rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
6909 	else
6910 		/* calculate RTS rate and fallback rate based on the frame rate
6911 		 * RTS must be sent at a basic rate since it is a
6912 		 * control frame, sec 9.6 of 802.11 spec
6913 		 */
6914 		rts_rspec = brcms_basic_rate(wlc, rspec);
6915 
6916 	if (BRCMS_PHY_11N_CAP(wlc->band)) {
6917 		/* set rts txbw to correct side band */
6918 		rts_rspec &= ~RSPEC_BW_MASK;
6919 
6920 		/*
6921 		 * if rspec/rspec_fallback is 40MHz, then send RTS on both
6922 		 * 20MHz channel (DUP), otherwise send RTS on control channel
6923 		 */
6924 		if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
6925 			rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
6926 		else
6927 			rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6928 
6929 		/* pick siso/cdd as default for ofdm */
6930 		if (is_ofdm_rate(rts_rspec)) {
6931 			rts_rspec &= ~RSPEC_STF_MASK;
6932 			rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
6933 		}
6934 	}
6935 	return rts_rspec;
6936 }
6937 
6938 /* Update beacon listen interval in shared memory */
6939 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
6940 {
6941 	/* wake up every DTIM is the default */
6942 	if (wlc->bcn_li_dtim == 1)
6943 		brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
6944 	else
6945 		brcms_b_write_shm(wlc->hw, M_BCN_LI,
6946 			      (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
6947 }
6948 
6949 static void
6950 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
6951 		  u32 *tsf_h_ptr)
6952 {
6953 	struct bcma_device *core = wlc_hw->d11core;
6954 
6955 	/* read the tsf timer low, then high to get an atomic read */
6956 	*tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
6957 	*tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
6958 }
6959 
6960 /*
6961  * recover 64bit TSF value from the 16bit TSF value in the rx header
6962  * given the assumption that the TSF passed in header is within 65ms
6963  * of the current tsf.
6964  *
6965  * 6       5       4       4       3       2       1
6966  * 3.......6.......8.......0.......2.......4.......6.......8......0
6967  * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
6968  *
6969  * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
6970  * tsf_l is filled in by brcms_b_recv, which is done earlier in the
6971  * receive call sequence after rx interrupt. Only the higher 16 bits
6972  * are used. Finally, the tsf_h is read from the tsf register.
6973  */
6974 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
6975 				 struct d11rxhdr *rxh)
6976 {
6977 	u32 tsf_h, tsf_l;
6978 	u16 rx_tsf_0_15, rx_tsf_16_31;
6979 
6980 	brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
6981 
6982 	rx_tsf_16_31 = (u16)(tsf_l >> 16);
6983 	rx_tsf_0_15 = rxh->RxTSFTime;
6984 
6985 	/*
6986 	 * a greater tsf time indicates the low 16 bits of
6987 	 * tsf_l wrapped, so decrement the high 16 bits.
6988 	 */
6989 	if ((u16)tsf_l < rx_tsf_0_15) {
6990 		rx_tsf_16_31 -= 1;
6991 		if (rx_tsf_16_31 == 0xffff)
6992 			tsf_h -= 1;
6993 	}
6994 
6995 	return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
6996 }
6997 
6998 static void
6999 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7000 		     struct sk_buff *p,
7001 		     struct ieee80211_rx_status *rx_status)
7002 {
7003 	int channel;
7004 	u32 rspec;
7005 	unsigned char *plcp;
7006 
7007 	/* fill in TSF and flag its presence */
7008 	rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7009 	rx_status->flag |= RX_FLAG_MACTIME_START;
7010 
7011 	channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7012 
7013 	rx_status->band =
7014 		channel > 14 ? NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
7015 	rx_status->freq =
7016 		ieee80211_channel_to_frequency(channel, rx_status->band);
7017 
7018 	rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7019 
7020 	/* noise */
7021 	/* qual */
7022 	rx_status->antenna =
7023 		(rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7024 
7025 	plcp = p->data;
7026 
7027 	rspec = brcms_c_compute_rspec(rxh, plcp);
7028 	if (is_mcs_rate(rspec)) {
7029 		rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7030 		rx_status->encoding = RX_ENC_HT;
7031 		if (rspec_is40mhz(rspec))
7032 			rx_status->bw = RATE_INFO_BW_40;
7033 	} else {
7034 		switch (rspec2rate(rspec)) {
7035 		case BRCM_RATE_1M:
7036 			rx_status->rate_idx = 0;
7037 			break;
7038 		case BRCM_RATE_2M:
7039 			rx_status->rate_idx = 1;
7040 			break;
7041 		case BRCM_RATE_5M5:
7042 			rx_status->rate_idx = 2;
7043 			break;
7044 		case BRCM_RATE_11M:
7045 			rx_status->rate_idx = 3;
7046 			break;
7047 		case BRCM_RATE_6M:
7048 			rx_status->rate_idx = 4;
7049 			break;
7050 		case BRCM_RATE_9M:
7051 			rx_status->rate_idx = 5;
7052 			break;
7053 		case BRCM_RATE_12M:
7054 			rx_status->rate_idx = 6;
7055 			break;
7056 		case BRCM_RATE_18M:
7057 			rx_status->rate_idx = 7;
7058 			break;
7059 		case BRCM_RATE_24M:
7060 			rx_status->rate_idx = 8;
7061 			break;
7062 		case BRCM_RATE_36M:
7063 			rx_status->rate_idx = 9;
7064 			break;
7065 		case BRCM_RATE_48M:
7066 			rx_status->rate_idx = 10;
7067 			break;
7068 		case BRCM_RATE_54M:
7069 			rx_status->rate_idx = 11;
7070 			break;
7071 		default:
7072 			brcms_err(wlc->hw->d11core,
7073 				  "%s: Unknown rate\n", __func__);
7074 		}
7075 
7076 		/*
7077 		 * For 5GHz, we should decrease the index as it is
7078 		 * a subset of the 2.4G rates. See bitrates field
7079 		 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7080 		 */
7081 		if (rx_status->band == NL80211_BAND_5GHZ)
7082 			rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7083 
7084 		/* Determine short preamble and rate_idx */
7085 		if (is_cck_rate(rspec)) {
7086 			if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7087 				rx_status->enc_flags |= RX_ENC_FLAG_SHORTPRE;
7088 		} else if (is_ofdm_rate(rspec)) {
7089 			rx_status->enc_flags |= RX_ENC_FLAG_SHORTPRE;
7090 		} else {
7091 			brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
7092 				  __func__);
7093 		}
7094 	}
7095 
7096 	if (plcp3_issgi(plcp[3]))
7097 		rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
7098 
7099 	if (rxh->RxStatus1 & RXS_DECERR) {
7100 		rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7101 		brcms_err(wlc->hw->d11core, "%s:  RX_FLAG_FAILED_PLCP_CRC\n",
7102 			  __func__);
7103 	}
7104 	if (rxh->RxStatus1 & RXS_FCSERR) {
7105 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7106 		brcms_err(wlc->hw->d11core, "%s:  RX_FLAG_FAILED_FCS_CRC\n",
7107 			  __func__);
7108 	}
7109 }
7110 
7111 static void
7112 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7113 		struct sk_buff *p)
7114 {
7115 	int len_mpdu;
7116 	struct ieee80211_rx_status rx_status;
7117 	struct ieee80211_hdr *hdr;
7118 
7119 	memset(&rx_status, 0, sizeof(rx_status));
7120 	prep_mac80211_status(wlc, rxh, p, &rx_status);
7121 
7122 	/* mac header+body length, exclude CRC and plcp header */
7123 	len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7124 	skb_pull(p, D11_PHY_HDR_LEN);
7125 	__skb_trim(p, len_mpdu);
7126 
7127 	/* unmute transmit */
7128 	if (wlc->hw->suspended_fifos) {
7129 		hdr = (struct ieee80211_hdr *)p->data;
7130 		if (ieee80211_is_beacon(hdr->frame_control))
7131 			brcms_b_mute(wlc->hw, false);
7132 	}
7133 
7134 	memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7135 	ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7136 }
7137 
7138 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7139  * number of bytes goes in the length field
7140  *
7141  * Formula given by HT PHY Spec v 1.13
7142  *   len = 3(nsyms + nstream + 3) - 3
7143  */
7144 u16
7145 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7146 		      uint mac_len)
7147 {
7148 	uint nsyms, len = 0, kNdps;
7149 
7150 	if (is_mcs_rate(ratespec)) {
7151 		uint mcs = ratespec & RSPEC_RATE_MASK;
7152 		int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7153 				  rspec_stc(ratespec);
7154 
7155 		/*
7156 		 * the payload duration calculation matches that
7157 		 * of regular ofdm
7158 		 */
7159 		/* 1000Ndbps = kbps * 4 */
7160 		kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7161 				   rspec_issgi(ratespec)) * 4;
7162 
7163 		if (rspec_stc(ratespec) == 0)
7164 			nsyms =
7165 			    CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7166 				  APHY_TAIL_NBITS) * 1000, kNdps);
7167 		else
7168 			/* STBC needs to have even number of symbols */
7169 			nsyms =
7170 			    2 *
7171 			    CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7172 				  APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7173 
7174 		/* (+3) account for HT-SIG(2) and HT-STF(1) */
7175 		nsyms += (tot_streams + 3);
7176 		/*
7177 		 * 3 bytes/symbol @ legacy 6Mbps rate
7178 		 * (-3) excluding service bits and tail bits
7179 		 */
7180 		len = (3 * nsyms) - 3;
7181 	}
7182 
7183 	return (u16) len;
7184 }
7185 
7186 static void
7187 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7188 {
7189 	const struct brcms_c_rateset *rs_dflt;
7190 	struct brcms_c_rateset rs;
7191 	u8 rate;
7192 	u16 entry_ptr;
7193 	u8 plcp[D11_PHY_HDR_LEN];
7194 	u16 dur, sifs;
7195 	uint i;
7196 
7197 	sifs = get_sifs(wlc->band);
7198 
7199 	rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7200 
7201 	brcms_c_rateset_copy(rs_dflt, &rs);
7202 	brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7203 
7204 	/*
7205 	 * walk the phy rate table and update MAC core SHM
7206 	 * basic rate table entries
7207 	 */
7208 	for (i = 0; i < rs.count; i++) {
7209 		rate = rs.rates[i] & BRCMS_RATE_MASK;
7210 
7211 		entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7212 
7213 		/* Calculate the Probe Response PLCP for the given rate */
7214 		brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7215 
7216 		/*
7217 		 * Calculate the duration of the Probe Response
7218 		 * frame plus SIFS for the MAC
7219 		 */
7220 		dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7221 						BRCMS_LONG_PREAMBLE, frame_len);
7222 		dur += sifs;
7223 
7224 		/* Update the SHM Rate Table entry Probe Response values */
7225 		brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7226 			      (u16) (plcp[0] + (plcp[1] << 8)));
7227 		brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7228 			      (u16) (plcp[2] + (plcp[3] << 8)));
7229 		brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7230 	}
7231 }
7232 
7233 int brcms_c_get_header_len(void)
7234 {
7235 	return TXOFF;
7236 }
7237 
7238 static void brcms_c_beacon_write(struct brcms_c_info *wlc,
7239 				 struct sk_buff *beacon, u16 tim_offset,
7240 				 u16 dtim_period, bool bcn0, bool bcn1)
7241 {
7242 	size_t len;
7243 	struct ieee80211_tx_info *tx_info;
7244 	struct brcms_hardware *wlc_hw = wlc->hw;
7245 	struct ieee80211_hw *ieee_hw = brcms_c_pub(wlc)->ieee_hw;
7246 
7247 	/* Get tx_info */
7248 	tx_info = IEEE80211_SKB_CB(beacon);
7249 
7250 	len = min_t(size_t, beacon->len, BCN_TMPL_LEN);
7251 	wlc->bcn_rspec = ieee80211_get_tx_rate(ieee_hw, tx_info)->hw_value;
7252 
7253 	brcms_c_compute_plcp(wlc, wlc->bcn_rspec,
7254 			     len + FCS_LEN - D11_PHY_HDR_LEN, beacon->data);
7255 
7256 	/* "Regular" and 16 MBSS but not for 4 MBSS */
7257 	/* Update the phytxctl for the beacon based on the rspec */
7258 	brcms_c_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec);
7259 
7260 	if (bcn0) {
7261 		/* write the probe response into the template region */
7262 		brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE,
7263 					    (len + 3) & ~3, beacon->data);
7264 
7265 		/* write beacon length to SCR */
7266 		brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
7267 	}
7268 	if (bcn1) {
7269 		/* write the probe response into the template region */
7270 		brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE,
7271 					    (len + 3) & ~3, beacon->data);
7272 
7273 		/* write beacon length to SCR */
7274 		brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
7275 	}
7276 
7277 	if (tim_offset != 0) {
7278 		brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7279 				  tim_offset + D11B_PHY_HDR_LEN);
7280 		brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, dtim_period);
7281 	} else {
7282 		brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7283 				  len + D11B_PHY_HDR_LEN);
7284 		brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, 0);
7285 	}
7286 }
7287 
7288 static void brcms_c_update_beacon_hw(struct brcms_c_info *wlc,
7289 				     struct sk_buff *beacon, u16 tim_offset,
7290 				     u16 dtim_period)
7291 {
7292 	struct brcms_hardware *wlc_hw = wlc->hw;
7293 	struct bcma_device *core = wlc_hw->d11core;
7294 
7295 	/* Hardware beaconing for this config */
7296 	u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD;
7297 
7298 	/* Check if both templates are in use, if so sched. an interrupt
7299 	 *      that will call back into this routine
7300 	 */
7301 	if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid)
7302 		/* clear any previous status */
7303 		bcma_write32(core, D11REGOFFS(macintstatus), MI_BCNTPL);
7304 
7305 	if (wlc->beacon_template_virgin) {
7306 		wlc->beacon_template_virgin = false;
7307 		brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true,
7308 				     true);
7309 		/* mark beacon0 valid */
7310 		bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD);
7311 		return;
7312 	}
7313 
7314 	/* Check that after scheduling the interrupt both of the
7315 	 *      templates are still busy. if not clear the int. & remask
7316 	 */
7317 	if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid) {
7318 		wlc->defmacintmask |= MI_BCNTPL;
7319 		return;
7320 	}
7321 
7322 	if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN0VLD)) {
7323 		brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true,
7324 				     false);
7325 		/* mark beacon0 valid */
7326 		bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD);
7327 		return;
7328 	}
7329 	if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN1VLD)) {
7330 		brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period,
7331 				     false, true);
7332 		/* mark beacon0 valid */
7333 		bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN1VLD);
7334 	}
7335 }
7336 
7337 /*
7338  * Update all beacons for the system.
7339  */
7340 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7341 {
7342 	struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7343 
7344 	if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP ||
7345 			     bsscfg->type == BRCMS_TYPE_ADHOC)) {
7346 		/* Clear the soft intmask */
7347 		wlc->defmacintmask &= ~MI_BCNTPL;
7348 		if (!wlc->beacon)
7349 			return;
7350 		brcms_c_update_beacon_hw(wlc, wlc->beacon,
7351 					 wlc->beacon_tim_offset,
7352 					 wlc->beacon_dtim_period);
7353 	}
7354 }
7355 
7356 void brcms_c_set_new_beacon(struct brcms_c_info *wlc, struct sk_buff *beacon,
7357 			    u16 tim_offset, u16 dtim_period)
7358 {
7359 	if (!beacon)
7360 		return;
7361 	if (wlc->beacon)
7362 		dev_kfree_skb_any(wlc->beacon);
7363 	wlc->beacon = beacon;
7364 
7365 	/* add PLCP */
7366 	skb_push(wlc->beacon, D11_PHY_HDR_LEN);
7367 	wlc->beacon_tim_offset = tim_offset;
7368 	wlc->beacon_dtim_period = dtim_period;
7369 	brcms_c_update_beacon(wlc);
7370 }
7371 
7372 void brcms_c_set_new_probe_resp(struct brcms_c_info *wlc,
7373 				struct sk_buff *probe_resp)
7374 {
7375 	if (!probe_resp)
7376 		return;
7377 	if (wlc->probe_resp)
7378 		dev_kfree_skb_any(wlc->probe_resp);
7379 	wlc->probe_resp = probe_resp;
7380 
7381 	/* add PLCP */
7382 	skb_push(wlc->probe_resp, D11_PHY_HDR_LEN);
7383 	brcms_c_update_probe_resp(wlc, false);
7384 }
7385 
7386 void brcms_c_enable_probe_resp(struct brcms_c_info *wlc, bool enable)
7387 {
7388 	/*
7389 	 * prevent ucode from sending probe responses by setting the timeout
7390 	 * to 1, it can not send it in that time frame.
7391 	 */
7392 	wlc->prb_resp_timeout = enable ? BRCMS_PRB_RESP_TIMEOUT : 1;
7393 	brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7394 	/* TODO: if (enable) => also deactivate receiving of probe request */
7395 }
7396 
7397 /* Write ssid into shared memory */
7398 static void
7399 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7400 {
7401 	u8 *ssidptr = cfg->SSID;
7402 	u16 base = M_SSID;
7403 	u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7404 
7405 	/* padding the ssid with zero and copy it into shm */
7406 	memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7407 	memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7408 
7409 	brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7410 	brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7411 }
7412 
7413 static void
7414 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7415 			      struct brcms_bss_cfg *cfg,
7416 			      struct sk_buff *probe_resp,
7417 			      bool suspend)
7418 {
7419 	int len;
7420 
7421 	len = min_t(size_t, probe_resp->len, BCN_TMPL_LEN);
7422 
7423 	if (suspend)
7424 		brcms_c_suspend_mac_and_wait(wlc);
7425 
7426 	/* write the probe response into the template region */
7427 	brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7428 				    (len + 3) & ~3, probe_resp->data);
7429 
7430 	/* write the length of the probe response frame (+PLCP/-FCS) */
7431 	brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7432 
7433 	/* write the SSID and SSID length */
7434 	brcms_c_shm_ssid_upd(wlc, cfg);
7435 
7436 	/*
7437 	 * Write PLCP headers and durations for probe response frames
7438 	 * at all rates. Use the actual frame length covered by the
7439 	 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7440 	 * by subtracting the PLCP len and adding the FCS.
7441 	 */
7442 	brcms_c_mod_prb_rsp_rate_table(wlc,
7443 				      (u16)len + FCS_LEN - D11_PHY_HDR_LEN);
7444 
7445 	if (suspend)
7446 		brcms_c_enable_mac(wlc);
7447 }
7448 
7449 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7450 {
7451 	struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7452 
7453 	/* update AP or IBSS probe responses */
7454 	if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP ||
7455 			     bsscfg->type == BRCMS_TYPE_ADHOC)) {
7456 		if (!wlc->probe_resp)
7457 			return;
7458 		brcms_c_bss_update_probe_resp(wlc, bsscfg, wlc->probe_resp,
7459 					      suspend);
7460 	}
7461 }
7462 
7463 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7464 			   uint *blocks)
7465 {
7466 	if (fifo >= NFIFO)
7467 		return -EINVAL;
7468 
7469 	*blocks = wlc_hw->xmtfifo_sz[fifo];
7470 
7471 	return 0;
7472 }
7473 
7474 void
7475 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7476 		  const u8 *addr)
7477 {
7478 	brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7479 	if (match_reg_offset == RCM_BSSID_OFFSET)
7480 		memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7481 }
7482 
7483 /*
7484  * Flag 'scan in progress' to withhold dynamic phy calibration
7485  */
7486 void brcms_c_scan_start(struct brcms_c_info *wlc)
7487 {
7488 	wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7489 }
7490 
7491 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7492 {
7493 	wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7494 }
7495 
7496 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7497 {
7498 	wlc->pub->associated = state;
7499 }
7500 
7501 /*
7502  * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7503  * AMPDU traffic, packets pending in hardware have to be invalidated so that
7504  * when later on hardware releases them, they can be handled appropriately.
7505  */
7506 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7507 			       struct ieee80211_sta *sta,
7508 			       void (*dma_callback_fn))
7509 {
7510 	struct dma_pub *dmah;
7511 	int i;
7512 	for (i = 0; i < NFIFO; i++) {
7513 		dmah = hw->di[i];
7514 		if (dmah != NULL)
7515 			dma_walk_packets(dmah, dma_callback_fn, sta);
7516 	}
7517 }
7518 
7519 int brcms_c_get_curband(struct brcms_c_info *wlc)
7520 {
7521 	return wlc->band->bandunit;
7522 }
7523 
7524 bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc)
7525 {
7526 	int i;
7527 
7528 	/* Kick DMA to send any pending AMPDU */
7529 	for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7530 		if (wlc->hw->di[i])
7531 			dma_kick_tx(wlc->hw->di[i]);
7532 
7533 	return !brcms_txpktpendtot(wlc);
7534 }
7535 
7536 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7537 {
7538 	wlc->bcn_li_bcn = interval;
7539 	if (wlc->pub->up)
7540 		brcms_c_bcn_li_upd(wlc);
7541 }
7542 
7543 u64 brcms_c_tsf_get(struct brcms_c_info *wlc)
7544 {
7545 	u32 tsf_h, tsf_l;
7546 	u64 tsf;
7547 
7548 	brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7549 
7550 	tsf = tsf_h;
7551 	tsf <<= 32;
7552 	tsf |= tsf_l;
7553 
7554 	return tsf;
7555 }
7556 
7557 void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf)
7558 {
7559 	u32 tsf_h, tsf_l;
7560 
7561 	brcms_c_time_lock(wlc);
7562 
7563 	tsf_l = tsf;
7564 	tsf_h = (tsf >> 32);
7565 
7566 	/* read the tsf timer low, then high to get an atomic read */
7567 	bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerlow), tsf_l);
7568 	bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerhigh), tsf_h);
7569 
7570 	brcms_c_time_unlock(wlc);
7571 }
7572 
7573 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7574 {
7575 	uint qdbm;
7576 
7577 	/* Remove override bit and clip to max qdbm value */
7578 	qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7579 	return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7580 }
7581 
7582 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7583 {
7584 	uint qdbm;
7585 	bool override;
7586 
7587 	wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7588 
7589 	/* Return qdbm units */
7590 	return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7591 }
7592 
7593 /* Process received frames */
7594 /*
7595  * Return true if more frames need to be processed. false otherwise.
7596  * Param 'bound' indicates max. # frames to process before break out.
7597  */
7598 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7599 {
7600 	struct d11rxhdr *rxh;
7601 	struct ieee80211_hdr *h;
7602 	uint len;
7603 	bool is_amsdu;
7604 
7605 	/* frame starts with rxhdr */
7606 	rxh = (struct d11rxhdr *) (p->data);
7607 
7608 	/* strip off rxhdr */
7609 	skb_pull(p, BRCMS_HWRXOFF);
7610 
7611 	/* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7612 	if (rxh->RxStatus1 & RXS_PBPRES) {
7613 		if (p->len < 2) {
7614 			brcms_err(wlc->hw->d11core,
7615 				  "wl%d: recv: rcvd runt of len %d\n",
7616 				  wlc->pub->unit, p->len);
7617 			goto toss;
7618 		}
7619 		skb_pull(p, 2);
7620 	}
7621 
7622 	h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7623 	len = p->len;
7624 
7625 	if (rxh->RxStatus1 & RXS_FCSERR) {
7626 		if (!(wlc->filter_flags & FIF_FCSFAIL))
7627 			goto toss;
7628 	}
7629 
7630 	/* check received pkt has at least frame control field */
7631 	if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7632 		goto toss;
7633 
7634 	/* not supporting A-MSDU */
7635 	is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7636 	if (is_amsdu)
7637 		goto toss;
7638 
7639 	brcms_c_recvctl(wlc, rxh, p);
7640 	return;
7641 
7642  toss:
7643 	brcmu_pkt_buf_free_skb(p);
7644 }
7645 
7646 /* Process received frames */
7647 /*
7648  * Return true if more frames need to be processed. false otherwise.
7649  * Param 'bound' indicates max. # frames to process before break out.
7650  */
7651 static bool
7652 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7653 {
7654 	struct sk_buff *p;
7655 	struct sk_buff *next = NULL;
7656 	struct sk_buff_head recv_frames;
7657 
7658 	uint n = 0;
7659 	uint bound_limit = bound ? RXBND : -1;
7660 	bool morepending = false;
7661 
7662 	skb_queue_head_init(&recv_frames);
7663 
7664 	/* gather received frames */
7665 	do {
7666 		/* !give others some time to run! */
7667 		if (n >= bound_limit)
7668 			break;
7669 
7670 		morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
7671 		n++;
7672 	} while (morepending);
7673 
7674 	/* post more rbufs */
7675 	dma_rxfill(wlc_hw->di[fifo]);
7676 
7677 	/* process each frame */
7678 	skb_queue_walk_safe(&recv_frames, p, next) {
7679 		struct d11rxhdr_le *rxh_le;
7680 		struct d11rxhdr *rxh;
7681 
7682 		skb_unlink(p, &recv_frames);
7683 		rxh_le = (struct d11rxhdr_le *)p->data;
7684 		rxh = (struct d11rxhdr *)p->data;
7685 
7686 		/* fixup rx header endianness */
7687 		rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7688 		rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7689 		rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7690 		rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7691 		rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7692 		rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7693 		rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7694 		rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7695 		rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7696 		rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7697 		rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7698 
7699 		brcms_c_recv(wlc_hw->wlc, p);
7700 	}
7701 
7702 	return morepending;
7703 }
7704 
7705 /* second-level interrupt processing
7706  *   Return true if another dpc needs to be re-scheduled. false otherwise.
7707  *   Param 'bounded' indicates if applicable loops should be bounded.
7708  */
7709 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7710 {
7711 	u32 macintstatus;
7712 	struct brcms_hardware *wlc_hw = wlc->hw;
7713 	struct bcma_device *core = wlc_hw->d11core;
7714 
7715 	if (brcms_deviceremoved(wlc)) {
7716 		brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7717 			  __func__);
7718 		brcms_down(wlc->wl);
7719 		return false;
7720 	}
7721 
7722 	/* grab and clear the saved software intstatus bits */
7723 	macintstatus = wlc->macintstatus;
7724 	wlc->macintstatus = 0;
7725 
7726 	brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
7727 		      wlc_hw->unit, macintstatus);
7728 
7729 	WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7730 
7731 	/* tx status */
7732 	if (macintstatus & MI_TFS) {
7733 		bool fatal;
7734 		if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7735 			wlc->macintstatus |= MI_TFS;
7736 		if (fatal) {
7737 			brcms_err(core, "MI_TFS: fatal\n");
7738 			goto fatal;
7739 		}
7740 	}
7741 
7742 	if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7743 		brcms_c_tbtt(wlc);
7744 
7745 	/* ATIM window end */
7746 	if (macintstatus & MI_ATIMWINEND) {
7747 		brcms_dbg_info(core, "end of ATIM window\n");
7748 		bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7749 		wlc->qvalid = 0;
7750 	}
7751 
7752 	/*
7753 	 * received data or control frame, MI_DMAINT is
7754 	 * indication of RX_FIFO interrupt
7755 	 */
7756 	if (macintstatus & MI_DMAINT)
7757 		if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7758 			wlc->macintstatus |= MI_DMAINT;
7759 
7760 	/* noise sample collected */
7761 	if (macintstatus & MI_BG_NOISE)
7762 		wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7763 
7764 	if (macintstatus & MI_GP0) {
7765 		brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
7766 			  "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7767 
7768 		printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7769 			    __func__, ai_get_chip_id(wlc_hw->sih),
7770 			    ai_get_chiprev(wlc_hw->sih));
7771 		brcms_fatal_error(wlc_hw->wlc->wl);
7772 	}
7773 
7774 	/* gptimer timeout */
7775 	if (macintstatus & MI_TO)
7776 		bcma_write32(core, D11REGOFFS(gptimer), 0);
7777 
7778 	if (macintstatus & MI_RFDISABLE) {
7779 		brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
7780 			       " RF Disable Input\n", wlc_hw->unit);
7781 		brcms_rfkill_set_hw_state(wlc->wl);
7782 	}
7783 
7784 	/* BCN template is available */
7785 	if (macintstatus & MI_BCNTPL)
7786 		brcms_c_update_beacon(wlc);
7787 
7788 	/* it isn't done and needs to be resched if macintstatus is non-zero */
7789 	return wlc->macintstatus != 0;
7790 
7791  fatal:
7792 	brcms_fatal_error(wlc_hw->wlc->wl);
7793 	return wlc->macintstatus != 0;
7794 }
7795 
7796 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
7797 {
7798 	struct bcma_device *core = wlc->hw->d11core;
7799 	struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.chandef.chan;
7800 	u16 chanspec;
7801 
7802 	brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
7803 
7804 	chanspec = ch20mhz_chspec(ch->hw_value);
7805 
7806 	brcms_b_init(wlc->hw, chanspec);
7807 
7808 	/* update beacon listen interval */
7809 	brcms_c_bcn_li_upd(wlc);
7810 
7811 	/* write ethernet address to core */
7812 	brcms_c_set_mac(wlc->bsscfg);
7813 	brcms_c_set_bssid(wlc->bsscfg);
7814 
7815 	/* Update tsf_cfprep if associated and up */
7816 	if (wlc->pub->associated && wlc->pub->up) {
7817 		u32 bi;
7818 
7819 		/* get beacon period and convert to uS */
7820 		bi = wlc->bsscfg->current_bss->beacon_period << 10;
7821 		/*
7822 		 * update since init path would reset
7823 		 * to default value
7824 		 */
7825 		bcma_write32(core, D11REGOFFS(tsf_cfprep),
7826 			     bi << CFPREP_CBI_SHIFT);
7827 
7828 		/* Update maccontrol PM related bits */
7829 		brcms_c_set_ps_ctrl(wlc);
7830 	}
7831 
7832 	brcms_c_bandinit_ordered(wlc, chanspec);
7833 
7834 	/* init probe response timeout */
7835 	brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7836 
7837 	/* init max burst txop (framebursting) */
7838 	brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
7839 		      (wlc->
7840 		       _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
7841 
7842 	/* initialize maximum allowed duty cycle */
7843 	brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
7844 	brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
7845 
7846 	/*
7847 	 * Update some shared memory locations related to
7848 	 * max AMPDU size allowed to received
7849 	 */
7850 	brcms_c_ampdu_shm_upd(wlc->ampdu);
7851 
7852 	/* band-specific inits */
7853 	brcms_c_bsinit(wlc);
7854 
7855 	/* Enable EDCF mode (while the MAC is suspended) */
7856 	bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
7857 	brcms_c_edcf_setparams(wlc, false);
7858 
7859 	/* read the ucode version if we have not yet done so */
7860 	if (wlc->ucode_rev == 0) {
7861 		u16 rev;
7862 		u16 patch;
7863 
7864 		rev = brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR);
7865 		patch = brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
7866 		wlc->ucode_rev = (rev << NBITS(u16)) | patch;
7867 		snprintf(wlc->wiphy->fw_version,
7868 			 sizeof(wlc->wiphy->fw_version), "%u.%u", rev, patch);
7869 	}
7870 
7871 	/* ..now really unleash hell (allow the MAC out of suspend) */
7872 	brcms_c_enable_mac(wlc);
7873 
7874 	/* suspend the tx fifos and mute the phy for preism cac time */
7875 	if (mute_tx)
7876 		brcms_b_mute(wlc->hw, true);
7877 
7878 	/* enable the RF Disable Delay timer */
7879 	bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
7880 
7881 	/*
7882 	 * Initialize WME parameters; if they haven't been set by some other
7883 	 * mechanism (IOVar, etc) then read them from the hardware.
7884 	 */
7885 	if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
7886 		/* Uninitialized; read from HW */
7887 		int ac;
7888 
7889 		for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
7890 			wlc->wme_retries[ac] =
7891 			    brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
7892 	}
7893 }
7894 
7895 /*
7896  * The common driver entry routine. Error codes should be unique
7897  */
7898 struct brcms_c_info *
7899 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
7900 	       bool piomode, uint *perr)
7901 {
7902 	struct brcms_c_info *wlc;
7903 	uint err = 0;
7904 	uint i, j;
7905 	struct brcms_pub *pub;
7906 
7907 	/* allocate struct brcms_c_info state and its substructures */
7908 	wlc = brcms_c_attach_malloc(unit, &err, 0);
7909 	if (wlc == NULL)
7910 		goto fail;
7911 	wlc->wiphy = wl->wiphy;
7912 	pub = wlc->pub;
7913 
7914 #if defined(DEBUG)
7915 	wlc_info_dbg = wlc;
7916 #endif
7917 
7918 	wlc->band = wlc->bandstate[0];
7919 	wlc->core = wlc->corestate;
7920 	wlc->wl = wl;
7921 	pub->unit = unit;
7922 	pub->_piomode = piomode;
7923 	wlc->bandinit_pending = false;
7924 	wlc->beacon_template_virgin = true;
7925 
7926 	/* populate struct brcms_c_info with default values  */
7927 	brcms_c_info_init(wlc, unit);
7928 
7929 	/* update sta/ap related parameters */
7930 	brcms_c_ap_upd(wlc);
7931 
7932 	/*
7933 	 * low level attach steps(all hw accesses go
7934 	 * inside, no more in rest of the attach)
7935 	 */
7936 	err = brcms_b_attach(wlc, core, unit, piomode);
7937 	if (err)
7938 		goto fail;
7939 
7940 	brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
7941 
7942 	pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
7943 
7944 	/* disable allowed duty cycle */
7945 	wlc->tx_duty_cycle_ofdm = 0;
7946 	wlc->tx_duty_cycle_cck = 0;
7947 
7948 	brcms_c_stf_phy_chain_calc(wlc);
7949 
7950 	/* txchain 1: txant 0, txchain 2: txant 1 */
7951 	if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
7952 		wlc->stf->txant = wlc->stf->hw_txchain - 1;
7953 
7954 	/* push to BMAC driver */
7955 	wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
7956 			       wlc->stf->hw_rxchain);
7957 
7958 	/* pull up some info resulting from the low attach */
7959 	for (i = 0; i < NFIFO; i++)
7960 		wlc->core->txavail[i] = wlc->hw->txavail[i];
7961 
7962 	memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7963 	memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7964 
7965 	for (j = 0; j < wlc->pub->_nbands; j++) {
7966 		wlc->band = wlc->bandstate[j];
7967 
7968 		if (!brcms_c_attach_stf_ant_init(wlc)) {
7969 			err = 24;
7970 			goto fail;
7971 		}
7972 
7973 		/* default contention windows size limits */
7974 		wlc->band->CWmin = APHY_CWMIN;
7975 		wlc->band->CWmax = PHY_CWMAX;
7976 
7977 		/* init gmode value */
7978 		if (wlc->band->bandtype == BRCM_BAND_2G) {
7979 			wlc->band->gmode = GMODE_AUTO;
7980 			brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
7981 					   wlc->band->gmode);
7982 		}
7983 
7984 		/* init _n_enab supported mode */
7985 		if (BRCMS_PHY_11N_CAP(wlc->band)) {
7986 			pub->_n_enab = SUPPORT_11N;
7987 			brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
7988 						   ((pub->_n_enab ==
7989 						     SUPPORT_11N) ? WL_11N_2x2 :
7990 						    WL_11N_3x3));
7991 		}
7992 
7993 		/* init per-band default rateset, depend on band->gmode */
7994 		brcms_default_rateset(wlc, &wlc->band->defrateset);
7995 
7996 		/* fill in hw_rateset */
7997 		brcms_c_rateset_filter(&wlc->band->defrateset,
7998 				   &wlc->band->hw_rateset, false,
7999 				   BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
8000 				   (bool) (wlc->pub->_n_enab & SUPPORT_11N));
8001 	}
8002 
8003 	/*
8004 	 * update antenna config due to
8005 	 * wlc->stf->txant/txchain/ant_rx_ovr change
8006 	 */
8007 	brcms_c_stf_phy_txant_upd(wlc);
8008 
8009 	/* attach each modules */
8010 	err = brcms_c_attach_module(wlc);
8011 	if (err != 0)
8012 		goto fail;
8013 
8014 	if (!brcms_c_timers_init(wlc, unit)) {
8015 		wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8016 			  __func__);
8017 		err = 32;
8018 		goto fail;
8019 	}
8020 
8021 	/* depend on rateset, gmode */
8022 	wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8023 	if (!wlc->cmi) {
8024 		wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8025 			  "\n", unit, __func__);
8026 		err = 33;
8027 		goto fail;
8028 	}
8029 
8030 	/* init default when all parameters are ready, i.e. ->rateset */
8031 	brcms_c_bss_default_init(wlc);
8032 
8033 	/*
8034 	 * Complete the wlc default state initializations..
8035 	 */
8036 
8037 	wlc->bsscfg->wlc = wlc;
8038 
8039 	wlc->mimoft = FT_HT;
8040 	wlc->mimo_40txbw = AUTO;
8041 	wlc->ofdm_40txbw = AUTO;
8042 	wlc->cck_40txbw = AUTO;
8043 	brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8044 
8045 	/* Set default values of SGI */
8046 	if (BRCMS_SGI_CAP_PHY(wlc)) {
8047 		brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8048 					       BRCMS_N_SGI_40));
8049 	} else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8050 		brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8051 					       BRCMS_N_SGI_40));
8052 	} else {
8053 		brcms_c_ht_update_sgi_rx(wlc, 0);
8054 	}
8055 
8056 	brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8057 
8058 	if (perr)
8059 		*perr = 0;
8060 
8061 	return wlc;
8062 
8063  fail:
8064 	wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8065 		  unit, __func__, err);
8066 	if (wlc)
8067 		brcms_c_detach(wlc);
8068 
8069 	if (perr)
8070 		*perr = err;
8071 	return NULL;
8072 }
8073