1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de> 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 12 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 14 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 15 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/pci_ids.h> 21 #include <linux/if_ether.h> 22 #include <net/cfg80211.h> 23 #include <net/mac80211.h> 24 #include <brcm_hw_ids.h> 25 #include <aiutils.h> 26 #include <chipcommon.h> 27 #include "rate.h" 28 #include "scb.h" 29 #include "phy/phy_hal.h" 30 #include "channel.h" 31 #include "antsel.h" 32 #include "stf.h" 33 #include "ampdu.h" 34 #include "mac80211_if.h" 35 #include "ucode_loader.h" 36 #include "main.h" 37 #include "soc.h" 38 #include "dma.h" 39 #include "debug.h" 40 #include "brcms_trace_events.h" 41 42 /* watchdog timer, in unit of ms */ 43 #define TIMER_INTERVAL_WATCHDOG 1000 44 /* radio monitor timer, in unit of ms */ 45 #define TIMER_INTERVAL_RADIOCHK 800 46 47 /* beacon interval, in unit of 1024TU */ 48 #define BEACON_INTERVAL_DEFAULT 100 49 50 /* n-mode support capability */ 51 /* 2x2 includes both 1x1 & 2x2 devices 52 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and 53 * control it independently 54 */ 55 #define WL_11N_2x2 1 56 #define WL_11N_3x3 3 57 #define WL_11N_4x4 4 58 59 #define EDCF_ACI_MASK 0x60 60 #define EDCF_ACI_SHIFT 5 61 #define EDCF_ECWMIN_MASK 0x0f 62 #define EDCF_ECWMAX_SHIFT 4 63 #define EDCF_AIFSN_MASK 0x0f 64 #define EDCF_AIFSN_MAX 15 65 #define EDCF_ECWMAX_MASK 0xf0 66 67 #define EDCF_AC_BE_TXOP_STA 0x0000 68 #define EDCF_AC_BK_TXOP_STA 0x0000 69 #define EDCF_AC_VO_ACI_STA 0x62 70 #define EDCF_AC_VO_ECW_STA 0x32 71 #define EDCF_AC_VI_ACI_STA 0x42 72 #define EDCF_AC_VI_ECW_STA 0x43 73 #define EDCF_AC_BK_ECW_STA 0xA4 74 #define EDCF_AC_VI_TXOP_STA 0x005e 75 #define EDCF_AC_VO_TXOP_STA 0x002f 76 #define EDCF_AC_BE_ACI_STA 0x03 77 #define EDCF_AC_BE_ECW_STA 0xA4 78 #define EDCF_AC_BK_ACI_STA 0x27 79 #define EDCF_AC_VO_TXOP_AP 0x002f 80 81 #define EDCF_TXOP2USEC(txop) ((txop) << 5) 82 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1) 83 84 #define APHY_SYMBOL_TIME 4 85 #define APHY_PREAMBLE_TIME 16 86 #define APHY_SIGNAL_TIME 4 87 #define APHY_SIFS_TIME 16 88 #define APHY_SERVICE_NBITS 16 89 #define APHY_TAIL_NBITS 6 90 #define BPHY_SIFS_TIME 10 91 #define BPHY_PLCP_SHORT_TIME 96 92 93 #define PREN_PREAMBLE 24 94 #define PREN_MM_EXT 12 95 #define PREN_PREAMBLE_EXT 4 96 97 #define DOT11_MAC_HDR_LEN 24 98 #define DOT11_ACK_LEN 10 99 #define DOT11_BA_LEN 4 100 #define DOT11_OFDM_SIGNAL_EXTENSION 6 101 #define DOT11_MIN_FRAG_LEN 256 102 #define DOT11_RTS_LEN 16 103 #define DOT11_CTS_LEN 10 104 #define DOT11_BA_BITMAP_LEN 128 105 #define DOT11_MAXNUMFRAGS 16 106 #define DOT11_MAX_FRAG_LEN 2346 107 108 #define BPHY_PLCP_TIME 192 109 #define RIFS_11N_TIME 2 110 111 /* length of the BCN template area */ 112 #define BCN_TMPL_LEN 512 113 114 /* brcms_bss_info flag bit values */ 115 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */ 116 117 /* chip rx buffer offset */ 118 #define BRCMS_HWRXOFF 38 119 120 /* rfdisable delay timer 500 ms, runs of ALP clock */ 121 #define RFDISABLE_DEFAULT 10000000 122 123 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */ 124 125 /* synthpu_dly times in us */ 126 #define SYNTHPU_DLY_APHY_US 3700 127 #define SYNTHPU_DLY_BPHY_US 1050 128 #define SYNTHPU_DLY_NPHY_US 2048 129 #define SYNTHPU_DLY_LPPHY_US 300 130 131 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */ 132 133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */ 134 #define EDCF_SHORT_S 0 135 #define EDCF_SFB_S 4 136 #define EDCF_LONG_S 8 137 #define EDCF_LFB_S 12 138 #define EDCF_SHORT_M BITFIELD_MASK(4) 139 #define EDCF_SFB_M BITFIELD_MASK(4) 140 #define EDCF_LONG_M BITFIELD_MASK(4) 141 #define EDCF_LFB_M BITFIELD_MASK(4) 142 143 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */ 144 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */ 145 #define RETRY_LONG_DEF 4 /* Default Long retry count */ 146 #define RETRY_SHORT_FB 3 /* Short count for fb rate */ 147 #define RETRY_LONG_FB 2 /* Long count for fb rate */ 148 149 #define APHY_CWMIN 15 150 #define PHY_CWMAX 1023 151 152 #define EDCF_AIFSN_MIN 1 153 154 #define FRAGNUM_MASK 0xF 155 156 #define APHY_SLOT_TIME 9 157 #define BPHY_SLOT_TIME 20 158 159 #define WL_SPURAVOID_OFF 0 160 #define WL_SPURAVOID_ON1 1 161 #define WL_SPURAVOID_ON2 2 162 163 /* invalid core flags, use the saved coreflags */ 164 #define BRCMS_USE_COREFLAGS 0xffffffff 165 166 /* values for PLCPHdr_override */ 167 #define BRCMS_PLCP_AUTO -1 168 #define BRCMS_PLCP_SHORT 0 169 #define BRCMS_PLCP_LONG 1 170 171 /* values for g_protection_override and n_protection_override */ 172 #define BRCMS_PROTECTION_AUTO -1 173 #define BRCMS_PROTECTION_OFF 0 174 #define BRCMS_PROTECTION_ON 1 175 #define BRCMS_PROTECTION_MMHDR_ONLY 2 176 #define BRCMS_PROTECTION_CTS_ONLY 3 177 178 /* values for g_protection_control and n_protection_control */ 179 #define BRCMS_PROTECTION_CTL_OFF 0 180 #define BRCMS_PROTECTION_CTL_LOCAL 1 181 #define BRCMS_PROTECTION_CTL_OVERLAP 2 182 183 /* values for n_protection */ 184 #define BRCMS_N_PROTECTION_OFF 0 185 #define BRCMS_N_PROTECTION_OPTIONAL 1 186 #define BRCMS_N_PROTECTION_20IN40 2 187 #define BRCMS_N_PROTECTION_MIXEDMODE 3 188 189 /* values for band specific 40MHz capabilities */ 190 #define BRCMS_N_BW_20ALL 0 191 #define BRCMS_N_BW_40ALL 1 192 #define BRCMS_N_BW_20IN2G_40IN5G 2 193 194 /* bitflags for SGI support (sgi_rx iovar) */ 195 #define BRCMS_N_SGI_20 0x01 196 #define BRCMS_N_SGI_40 0x02 197 198 /* defines used by the nrate iovar */ 199 /* MSC in use,indicates b0-6 holds an mcs */ 200 #define NRATE_MCS_INUSE 0x00000080 201 /* rate/mcs value */ 202 #define NRATE_RATE_MASK 0x0000007f 203 /* stf mode mask: siso, cdd, stbc, sdm */ 204 #define NRATE_STF_MASK 0x0000ff00 205 /* stf mode shift */ 206 #define NRATE_STF_SHIFT 8 207 /* bit indicate to override mcs only */ 208 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000 209 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */ 210 #define NRATE_SGI_SHIFT 23 /* sgi mode */ 211 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */ 212 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */ 213 214 #define NRATE_STF_SISO 0 /* stf mode SISO */ 215 #define NRATE_STF_CDD 1 /* stf mode CDD */ 216 #define NRATE_STF_STBC 2 /* stf mode STBC */ 217 #define NRATE_STF_SDM 3 /* stf mode SDM */ 218 219 #define MAX_DMA_SEGS 4 220 221 /* # of entries in Tx FIFO */ 222 #define NTXD 64 223 /* Max # of entries in Rx FIFO based on 4kb page size */ 224 #define NRXD 256 225 226 /* Amount of headroom to leave in Tx FIFO */ 227 #define TX_HEADROOM 4 228 229 /* try to keep this # rbufs posted to the chip */ 230 #define NRXBUFPOST 32 231 232 /* max # frames to process in brcms_c_recv() */ 233 #define RXBND 8 234 /* max # tx status to process in wlc_txstatus() */ 235 #define TXSBND 8 236 237 /* 238 * The following table lists the buffer memory allocated to xmt fifos in HW. 239 * the size is in units of 256bytes(one block), total size is HW dependent 240 * ucode has default fifo partition, sw can overwrite if necessary 241 * 242 * This is documented in twiki under the topic UcodeTxFifo. Please ensure 243 * the twiki is updated before making changes. 244 */ 245 246 /* Starting corerev for the fifo size table */ 247 #define XMTFIFOTBL_STARTREV 17 248 249 struct d11init { 250 __le16 addr; 251 __le16 size; 252 __le32 value; 253 }; 254 255 struct edcf_acparam { 256 u8 ACI; 257 u8 ECW; 258 u16 TXOP; 259 } __packed; 260 261 /* debug/trace */ 262 uint brcm_msg_level; 263 264 /* TX FIFO number to WME/802.1E Access Category */ 265 static const u8 wme_fifo2ac[] = { 266 IEEE80211_AC_BK, 267 IEEE80211_AC_BE, 268 IEEE80211_AC_VI, 269 IEEE80211_AC_VO, 270 IEEE80211_AC_BE, 271 IEEE80211_AC_BE 272 }; 273 274 /* ieee80211 Access Category to TX FIFO number */ 275 static const u8 wme_ac2fifo[] = { 276 TX_AC_VO_FIFO, 277 TX_AC_VI_FIFO, 278 TX_AC_BE_FIFO, 279 TX_AC_BK_FIFO 280 }; 281 282 static const u16 xmtfifo_sz[][NFIFO] = { 283 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */ 284 {20, 192, 192, 21, 17, 5}, 285 /* corerev 18: */ 286 {0, 0, 0, 0, 0, 0}, 287 /* corerev 19: */ 288 {0, 0, 0, 0, 0, 0}, 289 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */ 290 {20, 192, 192, 21, 17, 5}, 291 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */ 292 {9, 58, 22, 14, 14, 5}, 293 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */ 294 {20, 192, 192, 21, 17, 5}, 295 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */ 296 {20, 192, 192, 21, 17, 5}, 297 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */ 298 {9, 58, 22, 14, 14, 5}, 299 /* corerev 25: */ 300 {0, 0, 0, 0, 0, 0}, 301 /* corerev 26: */ 302 {0, 0, 0, 0, 0, 0}, 303 /* corerev 27: */ 304 {0, 0, 0, 0, 0, 0}, 305 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */ 306 {9, 58, 22, 14, 14, 5}, 307 }; 308 309 #ifdef DEBUG 310 static const char * const fifo_names[] = { 311 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" }; 312 #else 313 static const char fifo_names[6][1]; 314 #endif 315 316 #ifdef DEBUG 317 /* pointer to most recently allocated wl/wlc */ 318 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL); 319 #endif 320 321 /* Mapping of ieee80211 AC numbers to tx fifos */ 322 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = { 323 [IEEE80211_AC_VO] = TX_AC_VO_FIFO, 324 [IEEE80211_AC_VI] = TX_AC_VI_FIFO, 325 [IEEE80211_AC_BE] = TX_AC_BE_FIFO, 326 [IEEE80211_AC_BK] = TX_AC_BK_FIFO, 327 }; 328 329 /* Mapping of tx fifos to ieee80211 AC numbers */ 330 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = { 331 [TX_AC_BK_FIFO] = IEEE80211_AC_BK, 332 [TX_AC_BE_FIFO] = IEEE80211_AC_BE, 333 [TX_AC_VI_FIFO] = IEEE80211_AC_VI, 334 [TX_AC_VO_FIFO] = IEEE80211_AC_VO, 335 }; 336 337 static u8 brcms_ac_to_fifo(u8 ac) 338 { 339 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping)) 340 return TX_AC_BE_FIFO; 341 return ac_to_fifo_mapping[ac]; 342 } 343 344 static u8 brcms_fifo_to_ac(u8 fifo) 345 { 346 if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping)) 347 return IEEE80211_AC_BE; 348 return fifo_to_ac_mapping[fifo]; 349 } 350 351 /* Find basic rate for a given rate */ 352 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec) 353 { 354 if (is_mcs_rate(rspec)) 355 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK] 356 .leg_ofdm]; 357 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK]; 358 } 359 360 static u16 frametype(u32 rspec, u8 mimoframe) 361 { 362 if (is_mcs_rate(rspec)) 363 return mimoframe; 364 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM; 365 } 366 367 /* currently the best mechanism for determining SIFS is the band in use */ 368 static u16 get_sifs(struct brcms_band *band) 369 { 370 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME : 371 BPHY_SIFS_TIME; 372 } 373 374 /* 375 * Detect Card removed. 376 * Even checking an sbconfig register read will not false trigger when the core 377 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will 378 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible 379 * reg with fixed 0/1 pattern (some platforms return all 0). 380 * If clocks are present, call the sb routine which will figure out if the 381 * device is removed. 382 */ 383 static bool brcms_deviceremoved(struct brcms_c_info *wlc) 384 { 385 u32 macctrl; 386 387 if (!wlc->hw->clk) 388 return ai_deviceremoved(wlc->hw->sih); 389 macctrl = bcma_read32(wlc->hw->d11core, 390 D11REGOFFS(maccontrol)); 391 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN; 392 } 393 394 /* sum the individual fifo tx pending packet counts */ 395 static int brcms_txpktpendtot(struct brcms_c_info *wlc) 396 { 397 int i; 398 int pending = 0; 399 400 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++) 401 if (wlc->hw->di[i]) 402 pending += dma_txpending(wlc->hw->di[i]); 403 return pending; 404 } 405 406 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc) 407 { 408 return wlc->pub->_nbands > 1 && !wlc->bandlocked; 409 } 410 411 static int brcms_chspec_bw(u16 chanspec) 412 { 413 if (CHSPEC_IS40(chanspec)) 414 return BRCMS_40_MHZ; 415 if (CHSPEC_IS20(chanspec)) 416 return BRCMS_20_MHZ; 417 418 return BRCMS_10_MHZ; 419 } 420 421 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg) 422 { 423 if (cfg == NULL) 424 return; 425 426 kfree(cfg->current_bss); 427 kfree(cfg); 428 } 429 430 static void brcms_c_detach_mfree(struct brcms_c_info *wlc) 431 { 432 if (wlc == NULL) 433 return; 434 435 brcms_c_bsscfg_mfree(wlc->bsscfg); 436 kfree(wlc->pub); 437 kfree(wlc->modulecb); 438 kfree(wlc->default_bss); 439 kfree(wlc->protection); 440 kfree(wlc->stf); 441 kfree(wlc->bandstate[0]); 442 if (wlc->corestate) 443 kfree(wlc->corestate->macstat_snapshot); 444 kfree(wlc->corestate); 445 if (wlc->hw) 446 kfree(wlc->hw->bandstate[0]); 447 kfree(wlc->hw); 448 if (wlc->beacon) 449 dev_kfree_skb_any(wlc->beacon); 450 if (wlc->probe_resp) 451 dev_kfree_skb_any(wlc->probe_resp); 452 453 kfree(wlc); 454 } 455 456 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit) 457 { 458 struct brcms_bss_cfg *cfg; 459 460 cfg = kzalloc_obj(*cfg, GFP_ATOMIC); 461 if (cfg == NULL) 462 goto fail; 463 464 cfg->current_bss = kzalloc_obj(*cfg->current_bss, GFP_ATOMIC); 465 if (cfg->current_bss == NULL) 466 goto fail; 467 468 return cfg; 469 470 fail: 471 brcms_c_bsscfg_mfree(cfg); 472 return NULL; 473 } 474 475 static struct brcms_c_info * 476 brcms_c_attach_malloc(uint unit, uint *err, uint devid) 477 { 478 struct brcms_c_info *wlc; 479 480 wlc = kzalloc_obj(*wlc, GFP_ATOMIC); 481 if (wlc == NULL) { 482 *err = 1002; 483 goto fail; 484 } 485 486 /* allocate struct brcms_c_pub state structure */ 487 wlc->pub = kzalloc_obj(*wlc->pub, GFP_ATOMIC); 488 if (wlc->pub == NULL) { 489 *err = 1003; 490 goto fail; 491 } 492 wlc->pub->wlc = wlc; 493 494 /* allocate struct brcms_hardware state structure */ 495 496 wlc->hw = kzalloc_obj(*wlc->hw, GFP_ATOMIC); 497 if (wlc->hw == NULL) { 498 *err = 1005; 499 goto fail; 500 } 501 wlc->hw->wlc = wlc; 502 503 wlc->hw->bandstate[0] = 504 kzalloc_objs(struct brcms_hw_band, MAXBANDS, GFP_ATOMIC); 505 if (wlc->hw->bandstate[0] == NULL) { 506 *err = 1006; 507 goto fail; 508 } else { 509 int i; 510 511 for (i = 1; i < MAXBANDS; i++) 512 wlc->hw->bandstate[i] = (struct brcms_hw_band *) 513 ((unsigned long)wlc->hw->bandstate[0] + 514 (sizeof(struct brcms_hw_band) * i)); 515 } 516 517 wlc->modulecb = 518 kzalloc_objs(struct modulecb, BRCMS_MAXMODULES, GFP_ATOMIC); 519 if (wlc->modulecb == NULL) { 520 *err = 1009; 521 goto fail; 522 } 523 524 wlc->default_bss = kzalloc_obj(*wlc->default_bss, GFP_ATOMIC); 525 if (wlc->default_bss == NULL) { 526 *err = 1010; 527 goto fail; 528 } 529 530 wlc->bsscfg = brcms_c_bsscfg_malloc(unit); 531 if (wlc->bsscfg == NULL) { 532 *err = 1011; 533 goto fail; 534 } 535 536 wlc->protection = kzalloc_obj(*wlc->protection, GFP_ATOMIC); 537 if (wlc->protection == NULL) { 538 *err = 1016; 539 goto fail; 540 } 541 542 wlc->stf = kzalloc_obj(*wlc->stf, GFP_ATOMIC); 543 if (wlc->stf == NULL) { 544 *err = 1017; 545 goto fail; 546 } 547 548 wlc->bandstate[0] = 549 kzalloc_objs(*wlc->bandstate[0], MAXBANDS, GFP_ATOMIC); 550 if (wlc->bandstate[0] == NULL) { 551 *err = 1025; 552 goto fail; 553 } else { 554 int i; 555 556 for (i = 1; i < MAXBANDS; i++) 557 wlc->bandstate[i] = (struct brcms_band *) 558 ((unsigned long)wlc->bandstate[0] 559 + (sizeof(struct brcms_band)*i)); 560 } 561 562 wlc->corestate = kzalloc_obj(*wlc->corestate, GFP_ATOMIC); 563 if (wlc->corestate == NULL) { 564 *err = 1026; 565 goto fail; 566 } 567 568 wlc->corestate->macstat_snapshot = kzalloc_obj(*wlc->corestate->macstat_snapshot, 569 GFP_ATOMIC); 570 if (wlc->corestate->macstat_snapshot == NULL) { 571 *err = 1027; 572 goto fail; 573 } 574 575 return wlc; 576 577 fail: 578 brcms_c_detach_mfree(wlc); 579 return NULL; 580 } 581 582 /* 583 * Update the slot timing for standard 11b/g (20us slots) 584 * or shortslot 11g (9us slots) 585 * The PSM needs to be suspended for this call. 586 */ 587 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw, 588 bool shortslot) 589 { 590 struct bcma_device *core = wlc_hw->d11core; 591 592 if (shortslot) { 593 /* 11g short slot: 11a timing */ 594 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207); 595 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME); 596 } else { 597 /* 11g long slot: 11b timing */ 598 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212); 599 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME); 600 } 601 } 602 603 /* 604 * calculate frame duration of a given rate and length, return 605 * time in usec unit 606 */ 607 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec, 608 u8 preamble_type, uint mac_len) 609 { 610 uint nsyms, dur = 0, Ndps, kNdps; 611 uint rate = rspec2rate(ratespec); 612 613 if (rate == 0) { 614 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n", 615 wlc->pub->unit); 616 rate = BRCM_RATE_1M; 617 } 618 619 if (is_mcs_rate(ratespec)) { 620 uint mcs = ratespec & RSPEC_RATE_MASK; 621 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); 622 623 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); 624 if (preamble_type == BRCMS_MM_PREAMBLE) 625 dur += PREN_MM_EXT; 626 /* 1000Ndbps = kbps * 4 */ 627 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 628 rspec_issgi(ratespec)) * 4; 629 630 if (rspec_stc(ratespec) == 0) 631 nsyms = 632 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 633 APHY_TAIL_NBITS) * 1000, kNdps); 634 else 635 /* STBC needs to have even number of symbols */ 636 nsyms = 637 2 * 638 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 639 APHY_TAIL_NBITS) * 1000, 2 * kNdps); 640 641 dur += APHY_SYMBOL_TIME * nsyms; 642 if (wlc->band->bandtype == BRCM_BAND_2G) 643 dur += DOT11_OFDM_SIGNAL_EXTENSION; 644 } else if (is_ofdm_rate(rate)) { 645 dur = APHY_PREAMBLE_TIME; 646 dur += APHY_SIGNAL_TIME; 647 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ 648 Ndps = rate * 2; 649 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */ 650 nsyms = 651 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS), 652 Ndps); 653 dur += APHY_SYMBOL_TIME * nsyms; 654 if (wlc->band->bandtype == BRCM_BAND_2G) 655 dur += DOT11_OFDM_SIGNAL_EXTENSION; 656 } else { 657 /* 658 * calc # bits * 2 so factor of 2 in rate (1/2 mbps) 659 * will divide out 660 */ 661 mac_len = mac_len * 8 * 2; 662 /* calc ceiling of bits/rate = microseconds of air time */ 663 dur = (mac_len + rate - 1) / rate; 664 if (preamble_type & BRCMS_SHORT_PREAMBLE) 665 dur += BPHY_PLCP_SHORT_TIME; 666 else 667 dur += BPHY_PLCP_TIME; 668 } 669 return dur; 670 } 671 672 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw, 673 const struct d11init *inits) 674 { 675 struct bcma_device *core = wlc_hw->d11core; 676 int i; 677 uint offset; 678 u16 size; 679 u32 value; 680 681 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 682 683 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) { 684 size = le16_to_cpu(inits[i].size); 685 offset = le16_to_cpu(inits[i].addr); 686 value = le32_to_cpu(inits[i].value); 687 if (size == 2) 688 bcma_write16(core, offset, value); 689 else if (size == 4) 690 bcma_write32(core, offset, value); 691 else 692 break; 693 } 694 } 695 696 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs) 697 { 698 u8 idx; 699 static const u16 addr[] = { 700 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, 701 M_HOST_FLAGS5 702 }; 703 704 for (idx = 0; idx < MHFMAX; idx++) 705 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]); 706 } 707 708 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw) 709 { 710 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 711 712 /* init microcode host flags */ 713 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs); 714 715 /* do band-specific ucode IHR, SHM, and SCR inits */ 716 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) { 717 if (BRCMS_ISNPHY(wlc_hw->band)) 718 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16); 719 else 720 brcms_err(wlc_hw->d11core, 721 "%s: wl%d: unsupported phy in corerev %d\n", 722 __func__, wlc_hw->unit, 723 wlc_hw->corerev); 724 } else { 725 if (D11REV_IS(wlc_hw->corerev, 24)) { 726 if (BRCMS_ISLCNPHY(wlc_hw->band)) 727 brcms_c_write_inits(wlc_hw, 728 ucode->d11lcn0bsinitvals24); 729 else 730 brcms_err(wlc_hw->d11core, 731 "%s: wl%d: unsupported phy in core rev %d\n", 732 __func__, wlc_hw->unit, 733 wlc_hw->corerev); 734 } else { 735 brcms_err(wlc_hw->d11core, 736 "%s: wl%d: unsupported corerev %d\n", 737 __func__, wlc_hw->unit, wlc_hw->corerev); 738 } 739 } 740 } 741 742 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v) 743 { 744 struct bcma_device *core = wlc_hw->d11core; 745 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m; 746 747 bcma_awrite32(core, BCMA_IOCTL, ioctl | v); 748 } 749 750 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk) 751 { 752 brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk); 753 754 wlc_hw->phyclk = clk; 755 756 if (OFF == clk) { /* clear gmode bit, put phy into reset */ 757 758 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE), 759 (SICF_PRST | SICF_FGC)); 760 udelay(1); 761 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST); 762 udelay(1); 763 764 } else { /* take phy out of reset */ 765 766 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC); 767 udelay(1); 768 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0); 769 udelay(1); 770 771 } 772 } 773 774 /* low-level band switch utility routine */ 775 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit) 776 { 777 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit, 778 bandunit); 779 780 wlc_hw->band = wlc_hw->bandstate[bandunit]; 781 782 /* 783 * BMAC_NOTE: 784 * until we eliminate need for wlc->band refs in low level code 785 */ 786 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit]; 787 788 /* set gmode core flag */ 789 if (wlc_hw->sbclk && !wlc_hw->noreset) { 790 u32 gmode = 0; 791 792 if (bandunit == 0) 793 gmode = SICF_GMODE; 794 795 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode); 796 } 797 } 798 799 /* switch to new band but leave it inactive */ 800 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit) 801 { 802 struct brcms_hardware *wlc_hw = wlc->hw; 803 u32 macintmask; 804 u32 macctrl; 805 806 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 807 macctrl = bcma_read32(wlc_hw->d11core, 808 D11REGOFFS(maccontrol)); 809 WARN_ON((macctrl & MCTL_EN_MAC) != 0); 810 811 /* disable interrupts */ 812 macintmask = brcms_intrsoff(wlc->wl); 813 814 /* radio off */ 815 wlc_phy_switch_radio(wlc_hw->band->pi, OFF); 816 817 brcms_b_core_phy_clk(wlc_hw, OFF); 818 819 brcms_c_setxband(wlc_hw, bandunit); 820 821 return macintmask; 822 } 823 824 /* process an individual struct tx_status */ 825 static bool 826 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs) 827 { 828 struct sk_buff *p = NULL; 829 uint queue = NFIFO; 830 struct dma_pub *dma = NULL; 831 struct d11txh *txh = NULL; 832 struct scb *scb = NULL; 833 int tx_frame_count; 834 uint supr_status; 835 bool lastframe; 836 struct ieee80211_hdr *h; 837 struct ieee80211_tx_info *tx_info; 838 struct ieee80211_tx_rate *txrate; 839 int i; 840 bool fatal = true; 841 842 trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen, 843 txs->frameid, txs->status, txs->lasttxtime, 844 txs->sequence, txs->phyerr, txs->ackphyrxsh); 845 846 /* discard intermediate indications for ucode with one legitimate case: 847 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, 848 * but the subsequent tx of DATA failed. so it will start rts/cts 849 * from the beginning (resetting the rts transmission count) 850 */ 851 if (!(txs->status & TX_STATUS_AMPDU) 852 && (txs->status & TX_STATUS_INTERMEDIATE)) { 853 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n"); 854 fatal = false; 855 goto out; 856 } 857 858 queue = txs->frameid & TXFID_QUEUE_MASK; 859 if (queue >= NFIFO) { 860 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue); 861 goto out; 862 } 863 864 dma = wlc->hw->di[queue]; 865 866 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED); 867 if (p == NULL) { 868 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n"); 869 goto out; 870 } 871 872 txh = (struct d11txh *) (p->data); 873 874 if (txs->phyerr) 875 brcms_dbg_tx(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n", 876 txs->phyerr, txh->MainRates); 877 878 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) { 879 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n"); 880 goto out; 881 } 882 tx_info = IEEE80211_SKB_CB(p); 883 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN); 884 885 if (tx_info->rate_driver_data[0]) 886 scb = &wlc->pri_scb; 887 888 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 889 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs); 890 fatal = false; 891 goto out; 892 } 893 894 /* 895 * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU 896 * frames; this traces them for the rest. 897 */ 898 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh)); 899 900 supr_status = txs->status & TX_STATUS_SUPR_MASK; 901 if (supr_status == TX_STATUS_SUPR_BADCH) { 902 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes); 903 brcms_dbg_tx(wlc->hw->d11core, 904 "Pkt tx suppressed, dest chan %u, current %d\n", 905 (xfts >> XFTS_CHANNEL_SHIFT) & 0xff, 906 CHSPEC_CHANNEL(wlc->default_bss->chanspec)); 907 } 908 909 tx_frame_count = 910 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT; 911 912 lastframe = !ieee80211_has_morefrags(h->frame_control); 913 914 if (!lastframe) { 915 brcms_err(wlc->hw->d11core, "Not last frame!\n"); 916 } else { 917 /* 918 * Set information to be consumed by Minstrel ht. 919 * 920 * The "fallback limit" is the number of tx attempts a given 921 * MPDU is sent at the "primary" rate. Tx attempts beyond that 922 * limit are sent at the "secondary" rate. 923 * A 'short frame' does not exceed RTS threshold. 924 */ 925 u16 sfbl, /* Short Frame Rate Fallback Limit */ 926 lfbl, /* Long Frame Rate Fallback Limit */ 927 fbl; 928 929 if (queue < IEEE80211_NUM_ACS) { 930 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 931 EDCF_SFB); 932 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 933 EDCF_LFB); 934 } else { 935 sfbl = wlc->SFBL; 936 lfbl = wlc->LFBL; 937 } 938 939 txrate = tx_info->status.rates; 940 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) 941 fbl = lfbl; 942 else 943 fbl = sfbl; 944 945 ieee80211_tx_info_clear_status(tx_info); 946 947 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) { 948 /* 949 * rate selection requested a fallback rate 950 * and we used it 951 */ 952 txrate[0].count = fbl; 953 txrate[1].count = tx_frame_count - fbl; 954 } else { 955 /* 956 * rate selection did not request fallback rate, or 957 * we didn't need it 958 */ 959 txrate[0].count = tx_frame_count; 960 /* 961 * rc80211_minstrel.c:minstrel_tx_status() expects 962 * unused rates to be marked with idx = -1 963 */ 964 txrate[1].idx = -1; 965 txrate[1].count = 0; 966 } 967 968 /* clear the rest of the rates */ 969 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) { 970 txrate[i].idx = -1; 971 txrate[i].count = 0; 972 } 973 974 if (txs->status & TX_STATUS_ACK_RCV) 975 tx_info->flags |= IEEE80211_TX_STAT_ACK; 976 } 977 978 if (lastframe) { 979 /* remove PLCP & Broadcom tx descriptor header */ 980 skb_pull(p, D11_PHY_HDR_LEN); 981 skb_pull(p, D11_TXH_LEN); 982 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p); 983 } else { 984 brcms_err(wlc->hw->d11core, 985 "%s: Not last frame => not calling tx_status\n", 986 __func__); 987 } 988 989 fatal = false; 990 991 out: 992 if (fatal) { 993 if (txh) 994 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, 995 sizeof(*txh)); 996 brcmu_pkt_buf_free_skb(p); 997 } 998 999 if (dma && queue < NFIFO) { 1000 u16 ac_queue = brcms_fifo_to_ac(queue); 1001 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO && 1002 ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue)) 1003 ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue); 1004 dma_kick_tx(dma); 1005 } 1006 1007 return fatal; 1008 } 1009 1010 /* process tx completion events in BMAC 1011 * Return true if more tx status need to be processed. false otherwise. 1012 */ 1013 static bool 1014 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal) 1015 { 1016 struct bcma_device *core; 1017 struct tx_status txstatus, *txs; 1018 u32 s1, s2; 1019 uint n = 0; 1020 /* 1021 * Param 'max_tx_num' indicates max. # tx status to process before 1022 * break out. 1023 */ 1024 uint max_tx_num = bound ? TXSBND : -1; 1025 1026 txs = &txstatus; 1027 core = wlc_hw->d11core; 1028 *fatal = false; 1029 1030 while (n < max_tx_num) { 1031 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus)); 1032 if (s1 == 0xffffffff) { 1033 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 1034 __func__); 1035 *fatal = true; 1036 return false; 1037 } 1038 /* only process when valid */ 1039 if (!(s1 & TXS_V)) 1040 break; 1041 1042 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2)); 1043 txs->status = s1 & TXS_STATUS_MASK; 1044 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT; 1045 txs->sequence = s2 & TXS_SEQ_MASK; 1046 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT; 1047 txs->lasttxtime = 0; 1048 1049 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs); 1050 if (*fatal) 1051 return false; 1052 n++; 1053 } 1054 1055 return n >= max_tx_num; 1056 } 1057 1058 static void brcms_c_tbtt(struct brcms_c_info *wlc) 1059 { 1060 if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC) 1061 /* 1062 * DirFrmQ is now valid...defer setting until end 1063 * of ATIM window 1064 */ 1065 wlc->qvalid |= MCMD_DIRFRMQVAL; 1066 } 1067 1068 /* set initial host flags value */ 1069 static void 1070 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init) 1071 { 1072 struct brcms_hardware *wlc_hw = wlc->hw; 1073 1074 memset(mhfs, 0, MHFMAX * sizeof(u16)); 1075 1076 mhfs[MHF2] |= mhf2_init; 1077 1078 /* prohibit use of slowclock on multifunction boards */ 1079 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 1080 mhfs[MHF1] |= MHF1_FORCEFASTCLK; 1081 1082 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) { 1083 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR; 1084 mhfs[MHF1] |= MHF1_IQSWAP_WAR; 1085 } 1086 } 1087 1088 static uint 1089 dmareg(uint direction, uint fifonum) 1090 { 1091 if (direction == DMA_TX) 1092 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt); 1093 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv); 1094 } 1095 1096 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme) 1097 { 1098 uint i; 1099 char name[8]; 1100 /* 1101 * ucode host flag 2 needed for pio mode, independent of band and fifo 1102 */ 1103 u16 pio_mhf2 = 0; 1104 struct brcms_hardware *wlc_hw = wlc->hw; 1105 uint unit = wlc_hw->unit; 1106 1107 /* name and offsets for dma_attach */ 1108 snprintf(name, sizeof(name), "wl%d", unit); 1109 1110 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */ 1111 int dma_attach_err = 0; 1112 1113 /* 1114 * FIFO 0 1115 * TX: TX_AC_BK_FIFO (TX AC Background data packets) 1116 * RX: RX_FIFO (RX data packets) 1117 */ 1118 wlc_hw->di[0] = dma_attach(name, wlc, 1119 (wme ? dmareg(DMA_TX, 0) : 0), 1120 dmareg(DMA_RX, 0), 1121 (wme ? NTXD : 0), NRXD, 1122 RXBUFSZ, -1, NRXBUFPOST, 1123 BRCMS_HWRXOFF); 1124 dma_attach_err |= (NULL == wlc_hw->di[0]); 1125 1126 /* 1127 * FIFO 1 1128 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets) 1129 * (legacy) TX_DATA_FIFO (TX data packets) 1130 * RX: UNUSED 1131 */ 1132 wlc_hw->di[1] = dma_attach(name, wlc, 1133 dmareg(DMA_TX, 1), 0, 1134 NTXD, 0, 0, -1, 0, 0); 1135 dma_attach_err |= (NULL == wlc_hw->di[1]); 1136 1137 /* 1138 * FIFO 2 1139 * TX: TX_AC_VI_FIFO (TX AC Video data packets) 1140 * RX: UNUSED 1141 */ 1142 wlc_hw->di[2] = dma_attach(name, wlc, 1143 dmareg(DMA_TX, 2), 0, 1144 NTXD, 0, 0, -1, 0, 0); 1145 dma_attach_err |= (NULL == wlc_hw->di[2]); 1146 /* 1147 * FIFO 3 1148 * TX: TX_AC_VO_FIFO (TX AC Voice data packets) 1149 * (legacy) TX_CTL_FIFO (TX control & mgmt packets) 1150 */ 1151 wlc_hw->di[3] = dma_attach(name, wlc, 1152 dmareg(DMA_TX, 3), 1153 0, NTXD, 0, 0, -1, 1154 0, 0); 1155 dma_attach_err |= (NULL == wlc_hw->di[3]); 1156 /* Cleaner to leave this as if with AP defined */ 1157 1158 if (dma_attach_err) { 1159 brcms_err(wlc_hw->d11core, 1160 "wl%d: wlc_attach: dma_attach failed\n", 1161 unit); 1162 return false; 1163 } 1164 1165 /* get pointer to dma engine tx flow control variable */ 1166 for (i = 0; i < NFIFO; i++) 1167 if (wlc_hw->di[i]) 1168 wlc_hw->txavail[i] = 1169 (uint *) dma_getvar(wlc_hw->di[i], 1170 "&txavail"); 1171 } 1172 1173 /* initial ucode host flags */ 1174 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2); 1175 1176 return true; 1177 } 1178 1179 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw) 1180 { 1181 uint j; 1182 1183 for (j = 0; j < NFIFO; j++) { 1184 if (wlc_hw->di[j]) { 1185 dma_detach(wlc_hw->di[j]); 1186 wlc_hw->di[j] = NULL; 1187 } 1188 } 1189 } 1190 1191 /* 1192 * Initialize brcms_c_info default values ... 1193 * may get overrides later in this function 1194 * BMAC_NOTES, move low out and resolve the dangling ones 1195 */ 1196 static void brcms_b_info_init(struct brcms_hardware *wlc_hw) 1197 { 1198 struct brcms_c_info *wlc = wlc_hw->wlc; 1199 1200 /* set default sw macintmask value */ 1201 wlc->defmacintmask = DEF_MACINTMASK; 1202 1203 /* various 802.11g modes */ 1204 wlc_hw->shortslot = false; 1205 1206 wlc_hw->SFBL = RETRY_SHORT_FB; 1207 wlc_hw->LFBL = RETRY_LONG_FB; 1208 1209 /* default mac retry limits */ 1210 wlc_hw->SRL = RETRY_SHORT_DEF; 1211 wlc_hw->LRL = RETRY_LONG_DEF; 1212 wlc_hw->chanspec = ch20mhz_chspec(1); 1213 } 1214 1215 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw) 1216 { 1217 /* delay before first read of ucode state */ 1218 udelay(40); 1219 1220 /* wait until ucode is no longer asleep */ 1221 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) == 1222 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly); 1223 } 1224 1225 /* control chip clock to save power, enable dynamic clock or force fast clock */ 1226 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode) 1227 { 1228 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) { 1229 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock 1230 * on backplane, but mac core will still run on ALP(not HT) when 1231 * it enters powersave mode, which means the FCA bit may not be 1232 * set. Should wakeup mac if driver wants it to run on HT. 1233 */ 1234 1235 if (wlc_hw->clk) { 1236 if (mode == BCMA_CLKMODE_FAST) { 1237 bcma_set32(wlc_hw->d11core, 1238 D11REGOFFS(clk_ctl_st), 1239 CCS_FORCEHT); 1240 1241 udelay(64); 1242 1243 SPINWAIT( 1244 ((bcma_read32(wlc_hw->d11core, 1245 D11REGOFFS(clk_ctl_st)) & 1246 CCS_HTAVAIL) == 0), 1247 PMU_MAX_TRANSITION_DLY); 1248 WARN_ON(!(bcma_read32(wlc_hw->d11core, 1249 D11REGOFFS(clk_ctl_st)) & 1250 CCS_HTAVAIL)); 1251 } else { 1252 if ((ai_get_pmurev(wlc_hw->sih) == 0) && 1253 (bcma_read32(wlc_hw->d11core, 1254 D11REGOFFS(clk_ctl_st)) & 1255 (CCS_FORCEHT | CCS_HTAREQ))) 1256 SPINWAIT( 1257 ((bcma_read32(wlc_hw->d11core, 1258 offsetof(struct d11regs, 1259 clk_ctl_st)) & 1260 CCS_HTAVAIL) == 0), 1261 PMU_MAX_TRANSITION_DLY); 1262 bcma_mask32(wlc_hw->d11core, 1263 D11REGOFFS(clk_ctl_st), 1264 ~CCS_FORCEHT); 1265 } 1266 } 1267 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST); 1268 } else { 1269 1270 /* old chips w/o PMU, force HT through cc, 1271 * then use FCA to verify mac is running fast clock 1272 */ 1273 1274 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode); 1275 1276 /* check fast clock is available (if core is not in reset) */ 1277 if (wlc_hw->forcefastclk && wlc_hw->clk) 1278 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) & 1279 SISF_FCLKA)); 1280 1281 /* 1282 * keep the ucode wake bit on if forcefastclk is on since we 1283 * do not want ucode to put us back to slow clock when it dozes 1284 * for PM mode. Code below matches the wake override bit with 1285 * current forcefastclk state. Only setting bit in wake_override 1286 * instead of waking ucode immediately since old code had this 1287 * behavior. Older code set wlc->forcefastclk but only had the 1288 * wake happen if the wakup_ucode work (protected by an up 1289 * check) was executed just below. 1290 */ 1291 if (wlc_hw->forcefastclk) 1292 mboolset(wlc_hw->wake_override, 1293 BRCMS_WAKE_OVERRIDE_FORCEFAST); 1294 else 1295 mboolclr(wlc_hw->wake_override, 1296 BRCMS_WAKE_OVERRIDE_FORCEFAST); 1297 } 1298 } 1299 1300 /* set or clear ucode host flag bits 1301 * it has an optimization for no-change write 1302 * it only writes through shared memory when the core has clock; 1303 * pre-CLK changes should use wlc_write_mhf to get around the optimization 1304 * 1305 * 1306 * bands values are: BRCM_BAND_AUTO <--- Current band only 1307 * BRCM_BAND_5G <--- 5G band only 1308 * BRCM_BAND_2G <--- 2G band only 1309 * BRCM_BAND_ALL <--- All bands 1310 */ 1311 void 1312 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, 1313 int bands) 1314 { 1315 u16 save; 1316 u16 addr[MHFMAX] = { 1317 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, 1318 M_HOST_FLAGS5 1319 }; 1320 struct brcms_hw_band *band; 1321 1322 if ((val & ~mask) || idx >= MHFMAX) 1323 return; /* error condition */ 1324 1325 switch (bands) { 1326 /* Current band only or all bands, 1327 * then set the band to current band 1328 */ 1329 case BRCM_BAND_AUTO: 1330 case BRCM_BAND_ALL: 1331 band = wlc_hw->band; 1332 break; 1333 case BRCM_BAND_5G: 1334 band = wlc_hw->bandstate[BAND_5G_INDEX]; 1335 break; 1336 case BRCM_BAND_2G: 1337 band = wlc_hw->bandstate[BAND_2G_INDEX]; 1338 break; 1339 default: 1340 band = NULL; /* error condition */ 1341 } 1342 1343 if (band) { 1344 save = band->mhfs[idx]; 1345 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val; 1346 1347 /* optimization: only write through if changed, and 1348 * changed band is the current band 1349 */ 1350 if (wlc_hw->clk && (band->mhfs[idx] != save) 1351 && (band == wlc_hw->band)) 1352 brcms_b_write_shm(wlc_hw, addr[idx], 1353 (u16) band->mhfs[idx]); 1354 } 1355 1356 if (bands == BRCM_BAND_ALL) { 1357 wlc_hw->bandstate[0]->mhfs[idx] = 1358 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val; 1359 wlc_hw->bandstate[1]->mhfs[idx] = 1360 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val; 1361 } 1362 } 1363 1364 /* set the maccontrol register to desired reset state and 1365 * initialize the sw cache of the register 1366 */ 1367 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw) 1368 { 1369 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */ 1370 wlc_hw->maccontrol = 0; 1371 wlc_hw->suspended_fifos = 0; 1372 wlc_hw->wake_override = 0; 1373 wlc_hw->mute_override = 0; 1374 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE); 1375 } 1376 1377 /* 1378 * write the software state of maccontrol and 1379 * overrides to the maccontrol register 1380 */ 1381 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw) 1382 { 1383 u32 maccontrol = wlc_hw->maccontrol; 1384 1385 /* OR in the wake bit if overridden */ 1386 if (wlc_hw->wake_override) 1387 maccontrol |= MCTL_WAKE; 1388 1389 /* set AP and INFRA bits for mute if needed */ 1390 if (wlc_hw->mute_override) { 1391 maccontrol &= ~(MCTL_AP); 1392 maccontrol |= MCTL_INFRA; 1393 } 1394 1395 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol), 1396 maccontrol); 1397 } 1398 1399 /* set or clear maccontrol bits */ 1400 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val) 1401 { 1402 u32 maccontrol; 1403 u32 new_maccontrol; 1404 1405 if (val & ~mask) 1406 return; /* error condition */ 1407 maccontrol = wlc_hw->maccontrol; 1408 new_maccontrol = (maccontrol & ~mask) | val; 1409 1410 /* if the new maccontrol value is the same as the old, nothing to do */ 1411 if (new_maccontrol == maccontrol) 1412 return; 1413 1414 /* something changed, cache the new value */ 1415 wlc_hw->maccontrol = new_maccontrol; 1416 1417 /* write the new values with overrides applied */ 1418 brcms_c_mctrl_write(wlc_hw); 1419 } 1420 1421 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw, 1422 u32 override_bit) 1423 { 1424 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) { 1425 mboolset(wlc_hw->wake_override, override_bit); 1426 return; 1427 } 1428 1429 mboolset(wlc_hw->wake_override, override_bit); 1430 1431 brcms_c_mctrl_write(wlc_hw); 1432 brcms_b_wait_for_wake(wlc_hw); 1433 } 1434 1435 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw, 1436 u32 override_bit) 1437 { 1438 mboolclr(wlc_hw->wake_override, override_bit); 1439 1440 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) 1441 return; 1442 1443 brcms_c_mctrl_write(wlc_hw); 1444 } 1445 1446 /* When driver needs ucode to stop beaconing, it has to make sure that 1447 * MCTL_AP is clear and MCTL_INFRA is set 1448 * Mode MCTL_AP MCTL_INFRA 1449 * AP 1 1 1450 * STA 0 1 <--- This will ensure no beacons 1451 * IBSS 0 0 1452 */ 1453 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw) 1454 { 1455 wlc_hw->mute_override = 1; 1456 1457 /* if maccontrol already has AP == 0 and INFRA == 1 without this 1458 * override, then there is no change to write 1459 */ 1460 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA) 1461 return; 1462 1463 brcms_c_mctrl_write(wlc_hw); 1464 } 1465 1466 /* Clear the override on AP and INFRA bits */ 1467 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw) 1468 { 1469 if (wlc_hw->mute_override == 0) 1470 return; 1471 1472 wlc_hw->mute_override = 0; 1473 1474 /* if maccontrol already has AP == 0 and INFRA == 1 without this 1475 * override, then there is no change to write 1476 */ 1477 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA) 1478 return; 1479 1480 brcms_c_mctrl_write(wlc_hw); 1481 } 1482 1483 /* 1484 * Write a MAC address to the given match reg offset in the RXE match engine. 1485 */ 1486 static void 1487 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset, 1488 const u8 *addr) 1489 { 1490 struct bcma_device *core = wlc_hw->d11core; 1491 u16 mac_l; 1492 u16 mac_m; 1493 u16 mac_h; 1494 1495 brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit); 1496 1497 mac_l = addr[0] | (addr[1] << 8); 1498 mac_m = addr[2] | (addr[3] << 8); 1499 mac_h = addr[4] | (addr[5] << 8); 1500 1501 /* enter the MAC addr into the RXE match registers */ 1502 bcma_write16(core, D11REGOFFS(rcm_ctl), 1503 RCM_INC_DATA | match_reg_offset); 1504 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l); 1505 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m); 1506 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h); 1507 } 1508 1509 void 1510 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len, 1511 void *buf) 1512 { 1513 struct bcma_device *core = wlc_hw->d11core; 1514 u32 word; 1515 __le32 word_le; 1516 __be32 word_be; 1517 bool be_bit; 1518 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit); 1519 1520 bcma_write32(core, D11REGOFFS(tplatewrptr), offset); 1521 1522 /* if MCTL_BIGEND bit set in mac control register, 1523 * the chip swaps data in fifo, as well as data in 1524 * template ram 1525 */ 1526 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0; 1527 1528 while (len > 0) { 1529 memcpy(&word, buf, sizeof(u32)); 1530 1531 if (be_bit) { 1532 word_be = cpu_to_be32(word); 1533 word = *(u32 *)&word_be; 1534 } else { 1535 word_le = cpu_to_le32(word); 1536 word = *(u32 *)&word_le; 1537 } 1538 1539 bcma_write32(core, D11REGOFFS(tplatewrdata), word); 1540 1541 buf = (u8 *) buf + sizeof(u32); 1542 len -= sizeof(u32); 1543 } 1544 } 1545 1546 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin) 1547 { 1548 wlc_hw->band->CWmin = newmin; 1549 1550 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 1551 OBJADDR_SCR_SEL | S_DOT11_CWMIN); 1552 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 1553 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin); 1554 } 1555 1556 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax) 1557 { 1558 wlc_hw->band->CWmax = newmax; 1559 1560 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 1561 OBJADDR_SCR_SEL | S_DOT11_CWMAX); 1562 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 1563 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax); 1564 } 1565 1566 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw) 1567 { 1568 bool fastclk; 1569 1570 /* request FAST clock if not on */ 1571 fastclk = wlc_hw->forcefastclk; 1572 if (!fastclk) 1573 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 1574 1575 wlc_phy_bw_state_set(wlc_hw->band->pi, bw); 1576 1577 brcms_b_phy_reset(wlc_hw); 1578 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi)); 1579 1580 /* restore the clk */ 1581 if (!fastclk) 1582 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC); 1583 } 1584 1585 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw) 1586 { 1587 u16 v; 1588 struct brcms_c_info *wlc = wlc_hw->wlc; 1589 /* update SYNTHPU_DLY */ 1590 1591 if (BRCMS_ISLCNPHY(wlc->band)) 1592 v = SYNTHPU_DLY_LPPHY_US; 1593 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) 1594 v = SYNTHPU_DLY_NPHY_US; 1595 else 1596 v = SYNTHPU_DLY_BPHY_US; 1597 1598 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v); 1599 } 1600 1601 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw) 1602 { 1603 u16 phyctl; 1604 u16 phytxant = wlc_hw->bmac_phytxant; 1605 u16 mask = PHY_TXC_ANT_MASK; 1606 1607 /* set the Probe Response frame phy control word */ 1608 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS); 1609 phyctl = (phyctl & ~mask) | phytxant; 1610 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl); 1611 1612 /* set the Response (ACK/CTS) frame phy control word */ 1613 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD); 1614 phyctl = (phyctl & ~mask) | phytxant; 1615 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl); 1616 } 1617 1618 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw, 1619 u8 rate) 1620 { 1621 uint i; 1622 u8 plcp_rate = 0; 1623 struct plcp_signal_rate_lookup { 1624 u8 rate; 1625 u8 signal_rate; 1626 }; 1627 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */ 1628 const struct plcp_signal_rate_lookup rate_lookup[] = { 1629 {BRCM_RATE_6M, 0xB}, 1630 {BRCM_RATE_9M, 0xF}, 1631 {BRCM_RATE_12M, 0xA}, 1632 {BRCM_RATE_18M, 0xE}, 1633 {BRCM_RATE_24M, 0x9}, 1634 {BRCM_RATE_36M, 0xD}, 1635 {BRCM_RATE_48M, 0x8}, 1636 {BRCM_RATE_54M, 0xC} 1637 }; 1638 1639 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) { 1640 if (rate == rate_lookup[i].rate) { 1641 plcp_rate = rate_lookup[i].signal_rate; 1642 break; 1643 } 1644 } 1645 1646 /* Find the SHM pointer to the rate table entry by looking in the 1647 * Direct-map Table 1648 */ 1649 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2)); 1650 } 1651 1652 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw) 1653 { 1654 u8 rate; 1655 u8 rates[8] = { 1656 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M, 1657 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M 1658 }; 1659 u16 entry_ptr; 1660 u16 pctl1; 1661 uint i; 1662 1663 if (!BRCMS_PHY_11N_CAP(wlc_hw->band)) 1664 return; 1665 1666 /* walk the phy rate table and update the entries */ 1667 for (i = 0; i < ARRAY_SIZE(rates); i++) { 1668 rate = rates[i]; 1669 1670 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate); 1671 1672 /* read the SHM Rate Table entry OFDM PCTL1 values */ 1673 pctl1 = 1674 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS); 1675 1676 /* modify the value */ 1677 pctl1 &= ~PHY_TXC1_MODE_MASK; 1678 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT); 1679 1680 /* Update the SHM Rate Table entry OFDM PCTL1 values */ 1681 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS, 1682 pctl1); 1683 } 1684 } 1685 1686 /* band-specific init */ 1687 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec) 1688 { 1689 struct brcms_hardware *wlc_hw = wlc->hw; 1690 1691 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit, 1692 wlc_hw->band->bandunit); 1693 1694 brcms_c_ucode_bsinit(wlc_hw); 1695 1696 wlc_phy_init(wlc_hw->band->pi, chanspec); 1697 1698 brcms_c_ucode_txant_set(wlc_hw); 1699 1700 /* 1701 * cwmin is band-specific, update hardware 1702 * with value for current band 1703 */ 1704 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin); 1705 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax); 1706 1707 brcms_b_update_slot_timing(wlc_hw, 1708 wlc_hw->band->bandtype == BRCM_BAND_5G ? 1709 true : wlc_hw->shortslot); 1710 1711 /* write phytype and phyvers */ 1712 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype); 1713 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev); 1714 1715 /* 1716 * initialize the txphyctl1 rate table since 1717 * shmem is shared between bands 1718 */ 1719 brcms_upd_ofdm_pctl1_table(wlc_hw); 1720 1721 brcms_b_upd_synthpu(wlc_hw); 1722 } 1723 1724 /* Perform a soft reset of the PHY PLL */ 1725 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw) 1726 { 1727 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr), 1728 ~0, 0); 1729 udelay(1); 1730 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1731 0x4, 0); 1732 udelay(1); 1733 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1734 0x4, 4); 1735 udelay(1); 1736 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1737 0x4, 0); 1738 udelay(1); 1739 } 1740 1741 /* light way to turn on phy clock without reset for NPHY only 1742 * refer to brcms_b_core_phy_clk for full version 1743 */ 1744 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk) 1745 { 1746 /* support(necessary for NPHY and HYPHY) only */ 1747 if (!BRCMS_ISNPHY(wlc_hw->band)) 1748 return; 1749 1750 if (ON == clk) 1751 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC); 1752 else 1753 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0); 1754 1755 } 1756 1757 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk) 1758 { 1759 if (ON == clk) 1760 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE); 1761 else 1762 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0); 1763 } 1764 1765 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw) 1766 { 1767 struct brcms_phy_pub *pih = wlc_hw->band->pi; 1768 u32 phy_bw_clkbits; 1769 1770 brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit); 1771 1772 if (pih == NULL) 1773 return; 1774 1775 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi); 1776 1777 /* Specific reset sequence required for NPHY rev 3 and 4 */ 1778 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) && 1779 NREV_LE(wlc_hw->band->phyrev, 4)) { 1780 /* Set the PHY bandwidth */ 1781 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits); 1782 1783 udelay(1); 1784 1785 /* Perform a soft reset of the PHY PLL */ 1786 brcms_b_core_phypll_reset(wlc_hw); 1787 1788 /* reset the PHY */ 1789 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE), 1790 (SICF_PRST | SICF_PCLKE)); 1791 } else { 1792 brcms_b_core_ioctl(wlc_hw, 1793 (SICF_PRST | SICF_PCLKE | SICF_BWMASK), 1794 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits)); 1795 } 1796 1797 udelay(2); 1798 brcms_b_core_phy_clk(wlc_hw, ON); 1799 1800 wlc_phy_anacore(pih, ON); 1801 } 1802 1803 /* switch to and initialize new band */ 1804 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit, 1805 u16 chanspec) { 1806 struct brcms_c_info *wlc = wlc_hw->wlc; 1807 u32 macintmask; 1808 1809 /* Enable the d11 core before accessing it */ 1810 if (!bcma_core_is_enabled(wlc_hw->d11core)) { 1811 bcma_core_enable(wlc_hw->d11core, 0); 1812 brcms_c_mctrl_reset(wlc_hw); 1813 } 1814 1815 macintmask = brcms_c_setband_inact(wlc, bandunit); 1816 1817 if (!wlc_hw->up) 1818 return; 1819 1820 brcms_b_core_phy_clk(wlc_hw, ON); 1821 1822 /* band-specific initializations */ 1823 brcms_b_bsinit(wlc, chanspec); 1824 1825 /* 1826 * If there are any pending software interrupt bits, 1827 * then replace these with a harmless nonzero value 1828 * so brcms_c_dpc() will re-enable interrupts when done. 1829 */ 1830 if (wlc->macintstatus) 1831 wlc->macintstatus = MI_DMAINT; 1832 1833 /* restore macintmask */ 1834 brcms_intrsrestore(wlc->wl, macintmask); 1835 1836 /* ucode should still be suspended.. */ 1837 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) & 1838 MCTL_EN_MAC) != 0); 1839 } 1840 1841 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw) 1842 { 1843 1844 /* reject unsupported corerev */ 1845 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) { 1846 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n", 1847 wlc_hw->corerev); 1848 return false; 1849 } 1850 1851 return true; 1852 } 1853 1854 /* Validate some board info parameters */ 1855 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw) 1856 { 1857 uint boardrev = wlc_hw->boardrev; 1858 1859 /* 4 bits each for board type, major, minor, and tiny version */ 1860 uint brt = (boardrev & 0xf000) >> 12; 1861 uint b0 = (boardrev & 0xf00) >> 8; 1862 uint b1 = (boardrev & 0xf0) >> 4; 1863 uint b2 = boardrev & 0xf; 1864 1865 /* voards from other vendors are always considered valid */ 1866 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM) 1867 return true; 1868 1869 /* do some boardrev sanity checks when boardvendor is Broadcom */ 1870 if (boardrev == 0) 1871 return false; 1872 1873 if (boardrev <= 0xff) 1874 return true; 1875 1876 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9) 1877 || (b2 > 9)) 1878 return false; 1879 1880 return true; 1881 } 1882 1883 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN]) 1884 { 1885 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom; 1886 1887 /* If macaddr exists, use it (Sromrev4, CIS, ...). */ 1888 if (!is_zero_ether_addr(sprom->il0mac)) { 1889 memcpy(etheraddr, sprom->il0mac, ETH_ALEN); 1890 return; 1891 } 1892 1893 if (wlc_hw->_nbands > 1) 1894 memcpy(etheraddr, sprom->et1mac, ETH_ALEN); 1895 else 1896 memcpy(etheraddr, sprom->il0mac, ETH_ALEN); 1897 } 1898 1899 /* power both the pll and external oscillator on/off */ 1900 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want) 1901 { 1902 brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want); 1903 1904 /* 1905 * dont power down if plldown is false or 1906 * we must poll hw radio disable 1907 */ 1908 if (!want && wlc_hw->pllreq) 1909 return; 1910 1911 wlc_hw->sbclk = want; 1912 if (!wlc_hw->sbclk) { 1913 wlc_hw->clk = false; 1914 if (wlc_hw->band && wlc_hw->band->pi) 1915 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 1916 } 1917 } 1918 1919 /* 1920 * Return true if radio is disabled, otherwise false. 1921 * hw radio disable signal is an external pin, users activate it asynchronously 1922 * this function could be called when driver is down and w/o clock 1923 * it operates on different registers depending on corerev and boardflag. 1924 */ 1925 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw) 1926 { 1927 bool v, clk, xtal; 1928 u32 flags = 0; 1929 1930 xtal = wlc_hw->sbclk; 1931 if (!xtal) 1932 brcms_b_xtal(wlc_hw, ON); 1933 1934 /* may need to take core out of reset first */ 1935 clk = wlc_hw->clk; 1936 if (!clk) { 1937 /* 1938 * mac no longer enables phyclk automatically when driver 1939 * accesses phyreg throughput mac. This can be skipped since 1940 * only mac reg is accessed below 1941 */ 1942 if (D11REV_GE(wlc_hw->corerev, 18)) 1943 flags |= SICF_PCLKE; 1944 1945 /* 1946 * TODO: test suspend/resume 1947 * 1948 * AI chip doesn't restore bar0win2 on 1949 * hibernation/resume, need sw fixup 1950 */ 1951 1952 bcma_core_enable(wlc_hw->d11core, flags); 1953 brcms_c_mctrl_reset(wlc_hw); 1954 } 1955 1956 v = ((bcma_read32(wlc_hw->d11core, 1957 D11REGOFFS(phydebug)) & PDBG_RFD) != 0); 1958 1959 /* put core back into reset */ 1960 if (!clk) 1961 bcma_core_disable(wlc_hw->d11core, 0); 1962 1963 if (!xtal) 1964 brcms_b_xtal(wlc_hw, OFF); 1965 1966 return v; 1967 } 1968 1969 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo) 1970 { 1971 struct dma_pub *di = wlc_hw->di[fifo]; 1972 return dma_rxreset(di); 1973 } 1974 1975 /* d11 core reset 1976 * ensure fask clock during reset 1977 * reset dma 1978 * reset d11(out of reset) 1979 * reset phy(out of reset) 1980 * clear software macintstatus for fresh new start 1981 * one testing hack wlc_hw->noreset will bypass the d11/phy reset 1982 */ 1983 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags) 1984 { 1985 uint i; 1986 bool fastclk; 1987 1988 if (flags == BRCMS_USE_COREFLAGS) 1989 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0); 1990 1991 brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit); 1992 1993 /* request FAST clock if not on */ 1994 fastclk = wlc_hw->forcefastclk; 1995 if (!fastclk) 1996 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 1997 1998 /* reset the dma engines except first time thru */ 1999 if (bcma_core_is_enabled(wlc_hw->d11core)) { 2000 for (i = 0; i < NFIFO; i++) 2001 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) 2002 brcms_err(wlc_hw->d11core, "wl%d: %s: " 2003 "dma_txreset[%d]: cannot stop dma\n", 2004 wlc_hw->unit, __func__, i); 2005 2006 if ((wlc_hw->di[RX_FIFO]) 2007 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) 2008 brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset" 2009 "[%d]: cannot stop dma\n", 2010 wlc_hw->unit, __func__, RX_FIFO); 2011 } 2012 /* if noreset, just stop the psm and return */ 2013 if (wlc_hw->noreset) { 2014 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */ 2015 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0); 2016 return; 2017 } 2018 2019 /* 2020 * mac no longer enables phyclk automatically when driver accesses 2021 * phyreg throughput mac, AND phy_reset is skipped at early stage when 2022 * band->pi is invalid. need to enable PHY CLK 2023 */ 2024 if (D11REV_GE(wlc_hw->corerev, 18)) 2025 flags |= SICF_PCLKE; 2026 2027 /* 2028 * reset the core 2029 * In chips with PMU, the fastclk request goes through d11 core 2030 * reg 0x1e0, which is cleared by the core_reset. have to re-request it. 2031 * 2032 * This adds some delay and we can optimize it by also requesting 2033 * fastclk through chipcommon during this period if necessary. But 2034 * that has to work coordinate with other driver like mips/arm since 2035 * they may touch chipcommon as well. 2036 */ 2037 wlc_hw->clk = false; 2038 bcma_core_enable(wlc_hw->d11core, flags); 2039 wlc_hw->clk = true; 2040 if (wlc_hw->band && wlc_hw->band->pi) 2041 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true); 2042 2043 brcms_c_mctrl_reset(wlc_hw); 2044 2045 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) 2046 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 2047 2048 brcms_b_phy_reset(wlc_hw); 2049 2050 /* turn on PHY_PLL */ 2051 brcms_b_core_phypll_ctl(wlc_hw, true); 2052 2053 /* clear sw intstatus */ 2054 wlc_hw->wlc->macintstatus = 0; 2055 2056 /* restore the clk setting */ 2057 if (!fastclk) 2058 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC); 2059 } 2060 2061 /* txfifo sizes needs to be modified(increased) since the newer cores 2062 * have more memory. 2063 */ 2064 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw) 2065 { 2066 struct bcma_device *core = wlc_hw->d11core; 2067 u16 fifo_nu; 2068 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk; 2069 u16 txfifo_def, txfifo_def1; 2070 u16 txfifo_cmd; 2071 2072 /* tx fifos start at TXFIFO_START_BLK from the Base address */ 2073 txfifo_startblk = TXFIFO_START_BLK; 2074 2075 /* sequence of operations: reset fifo, set fifo size, reset fifo */ 2076 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) { 2077 2078 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu]; 2079 txfifo_def = (txfifo_startblk & 0xff) | 2080 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT); 2081 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) | 2082 ((((txfifo_endblk - 2083 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT); 2084 txfifo_cmd = 2085 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT); 2086 2087 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd); 2088 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def); 2089 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1); 2090 2091 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd); 2092 2093 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu]; 2094 } 2095 /* 2096 * need to propagate to shm location to be in sync since ucode/hw won't 2097 * do this 2098 */ 2099 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0, 2100 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]); 2101 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1, 2102 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]); 2103 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2, 2104 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw-> 2105 xmtfifo_sz[TX_AC_BK_FIFO])); 2106 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3, 2107 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw-> 2108 xmtfifo_sz[TX_BCMC_FIFO])); 2109 } 2110 2111 /* This function is used for changing the tsf frac register 2112 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz 2113 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz 2114 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz 2115 * HTPHY Formula is 2^26/freq(MHz) e.g. 2116 * For spuron2 - 126MHz -> 2^26/126 = 532610.0 2117 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082 2118 * For spuron: 123MHz -> 2^26/123 = 545600.5 2119 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341 2120 * For spur off: 120MHz -> 2^26/120 = 559240.5 2121 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889 2122 */ 2123 2124 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode) 2125 { 2126 struct bcma_device *core = wlc_hw->d11core; 2127 2128 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) || 2129 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) { 2130 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */ 2131 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082); 2132 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2133 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */ 2134 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341); 2135 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2136 } else { /* 120Mhz */ 2137 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889); 2138 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2139 } 2140 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2141 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */ 2142 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0); 2143 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC); 2144 } else { /* 80Mhz */ 2145 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD); 2146 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC); 2147 } 2148 } 2149 } 2150 2151 void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr) 2152 { 2153 memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr)); 2154 wlc->bsscfg->type = BRCMS_TYPE_STATION; 2155 } 2156 2157 void brcms_c_start_ap(struct brcms_c_info *wlc, u8 *addr, const u8 *bssid, 2158 u8 *ssid, size_t ssid_len) 2159 { 2160 brcms_c_set_ssid(wlc, ssid, ssid_len); 2161 2162 memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr)); 2163 memcpy(wlc->bsscfg->BSSID, bssid, sizeof(wlc->bsscfg->BSSID)); 2164 wlc->bsscfg->type = BRCMS_TYPE_AP; 2165 2166 brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, MCTL_AP | MCTL_INFRA); 2167 } 2168 2169 void brcms_c_start_adhoc(struct brcms_c_info *wlc, u8 *addr) 2170 { 2171 memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr)); 2172 wlc->bsscfg->type = BRCMS_TYPE_ADHOC; 2173 2174 brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, 0); 2175 } 2176 2177 /* Initialize GPIOs that are controlled by D11 core */ 2178 static void brcms_c_gpio_init(struct brcms_c_info *wlc) 2179 { 2180 struct brcms_hardware *wlc_hw = wlc->hw; 2181 u32 gc, gm; 2182 2183 /* use GPIO select 0 to get all gpio signals from the gpio out reg */ 2184 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0); 2185 2186 /* 2187 * Common GPIO setup: 2188 * G0 = LED 0 = WLAN Activity 2189 * G1 = LED 1 = WLAN 2.4 GHz Radio State 2190 * G2 = LED 2 = WLAN 5 GHz Radio State 2191 * G4 = radio disable input (HI enabled, LO disabled) 2192 */ 2193 2194 gc = gm = 0; 2195 2196 /* Allocate GPIOs for mimo antenna diversity feature */ 2197 if (wlc_hw->antsel_type == ANTSEL_2x3) { 2198 /* Enable antenna diversity, use 2x3 mode */ 2199 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2200 MHF3_ANTSEL_EN, BRCM_BAND_ALL); 2201 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 2202 MHF3_ANTSEL_MODE, BRCM_BAND_ALL); 2203 2204 /* init superswitch control */ 2205 wlc_phy_antsel_init(wlc_hw->band->pi, false); 2206 2207 } else if (wlc_hw->antsel_type == ANTSEL_2x4) { 2208 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13); 2209 /* 2210 * The board itself is powered by these GPIOs 2211 * (when not sending pattern) so set them high 2212 */ 2213 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe), 2214 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2215 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out), 2216 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2217 2218 /* Enable antenna diversity, use 2x4 mode */ 2219 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2220 MHF3_ANTSEL_EN, BRCM_BAND_ALL); 2221 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0, 2222 BRCM_BAND_ALL); 2223 2224 /* Configure the desired clock to be 4Mhz */ 2225 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV, 2226 ANTSEL_CLKDIV_4MHZ); 2227 } 2228 2229 /* 2230 * gpio 9 controls the PA. ucode is responsible 2231 * for wiggling out and oe 2232 */ 2233 if (wlc_hw->boardflags & BFL_PACTRL) 2234 gm |= gc |= BOARD_GPIO_PACTRL; 2235 2236 /* apply to gpiocontrol register */ 2237 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc); 2238 } 2239 2240 static void brcms_ucode_write(struct brcms_hardware *wlc_hw, 2241 const __le32 ucode[], const size_t nbytes) 2242 { 2243 struct bcma_device *core = wlc_hw->d11core; 2244 uint i; 2245 uint count; 2246 2247 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 2248 2249 count = (nbytes / sizeof(u32)); 2250 2251 bcma_write32(core, D11REGOFFS(objaddr), 2252 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL); 2253 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2254 for (i = 0; i < count; i++) 2255 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i])); 2256 2257 } 2258 2259 static void brcms_ucode_download(struct brcms_hardware *wlc_hw) 2260 { 2261 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 2262 2263 if (wlc_hw->ucode_loaded) 2264 return; 2265 2266 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) { 2267 if (BRCMS_ISNPHY(wlc_hw->band)) { 2268 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo, 2269 ucode->bcm43xx_16_mimosz); 2270 wlc_hw->ucode_loaded = true; 2271 } else 2272 brcms_err(wlc_hw->d11core, 2273 "%s: wl%d: unsupported phy in corerev %d\n", 2274 __func__, wlc_hw->unit, wlc_hw->corerev); 2275 } else if (D11REV_IS(wlc_hw->corerev, 24)) { 2276 if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2277 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn, 2278 ucode->bcm43xx_24_lcnsz); 2279 wlc_hw->ucode_loaded = true; 2280 } else { 2281 brcms_err(wlc_hw->d11core, 2282 "%s: wl%d: unsupported phy in corerev %d\n", 2283 __func__, wlc_hw->unit, wlc_hw->corerev); 2284 } 2285 } 2286 } 2287 2288 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant) 2289 { 2290 /* update sw state */ 2291 wlc_hw->bmac_phytxant = phytxant; 2292 2293 /* push to ucode if up */ 2294 if (!wlc_hw->up) 2295 return; 2296 brcms_c_ucode_txant_set(wlc_hw); 2297 2298 } 2299 2300 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw) 2301 { 2302 return (u16) wlc_hw->wlc->stf->txant; 2303 } 2304 2305 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type) 2306 { 2307 wlc_hw->antsel_type = antsel_type; 2308 2309 /* Update the antsel type for phy module to use */ 2310 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type); 2311 } 2312 2313 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw) 2314 { 2315 bool fatal = false; 2316 uint unit; 2317 uint intstatus, idx; 2318 struct bcma_device *core = wlc_hw->d11core; 2319 2320 unit = wlc_hw->unit; 2321 2322 for (idx = 0; idx < NFIFO; idx++) { 2323 /* read intstatus register and ignore any non-error bits */ 2324 intstatus = 2325 bcma_read32(core, 2326 D11REGOFFS(intctrlregs[idx].intstatus)) & 2327 I_ERRORS; 2328 if (!intstatus) 2329 continue; 2330 2331 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n", 2332 unit, idx, intstatus); 2333 2334 if (intstatus & I_RO) { 2335 brcms_err(core, "wl%d: fifo %d: receive fifo " 2336 "overflow\n", unit, idx); 2337 fatal = true; 2338 } 2339 2340 if (intstatus & I_PC) { 2341 brcms_err(core, "wl%d: fifo %d: descriptor error\n", 2342 unit, idx); 2343 fatal = true; 2344 } 2345 2346 if (intstatus & I_PD) { 2347 brcms_err(core, "wl%d: fifo %d: data error\n", unit, 2348 idx); 2349 fatal = true; 2350 } 2351 2352 if (intstatus & I_DE) { 2353 brcms_err(core, "wl%d: fifo %d: descriptor protocol " 2354 "error\n", unit, idx); 2355 fatal = true; 2356 } 2357 2358 if (intstatus & I_RU) 2359 brcms_err(core, "wl%d: fifo %d: receive descriptor " 2360 "underflow\n", idx, unit); 2361 2362 if (intstatus & I_XU) { 2363 brcms_err(core, "wl%d: fifo %d: transmit fifo " 2364 "underflow\n", idx, unit); 2365 fatal = true; 2366 } 2367 2368 if (fatal) { 2369 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */ 2370 break; 2371 } else 2372 bcma_write32(core, 2373 D11REGOFFS(intctrlregs[idx].intstatus), 2374 intstatus); 2375 } 2376 } 2377 2378 void brcms_c_intrson(struct brcms_c_info *wlc) 2379 { 2380 struct brcms_hardware *wlc_hw = wlc->hw; 2381 wlc->macintmask = wlc->defmacintmask; 2382 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask); 2383 } 2384 2385 u32 brcms_c_intrsoff(struct brcms_c_info *wlc) 2386 { 2387 struct brcms_hardware *wlc_hw = wlc->hw; 2388 u32 macintmask; 2389 2390 if (!wlc_hw->clk) 2391 return 0; 2392 2393 macintmask = wlc->macintmask; /* isr can still happen */ 2394 2395 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0); 2396 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask)); 2397 udelay(1); /* ensure int line is no longer driven */ 2398 wlc->macintmask = 0; 2399 2400 /* return previous macintmask; resolve race between us and our isr */ 2401 return wlc->macintstatus ? 0 : macintmask; 2402 } 2403 2404 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask) 2405 { 2406 struct brcms_hardware *wlc_hw = wlc->hw; 2407 if (!wlc_hw->clk) 2408 return; 2409 2410 wlc->macintmask = macintmask; 2411 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask); 2412 } 2413 2414 /* assumes that the d11 MAC is enabled */ 2415 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw, 2416 uint tx_fifo) 2417 { 2418 u8 fifo = 1 << tx_fifo; 2419 2420 /* Two clients of this code, 11h Quiet period and scanning. */ 2421 2422 /* only suspend if not already suspended */ 2423 if ((wlc_hw->suspended_fifos & fifo) == fifo) 2424 return; 2425 2426 /* force the core awake only if not already */ 2427 if (wlc_hw->suspended_fifos == 0) 2428 brcms_c_ucode_wake_override_set(wlc_hw, 2429 BRCMS_WAKE_OVERRIDE_TXFIFO); 2430 2431 wlc_hw->suspended_fifos |= fifo; 2432 2433 if (wlc_hw->di[tx_fifo]) { 2434 /* 2435 * Suspending AMPDU transmissions in the middle can cause 2436 * underflow which may result in mismatch between ucode and 2437 * driver so suspend the mac before suspending the FIFO 2438 */ 2439 if (BRCMS_PHY_11N_CAP(wlc_hw->band)) 2440 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 2441 2442 dma_txsuspend(wlc_hw->di[tx_fifo]); 2443 2444 if (BRCMS_PHY_11N_CAP(wlc_hw->band)) 2445 brcms_c_enable_mac(wlc_hw->wlc); 2446 } 2447 } 2448 2449 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw, 2450 uint tx_fifo) 2451 { 2452 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case 2453 * but need to be done here for PIO otherwise the watchdog will catch 2454 * the inconsistency and fire 2455 */ 2456 /* Two clients of this code, 11h Quiet period and scanning. */ 2457 if (wlc_hw->di[tx_fifo]) 2458 dma_txresume(wlc_hw->di[tx_fifo]); 2459 2460 /* allow core to sleep again */ 2461 if (wlc_hw->suspended_fifos == 0) 2462 return; 2463 else { 2464 wlc_hw->suspended_fifos &= ~(1 << tx_fifo); 2465 if (wlc_hw->suspended_fifos == 0) 2466 brcms_c_ucode_wake_override_clear(wlc_hw, 2467 BRCMS_WAKE_OVERRIDE_TXFIFO); 2468 } 2469 } 2470 2471 /* precondition: requires the mac core to be enabled */ 2472 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx) 2473 { 2474 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 2475 u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr; 2476 2477 if (mute_tx) { 2478 /* suspend tx fifos */ 2479 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO); 2480 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO); 2481 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO); 2482 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO); 2483 2484 /* zero the address match register so we do not send ACKs */ 2485 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr); 2486 } else { 2487 /* resume tx fifos */ 2488 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO); 2489 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO); 2490 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO); 2491 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO); 2492 2493 /* Restore address */ 2494 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr); 2495 } 2496 2497 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0); 2498 2499 if (mute_tx) 2500 brcms_c_ucode_mute_override_set(wlc_hw); 2501 else 2502 brcms_c_ucode_mute_override_clear(wlc_hw); 2503 } 2504 2505 void 2506 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx) 2507 { 2508 brcms_b_mute(wlc->hw, mute_tx); 2509 } 2510 2511 /* 2512 * Read and clear macintmask and macintstatus and intstatus registers. 2513 * This routine should be called with interrupts off 2514 * Return: 2515 * -1 if brcms_deviceremoved(wlc) evaluates to true; 2516 * 0 if the interrupt is not for us, or we are in some special cases; 2517 * device interrupt status bits otherwise. 2518 */ 2519 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr) 2520 { 2521 struct brcms_hardware *wlc_hw = wlc->hw; 2522 struct bcma_device *core = wlc_hw->d11core; 2523 u32 macintstatus, mask; 2524 2525 /* macintstatus includes a DMA interrupt summary bit */ 2526 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus)); 2527 mask = in_isr ? wlc->macintmask : wlc->defmacintmask; 2528 2529 trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask); 2530 2531 /* detect cardbus removed, in power down(suspend) and in reset */ 2532 if (brcms_deviceremoved(wlc)) 2533 return -1; 2534 2535 /* brcms_deviceremoved() succeeds even when the core is still resetting, 2536 * handle that case here. 2537 */ 2538 if (macintstatus == 0xffffffff) 2539 return 0; 2540 2541 /* defer unsolicited interrupts */ 2542 macintstatus &= mask; 2543 2544 /* if not for us */ 2545 if (macintstatus == 0) 2546 return 0; 2547 2548 /* turn off the interrupts */ 2549 bcma_write32(core, D11REGOFFS(macintmask), 0); 2550 (void)bcma_read32(core, D11REGOFFS(macintmask)); 2551 wlc->macintmask = 0; 2552 2553 /* clear device interrupts */ 2554 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus); 2555 2556 /* MI_DMAINT is indication of non-zero intstatus */ 2557 if (macintstatus & MI_DMAINT) 2558 /* 2559 * only fifo interrupt enabled is I_RI in 2560 * RX_FIFO. If MI_DMAINT is set, assume it 2561 * is set and clear the interrupt. 2562 */ 2563 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus), 2564 DEF_RXINTMASK); 2565 2566 return macintstatus; 2567 } 2568 2569 /* Update wlc->macintstatus and wlc->intstatus[]. */ 2570 /* Return true if they are updated successfully. false otherwise */ 2571 bool brcms_c_intrsupd(struct brcms_c_info *wlc) 2572 { 2573 u32 macintstatus; 2574 2575 /* read and clear macintstatus and intstatus registers */ 2576 macintstatus = wlc_intstatus(wlc, false); 2577 2578 /* device is removed */ 2579 if (macintstatus == 0xffffffff) 2580 return false; 2581 2582 /* update interrupt status in software */ 2583 wlc->macintstatus |= macintstatus; 2584 2585 return true; 2586 } 2587 2588 /* 2589 * First-level interrupt processing. 2590 * Return true if this was our interrupt 2591 * and if further brcms_c_dpc() processing is required, 2592 * false otherwise. 2593 */ 2594 bool brcms_c_isr(struct brcms_c_info *wlc) 2595 { 2596 struct brcms_hardware *wlc_hw = wlc->hw; 2597 u32 macintstatus; 2598 2599 if (!wlc_hw->up || !wlc->macintmask) 2600 return false; 2601 2602 /* read and clear macintstatus and intstatus registers */ 2603 macintstatus = wlc_intstatus(wlc, true); 2604 2605 if (macintstatus == 0xffffffff) { 2606 brcms_err(wlc_hw->d11core, 2607 "DEVICEREMOVED detected in the ISR code path\n"); 2608 return false; 2609 } 2610 2611 /* it is not for us */ 2612 if (macintstatus == 0) 2613 return false; 2614 2615 /* save interrupt status bits */ 2616 wlc->macintstatus = macintstatus; 2617 2618 return true; 2619 2620 } 2621 2622 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc) 2623 { 2624 struct brcms_hardware *wlc_hw = wlc->hw; 2625 struct bcma_device *core = wlc_hw->d11core; 2626 u32 mc, mi; 2627 2628 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit, 2629 wlc_hw->band->bandunit); 2630 2631 /* 2632 * Track overlapping suspend requests 2633 */ 2634 wlc_hw->mac_suspend_depth++; 2635 if (wlc_hw->mac_suspend_depth > 1) 2636 return; 2637 2638 /* force the core awake */ 2639 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2640 2641 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2642 2643 if (mc == 0xffffffff) { 2644 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 2645 __func__); 2646 brcms_down(wlc->wl); 2647 return; 2648 } 2649 WARN_ON(mc & MCTL_PSM_JMP_0); 2650 WARN_ON(!(mc & MCTL_PSM_RUN)); 2651 WARN_ON(!(mc & MCTL_EN_MAC)); 2652 2653 mi = bcma_read32(core, D11REGOFFS(macintstatus)); 2654 if (mi == 0xffffffff) { 2655 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 2656 __func__); 2657 brcms_down(wlc->wl); 2658 return; 2659 } 2660 WARN_ON(mi & MI_MACSSPNDD); 2661 2662 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0); 2663 2664 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD), 2665 BRCMS_MAX_MAC_SUSPEND); 2666 2667 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) { 2668 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS" 2669 " and MI_MACSSPNDD is still not on.\n", 2670 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND); 2671 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, " 2672 "psm_brc 0x%04x\n", wlc_hw->unit, 2673 bcma_read32(core, D11REGOFFS(psmdebug)), 2674 bcma_read32(core, D11REGOFFS(phydebug)), 2675 bcma_read16(core, D11REGOFFS(psm_brc))); 2676 } 2677 2678 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2679 if (mc == 0xffffffff) { 2680 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 2681 __func__); 2682 brcms_down(wlc->wl); 2683 return; 2684 } 2685 WARN_ON(mc & MCTL_PSM_JMP_0); 2686 WARN_ON(!(mc & MCTL_PSM_RUN)); 2687 WARN_ON(mc & MCTL_EN_MAC); 2688 } 2689 2690 void brcms_c_enable_mac(struct brcms_c_info *wlc) 2691 { 2692 struct brcms_hardware *wlc_hw = wlc->hw; 2693 struct bcma_device *core = wlc_hw->d11core; 2694 u32 mc, mi; 2695 2696 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit, 2697 wlc->band->bandunit); 2698 2699 /* 2700 * Track overlapping suspend requests 2701 */ 2702 wlc_hw->mac_suspend_depth--; 2703 if (wlc_hw->mac_suspend_depth > 0) 2704 return; 2705 2706 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2707 WARN_ON(mc & MCTL_PSM_JMP_0); 2708 WARN_ON(mc & MCTL_EN_MAC); 2709 WARN_ON(!(mc & MCTL_PSM_RUN)); 2710 2711 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC); 2712 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD); 2713 2714 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2715 WARN_ON(mc & MCTL_PSM_JMP_0); 2716 WARN_ON(!(mc & MCTL_EN_MAC)); 2717 WARN_ON(!(mc & MCTL_PSM_RUN)); 2718 2719 mi = bcma_read32(core, D11REGOFFS(macintstatus)); 2720 WARN_ON(mi & MI_MACSSPNDD); 2721 2722 brcms_c_ucode_wake_override_clear(wlc_hw, 2723 BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2724 } 2725 2726 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode) 2727 { 2728 wlc_hw->hw_stf_ss_opmode = stf_mode; 2729 2730 if (wlc_hw->clk) 2731 brcms_upd_ofdm_pctl1_table(wlc_hw); 2732 } 2733 2734 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw) 2735 { 2736 struct bcma_device *core = wlc_hw->d11core; 2737 u32 w, val; 2738 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 2739 2740 /* Validate dchip register access */ 2741 2742 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2743 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2744 w = bcma_read32(core, D11REGOFFS(objdata)); 2745 2746 /* Can we write and read back a 32bit register? */ 2747 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2748 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2749 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa); 2750 2751 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2752 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2753 val = bcma_read32(core, D11REGOFFS(objdata)); 2754 if (val != (u32) 0xaa5555aa) { 2755 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2756 "expected 0xaa5555aa\n", wlc_hw->unit, val); 2757 return false; 2758 } 2759 2760 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2761 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2762 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55); 2763 2764 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2765 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2766 val = bcma_read32(core, D11REGOFFS(objdata)); 2767 if (val != (u32) 0x55aaaa55) { 2768 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2769 "expected 0x55aaaa55\n", wlc_hw->unit, val); 2770 return false; 2771 } 2772 2773 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2774 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2775 bcma_write32(core, D11REGOFFS(objdata), w); 2776 2777 /* clear CFPStart */ 2778 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0); 2779 2780 w = bcma_read32(core, D11REGOFFS(maccontrol)); 2781 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) && 2782 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) { 2783 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = " 2784 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, 2785 (MCTL_IHR_EN | MCTL_WAKE), 2786 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)); 2787 return false; 2788 } 2789 2790 return true; 2791 } 2792 2793 #define PHYPLL_WAIT_US 100000 2794 2795 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on) 2796 { 2797 struct bcma_device *core = wlc_hw->d11core; 2798 u32 tmp; 2799 2800 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit); 2801 2802 tmp = 0; 2803 2804 if (on) { 2805 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) { 2806 bcma_set32(core, D11REGOFFS(clk_ctl_st), 2807 CCS_ERSRC_REQ_HT | 2808 CCS_ERSRC_REQ_D11PLL | 2809 CCS_ERSRC_REQ_PHYPLL); 2810 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) & 2811 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT, 2812 PHYPLL_WAIT_US); 2813 2814 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2815 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT) 2816 brcms_err(core, "%s: turn on PHY PLL failed\n", 2817 __func__); 2818 } else { 2819 bcma_set32(core, D11REGOFFS(clk_ctl_st), 2820 tmp | CCS_ERSRC_REQ_D11PLL | 2821 CCS_ERSRC_REQ_PHYPLL); 2822 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) & 2823 (CCS_ERSRC_AVAIL_D11PLL | 2824 CCS_ERSRC_AVAIL_PHYPLL)) != 2825 (CCS_ERSRC_AVAIL_D11PLL | 2826 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US); 2827 2828 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2829 if ((tmp & 2830 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2831 != 2832 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2833 brcms_err(core, "%s: turn on PHY PLL failed\n", 2834 __func__); 2835 } 2836 } else { 2837 /* 2838 * Since the PLL may be shared, other cores can still 2839 * be requesting it; so we'll deassert the request but 2840 * not wait for status to comply. 2841 */ 2842 bcma_mask32(core, D11REGOFFS(clk_ctl_st), 2843 ~CCS_ERSRC_REQ_PHYPLL); 2844 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2845 } 2846 } 2847 2848 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw) 2849 { 2850 bool dev_gone; 2851 2852 brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit); 2853 2854 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 2855 2856 if (dev_gone) 2857 return; 2858 2859 if (wlc_hw->noreset) 2860 return; 2861 2862 /* radio off */ 2863 wlc_phy_switch_radio(wlc_hw->band->pi, OFF); 2864 2865 /* turn off analog core */ 2866 wlc_phy_anacore(wlc_hw->band->pi, OFF); 2867 2868 /* turn off PHYPLL to save power */ 2869 brcms_b_core_phypll_ctl(wlc_hw, false); 2870 2871 wlc_hw->clk = false; 2872 bcma_core_disable(wlc_hw->d11core, 0); 2873 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 2874 } 2875 2876 static void brcms_c_flushqueues(struct brcms_c_info *wlc) 2877 { 2878 struct brcms_hardware *wlc_hw = wlc->hw; 2879 uint i; 2880 2881 /* free any posted tx packets */ 2882 for (i = 0; i < NFIFO; i++) { 2883 if (wlc_hw->di[i]) { 2884 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL); 2885 if (i < TX_BCMC_FIFO) 2886 ieee80211_wake_queue(wlc->pub->ieee_hw, 2887 brcms_fifo_to_ac(i)); 2888 } 2889 } 2890 2891 /* free any posted rx packets */ 2892 dma_rxreclaim(wlc_hw->di[RX_FIFO]); 2893 } 2894 2895 static u16 2896 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel) 2897 { 2898 struct bcma_device *core = wlc_hw->d11core; 2899 u16 objoff = D11REGOFFS(objdata); 2900 2901 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2)); 2902 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2903 if (offset & 2) 2904 objoff += 2; 2905 2906 return bcma_read16(core, objoff); 2907 } 2908 2909 static void 2910 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v, 2911 u32 sel) 2912 { 2913 struct bcma_device *core = wlc_hw->d11core; 2914 u16 objoff = D11REGOFFS(objdata); 2915 2916 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2)); 2917 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2918 if (offset & 2) 2919 objoff += 2; 2920 2921 bcma_wflush16(core, objoff, v); 2922 } 2923 2924 /* 2925 * Read a single u16 from shared memory. 2926 * SHM 'offset' needs to be an even address 2927 */ 2928 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset) 2929 { 2930 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL); 2931 } 2932 2933 /* 2934 * Write a single u16 to shared memory. 2935 * SHM 'offset' needs to be an even address 2936 */ 2937 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v) 2938 { 2939 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL); 2940 } 2941 2942 /* 2943 * Copy a buffer to shared memory of specified type . 2944 * SHM 'offset' needs to be an even address and 2945 * Buffer length 'len' must be an even number of bytes 2946 * 'sel' selects the type of memory 2947 */ 2948 void 2949 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset, 2950 const void *buf, int len, u32 sel) 2951 { 2952 u16 v; 2953 const u8 *p = (const u8 *)buf; 2954 int i; 2955 2956 if (len <= 0 || (offset & 1) || (len & 1)) 2957 return; 2958 2959 for (i = 0; i < len; i += 2) { 2960 v = p[i] | (p[i + 1] << 8); 2961 brcms_b_write_objmem(wlc_hw, offset + i, v, sel); 2962 } 2963 } 2964 2965 /* 2966 * Copy a piece of shared memory of specified type to a buffer . 2967 * SHM 'offset' needs to be an even address and 2968 * Buffer length 'len' must be an even number of bytes 2969 * 'sel' selects the type of memory 2970 */ 2971 void 2972 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf, 2973 int len, u32 sel) 2974 { 2975 u16 v; 2976 u8 *p = (u8 *) buf; 2977 int i; 2978 2979 if (len <= 0 || (offset & 1) || (len & 1)) 2980 return; 2981 2982 for (i = 0; i < len; i += 2) { 2983 v = brcms_b_read_objmem(wlc_hw, offset + i, sel); 2984 p[i] = v & 0xFF; 2985 p[i + 1] = (v >> 8) & 0xFF; 2986 } 2987 } 2988 2989 /* Copy a buffer to shared memory. 2990 * SHM 'offset' needs to be an even address and 2991 * Buffer length 'len' must be an even number of bytes 2992 */ 2993 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset, 2994 const void *buf, int len) 2995 { 2996 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL); 2997 } 2998 2999 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw, 3000 u16 SRL, u16 LRL) 3001 { 3002 wlc_hw->SRL = SRL; 3003 wlc_hw->LRL = LRL; 3004 3005 /* write retry limit to SCR, shouldn't need to suspend */ 3006 if (wlc_hw->up) { 3007 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 3008 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3009 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 3010 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL); 3011 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 3012 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3013 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 3014 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL); 3015 } 3016 } 3017 3018 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit) 3019 { 3020 if (set) { 3021 if (mboolisset(wlc_hw->pllreq, req_bit)) 3022 return; 3023 3024 mboolset(wlc_hw->pllreq, req_bit); 3025 3026 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) { 3027 if (!wlc_hw->sbclk) 3028 brcms_b_xtal(wlc_hw, ON); 3029 } 3030 } else { 3031 if (!mboolisset(wlc_hw->pllreq, req_bit)) 3032 return; 3033 3034 mboolclr(wlc_hw->pllreq, req_bit); 3035 3036 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) { 3037 if (wlc_hw->sbclk) 3038 brcms_b_xtal(wlc_hw, OFF); 3039 } 3040 } 3041 } 3042 3043 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail) 3044 { 3045 wlc_hw->antsel_avail = antsel_avail; 3046 } 3047 3048 /* 3049 * conditions under which the PM bit should be set in outgoing frames 3050 * and STAY_AWAKE is meaningful 3051 */ 3052 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc) 3053 { 3054 /* not supporting PS so always return false for now */ 3055 return false; 3056 } 3057 3058 static void brcms_c_statsupd(struct brcms_c_info *wlc) 3059 { 3060 int i; 3061 struct macstat *macstats; 3062 #ifdef DEBUG 3063 u16 delta; 3064 u16 rxf0ovfl; 3065 u16 txfunfl[NFIFO]; 3066 #endif /* DEBUG */ 3067 3068 /* if driver down, make no sense to update stats */ 3069 if (!wlc->pub->up) 3070 return; 3071 3072 macstats = wlc->core->macstat_snapshot; 3073 3074 #ifdef DEBUG 3075 /* save last rx fifo 0 overflow count */ 3076 rxf0ovfl = macstats->rxf0ovfl; 3077 3078 /* save last tx fifo underflow count */ 3079 for (i = 0; i < NFIFO; i++) 3080 txfunfl[i] = macstats->txfunfl[i]; 3081 #endif /* DEBUG */ 3082 3083 /* Read mac stats from contiguous shared memory */ 3084 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, macstats, 3085 sizeof(*macstats), OBJADDR_SHM_SEL); 3086 3087 #ifdef DEBUG 3088 /* check for rx fifo 0 overflow */ 3089 delta = (u16)(macstats->rxf0ovfl - rxf0ovfl); 3090 if (delta) 3091 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n", 3092 wlc->pub->unit, delta); 3093 3094 /* check for tx fifo underflows */ 3095 for (i = 0; i < NFIFO; i++) { 3096 delta = macstats->txfunfl[i] - txfunfl[i]; 3097 if (delta) 3098 brcms_err(wlc->hw->d11core, 3099 "wl%d: %u tx fifo %d underflows!\n", 3100 wlc->pub->unit, delta, i); 3101 } 3102 #endif /* DEBUG */ 3103 3104 /* merge counters from dma module */ 3105 for (i = 0; i < NFIFO; i++) { 3106 if (wlc->hw->di[i]) 3107 dma_counterreset(wlc->hw->di[i]); 3108 } 3109 } 3110 3111 static void brcms_b_reset(struct brcms_hardware *wlc_hw) 3112 { 3113 /* reset the core */ 3114 if (!brcms_deviceremoved(wlc_hw->wlc)) 3115 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 3116 3117 /* purge the dma rings */ 3118 brcms_c_flushqueues(wlc_hw->wlc); 3119 } 3120 3121 void brcms_c_reset(struct brcms_c_info *wlc) 3122 { 3123 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit); 3124 3125 /* slurp up hw mac counters before core reset */ 3126 brcms_c_statsupd(wlc); 3127 3128 /* reset our snapshot of macstat counters */ 3129 memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat)); 3130 3131 brcms_b_reset(wlc->hw); 3132 } 3133 3134 void brcms_c_init_scb(struct scb *scb) 3135 { 3136 int i; 3137 3138 memset(scb, 0, sizeof(struct scb)); 3139 scb->flags = SCB_WMECAP | SCB_HTCAP; 3140 for (i = 0; i < NUMPRIO; i++) { 3141 scb->seqnum[i] = 0; 3142 } 3143 3144 scb->magic = SCB_MAGIC; 3145 } 3146 3147 /* d11 core init 3148 * reset PSM 3149 * download ucode/PCM 3150 * let ucode run to suspended 3151 * download ucode inits 3152 * config other core registers 3153 * init dma 3154 */ 3155 static void brcms_b_coreinit(struct brcms_c_info *wlc) 3156 { 3157 struct brcms_hardware *wlc_hw = wlc->hw; 3158 struct bcma_device *core = wlc_hw->d11core; 3159 u32 bcnint_us; 3160 uint i = 0; 3161 bool fifosz_fixup = false; 3162 int err = 0; 3163 u16 buf[NFIFO]; 3164 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 3165 3166 brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit); 3167 3168 /* reset PSM */ 3169 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE)); 3170 3171 brcms_ucode_download(wlc_hw); 3172 /* 3173 * FIFOSZ fixup. driver wants to controls the fifo allocation. 3174 */ 3175 fifosz_fixup = true; 3176 3177 /* let the PSM run to the suspended state, set mode to BSS STA */ 3178 bcma_write32(core, D11REGOFFS(macintstatus), -1); 3179 brcms_b_mctrl(wlc_hw, ~0, 3180 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE)); 3181 3182 /* wait for ucode to self-suspend after auto-init */ 3183 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) & 3184 MI_MACSSPNDD) == 0), 1000 * 1000); 3185 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0) 3186 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-" 3187 "suspend!\n", wlc_hw->unit); 3188 3189 brcms_c_gpio_init(wlc); 3190 3191 bcma_aread32(core, BCMA_IOST); 3192 3193 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) { 3194 if (BRCMS_ISNPHY(wlc_hw->band)) 3195 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16); 3196 else 3197 brcms_err(core, "%s: wl%d: unsupported phy in corerev" 3198 " %d\n", __func__, wlc_hw->unit, 3199 wlc_hw->corerev); 3200 } else if (D11REV_IS(wlc_hw->corerev, 24)) { 3201 if (BRCMS_ISLCNPHY(wlc_hw->band)) 3202 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24); 3203 else 3204 brcms_err(core, "%s: wl%d: unsupported phy in corerev" 3205 " %d\n", __func__, wlc_hw->unit, 3206 wlc_hw->corerev); 3207 } else { 3208 brcms_err(core, "%s: wl%d: unsupported corerev %d\n", 3209 __func__, wlc_hw->unit, wlc_hw->corerev); 3210 } 3211 3212 /* For old ucode, txfifo sizes needs to be modified(increased) */ 3213 if (fifosz_fixup) 3214 brcms_b_corerev_fifofixup(wlc_hw); 3215 3216 /* check txfifo allocations match between ucode and driver */ 3217 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0); 3218 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) { 3219 i = TX_AC_BE_FIFO; 3220 err = -1; 3221 } 3222 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1); 3223 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) { 3224 i = TX_AC_VI_FIFO; 3225 err = -1; 3226 } 3227 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2); 3228 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff; 3229 buf[TX_AC_BK_FIFO] &= 0xff; 3230 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) { 3231 i = TX_AC_BK_FIFO; 3232 err = -1; 3233 } 3234 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) { 3235 i = TX_AC_VO_FIFO; 3236 err = -1; 3237 } 3238 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3); 3239 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff; 3240 buf[TX_BCMC_FIFO] &= 0xff; 3241 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) { 3242 i = TX_BCMC_FIFO; 3243 err = -1; 3244 } 3245 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) { 3246 i = TX_ATIM_FIFO; 3247 err = -1; 3248 } 3249 if (err != 0) 3250 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d" 3251 " driver size %d index %d\n", buf[i], 3252 wlc_hw->xmtfifo_sz[i], i); 3253 3254 /* make sure we can still talk to the mac */ 3255 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff); 3256 3257 /* band-specific inits done by wlc_bsinit() */ 3258 3259 /* Set up frame burst size and antenna swap threshold init values */ 3260 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST); 3261 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT); 3262 3263 /* enable one rx interrupt per received frame */ 3264 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT)); 3265 3266 /* set the station mode (BSS STA) */ 3267 brcms_b_mctrl(wlc_hw, 3268 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP), 3269 (MCTL_INFRA | MCTL_DISCARD_PMQ)); 3270 3271 /* set up Beacon interval */ 3272 bcnint_us = 0x8000 << 10; 3273 bcma_write32(core, D11REGOFFS(tsf_cfprep), 3274 (bcnint_us << CFPREP_CBI_SHIFT)); 3275 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us); 3276 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1); 3277 3278 /* write interrupt mask */ 3279 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask), 3280 DEF_RXINTMASK); 3281 3282 /* allow the MAC to control the PHY clock (dynamic on/off) */ 3283 brcms_b_macphyclk_set(wlc_hw, ON); 3284 3285 /* program dynamic clock control fast powerup delay register */ 3286 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih); 3287 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly); 3288 3289 /* tell the ucode the corerev */ 3290 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev); 3291 3292 /* tell the ucode MAC capabilities */ 3293 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L, 3294 (u16) (wlc_hw->machwcap & 0xffff)); 3295 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H, 3296 (u16) ((wlc_hw-> 3297 machwcap >> 16) & 0xffff)); 3298 3299 /* write retry limits to SCR, this done after PSM init */ 3300 bcma_write32(core, D11REGOFFS(objaddr), 3301 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3302 (void)bcma_read32(core, D11REGOFFS(objaddr)); 3303 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL); 3304 bcma_write32(core, D11REGOFFS(objaddr), 3305 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3306 (void)bcma_read32(core, D11REGOFFS(objaddr)); 3307 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL); 3308 3309 /* write rate fallback retry limits */ 3310 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL); 3311 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL); 3312 3313 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF); 3314 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN); 3315 3316 /* init the tx dma engines */ 3317 for (i = 0; i < NFIFO; i++) { 3318 if (wlc_hw->di[i]) 3319 dma_txinit(wlc_hw->di[i]); 3320 } 3321 3322 /* init the rx dma engine(s) and post receive buffers */ 3323 dma_rxinit(wlc_hw->di[RX_FIFO]); 3324 dma_rxfill(wlc_hw->di[RX_FIFO]); 3325 } 3326 3327 static void brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) 3328 { 3329 u32 macintmask; 3330 bool fastclk; 3331 struct brcms_c_info *wlc = wlc_hw->wlc; 3332 3333 /* request FAST clock if not on */ 3334 fastclk = wlc_hw->forcefastclk; 3335 if (!fastclk) 3336 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 3337 3338 /* disable interrupts */ 3339 macintmask = brcms_intrsoff(wlc->wl); 3340 3341 /* set up the specified band and chanspec */ 3342 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec)); 3343 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec); 3344 3345 /* do one-time phy inits and calibration */ 3346 wlc_phy_cal_init(wlc_hw->band->pi); 3347 3348 /* core-specific initialization */ 3349 brcms_b_coreinit(wlc); 3350 3351 /* band-specific inits */ 3352 brcms_b_bsinit(wlc, chanspec); 3353 3354 /* restore macintmask */ 3355 brcms_intrsrestore(wlc->wl, macintmask); 3356 3357 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac 3358 * is suspended and brcms_c_enable_mac() will clear this override bit. 3359 */ 3360 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 3361 3362 /* 3363 * initialize mac_suspend_depth to 1 to match ucode 3364 * initial suspended state 3365 */ 3366 wlc_hw->mac_suspend_depth = 1; 3367 3368 /* restore the clk */ 3369 if (!fastclk) 3370 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC); 3371 } 3372 3373 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc, 3374 u16 chanspec) 3375 { 3376 /* Save our copy of the chanspec */ 3377 wlc->chanspec = chanspec; 3378 3379 /* Set the chanspec and power limits for this locale */ 3380 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX); 3381 3382 if (wlc->stf->ss_algosel_auto) 3383 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel, 3384 chanspec); 3385 3386 brcms_c_stf_ss_update(wlc, wlc->band); 3387 } 3388 3389 static void 3390 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs) 3391 { 3392 brcms_c_rateset_default(rs, NULL, wlc->band->phytype, 3393 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL, 3394 (bool) (wlc->pub->_n_enab & SUPPORT_11N), 3395 brcms_chspec_bw(wlc->default_bss->chanspec), 3396 wlc->stf->txstreams); 3397 } 3398 3399 /* derive wlc->band->basic_rate[] table from 'rateset' */ 3400 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc, 3401 struct brcms_c_rateset *rateset) 3402 { 3403 u8 rate; 3404 u8 mandatory; 3405 u8 cck_basic = 0; 3406 u8 ofdm_basic = 0; 3407 u8 *br = wlc->band->basic_rate; 3408 uint i; 3409 3410 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */ 3411 memset(br, 0, BRCM_MAXRATE + 1); 3412 3413 /* For each basic rate in the rates list, make an entry in the 3414 * best basic lookup. 3415 */ 3416 for (i = 0; i < rateset->count; i++) { 3417 /* only make an entry for a basic rate */ 3418 if (!(rateset->rates[i] & BRCMS_RATE_FLAG)) 3419 continue; 3420 3421 /* mask off basic bit */ 3422 rate = (rateset->rates[i] & BRCMS_RATE_MASK); 3423 3424 if (rate > BRCM_MAXRATE) { 3425 brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: " 3426 "invalid rate 0x%X in rate set\n", 3427 rateset->rates[i]); 3428 continue; 3429 } 3430 3431 br[rate] = rate; 3432 } 3433 3434 /* The rate lookup table now has non-zero entries for each 3435 * basic rate, equal to the basic rate: br[basicN] = basicN 3436 * 3437 * To look up the best basic rate corresponding to any 3438 * particular rate, code can use the basic_rate table 3439 * like this 3440 * 3441 * basic_rate = wlc->band->basic_rate[tx_rate] 3442 * 3443 * Make sure there is a best basic rate entry for 3444 * every rate by walking up the table from low rates 3445 * to high, filling in holes in the lookup table 3446 */ 3447 3448 for (i = 0; i < wlc->band->hw_rateset.count; i++) { 3449 rate = wlc->band->hw_rateset.rates[i]; 3450 3451 if (br[rate] != 0) { 3452 /* This rate is a basic rate. 3453 * Keep track of the best basic rate so far by 3454 * modulation type. 3455 */ 3456 if (is_ofdm_rate(rate)) 3457 ofdm_basic = rate; 3458 else 3459 cck_basic = rate; 3460 3461 continue; 3462 } 3463 3464 /* This rate is not a basic rate so figure out the 3465 * best basic rate less than this rate and fill in 3466 * the hole in the table 3467 */ 3468 3469 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic; 3470 3471 if (br[rate] != 0) 3472 continue; 3473 3474 if (is_ofdm_rate(rate)) { 3475 /* 3476 * In 11g and 11a, the OFDM mandatory rates 3477 * are 6, 12, and 24 Mbps 3478 */ 3479 if (rate >= BRCM_RATE_24M) 3480 mandatory = BRCM_RATE_24M; 3481 else if (rate >= BRCM_RATE_12M) 3482 mandatory = BRCM_RATE_12M; 3483 else 3484 mandatory = BRCM_RATE_6M; 3485 } else { 3486 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */ 3487 mandatory = rate; 3488 } 3489 3490 br[rate] = mandatory; 3491 } 3492 } 3493 3494 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc, 3495 u16 chanspec) 3496 { 3497 struct brcms_c_rateset default_rateset; 3498 uint parkband; 3499 uint i, band_order[2]; 3500 3501 /* 3502 * We might have been bandlocked during down and the chip 3503 * power-cycled (hibernate). Figure out the right band to park on 3504 */ 3505 if (wlc->bandlocked || wlc->pub->_nbands == 1) { 3506 /* updated in brcms_c_bandlock() */ 3507 parkband = wlc->band->bandunit; 3508 band_order[0] = band_order[1] = parkband; 3509 } else { 3510 /* park on the band of the specified chanspec */ 3511 parkband = chspec_bandunit(chanspec); 3512 3513 /* order so that parkband initialize last */ 3514 band_order[0] = parkband ^ 1; 3515 band_order[1] = parkband; 3516 } 3517 3518 /* make each band operational, software state init */ 3519 for (i = 0; i < wlc->pub->_nbands; i++) { 3520 uint j = band_order[i]; 3521 3522 wlc->band = wlc->bandstate[j]; 3523 3524 brcms_default_rateset(wlc, &default_rateset); 3525 3526 /* fill in hw_rate */ 3527 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset, 3528 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK, 3529 (bool) (wlc->pub->_n_enab & SUPPORT_11N)); 3530 3531 /* init basic rate lookup */ 3532 brcms_c_rate_lookup_init(wlc, &default_rateset); 3533 } 3534 3535 /* sync up phy/radio chanspec */ 3536 brcms_c_set_phy_chanspec(wlc, chanspec); 3537 } 3538 3539 /* 3540 * Set or clear filtering related maccontrol bits based on 3541 * specified filter flags 3542 */ 3543 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags) 3544 { 3545 u32 promisc_bits = 0; 3546 3547 wlc->filter_flags = filter_flags; 3548 3549 if (filter_flags & FIF_OTHER_BSS) 3550 promisc_bits |= MCTL_PROMISC; 3551 3552 if (filter_flags & FIF_BCN_PRBRESP_PROMISC) 3553 promisc_bits |= MCTL_BCNS_PROMISC; 3554 3555 if (filter_flags & FIF_FCSFAIL) 3556 promisc_bits |= MCTL_KEEPBADFCS; 3557 3558 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL)) 3559 promisc_bits |= MCTL_KEEPCONTROL; 3560 3561 brcms_b_mctrl(wlc->hw, 3562 MCTL_PROMISC | MCTL_BCNS_PROMISC | 3563 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS, 3564 promisc_bits); 3565 } 3566 3567 /* 3568 * ucode, hwmac update 3569 * Channel dependent updates for ucode and hw 3570 */ 3571 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc) 3572 { 3573 /* enable or disable any active IBSSs depending on whether or not 3574 * we are on the home channel 3575 */ 3576 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) { 3577 if (wlc->pub->associated) { 3578 /* 3579 * BMAC_NOTE: This is something that should be fixed 3580 * in ucode inits. I think that the ucode inits set 3581 * up the bcn templates and shm values with a bogus 3582 * beacon. This should not be done in the inits. If 3583 * ucode needs to set up a beacon for testing, the 3584 * test routines should write it down, not expect the 3585 * inits to populate a bogus beacon. 3586 */ 3587 if (BRCMS_PHY_11N_CAP(wlc->band)) 3588 brcms_b_write_shm(wlc->hw, 3589 M_BCN_TXTSF_OFFSET, 0); 3590 } 3591 } else { 3592 /* disable an active IBSS if we are not on the home channel */ 3593 } 3594 } 3595 3596 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate, 3597 u8 basic_rate) 3598 { 3599 u8 phy_rate, index; 3600 u8 basic_phy_rate, basic_index; 3601 u16 dir_table, basic_table; 3602 u16 basic_ptr; 3603 3604 /* Shared memory address for the table we are reading */ 3605 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B; 3606 3607 /* Shared memory address for the table we are writing */ 3608 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B; 3609 3610 /* 3611 * for a given rate, the LS-nibble of the PLCP SIGNAL field is 3612 * the index into the rate table. 3613 */ 3614 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; 3615 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK; 3616 index = phy_rate & 0xf; 3617 basic_index = basic_phy_rate & 0xf; 3618 3619 /* Find the SHM pointer to the ACK rate entry by looking in the 3620 * Direct-map Table 3621 */ 3622 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2)); 3623 3624 /* Update the SHM BSS-basic-rate-set mapping table with the pointer 3625 * to the correct basic rate for the given incoming rate 3626 */ 3627 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr); 3628 } 3629 3630 static const struct brcms_c_rateset * 3631 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc) 3632 { 3633 const struct brcms_c_rateset *rs_dflt; 3634 3635 if (BRCMS_PHY_11N_CAP(wlc->band)) { 3636 if (wlc->band->bandtype == BRCM_BAND_5G) 3637 rs_dflt = &ofdm_mimo_rates; 3638 else 3639 rs_dflt = &cck_ofdm_mimo_rates; 3640 } else if (wlc->band->gmode) 3641 rs_dflt = &cck_ofdm_rates; 3642 else 3643 rs_dflt = &cck_rates; 3644 3645 return rs_dflt; 3646 } 3647 3648 static void brcms_c_set_ratetable(struct brcms_c_info *wlc) 3649 { 3650 const struct brcms_c_rateset *rs_dflt; 3651 struct brcms_c_rateset rs; 3652 u8 rate, basic_rate; 3653 uint i; 3654 3655 rs_dflt = brcms_c_rateset_get_hwrs(wlc); 3656 3657 brcms_c_rateset_copy(rs_dflt, &rs); 3658 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams); 3659 3660 /* walk the phy rate table and update SHM basic rate lookup table */ 3661 for (i = 0; i < rs.count; i++) { 3662 rate = rs.rates[i] & BRCMS_RATE_MASK; 3663 3664 /* for a given rate brcms_basic_rate returns the rate at 3665 * which a response ACK/CTS should be sent. 3666 */ 3667 basic_rate = brcms_basic_rate(wlc, rate); 3668 if (basic_rate == 0) 3669 /* This should only happen if we are using a 3670 * restricted rateset. 3671 */ 3672 basic_rate = rs.rates[0] & BRCMS_RATE_MASK; 3673 3674 brcms_c_write_rate_shm(wlc, rate, basic_rate); 3675 } 3676 } 3677 3678 /* band-specific init */ 3679 static void brcms_c_bsinit(struct brcms_c_info *wlc) 3680 { 3681 brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n", 3682 wlc->pub->unit, wlc->band->bandunit); 3683 3684 /* write ucode ACK/CTS rate table */ 3685 brcms_c_set_ratetable(wlc); 3686 3687 /* update some band specific mac configuration */ 3688 brcms_c_ucode_mac_upd(wlc); 3689 3690 /* init antenna selection */ 3691 brcms_c_antsel_init(wlc->asi); 3692 3693 } 3694 3695 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */ 3696 static int 3697 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM, 3698 bool writeToShm) 3699 { 3700 int idle_busy_ratio_x_16 = 0; 3701 uint offset = 3702 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM : 3703 M_TX_IDLE_BUSY_RATIO_X_16_CCK; 3704 if (duty_cycle > 100 || duty_cycle < 0) { 3705 brcms_err(wlc->hw->d11core, 3706 "wl%d: duty cycle value off limit\n", 3707 wlc->pub->unit); 3708 return -EINVAL; 3709 } 3710 if (duty_cycle) 3711 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle; 3712 /* Only write to shared memory when wl is up */ 3713 if (writeToShm) 3714 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16); 3715 3716 if (isOFDM) 3717 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle; 3718 else 3719 wlc->tx_duty_cycle_cck = (u16) duty_cycle; 3720 3721 return 0; 3722 } 3723 3724 /* push sw hps and wake state through hardware */ 3725 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc) 3726 { 3727 u32 v1, v2; 3728 bool hps; 3729 bool awake_before; 3730 3731 hps = brcms_c_ps_allowed(wlc); 3732 3733 brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit, 3734 hps); 3735 3736 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol)); 3737 v2 = MCTL_WAKE; 3738 if (hps) 3739 v2 |= MCTL_HPS; 3740 3741 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2); 3742 3743 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0)); 3744 3745 if (!awake_before) 3746 brcms_b_wait_for_wake(wlc->hw); 3747 } 3748 3749 /* 3750 * Write this BSS config's MAC address to core. 3751 * Updates RXE match engine. 3752 */ 3753 static void brcms_c_set_mac(struct brcms_bss_cfg *bsscfg) 3754 { 3755 struct brcms_c_info *wlc = bsscfg->wlc; 3756 3757 /* enter the MAC addr into the RXE match registers */ 3758 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, wlc->pub->cur_etheraddr); 3759 3760 brcms_c_ampdu_macaddr_upd(wlc); 3761 } 3762 3763 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl). 3764 * Updates RXE match engine. 3765 */ 3766 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg) 3767 { 3768 /* we need to update BSSID in RXE match registers */ 3769 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID); 3770 } 3771 3772 void brcms_c_set_ssid(struct brcms_c_info *wlc, u8 *ssid, size_t ssid_len) 3773 { 3774 u8 len = min_t(u8, sizeof(wlc->bsscfg->SSID), ssid_len); 3775 memset(wlc->bsscfg->SSID, 0, sizeof(wlc->bsscfg->SSID)); 3776 3777 memcpy(wlc->bsscfg->SSID, ssid, len); 3778 wlc->bsscfg->SSID_len = len; 3779 } 3780 3781 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot) 3782 { 3783 wlc_hw->shortslot = shortslot; 3784 3785 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) { 3786 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 3787 brcms_b_update_slot_timing(wlc_hw, shortslot); 3788 brcms_c_enable_mac(wlc_hw->wlc); 3789 } 3790 } 3791 3792 /* 3793 * Suspend the MAC and update the slot timing 3794 * for standard 11b/g (20us slots) or shortslot 11g (9us slots). 3795 */ 3796 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot) 3797 { 3798 /* use the override if it is set */ 3799 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO) 3800 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON); 3801 3802 if (wlc->shortslot == shortslot) 3803 return; 3804 3805 wlc->shortslot = shortslot; 3806 3807 brcms_b_set_shortslot(wlc->hw, shortslot); 3808 } 3809 3810 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec) 3811 { 3812 if (wlc->home_chanspec != chanspec) { 3813 wlc->home_chanspec = chanspec; 3814 3815 if (wlc->pub->associated) 3816 wlc->bsscfg->current_bss->chanspec = chanspec; 3817 } 3818 } 3819 3820 void 3821 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec, 3822 bool mute_tx, struct txpwr_limits *txpwr) 3823 { 3824 uint bandunit; 3825 3826 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit, 3827 chanspec); 3828 3829 wlc_hw->chanspec = chanspec; 3830 3831 /* Switch bands if necessary */ 3832 if (wlc_hw->_nbands > 1) { 3833 bandunit = chspec_bandunit(chanspec); 3834 if (wlc_hw->band->bandunit != bandunit) { 3835 /* brcms_b_setband disables other bandunit, 3836 * use light band switch if not up yet 3837 */ 3838 if (wlc_hw->up) { 3839 wlc_phy_chanspec_radio_set(wlc_hw-> 3840 bandstate[bandunit]-> 3841 pi, chanspec); 3842 brcms_b_setband(wlc_hw, bandunit, chanspec); 3843 } else { 3844 brcms_c_setxband(wlc_hw, bandunit); 3845 } 3846 } 3847 } 3848 3849 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx); 3850 3851 if (!wlc_hw->up) { 3852 if (wlc_hw->clk) 3853 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, 3854 chanspec); 3855 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec); 3856 } else { 3857 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec); 3858 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec); 3859 3860 /* Update muting of the channel */ 3861 brcms_b_mute(wlc_hw, mute_tx); 3862 } 3863 } 3864 3865 /* switch to and initialize new band */ 3866 static void brcms_c_setband(struct brcms_c_info *wlc, 3867 uint bandunit) 3868 { 3869 wlc->band = wlc->bandstate[bandunit]; 3870 3871 if (!wlc->pub->up) 3872 return; 3873 3874 /* wait for at least one beacon before entering sleeping state */ 3875 brcms_c_set_ps_ctrl(wlc); 3876 3877 /* band-specific initializations */ 3878 brcms_c_bsinit(wlc); 3879 } 3880 3881 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec) 3882 { 3883 uint bandunit; 3884 u16 old_chanspec = wlc->chanspec; 3885 3886 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) { 3887 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n", 3888 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec)); 3889 return; 3890 } 3891 3892 /* Switch bands if necessary */ 3893 if (wlc->pub->_nbands > 1) { 3894 bandunit = chspec_bandunit(chanspec); 3895 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) { 3896 if (wlc->bandlocked) { 3897 brcms_err(wlc->hw->d11core, 3898 "wl%d: %s: chspec %d band is locked!\n", 3899 wlc->pub->unit, __func__, 3900 CHSPEC_CHANNEL(chanspec)); 3901 return; 3902 } 3903 /* 3904 * should the setband call come after the 3905 * brcms_b_chanspec() ? if the setband updates 3906 * (brcms_c_bsinit) use low level calls to inspect and 3907 * set state, the state inspected may be from the wrong 3908 * band, or the following brcms_b_set_chanspec() may 3909 * undo the work. 3910 */ 3911 brcms_c_setband(wlc, bandunit); 3912 } 3913 } 3914 3915 /* sync up phy/radio chanspec */ 3916 brcms_c_set_phy_chanspec(wlc, chanspec); 3917 3918 /* init antenna selection */ 3919 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) { 3920 brcms_c_antsel_init(wlc->asi); 3921 3922 /* Fix the hardware rateset based on bw. 3923 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz 3924 */ 3925 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset, 3926 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0); 3927 } 3928 3929 /* update some mac configuration since chanspec changed */ 3930 brcms_c_ucode_mac_upd(wlc); 3931 } 3932 3933 /* 3934 * This function changes the phytxctl for beacon based on current 3935 * beacon ratespec AND txant setting as per this table: 3936 * ratespec CCK ant = wlc->stf->txant 3937 * OFDM ant = 3 3938 */ 3939 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc, 3940 u32 bcn_rspec) 3941 { 3942 u16 phyctl; 3943 u16 phytxant = wlc->stf->phytxant; 3944 u16 mask = PHY_TXC_ANT_MASK; 3945 3946 /* for non-siso rates or default setting, use the available chains */ 3947 if (BRCMS_PHY_11N_CAP(wlc->band)) 3948 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec); 3949 3950 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD); 3951 phyctl = (phyctl & ~mask) | phytxant; 3952 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl); 3953 } 3954 3955 /* 3956 * centralized protection config change function to simplify debugging, no 3957 * consistency checking this should be called only on changes to avoid overhead 3958 * in periodic function 3959 */ 3960 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val) 3961 { 3962 /* 3963 * Cannot use brcms_dbg_* here because this function is called 3964 * before wlc is sufficiently initialized. 3965 */ 3966 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val); 3967 3968 switch (idx) { 3969 case BRCMS_PROT_G_SPEC: 3970 wlc->protection->_g = (bool) val; 3971 break; 3972 case BRCMS_PROT_G_OVR: 3973 wlc->protection->g_override = (s8) val; 3974 break; 3975 case BRCMS_PROT_G_USER: 3976 wlc->protection->gmode_user = (u8) val; 3977 break; 3978 case BRCMS_PROT_OVERLAP: 3979 wlc->protection->overlap = (s8) val; 3980 break; 3981 case BRCMS_PROT_N_USER: 3982 wlc->protection->nmode_user = (s8) val; 3983 break; 3984 case BRCMS_PROT_N_CFG: 3985 wlc->protection->n_cfg = (s8) val; 3986 break; 3987 case BRCMS_PROT_N_CFG_OVR: 3988 wlc->protection->n_cfg_override = (s8) val; 3989 break; 3990 case BRCMS_PROT_N_NONGF: 3991 wlc->protection->nongf = (bool) val; 3992 break; 3993 case BRCMS_PROT_N_NONGF_OVR: 3994 wlc->protection->nongf_override = (s8) val; 3995 break; 3996 case BRCMS_PROT_N_PAM_OVR: 3997 wlc->protection->n_pam_override = (s8) val; 3998 break; 3999 case BRCMS_PROT_N_OBSS: 4000 wlc->protection->n_obss = (bool) val; 4001 break; 4002 4003 default: 4004 break; 4005 } 4006 4007 } 4008 4009 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val) 4010 { 4011 if (wlc->pub->up) { 4012 brcms_c_update_beacon(wlc); 4013 brcms_c_update_probe_resp(wlc, true); 4014 } 4015 } 4016 4017 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val) 4018 { 4019 wlc->stf->ldpc = val; 4020 4021 if (wlc->pub->up) { 4022 brcms_c_update_beacon(wlc); 4023 brcms_c_update_probe_resp(wlc, true); 4024 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false)); 4025 } 4026 } 4027 4028 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci, 4029 const struct ieee80211_tx_queue_params *params, 4030 bool suspend) 4031 { 4032 int i; 4033 struct shm_acparams acp_shm; 4034 u16 *shm_entry; 4035 4036 /* Only apply params if the core is out of reset and has clocks */ 4037 if (!wlc->clk) { 4038 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n", 4039 wlc->pub->unit, __func__); 4040 return; 4041 } 4042 4043 memset(&acp_shm, 0, sizeof(struct shm_acparams)); 4044 /* fill in shm ac params struct */ 4045 acp_shm.txop = params->txop; 4046 /* convert from units of 32us to us for ucode */ 4047 wlc->edcf_txop[aci & 0x3] = acp_shm.txop = 4048 EDCF_TXOP2USEC(acp_shm.txop); 4049 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK); 4050 4051 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0 4052 && acp_shm.aifs < EDCF_AIFSN_MAX) 4053 acp_shm.aifs++; 4054 4055 if (acp_shm.aifs < EDCF_AIFSN_MIN 4056 || acp_shm.aifs > EDCF_AIFSN_MAX) { 4057 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad " 4058 "aifs %d\n", wlc->pub->unit, acp_shm.aifs); 4059 } else { 4060 acp_shm.cwmin = params->cw_min; 4061 acp_shm.cwmax = params->cw_max; 4062 acp_shm.cwcur = acp_shm.cwmin; 4063 acp_shm.bslots = 4064 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) & 4065 acp_shm.cwcur; 4066 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs; 4067 /* Indicate the new params to the ucode */ 4068 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO + 4069 wme_ac2fifo[aci] * 4070 M_EDCF_QLEN + 4071 M_EDCF_STATUS_OFF)); 4072 acp_shm.status |= WME_STATUS_NEWAC; 4073 4074 /* Fill in shm acparam table */ 4075 shm_entry = (u16 *) &acp_shm; 4076 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2) 4077 brcms_b_write_shm(wlc->hw, 4078 M_EDCF_QINFO + 4079 wme_ac2fifo[aci] * M_EDCF_QLEN + i, 4080 *shm_entry++); 4081 } 4082 4083 if (suspend) 4084 brcms_c_suspend_mac_and_wait(wlc); 4085 4086 brcms_c_update_beacon(wlc); 4087 brcms_c_update_probe_resp(wlc, false); 4088 4089 if (suspend) 4090 brcms_c_enable_mac(wlc); 4091 } 4092 4093 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend) 4094 { 4095 u16 aci; 4096 int i_ac; 4097 struct ieee80211_tx_queue_params txq_pars; 4098 static const struct edcf_acparam default_edcf_acparams[] = { 4099 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA}, 4100 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA}, 4101 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA}, 4102 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA} 4103 }; /* ucode needs these parameters during its initialization */ 4104 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0]; 4105 4106 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) { 4107 /* find out which ac this set of params applies to */ 4108 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT; 4109 4110 /* fill in shm ac params struct */ 4111 txq_pars.txop = edcf_acp->TXOP; 4112 txq_pars.aifs = edcf_acp->ACI; 4113 4114 /* CWmin = 2^(ECWmin) - 1 */ 4115 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK); 4116 /* CWmax = 2^(ECWmax) - 1 */ 4117 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK) 4118 >> EDCF_ECWMAX_SHIFT); 4119 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend); 4120 } 4121 4122 if (suspend) { 4123 brcms_c_suspend_mac_and_wait(wlc); 4124 brcms_c_enable_mac(wlc); 4125 } 4126 } 4127 4128 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc) 4129 { 4130 /* Don't start the timer if HWRADIO feature is disabled */ 4131 if (wlc->radio_monitor) 4132 return; 4133 4134 wlc->radio_monitor = true; 4135 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON); 4136 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true); 4137 } 4138 4139 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc) 4140 { 4141 if (!wlc->radio_monitor) 4142 return true; 4143 4144 wlc->radio_monitor = false; 4145 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON); 4146 return brcms_del_timer(wlc->radio_timer); 4147 } 4148 4149 /* read hwdisable state and propagate to wlc flag */ 4150 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc) 4151 { 4152 if (wlc->pub->hw_off) 4153 return; 4154 4155 if (brcms_b_radio_read_hwdisabled(wlc->hw)) 4156 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4157 else 4158 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4159 } 4160 4161 /* update hwradio status and return it */ 4162 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc) 4163 { 4164 brcms_c_radio_hwdisable_upd(wlc); 4165 4166 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ? 4167 true : false; 4168 } 4169 4170 /* periodical query hw radio button while driver is "down" */ 4171 static void brcms_c_radio_timer(void *arg) 4172 { 4173 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4174 4175 if (brcms_deviceremoved(wlc)) { 4176 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n", 4177 wlc->pub->unit, __func__); 4178 brcms_down(wlc->wl); 4179 return; 4180 } 4181 4182 brcms_c_radio_hwdisable_upd(wlc); 4183 } 4184 4185 /* common low-level watchdog code */ 4186 static void brcms_b_watchdog(struct brcms_c_info *wlc) 4187 { 4188 struct brcms_hardware *wlc_hw = wlc->hw; 4189 4190 if (!wlc_hw->up) 4191 return; 4192 4193 /* increment second count */ 4194 wlc_hw->now++; 4195 4196 /* Check for FIFO error interrupts */ 4197 brcms_b_fifoerrors(wlc_hw); 4198 4199 /* make sure RX dma has buffers */ 4200 dma_rxfill(wlc->hw->di[RX_FIFO]); 4201 4202 wlc_phy_watchdog(wlc_hw->band->pi); 4203 } 4204 4205 /* common watchdog code */ 4206 static void brcms_c_watchdog(struct brcms_c_info *wlc) 4207 { 4208 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit); 4209 4210 if (!wlc->pub->up) 4211 return; 4212 4213 if (brcms_deviceremoved(wlc)) { 4214 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n", 4215 wlc->pub->unit, __func__); 4216 brcms_down(wlc->wl); 4217 return; 4218 } 4219 4220 /* increment second count */ 4221 wlc->pub->now++; 4222 4223 brcms_c_radio_hwdisable_upd(wlc); 4224 /* if radio is disable, driver may be down, quit here */ 4225 if (wlc->pub->radio_disabled) 4226 return; 4227 4228 brcms_b_watchdog(wlc); 4229 4230 /* 4231 * occasionally sample mac stat counters to 4232 * detect 16-bit counter wrap 4233 */ 4234 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0) 4235 brcms_c_statsupd(wlc); 4236 4237 if (BRCMS_ISNPHY(wlc->band) && 4238 ((wlc->pub->now - wlc->tempsense_lasttime) >= 4239 BRCMS_TEMPSENSE_PERIOD)) { 4240 wlc->tempsense_lasttime = wlc->pub->now; 4241 brcms_c_tempsense_upd(wlc); 4242 } 4243 } 4244 4245 static void brcms_c_watchdog_by_timer(void *arg) 4246 { 4247 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4248 4249 brcms_c_watchdog(wlc); 4250 } 4251 4252 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit) 4253 { 4254 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer, 4255 wlc, "watchdog"); 4256 if (!wlc->wdtimer) { 4257 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer " 4258 "failed\n", unit); 4259 goto fail; 4260 } 4261 4262 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer, 4263 wlc, "radio"); 4264 if (!wlc->radio_timer) { 4265 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer " 4266 "failed\n", unit); 4267 goto fail; 4268 } 4269 4270 return true; 4271 4272 fail: 4273 return false; 4274 } 4275 4276 /* 4277 * Initialize brcms_c_info default values ... 4278 * may get overrides later in this function 4279 */ 4280 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit) 4281 { 4282 int i; 4283 4284 /* Save our copy of the chanspec */ 4285 wlc->chanspec = ch20mhz_chspec(1); 4286 4287 /* various 802.11g modes */ 4288 wlc->shortslot = false; 4289 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO; 4290 4291 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO); 4292 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false); 4293 4294 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR, 4295 BRCMS_PROTECTION_AUTO); 4296 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF); 4297 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR, 4298 BRCMS_PROTECTION_AUTO); 4299 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false); 4300 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO); 4301 4302 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP, 4303 BRCMS_PROTECTION_CTL_OVERLAP); 4304 4305 /* 802.11g draft 4.0 NonERP elt advertisement */ 4306 wlc->include_legacy_erp = true; 4307 4308 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF; 4309 wlc->stf->txant = ANT_TX_DEF; 4310 4311 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT; 4312 4313 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN; 4314 for (i = 0; i < NFIFO; i++) 4315 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN; 4316 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN; 4317 4318 /* default rate fallback retry limits */ 4319 wlc->SFBL = RETRY_SHORT_FB; 4320 wlc->LFBL = RETRY_LONG_FB; 4321 4322 /* default mac retry limits */ 4323 wlc->SRL = RETRY_SHORT_DEF; 4324 wlc->LRL = RETRY_LONG_DEF; 4325 4326 /* WME QoS mode is Auto by default */ 4327 wlc->pub->_ampdu = AMPDU_AGG_HOST; 4328 } 4329 4330 static uint brcms_c_attach_module(struct brcms_c_info *wlc) 4331 { 4332 uint err = 0; 4333 uint unit; 4334 unit = wlc->pub->unit; 4335 4336 wlc->asi = brcms_c_antsel_attach(wlc); 4337 if (wlc->asi == NULL) { 4338 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach " 4339 "failed\n", unit); 4340 err = 44; 4341 goto fail; 4342 } 4343 4344 wlc->ampdu = brcms_c_ampdu_attach(wlc); 4345 if (wlc->ampdu == NULL) { 4346 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach " 4347 "failed\n", unit); 4348 err = 50; 4349 goto fail; 4350 } 4351 4352 if ((brcms_c_stf_attach(wlc) != 0)) { 4353 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach " 4354 "failed\n", unit); 4355 err = 68; 4356 goto fail; 4357 } 4358 fail: 4359 return err; 4360 } 4361 4362 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc) 4363 { 4364 return wlc->pub; 4365 } 4366 4367 /* low level attach 4368 * run backplane attach, init nvram 4369 * run phy attach 4370 * initialize software state for each core and band 4371 * put the whole chip in reset(driver down state), no clock 4372 */ 4373 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core, 4374 uint unit, bool piomode) 4375 { 4376 struct brcms_hardware *wlc_hw; 4377 uint err = 0; 4378 uint j; 4379 bool wme = false; 4380 struct shared_phy_params sha_params; 4381 struct wiphy *wiphy = wlc->wiphy; 4382 struct pci_dev *pcidev = core->bus->host_pci; 4383 struct ssb_sprom *sprom = &core->bus->sprom; 4384 4385 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) 4386 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit, 4387 pcidev->vendor, 4388 pcidev->device); 4389 else 4390 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit, 4391 core->bus->boardinfo.vendor, 4392 core->bus->boardinfo.type); 4393 4394 wme = true; 4395 4396 wlc_hw = wlc->hw; 4397 wlc_hw->wlc = wlc; 4398 wlc_hw->unit = unit; 4399 wlc_hw->band = wlc_hw->bandstate[0]; 4400 wlc_hw->_piomode = piomode; 4401 4402 /* populate struct brcms_hardware with default values */ 4403 brcms_b_info_init(wlc_hw); 4404 4405 /* 4406 * Do the hardware portion of the attach. Also initialize software 4407 * state that depends on the particular hardware we are running. 4408 */ 4409 wlc_hw->sih = ai_attach(core->bus); 4410 if (wlc_hw->sih == NULL) { 4411 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n", 4412 unit); 4413 err = 11; 4414 goto fail; 4415 } 4416 4417 /* verify again the device is supported */ 4418 if (!brcms_c_chipmatch(core)) { 4419 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n", 4420 unit); 4421 err = 12; 4422 goto fail; 4423 } 4424 4425 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 4426 wlc_hw->vendorid = pcidev->vendor; 4427 wlc_hw->deviceid = pcidev->device; 4428 } else { 4429 wlc_hw->vendorid = core->bus->boardinfo.vendor; 4430 wlc_hw->deviceid = core->bus->boardinfo.type; 4431 } 4432 4433 wlc_hw->d11core = core; 4434 wlc_hw->corerev = core->id.rev; 4435 4436 /* validate chip, chiprev and corerev */ 4437 if (!brcms_c_isgoodchip(wlc_hw)) { 4438 err = 13; 4439 goto fail; 4440 } 4441 4442 /* initialize power control registers */ 4443 ai_clkctl_init(wlc_hw->sih); 4444 4445 /* request fastclock and force fastclock for the rest of attach 4446 * bring the d11 core out of reset. 4447 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk 4448 * is still false; But it will be called again inside wlc_corereset, 4449 * after d11 is out of reset. 4450 */ 4451 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 4452 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 4453 4454 if (!brcms_b_validate_chip_access(wlc_hw)) { 4455 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access " 4456 "failed\n", unit); 4457 err = 14; 4458 goto fail; 4459 } 4460 4461 /* get the board rev, used just below */ 4462 j = sprom->board_rev; 4463 /* promote srom boardrev of 0xFF to 1 */ 4464 if (j == BOARDREV_PROMOTABLE) 4465 j = BOARDREV_PROMOTED; 4466 wlc_hw->boardrev = (u16) j; 4467 if (!brcms_c_validboardtype(wlc_hw)) { 4468 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom " 4469 "board type (0x%x)" " or revision level (0x%x)\n", 4470 unit, ai_get_boardtype(wlc_hw->sih), 4471 wlc_hw->boardrev); 4472 err = 15; 4473 goto fail; 4474 } 4475 wlc_hw->sromrev = sprom->revision; 4476 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16); 4477 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16); 4478 4479 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 4480 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED); 4481 4482 /* check device id(srom, nvram etc.) to set bands */ 4483 if (wlc_hw->deviceid == BCM43224_D11N_ID || 4484 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 || 4485 wlc_hw->deviceid == BCM43224_CHIP_ID) 4486 /* Dualband boards */ 4487 wlc_hw->_nbands = 2; 4488 else 4489 wlc_hw->_nbands = 1; 4490 4491 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) 4492 wlc_hw->_nbands = 1; 4493 4494 /* BMAC_NOTE: remove init of pub values when brcms_c_attach() 4495 * unconditionally does the init of these values 4496 */ 4497 wlc->vendorid = wlc_hw->vendorid; 4498 wlc->deviceid = wlc_hw->deviceid; 4499 wlc->pub->sih = wlc_hw->sih; 4500 wlc->pub->corerev = wlc_hw->corerev; 4501 wlc->pub->sromrev = wlc_hw->sromrev; 4502 wlc->pub->boardrev = wlc_hw->boardrev; 4503 wlc->pub->boardflags = wlc_hw->boardflags; 4504 wlc->pub->boardflags2 = wlc_hw->boardflags2; 4505 wlc->pub->_nbands = wlc_hw->_nbands; 4506 4507 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc); 4508 4509 if (wlc_hw->physhim == NULL) { 4510 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach " 4511 "failed\n", unit); 4512 err = 25; 4513 goto fail; 4514 } 4515 4516 /* pass all the parameters to wlc_phy_shared_attach in one struct */ 4517 sha_params.sih = wlc_hw->sih; 4518 sha_params.physhim = wlc_hw->physhim; 4519 sha_params.unit = unit; 4520 sha_params.corerev = wlc_hw->corerev; 4521 sha_params.vid = wlc_hw->vendorid; 4522 sha_params.did = wlc_hw->deviceid; 4523 sha_params.chip = ai_get_chip_id(wlc_hw->sih); 4524 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih); 4525 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih); 4526 sha_params.sromrev = wlc_hw->sromrev; 4527 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih); 4528 sha_params.boardrev = wlc_hw->boardrev; 4529 sha_params.boardflags = wlc_hw->boardflags; 4530 sha_params.boardflags2 = wlc_hw->boardflags2; 4531 4532 /* alloc and save pointer to shared phy state area */ 4533 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params); 4534 if (!wlc_hw->phy_sh) { 4535 err = 16; 4536 goto fail; 4537 } 4538 4539 /* initialize software state for each core and band */ 4540 for (j = 0; j < wlc_hw->_nbands; j++) { 4541 /* 4542 * band0 is always 2.4Ghz 4543 * band1, if present, is 5Ghz 4544 */ 4545 4546 brcms_c_setxband(wlc_hw, j); 4547 4548 wlc_hw->band->bandunit = j; 4549 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4550 wlc->band->bandunit = j; 4551 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4552 wlc->core->coreidx = core->core_index; 4553 4554 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap)); 4555 wlc_hw->machwcap_backup = wlc_hw->machwcap; 4556 4557 /* init tx fifo size */ 4558 WARN_ON(wlc_hw->corerev < XMTFIFOTBL_STARTREV || 4559 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) > 4560 ARRAY_SIZE(xmtfifo_sz)); 4561 wlc_hw->xmtfifo_sz = 4562 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)]; 4563 WARN_ON(!wlc_hw->xmtfifo_sz[0]); 4564 4565 /* Get a phy for this band */ 4566 wlc_hw->band->pi = 4567 wlc_phy_attach(wlc_hw->phy_sh, core, 4568 wlc_hw->band->bandtype, 4569 wlc->wiphy); 4570 if (wlc_hw->band->pi == NULL) { 4571 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_" 4572 "attach failed\n", unit); 4573 err = 17; 4574 goto fail; 4575 } 4576 4577 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap); 4578 4579 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype, 4580 &wlc_hw->band->phyrev, 4581 &wlc_hw->band->radioid, 4582 &wlc_hw->band->radiorev); 4583 wlc_hw->band->abgphy_encore = 4584 wlc_phy_get_encore(wlc_hw->band->pi); 4585 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi); 4586 wlc_hw->band->core_flags = 4587 wlc_phy_get_coreflags(wlc_hw->band->pi); 4588 4589 /* verify good phy_type & supported phy revision */ 4590 if (BRCMS_ISNPHY(wlc_hw->band)) { 4591 if (NCONF_HAS(wlc_hw->band->phyrev)) 4592 goto good_phy; 4593 else 4594 goto bad_phy; 4595 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 4596 if (LCNCONF_HAS(wlc_hw->band->phyrev)) 4597 goto good_phy; 4598 else 4599 goto bad_phy; 4600 } else { 4601 bad_phy: 4602 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported " 4603 "phy type/rev (%d/%d)\n", unit, 4604 wlc_hw->band->phytype, wlc_hw->band->phyrev); 4605 err = 18; 4606 goto fail; 4607 } 4608 4609 good_phy: 4610 /* 4611 * BMAC_NOTE: wlc->band->pi should not be set below and should 4612 * be done in the high level attach. However we can not make 4613 * that change until all low level access is changed to 4614 * wlc_hw->band->pi. Instead do the wlc->band->pi init below, 4615 * keeping wlc_hw->band->pi as well for incremental update of 4616 * low level fns, and cut over low only init when all fns 4617 * updated. 4618 */ 4619 wlc->band->pi = wlc_hw->band->pi; 4620 wlc->band->phytype = wlc_hw->band->phytype; 4621 wlc->band->phyrev = wlc_hw->band->phyrev; 4622 wlc->band->radioid = wlc_hw->band->radioid; 4623 wlc->band->radiorev = wlc_hw->band->radiorev; 4624 brcms_dbg_info(core, "wl%d: phy %u/%u radio %x/%u\n", unit, 4625 wlc->band->phytype, wlc->band->phyrev, 4626 wlc->band->radioid, wlc->band->radiorev); 4627 /* default contention windows size limits */ 4628 wlc_hw->band->CWmin = APHY_CWMIN; 4629 wlc_hw->band->CWmax = PHY_CWMAX; 4630 4631 if (!brcms_b_attach_dmapio(wlc, j, wme)) { 4632 err = 19; 4633 goto fail; 4634 } 4635 } 4636 4637 /* disable core to match driver "down" state */ 4638 brcms_c_coredisable(wlc_hw); 4639 4640 /* Match driver "down" state */ 4641 bcma_host_pci_down(wlc_hw->d11core->bus); 4642 4643 /* turn off pll and xtal to match driver "down" state */ 4644 brcms_b_xtal(wlc_hw, OFF); 4645 4646 /* ******************************************************************* 4647 * The hardware is in the DOWN state at this point. D11 core 4648 * or cores are in reset with clocks off, and the board PLLs 4649 * are off if possible. 4650 * 4651 * Beyond this point, wlc->sbclk == false and chip registers 4652 * should not be touched. 4653 ********************************************************************* 4654 */ 4655 4656 /* init etheraddr state variables */ 4657 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr); 4658 4659 if (is_broadcast_ether_addr(wlc_hw->etheraddr) || 4660 is_zero_ether_addr(wlc_hw->etheraddr)) { 4661 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n", 4662 unit); 4663 err = 22; 4664 goto fail; 4665 } 4666 4667 brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n", 4668 wlc_hw->deviceid, wlc_hw->_nbands, 4669 ai_get_boardtype(wlc_hw->sih)); 4670 4671 return err; 4672 4673 fail: 4674 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit, 4675 err); 4676 return err; 4677 } 4678 4679 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc) 4680 { 4681 int aa; 4682 uint unit; 4683 int bandtype; 4684 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom; 4685 4686 unit = wlc->pub->unit; 4687 bandtype = wlc->band->bandtype; 4688 4689 /* get antennas available */ 4690 if (bandtype == BRCM_BAND_5G) 4691 aa = sprom->ant_available_a; 4692 else 4693 aa = sprom->ant_available_bg; 4694 4695 if ((aa < 1) || (aa > 15)) { 4696 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in" 4697 " srom (0x%x), using 3\n", unit, __func__, aa); 4698 aa = 3; 4699 } 4700 4701 /* reset the defaults if we have a single antenna */ 4702 if (aa == 1) { 4703 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0; 4704 wlc->stf->txant = ANT_TX_FORCE_0; 4705 } else if (aa == 2) { 4706 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1; 4707 wlc->stf->txant = ANT_TX_FORCE_1; 4708 } else { 4709 } 4710 4711 /* Compute Antenna Gain */ 4712 if (bandtype == BRCM_BAND_5G) 4713 wlc->band->antgain = sprom->antenna_gain.a1; 4714 else 4715 wlc->band->antgain = sprom->antenna_gain.a0; 4716 4717 return true; 4718 } 4719 4720 static void brcms_c_bss_default_init(struct brcms_c_info *wlc) 4721 { 4722 u16 chanspec; 4723 struct brcms_band *band; 4724 struct brcms_bss_info *bi = wlc->default_bss; 4725 4726 /* init default and target BSS with some sane initial values */ 4727 memset(bi, 0, sizeof(*bi)); 4728 bi->beacon_period = BEACON_INTERVAL_DEFAULT; 4729 4730 /* fill the default channel as the first valid channel 4731 * starting from the 2G channels 4732 */ 4733 chanspec = ch20mhz_chspec(1); 4734 wlc->home_chanspec = bi->chanspec = chanspec; 4735 4736 /* find the band of our default channel */ 4737 band = wlc->band; 4738 if (wlc->pub->_nbands > 1 && 4739 band->bandunit != chspec_bandunit(chanspec)) 4740 band = wlc->bandstate[OTHERBANDUNIT(wlc)]; 4741 4742 /* init bss rates to the band specific default rate set */ 4743 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype, 4744 band->bandtype, false, BRCMS_RATE_MASK_FULL, 4745 (bool) (wlc->pub->_n_enab & SUPPORT_11N), 4746 brcms_chspec_bw(chanspec), wlc->stf->txstreams); 4747 4748 if (wlc->pub->_n_enab & SUPPORT_11N) 4749 bi->flags |= BRCMS_BSS_HT; 4750 } 4751 4752 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap) 4753 { 4754 uint i; 4755 struct brcms_band *band; 4756 4757 for (i = 0; i < wlc->pub->_nbands; i++) { 4758 band = wlc->bandstate[i]; 4759 if (band->bandtype == BRCM_BAND_5G) { 4760 if ((bwcap == BRCMS_N_BW_40ALL) 4761 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G)) 4762 band->mimo_cap_40 = true; 4763 else 4764 band->mimo_cap_40 = false; 4765 } else { 4766 if (bwcap == BRCMS_N_BW_40ALL) 4767 band->mimo_cap_40 = true; 4768 else 4769 band->mimo_cap_40 = false; 4770 } 4771 } 4772 } 4773 4774 static void brcms_c_timers_deinit(struct brcms_c_info *wlc) 4775 { 4776 /* free timer state */ 4777 if (wlc->wdtimer) { 4778 brcms_free_timer(wlc->wdtimer); 4779 wlc->wdtimer = NULL; 4780 } 4781 if (wlc->radio_timer) { 4782 brcms_free_timer(wlc->radio_timer); 4783 wlc->radio_timer = NULL; 4784 } 4785 } 4786 4787 static void brcms_c_detach_module(struct brcms_c_info *wlc) 4788 { 4789 if (wlc->asi) { 4790 brcms_c_antsel_detach(wlc->asi); 4791 wlc->asi = NULL; 4792 } 4793 4794 if (wlc->ampdu) { 4795 brcms_c_ampdu_detach(wlc->ampdu); 4796 wlc->ampdu = NULL; 4797 } 4798 4799 brcms_c_stf_detach(wlc); 4800 } 4801 4802 /* 4803 * low level detach 4804 */ 4805 static void brcms_b_detach(struct brcms_c_info *wlc) 4806 { 4807 uint i; 4808 struct brcms_hw_band *band; 4809 struct brcms_hardware *wlc_hw = wlc->hw; 4810 4811 brcms_b_detach_dmapio(wlc_hw); 4812 4813 band = wlc_hw->band; 4814 for (i = 0; i < wlc_hw->_nbands; i++) { 4815 if (band->pi) { 4816 /* Detach this band's phy */ 4817 wlc_phy_detach(band->pi); 4818 band->pi = NULL; 4819 } 4820 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)]; 4821 } 4822 4823 /* Free shared phy state */ 4824 kfree(wlc_hw->phy_sh); 4825 4826 wlc_phy_shim_detach(wlc_hw->physhim); 4827 4828 if (wlc_hw->sih) { 4829 ai_detach(wlc_hw->sih); 4830 wlc_hw->sih = NULL; 4831 } 4832 } 4833 4834 /* 4835 * Return a count of the number of driver callbacks still pending. 4836 * 4837 * General policy is that brcms_c_detach can only dealloc/free software states. 4838 * It can NOT touch hardware registers since the d11core may be in reset and 4839 * clock may not be available. 4840 * One exception is sb register access, which is possible if crystal is turned 4841 * on after "down" state, driver should avoid software timer with the exception 4842 * of radio_monitor. 4843 */ 4844 uint brcms_c_detach(struct brcms_c_info *wlc) 4845 { 4846 uint callbacks; 4847 4848 if (wlc == NULL) 4849 return 0; 4850 4851 brcms_b_detach(wlc); 4852 4853 /* delete software timers */ 4854 callbacks = 0; 4855 if (!brcms_c_radio_monitor_stop(wlc)) 4856 callbacks++; 4857 4858 brcms_c_channel_mgr_detach(wlc->cmi); 4859 4860 brcms_c_timers_deinit(wlc); 4861 4862 brcms_c_detach_module(wlc); 4863 4864 brcms_c_detach_mfree(wlc); 4865 return callbacks; 4866 } 4867 4868 /* update state that depends on the current value of "ap" */ 4869 static void brcms_c_ap_upd(struct brcms_c_info *wlc) 4870 { 4871 /* STA-BSS; short capable */ 4872 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT; 4873 } 4874 4875 /* Initialize just the hardware when coming out of POR or S3/S5 system states */ 4876 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw) 4877 { 4878 if (wlc_hw->wlc->pub->hw_up) 4879 return; 4880 4881 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 4882 4883 /* 4884 * Enable pll and xtal, initialize the power control registers, 4885 * and force fastclock for the remainder of brcms_c_up(). 4886 */ 4887 brcms_b_xtal(wlc_hw, ON); 4888 ai_clkctl_init(wlc_hw->sih); 4889 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 4890 4891 /* 4892 * TODO: test suspend/resume 4893 * 4894 * AI chip doesn't restore bar0win2 on 4895 * hibernation/resume, need sw fixup 4896 */ 4897 4898 /* 4899 * Inform phy that a POR reset has occurred so 4900 * it does a complete phy init 4901 */ 4902 wlc_phy_por_inform(wlc_hw->band->pi); 4903 4904 wlc_hw->ucode_loaded = false; 4905 wlc_hw->wlc->pub->hw_up = true; 4906 4907 if ((wlc_hw->boardflags & BFL_FEM) 4908 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) { 4909 if (! 4910 (wlc_hw->boardrev >= 0x1250 4911 && (wlc_hw->boardflags & BFL_FEM_BT))) 4912 ai_epa_4313war(wlc_hw->sih); 4913 } 4914 } 4915 4916 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw) 4917 { 4918 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 4919 4920 /* 4921 * Enable pll and xtal, initialize the power control registers, 4922 * and force fastclock for the remainder of brcms_c_up(). 4923 */ 4924 brcms_b_xtal(wlc_hw, ON); 4925 ai_clkctl_init(wlc_hw->sih); 4926 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 4927 4928 /* 4929 * Configure pci/pcmcia here instead of in brcms_c_attach() 4930 * to allow mfg hotswap: down, hotswap (chip power cycle), up. 4931 */ 4932 bcma_host_pci_irq_ctl(wlc_hw->d11core->bus, wlc_hw->d11core, 4933 true); 4934 4935 /* 4936 * Need to read the hwradio status here to cover the case where the 4937 * system is loaded with the hw radio disabled. We do not want to 4938 * bring the driver up in this case. 4939 */ 4940 if (brcms_b_radio_read_hwdisabled(wlc_hw)) { 4941 /* put SB PCI in down state again */ 4942 bcma_host_pci_down(wlc_hw->d11core->bus); 4943 brcms_b_xtal(wlc_hw, OFF); 4944 return -ENOMEDIUM; 4945 } 4946 4947 bcma_host_pci_up(wlc_hw->d11core->bus); 4948 4949 /* reset the d11 core */ 4950 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 4951 4952 return 0; 4953 } 4954 4955 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw) 4956 { 4957 wlc_hw->up = true; 4958 wlc_phy_hw_state_upd(wlc_hw->band->pi, true); 4959 4960 /* FULLY enable dynamic power control and d11 core interrupt */ 4961 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC); 4962 brcms_intrson(wlc_hw->wlc->wl); 4963 return 0; 4964 } 4965 4966 /* 4967 * Write WME tunable parameters for retransmit/max rate 4968 * from wlc struct to ucode 4969 */ 4970 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc) 4971 { 4972 int ac; 4973 4974 /* Need clock to do this */ 4975 if (!wlc->clk) 4976 return; 4977 4978 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 4979 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac), 4980 wlc->wme_retries[ac]); 4981 } 4982 4983 /* make interface operational */ 4984 int brcms_c_up(struct brcms_c_info *wlc) 4985 { 4986 struct ieee80211_channel *ch; 4987 4988 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit); 4989 4990 /* HW is turned off so don't try to access it */ 4991 if (wlc->pub->hw_off || brcms_deviceremoved(wlc)) 4992 return -ENOMEDIUM; 4993 4994 if (!wlc->pub->hw_up) { 4995 brcms_b_hw_up(wlc->hw); 4996 wlc->pub->hw_up = true; 4997 } 4998 4999 if ((wlc->pub->boardflags & BFL_FEM) 5000 && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) { 5001 if (wlc->pub->boardrev >= 0x1250 5002 && (wlc->pub->boardflags & BFL_FEM_BT)) 5003 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL, 5004 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL); 5005 else 5006 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE, 5007 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL); 5008 } 5009 5010 /* 5011 * Need to read the hwradio status here to cover the case where the 5012 * system is loaded with the hw radio disabled. We do not want to bring 5013 * the driver up in this case. If radio is disabled, abort up, lower 5014 * power, start radio timer and return 0(for NDIS) don't call 5015 * radio_update to avoid looping brcms_c_up. 5016 * 5017 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only 5018 */ 5019 if (!wlc->pub->radio_disabled) { 5020 int status = brcms_b_up_prep(wlc->hw); 5021 if (status == -ENOMEDIUM) { 5022 if (!mboolisset 5023 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) { 5024 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 5025 mboolset(wlc->pub->radio_disabled, 5026 WL_RADIO_HW_DISABLE); 5027 if (bsscfg->type == BRCMS_TYPE_STATION || 5028 bsscfg->type == BRCMS_TYPE_ADHOC) 5029 brcms_err(wlc->hw->d11core, 5030 "wl%d: up: rfdisable -> " 5031 "bsscfg_disable()\n", 5032 wlc->pub->unit); 5033 } 5034 } 5035 } 5036 5037 if (wlc->pub->radio_disabled) { 5038 brcms_c_radio_monitor_start(wlc); 5039 return 0; 5040 } 5041 5042 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */ 5043 wlc->clk = true; 5044 5045 brcms_c_radio_monitor_stop(wlc); 5046 5047 /* Set EDCF hostflags */ 5048 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL); 5049 5050 brcms_init(wlc->wl); 5051 wlc->pub->up = true; 5052 5053 if (wlc->bandinit_pending) { 5054 ch = wlc->pub->ieee_hw->conf.chandef.chan; 5055 brcms_c_suspend_mac_and_wait(wlc); 5056 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value)); 5057 wlc->bandinit_pending = false; 5058 brcms_c_enable_mac(wlc); 5059 } 5060 5061 brcms_b_up_finish(wlc->hw); 5062 5063 /* Program the TX wme params with the current settings */ 5064 brcms_c_wme_retries_write(wlc); 5065 5066 /* start one second watchdog timer */ 5067 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true); 5068 wlc->WDarmed = true; 5069 5070 /* ensure antenna config is up to date */ 5071 brcms_c_stf_phy_txant_upd(wlc); 5072 /* ensure LDPC config is in sync */ 5073 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc); 5074 5075 return 0; 5076 } 5077 5078 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw) 5079 { 5080 bool dev_gone; 5081 uint callbacks = 0; 5082 5083 if (!wlc_hw->up) 5084 return callbacks; 5085 5086 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 5087 5088 /* disable interrupts */ 5089 if (dev_gone) 5090 wlc_hw->wlc->macintmask = 0; 5091 else { 5092 /* now disable interrupts */ 5093 brcms_intrsoff(wlc_hw->wlc->wl); 5094 5095 /* ensure we're running on the pll clock again */ 5096 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 5097 } 5098 /* down phy at the last of this stage */ 5099 callbacks += wlc_phy_down(wlc_hw->band->pi); 5100 5101 return callbacks; 5102 } 5103 5104 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw) 5105 { 5106 uint callbacks = 0; 5107 bool dev_gone; 5108 5109 if (!wlc_hw->up) 5110 return callbacks; 5111 5112 wlc_hw->up = false; 5113 wlc_phy_hw_state_upd(wlc_hw->band->pi, false); 5114 5115 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 5116 5117 if (dev_gone) { 5118 wlc_hw->sbclk = false; 5119 wlc_hw->clk = false; 5120 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 5121 5122 /* reclaim any posted packets */ 5123 brcms_c_flushqueues(wlc_hw->wlc); 5124 } else { 5125 5126 /* Reset and disable the core */ 5127 if (bcma_core_is_enabled(wlc_hw->d11core)) { 5128 if (bcma_read32(wlc_hw->d11core, 5129 D11REGOFFS(maccontrol)) & MCTL_EN_MAC) 5130 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 5131 callbacks += brcms_reset(wlc_hw->wlc->wl); 5132 brcms_c_coredisable(wlc_hw); 5133 } 5134 5135 /* turn off primary xtal and pll */ 5136 if (!wlc_hw->noreset) { 5137 bcma_host_pci_down(wlc_hw->d11core->bus); 5138 brcms_b_xtal(wlc_hw, OFF); 5139 } 5140 } 5141 5142 return callbacks; 5143 } 5144 5145 /* 5146 * Mark the interface nonoperational, stop the software mechanisms, 5147 * disable the hardware, free any transient buffer state. 5148 * Return a count of the number of driver callbacks still pending. 5149 */ 5150 uint brcms_c_down(struct brcms_c_info *wlc) 5151 { 5152 5153 uint callbacks = 0; 5154 int i; 5155 5156 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit); 5157 5158 /* check if we are already in the going down path */ 5159 if (wlc->going_down) { 5160 brcms_err(wlc->hw->d11core, 5161 "wl%d: %s: Driver going down so return\n", 5162 wlc->pub->unit, __func__); 5163 return 0; 5164 } 5165 if (!wlc->pub->up) 5166 return callbacks; 5167 5168 wlc->going_down = true; 5169 5170 callbacks += brcms_b_bmac_down_prep(wlc->hw); 5171 5172 brcms_deviceremoved(wlc); 5173 5174 /* Call any registered down handlers */ 5175 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5176 if (wlc->modulecb[i].down_fn) 5177 callbacks += 5178 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl); 5179 } 5180 5181 /* cancel the watchdog timer */ 5182 if (wlc->WDarmed) { 5183 if (!brcms_del_timer(wlc->wdtimer)) 5184 callbacks++; 5185 wlc->WDarmed = false; 5186 } 5187 5188 wlc->pub->up = false; 5189 5190 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL); 5191 5192 callbacks += brcms_b_down_finish(wlc->hw); 5193 5194 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */ 5195 wlc->clk = false; 5196 5197 wlc->going_down = false; 5198 return callbacks; 5199 } 5200 5201 /* Set the current gmode configuration */ 5202 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config) 5203 { 5204 int ret = 0; 5205 uint i; 5206 struct brcms_c_rateset rs; 5207 /* Default to 54g Auto */ 5208 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */ 5209 s8 shortslot = BRCMS_SHORTSLOT_AUTO; 5210 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */ 5211 struct brcms_band *band; 5212 5213 /* if N-support is enabled, allow Gmode set as long as requested 5214 * Gmode is not GMODE_LEGACY_B 5215 */ 5216 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B) 5217 return -ENOTSUPP; 5218 5219 /* verify that we are dealing with 2G band and grab the band pointer */ 5220 if (wlc->band->bandtype == BRCM_BAND_2G) 5221 band = wlc->band; 5222 else if ((wlc->pub->_nbands > 1) && 5223 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G)) 5224 band = wlc->bandstate[OTHERBANDUNIT(wlc)]; 5225 else 5226 return -EINVAL; 5227 5228 /* update configuration value */ 5229 if (config) 5230 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode); 5231 5232 /* Clear rateset override */ 5233 memset(&rs, 0, sizeof(rs)); 5234 5235 switch (gmode) { 5236 case GMODE_LEGACY_B: 5237 shortslot = BRCMS_SHORTSLOT_OFF; 5238 brcms_c_rateset_copy(&gphy_legacy_rates, &rs); 5239 5240 break; 5241 5242 case GMODE_LRS: 5243 break; 5244 5245 case GMODE_AUTO: 5246 /* Accept defaults */ 5247 break; 5248 5249 case GMODE_ONLY: 5250 ofdm_basic = true; 5251 break; 5252 5253 case GMODE_PERFORMANCE: 5254 shortslot = BRCMS_SHORTSLOT_ON; 5255 ofdm_basic = true; 5256 break; 5257 5258 default: 5259 /* Error */ 5260 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n", 5261 wlc->pub->unit, __func__, gmode); 5262 return -ENOTSUPP; 5263 } 5264 5265 band->gmode = gmode; 5266 5267 wlc->shortslot_override = shortslot; 5268 5269 /* Use the default 11g rateset */ 5270 if (!rs.count) 5271 brcms_c_rateset_copy(&cck_ofdm_rates, &rs); 5272 5273 if (ofdm_basic) { 5274 for (i = 0; i < rs.count; i++) { 5275 if (rs.rates[i] == BRCM_RATE_6M 5276 || rs.rates[i] == BRCM_RATE_12M 5277 || rs.rates[i] == BRCM_RATE_24M) 5278 rs.rates[i] |= BRCMS_RATE_FLAG; 5279 } 5280 } 5281 5282 /* Set default bss rateset */ 5283 wlc->default_bss->rateset.count = rs.count; 5284 memcpy(wlc->default_bss->rateset.rates, rs.rates, 5285 sizeof(wlc->default_bss->rateset.rates)); 5286 5287 return ret; 5288 } 5289 5290 int brcms_c_set_nmode(struct brcms_c_info *wlc) 5291 { 5292 uint i; 5293 s32 nmode = AUTO; 5294 5295 if (wlc->stf->txstreams == WL_11N_3x3) 5296 nmode = WL_11N_3x3; 5297 else 5298 nmode = WL_11N_2x2; 5299 5300 /* force GMODE_AUTO if NMODE is ON */ 5301 brcms_c_set_gmode(wlc, GMODE_AUTO, true); 5302 if (nmode == WL_11N_3x3) 5303 wlc->pub->_n_enab = SUPPORT_HT; 5304 else 5305 wlc->pub->_n_enab = SUPPORT_11N; 5306 wlc->default_bss->flags |= BRCMS_BSS_HT; 5307 /* add the mcs rates to the default and hw ratesets */ 5308 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset, 5309 wlc->stf->txstreams); 5310 for (i = 0; i < wlc->pub->_nbands; i++) 5311 memcpy(wlc->bandstate[i]->hw_rateset.mcs, 5312 wlc->default_bss->rateset.mcs, MCSSET_LEN); 5313 5314 return 0; 5315 } 5316 5317 static int 5318 brcms_c_set_internal_rateset(struct brcms_c_info *wlc, 5319 struct brcms_c_rateset *rs_arg) 5320 { 5321 struct brcms_c_rateset rs, new; 5322 uint bandunit; 5323 5324 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset)); 5325 5326 /* check for bad count value */ 5327 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES)) 5328 return -EINVAL; 5329 5330 /* try the current band */ 5331 bandunit = wlc->band->bandunit; 5332 memcpy(&new, &rs, sizeof(struct brcms_c_rateset)); 5333 if (brcms_c_rate_hwrs_filter_sort_validate 5334 (&new, &wlc->bandstate[bandunit]->hw_rateset, true, 5335 wlc->stf->txstreams)) 5336 goto good; 5337 5338 /* try the other band */ 5339 if (brcms_is_mband_unlocked(wlc)) { 5340 bandunit = OTHERBANDUNIT(wlc); 5341 memcpy(&new, &rs, sizeof(struct brcms_c_rateset)); 5342 if (brcms_c_rate_hwrs_filter_sort_validate(&new, 5343 &wlc-> 5344 bandstate[bandunit]-> 5345 hw_rateset, true, 5346 wlc->stf->txstreams)) 5347 goto good; 5348 } 5349 5350 return -EBADE; 5351 5352 good: 5353 /* apply new rateset */ 5354 memcpy(&wlc->default_bss->rateset, &new, 5355 sizeof(struct brcms_c_rateset)); 5356 memcpy(&wlc->bandstate[bandunit]->defrateset, &new, 5357 sizeof(struct brcms_c_rateset)); 5358 return 0; 5359 } 5360 5361 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc) 5362 { 5363 wlc_phy_ofdm_rateset_war(wlc->band->pi, false); 5364 } 5365 5366 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel) 5367 { 5368 u16 chspec = ch20mhz_chspec(channel); 5369 5370 if (channel > MAXCHANNEL) 5371 return -EINVAL; 5372 5373 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec)) 5374 return -EINVAL; 5375 5376 5377 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) { 5378 if (wlc->band->bandunit != chspec_bandunit(chspec)) 5379 wlc->bandinit_pending = true; 5380 else 5381 wlc->bandinit_pending = false; 5382 } 5383 5384 wlc->default_bss->chanspec = chspec; 5385 /* brcms_c_BSSinit() will sanitize the rateset before 5386 * using it.. */ 5387 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) { 5388 brcms_c_set_home_chanspec(wlc, chspec); 5389 brcms_c_suspend_mac_and_wait(wlc); 5390 brcms_c_set_chanspec(wlc, chspec); 5391 brcms_c_enable_mac(wlc); 5392 } 5393 return 0; 5394 } 5395 5396 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl) 5397 { 5398 int ac; 5399 5400 if (srl < 1 || srl > RETRY_SHORT_MAX || 5401 lrl < 1 || lrl > RETRY_SHORT_MAX) 5402 return -EINVAL; 5403 5404 wlc->SRL = srl; 5405 wlc->LRL = lrl; 5406 5407 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); 5408 5409 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) { 5410 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5411 EDCF_SHORT, wlc->SRL); 5412 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5413 EDCF_LONG, wlc->LRL); 5414 } 5415 brcms_c_wme_retries_write(wlc); 5416 5417 return 0; 5418 } 5419 5420 void brcms_c_get_current_rateset(struct brcms_c_info *wlc, 5421 struct brcm_rateset *currs) 5422 { 5423 struct brcms_c_rateset *rs; 5424 5425 if (wlc->pub->associated) 5426 rs = &wlc->bsscfg->current_bss->rateset; 5427 else 5428 rs = &wlc->default_bss->rateset; 5429 5430 /* Copy only legacy rateset section */ 5431 currs->count = rs->count; 5432 memcpy(&currs->rates, &rs->rates, rs->count); 5433 } 5434 5435 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs) 5436 { 5437 struct brcms_c_rateset internal_rs; 5438 int bcmerror; 5439 5440 if (rs->count > BRCMS_NUMRATES) 5441 return -ENOBUFS; 5442 5443 memset(&internal_rs, 0, sizeof(internal_rs)); 5444 5445 /* Copy only legacy rateset section */ 5446 internal_rs.count = rs->count; 5447 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count); 5448 5449 /* merge rateset coming in with the current mcsset */ 5450 if (wlc->pub->_n_enab & SUPPORT_11N) { 5451 struct brcms_bss_info *mcsset_bss; 5452 if (wlc->pub->associated) 5453 mcsset_bss = wlc->bsscfg->current_bss; 5454 else 5455 mcsset_bss = wlc->default_bss; 5456 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0], 5457 MCSSET_LEN); 5458 } 5459 5460 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs); 5461 if (!bcmerror) 5462 brcms_c_ofdm_rateset_war(wlc); 5463 5464 return bcmerror; 5465 } 5466 5467 static void brcms_c_time_lock(struct brcms_c_info *wlc) 5468 { 5469 bcma_set32(wlc->hw->d11core, D11REGOFFS(maccontrol), MCTL_TBTTHOLD); 5470 /* Commit the write */ 5471 bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol)); 5472 } 5473 5474 static void brcms_c_time_unlock(struct brcms_c_info *wlc) 5475 { 5476 bcma_mask32(wlc->hw->d11core, D11REGOFFS(maccontrol), ~MCTL_TBTTHOLD); 5477 /* Commit the write */ 5478 bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol)); 5479 } 5480 5481 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period) 5482 { 5483 u32 bcnint_us; 5484 5485 if (period == 0) 5486 return -EINVAL; 5487 5488 wlc->default_bss->beacon_period = period; 5489 5490 bcnint_us = period << 10; 5491 brcms_c_time_lock(wlc); 5492 bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfprep), 5493 (bcnint_us << CFPREP_CBI_SHIFT)); 5494 bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfpstart), bcnint_us); 5495 brcms_c_time_unlock(wlc); 5496 5497 return 0; 5498 } 5499 5500 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx) 5501 { 5502 return wlc->band->phytype; 5503 } 5504 5505 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override) 5506 { 5507 wlc->shortslot_override = sslot_override; 5508 5509 /* 5510 * shortslot is an 11g feature, so no more work if we are 5511 * currently on the 5G band 5512 */ 5513 if (wlc->band->bandtype == BRCM_BAND_5G) 5514 return; 5515 5516 if (wlc->pub->up && wlc->pub->associated) { 5517 /* let watchdog or beacon processing update shortslot */ 5518 } else if (wlc->pub->up) { 5519 /* unassociated shortslot is off */ 5520 brcms_c_switch_shortslot(wlc, false); 5521 } else { 5522 /* driver is down, so just update the brcms_c_info 5523 * value */ 5524 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO) 5525 wlc->shortslot = false; 5526 else 5527 wlc->shortslot = 5528 (wlc->shortslot_override == 5529 BRCMS_SHORTSLOT_ON); 5530 } 5531 } 5532 5533 /* 5534 * register watchdog and down handlers. 5535 */ 5536 int brcms_c_module_register(struct brcms_pub *pub, 5537 const char *name, struct brcms_info *hdl, 5538 int (*d_fn)(void *handle)) 5539 { 5540 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc; 5541 int i; 5542 5543 /* find an empty entry and just add, no duplication check! */ 5544 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5545 if (wlc->modulecb[i].name[0] == '\0') { 5546 strscpy(wlc->modulecb[i].name, name, 5547 sizeof(wlc->modulecb[i].name)); 5548 wlc->modulecb[i].hdl = hdl; 5549 wlc->modulecb[i].down_fn = d_fn; 5550 return 0; 5551 } 5552 } 5553 5554 return -ENOSR; 5555 } 5556 5557 /* unregister module callbacks */ 5558 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name, 5559 struct brcms_info *hdl) 5560 { 5561 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc; 5562 int i; 5563 5564 if (wlc == NULL) 5565 return -ENODATA; 5566 5567 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5568 if (!strcmp(wlc->modulecb[i].name, name) && 5569 (wlc->modulecb[i].hdl == hdl)) { 5570 memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i])); 5571 return 0; 5572 } 5573 } 5574 5575 /* table not found! */ 5576 return -ENODATA; 5577 } 5578 5579 static bool brcms_c_chipmatch_pci(struct bcma_device *core) 5580 { 5581 struct pci_dev *pcidev = core->bus->host_pci; 5582 u16 vendor = pcidev->vendor; 5583 u16 device = pcidev->device; 5584 5585 if (vendor != PCI_VENDOR_ID_BROADCOM) { 5586 pr_err("unknown vendor id %04x\n", vendor); 5587 return false; 5588 } 5589 5590 if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID) 5591 return true; 5592 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID)) 5593 return true; 5594 if (device == BCM4313_D11N2G_ID || device == BCM4313_CHIP_ID) 5595 return true; 5596 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID)) 5597 return true; 5598 5599 pr_err("unknown device id %04x\n", device); 5600 return false; 5601 } 5602 5603 static bool brcms_c_chipmatch_soc(struct bcma_device *core) 5604 { 5605 struct bcma_chipinfo *chipinfo = &core->bus->chipinfo; 5606 5607 if (chipinfo->id == BCMA_CHIP_ID_BCM4716) 5608 return true; 5609 5610 pr_err("unknown chip id %04x\n", chipinfo->id); 5611 return false; 5612 } 5613 5614 bool brcms_c_chipmatch(struct bcma_device *core) 5615 { 5616 switch (core->bus->hosttype) { 5617 case BCMA_HOSTTYPE_PCI: 5618 return brcms_c_chipmatch_pci(core); 5619 case BCMA_HOSTTYPE_SOC: 5620 return brcms_c_chipmatch_soc(core); 5621 default: 5622 pr_err("unknown host type: %i\n", core->bus->hosttype); 5623 return false; 5624 } 5625 } 5626 5627 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate) 5628 { 5629 u16 table_ptr; 5630 u8 phy_rate, index; 5631 5632 /* get the phy specific rate encoding for the PLCP SIGNAL field */ 5633 if (is_ofdm_rate(rate)) 5634 table_ptr = M_RT_DIRMAP_A; 5635 else 5636 table_ptr = M_RT_DIRMAP_B; 5637 5638 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is 5639 * the index into the rate table. 5640 */ 5641 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; 5642 index = phy_rate & 0xf; 5643 5644 /* Find the SHM pointer to the rate table entry by looking in the 5645 * Direct-map Table 5646 */ 5647 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2)); 5648 } 5649 5650 /* 5651 * bcmc_fid_generate: 5652 * Generate frame ID for a BCMC packet. The frag field is not used 5653 * for MC frames so is used as part of the sequence number. 5654 */ 5655 static inline u16 5656 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg, 5657 struct d11txh *txh) 5658 { 5659 u16 frameid; 5660 5661 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK | 5662 TXFID_QUEUE_MASK); 5663 frameid |= 5664 (((wlc-> 5665 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) | 5666 TX_BCMC_FIFO; 5667 5668 return frameid; 5669 } 5670 5671 static uint 5672 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec, 5673 u8 preamble_type) 5674 { 5675 uint dur = 0; 5676 5677 /* 5678 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that 5679 * is less than or equal to the rate of the immediately previous 5680 * frame in the FES 5681 */ 5682 rspec = brcms_basic_rate(wlc, rspec); 5683 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */ 5684 dur = 5685 brcms_c_calc_frame_time(wlc, rspec, preamble_type, 5686 (DOT11_ACK_LEN + FCS_LEN)); 5687 return dur; 5688 } 5689 5690 static uint 5691 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec, 5692 u8 preamble_type) 5693 { 5694 return brcms_c_calc_ack_time(wlc, rspec, preamble_type); 5695 } 5696 5697 static uint 5698 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec, 5699 u8 preamble_type) 5700 { 5701 /* 5702 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that 5703 * is less than or equal to the rate of the immediately previous 5704 * frame in the FES 5705 */ 5706 rspec = brcms_basic_rate(wlc, rspec); 5707 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */ 5708 return brcms_c_calc_frame_time(wlc, rspec, preamble_type, 5709 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN + 5710 FCS_LEN)); 5711 } 5712 5713 /* brcms_c_compute_frame_dur() 5714 * 5715 * Calculate the 802.11 MAC header DUR field for MPDU 5716 * DUR for a single frame = 1 SIFS + 1 ACK 5717 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time 5718 * 5719 * rate MPDU rate in unit of 500kbps 5720 * next_frag_len next MPDU length in bytes 5721 * preamble_type use short/GF or long/MM PLCP header 5722 */ 5723 static u16 5724 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate, 5725 u8 preamble_type, uint next_frag_len) 5726 { 5727 u16 dur, sifs; 5728 5729 sifs = get_sifs(wlc->band); 5730 5731 dur = sifs; 5732 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type); 5733 5734 if (next_frag_len) { 5735 /* Double the current DUR to get 2 SIFS + 2 ACKs */ 5736 dur *= 2; 5737 /* add another SIFS and the frag time */ 5738 dur += sifs; 5739 dur += 5740 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type, 5741 next_frag_len); 5742 } 5743 return dur; 5744 } 5745 5746 /* The opposite of brcms_c_calc_frame_time */ 5747 static uint 5748 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec, 5749 u8 preamble_type, uint dur) 5750 { 5751 uint nsyms, mac_len, Ndps, kNdps; 5752 uint rate = rspec2rate(ratespec); 5753 5754 if (is_mcs_rate(ratespec)) { 5755 uint mcs = ratespec & RSPEC_RATE_MASK; 5756 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); 5757 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); 5758 /* payload calculation matches that of regular ofdm */ 5759 if (wlc->band->bandtype == BRCM_BAND_2G) 5760 dur -= DOT11_OFDM_SIGNAL_EXTENSION; 5761 /* kNdbps = kbps * 4 */ 5762 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 5763 rspec_issgi(ratespec)) * 4; 5764 nsyms = dur / APHY_SYMBOL_TIME; 5765 mac_len = 5766 ((nsyms * kNdps) - 5767 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000; 5768 } else if (is_ofdm_rate(ratespec)) { 5769 dur -= APHY_PREAMBLE_TIME; 5770 dur -= APHY_SIGNAL_TIME; 5771 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ 5772 Ndps = rate * 2; 5773 nsyms = dur / APHY_SYMBOL_TIME; 5774 mac_len = 5775 ((nsyms * Ndps) - 5776 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8; 5777 } else { 5778 if (preamble_type & BRCMS_SHORT_PREAMBLE) 5779 dur -= BPHY_PLCP_SHORT_TIME; 5780 else 5781 dur -= BPHY_PLCP_TIME; 5782 mac_len = dur * rate; 5783 /* divide out factor of 2 in rate (1/2 mbps) */ 5784 mac_len = mac_len / 8 / 2; 5785 } 5786 return mac_len; 5787 } 5788 5789 /* 5790 * Return true if the specified rate is supported by the specified band. 5791 * BRCM_BAND_AUTO indicates the current band. 5792 */ 5793 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band, 5794 bool verbose) 5795 { 5796 struct brcms_c_rateset *hw_rateset; 5797 uint i; 5798 5799 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype)) 5800 hw_rateset = &wlc->band->hw_rateset; 5801 else if (wlc->pub->_nbands > 1) 5802 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset; 5803 else 5804 /* other band specified and we are a single band device */ 5805 return false; 5806 5807 /* check if this is a mimo rate */ 5808 if (is_mcs_rate(rspec)) { 5809 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE) 5810 goto error; 5811 5812 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK)); 5813 } 5814 5815 for (i = 0; i < hw_rateset->count; i++) 5816 if (hw_rateset->rates[i] == rspec2rate(rspec)) 5817 return true; 5818 error: 5819 if (verbose) 5820 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x " 5821 "not in hw_rateset\n", wlc->pub->unit, rspec); 5822 5823 return false; 5824 } 5825 5826 static u32 5827 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band, 5828 u32 int_val) 5829 { 5830 struct bcma_device *core = wlc->hw->d11core; 5831 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT; 5832 u8 rate = int_val & NRATE_RATE_MASK; 5833 u32 rspec; 5834 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE); 5835 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT); 5836 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY) 5837 == NRATE_OVERRIDE_MCS_ONLY); 5838 5839 if (!ismcs) 5840 return (u32) rate; 5841 5842 /* validate the combination of rate/mcs/stf is allowed */ 5843 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) { 5844 /* mcs only allowed when nmode */ 5845 if (stf > PHY_TXC1_MODE_SDM) { 5846 brcms_err(core, "wl%d: %s: Invalid stf\n", 5847 wlc->pub->unit, __func__); 5848 goto done; 5849 } 5850 5851 /* mcs 32 is a special case, DUP mode 40 only */ 5852 if (rate == 32) { 5853 if (!CHSPEC_IS40(wlc->home_chanspec) || 5854 ((stf != PHY_TXC1_MODE_SISO) 5855 && (stf != PHY_TXC1_MODE_CDD))) { 5856 brcms_err(core, "wl%d: %s: Invalid mcs 32\n", 5857 wlc->pub->unit, __func__); 5858 goto done; 5859 } 5860 /* mcs > 7 must use stf SDM */ 5861 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) { 5862 /* mcs > 7 must use stf SDM */ 5863 if (stf != PHY_TXC1_MODE_SDM) { 5864 brcms_dbg_mac80211(core, "wl%d: enabling " 5865 "SDM mode for mcs %d\n", 5866 wlc->pub->unit, rate); 5867 stf = PHY_TXC1_MODE_SDM; 5868 } 5869 } else { 5870 /* 5871 * MCS 0-7 may use SISO, CDD, and for 5872 * phy_rev >= 3 STBC 5873 */ 5874 if ((stf > PHY_TXC1_MODE_STBC) || 5875 (!BRCMS_STBC_CAP_PHY(wlc) 5876 && (stf == PHY_TXC1_MODE_STBC))) { 5877 brcms_err(core, "wl%d: %s: Invalid STBC\n", 5878 wlc->pub->unit, __func__); 5879 goto done; 5880 } 5881 } 5882 } else if (is_ofdm_rate(rate)) { 5883 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) { 5884 brcms_err(core, "wl%d: %s: Invalid OFDM\n", 5885 wlc->pub->unit, __func__); 5886 goto done; 5887 } 5888 } else if (is_cck_rate(rate)) { 5889 if ((cur_band->bandtype != BRCM_BAND_2G) 5890 || (stf != PHY_TXC1_MODE_SISO)) { 5891 brcms_err(core, "wl%d: %s: Invalid CCK\n", 5892 wlc->pub->unit, __func__); 5893 goto done; 5894 } 5895 } else { 5896 brcms_err(core, "wl%d: %s: Unknown rate type\n", 5897 wlc->pub->unit, __func__); 5898 goto done; 5899 } 5900 /* make sure multiple antennae are available for non-siso rates */ 5901 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) { 5902 brcms_err(core, "wl%d: %s: SISO antenna but !SISO " 5903 "request\n", wlc->pub->unit, __func__); 5904 goto done; 5905 } 5906 5907 rspec = rate; 5908 if (ismcs) { 5909 rspec |= RSPEC_MIMORATE; 5910 /* For STBC populate the STC field of the ratespec */ 5911 if (stf == PHY_TXC1_MODE_STBC) { 5912 u8 stc; 5913 stc = 1; /* Nss for single stream is always 1 */ 5914 rspec |= (stc << RSPEC_STC_SHIFT); 5915 } 5916 } 5917 5918 rspec |= (stf << RSPEC_STF_SHIFT); 5919 5920 if (override_mcs_only) 5921 rspec |= RSPEC_OVERRIDE_MCS_ONLY; 5922 5923 if (issgi) 5924 rspec |= RSPEC_SHORT_GI; 5925 5926 if ((rate != 0) 5927 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true)) 5928 return rate; 5929 5930 return rspec; 5931 done: 5932 return rate; 5933 } 5934 5935 /* 5936 * Compute PLCP, but only requires actual rate and length of pkt. 5937 * Rate is given in the driver standard multiple of 500 kbps. 5938 * le is set for 11 Mbps rate if necessary. 5939 * Broken out for PRQ. 5940 */ 5941 5942 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500, 5943 uint length, u8 *plcp) 5944 { 5945 u16 usec = 0; 5946 u8 le = 0; 5947 5948 switch (rate_500) { 5949 case BRCM_RATE_1M: 5950 usec = length << 3; 5951 break; 5952 case BRCM_RATE_2M: 5953 usec = length << 2; 5954 break; 5955 case BRCM_RATE_5M5: 5956 usec = (length << 4) / 11; 5957 if ((length << 4) - (usec * 11) > 0) 5958 usec++; 5959 break; 5960 case BRCM_RATE_11M: 5961 usec = (length << 3) / 11; 5962 if ((length << 3) - (usec * 11) > 0) { 5963 usec++; 5964 if ((usec * 11) - (length << 3) >= 8) 5965 le = D11B_PLCP_SIGNAL_LE; 5966 } 5967 break; 5968 5969 default: 5970 brcms_err(wlc->hw->d11core, 5971 "brcms_c_cck_plcp_set: unsupported rate %d\n", 5972 rate_500); 5973 rate_500 = BRCM_RATE_1M; 5974 usec = length << 3; 5975 break; 5976 } 5977 /* PLCP signal byte */ 5978 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */ 5979 /* PLCP service byte */ 5980 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED); 5981 /* PLCP length u16, little endian */ 5982 plcp[2] = usec & 0xff; 5983 plcp[3] = (usec >> 8) & 0xff; 5984 /* PLCP CRC16 */ 5985 plcp[4] = 0; 5986 plcp[5] = 0; 5987 } 5988 5989 /* Rate: 802.11 rate code, length: PSDU length in octets */ 5990 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp) 5991 { 5992 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK); 5993 plcp[0] = mcs; 5994 if (rspec_is40mhz(rspec) || (mcs == 32)) 5995 plcp[0] |= MIMO_PLCP_40MHZ; 5996 BRCMS_SET_MIMO_PLCP_LEN(plcp, length); 5997 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */ 5998 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */ 5999 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */ 6000 plcp[5] = 0; 6001 } 6002 6003 /* Rate: 802.11 rate code, length: PSDU length in octets */ 6004 static void 6005 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp) 6006 { 6007 u8 rate_signal; 6008 u32 tmp = 0; 6009 int rate = rspec2rate(rspec); 6010 6011 /* 6012 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb 6013 * transmitted first 6014 */ 6015 rate_signal = rate_info[rate] & BRCMS_RATE_MASK; 6016 memset(plcp, 0, D11_PHY_HDR_LEN); 6017 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal); 6018 6019 tmp = (length & 0xfff) << 5; 6020 plcp[2] |= (tmp >> 16) & 0xff; 6021 plcp[1] |= (tmp >> 8) & 0xff; 6022 plcp[0] |= tmp & 0xff; 6023 } 6024 6025 /* Rate: 802.11 rate code, length: PSDU length in octets */ 6026 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec, 6027 uint length, u8 *plcp) 6028 { 6029 int rate = rspec2rate(rspec); 6030 6031 brcms_c_cck_plcp_set(wlc, rate, length, plcp); 6032 } 6033 6034 static void 6035 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec, 6036 uint length, u8 *plcp) 6037 { 6038 if (is_mcs_rate(rspec)) 6039 brcms_c_compute_mimo_plcp(rspec, length, plcp); 6040 else if (is_ofdm_rate(rspec)) 6041 brcms_c_compute_ofdm_plcp(rspec, length, plcp); 6042 else 6043 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp); 6044 } 6045 6046 /* brcms_c_compute_rtscts_dur() 6047 * 6048 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame 6049 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK 6050 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK 6051 * 6052 * cts cts-to-self or rts/cts 6053 * rts_rate rts or cts rate in unit of 500kbps 6054 * rate next MPDU rate in unit of 500kbps 6055 * frame_len next MPDU frame length in bytes 6056 */ 6057 u16 6058 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only, 6059 u32 rts_rate, 6060 u32 frame_rate, u8 rts_preamble_type, 6061 u8 frame_preamble_type, uint frame_len, bool ba) 6062 { 6063 u16 dur, sifs; 6064 6065 sifs = get_sifs(wlc->band); 6066 6067 if (!cts_only) { 6068 /* RTS/CTS */ 6069 dur = 3 * sifs; 6070 dur += 6071 (u16) brcms_c_calc_cts_time(wlc, rts_rate, 6072 rts_preamble_type); 6073 } else { 6074 /* CTS-TO-SELF */ 6075 dur = 2 * sifs; 6076 } 6077 6078 dur += 6079 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type, 6080 frame_len); 6081 if (ba) 6082 dur += 6083 (u16) brcms_c_calc_ba_time(wlc, frame_rate, 6084 BRCMS_SHORT_PREAMBLE); 6085 else 6086 dur += 6087 (u16) brcms_c_calc_ack_time(wlc, frame_rate, 6088 frame_preamble_type); 6089 return dur; 6090 } 6091 6092 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec) 6093 { 6094 u16 phyctl1 = 0; 6095 u16 bw; 6096 6097 if (BRCMS_ISLCNPHY(wlc->band)) { 6098 bw = PHY_TXC1_BW_20MHZ; 6099 } else { 6100 bw = rspec_get_bw(rspec); 6101 /* 10Mhz is not supported yet */ 6102 if (bw < PHY_TXC1_BW_20MHZ) { 6103 brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is " 6104 "not supported yet, set to 20L\n", bw); 6105 bw = PHY_TXC1_BW_20MHZ; 6106 } 6107 } 6108 6109 if (is_mcs_rate(rspec)) { 6110 uint mcs = rspec & RSPEC_RATE_MASK; 6111 6112 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */ 6113 phyctl1 = rspec_phytxbyte2(rspec); 6114 /* set the upper byte of phyctl1 */ 6115 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8); 6116 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band) 6117 && !BRCMS_ISSSLPNPHY(wlc->band)) { 6118 /* 6119 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK 6120 * Data Rate. Eventually MIMOPHY would also be converted to 6121 * this format 6122 */ 6123 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */ 6124 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT)); 6125 } else { /* legacy OFDM/CCK */ 6126 s16 phycfg; 6127 /* get the phyctl byte from rate phycfg table */ 6128 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec)); 6129 if (phycfg == -1) { 6130 brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong " 6131 "legacy OFDM/CCK rate\n"); 6132 phycfg = 0; 6133 } 6134 /* set the upper byte of phyctl1 */ 6135 phyctl1 = 6136 (bw | (phycfg << 8) | 6137 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT)); 6138 } 6139 return phyctl1; 6140 } 6141 6142 /* 6143 * Add struct d11txh, struct cck_phy_hdr. 6144 * 6145 * 'p' data must start with 802.11 MAC header 6146 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet 6147 * 6148 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes) 6149 * 6150 */ 6151 static u16 6152 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw, 6153 struct sk_buff *p, struct scb *scb, uint frag, 6154 uint nfrags, uint queue, uint next_frag_len) 6155 { 6156 struct ieee80211_hdr *h; 6157 struct d11txh *txh; 6158 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN]; 6159 int len, phylen, rts_phylen; 6160 u16 mch, phyctl, xfts, mainrates; 6161 u16 seq = 0, mcl = 0, status = 0, frameid = 0; 6162 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M }; 6163 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M }; 6164 bool use_rts = false; 6165 bool use_cts = false; 6166 bool use_rifs = false; 6167 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE }; 6168 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE }; 6169 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN]; 6170 struct ieee80211_rts *rts = NULL; 6171 bool qos; 6172 uint ac; 6173 bool hwtkmic = false; 6174 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; 6175 #define ANTCFG_NONE 0xFF 6176 u8 antcfg = ANTCFG_NONE; 6177 u8 fbantcfg = ANTCFG_NONE; 6178 uint phyctl1_stf = 0; 6179 u16 durid = 0; 6180 struct ieee80211_tx_rate *txrate[2]; 6181 int k; 6182 struct ieee80211_tx_info *tx_info; 6183 bool is_mcs; 6184 u16 mimo_txbw; 6185 u8 mimo_preamble_type; 6186 6187 /* locate 802.11 MAC header */ 6188 h = (struct ieee80211_hdr *)(p->data); 6189 qos = ieee80211_is_data_qos(h->frame_control); 6190 6191 /* compute length of frame in bytes for use in PLCP computations */ 6192 len = p->len; 6193 phylen = len + FCS_LEN; 6194 6195 /* Get tx_info */ 6196 tx_info = IEEE80211_SKB_CB(p); 6197 6198 /* add PLCP */ 6199 plcp = skb_push(p, D11_PHY_HDR_LEN); 6200 6201 /* add Broadcom tx descriptor header */ 6202 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN); 6203 memset(txh, 0, D11_TXH_LEN); 6204 6205 /* setup frameid */ 6206 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 6207 /* non-AP STA should never use BCMC queue */ 6208 if (queue == TX_BCMC_FIFO) { 6209 brcms_err(wlc->hw->d11core, 6210 "wl%d: %s: ASSERT queue == TX_BCMC!\n", 6211 wlc->pub->unit, __func__); 6212 frameid = bcmc_fid_generate(wlc, NULL, txh); 6213 } else { 6214 /* Increment the counter for first fragment */ 6215 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 6216 scb->seqnum[p->priority]++; 6217 6218 /* extract fragment number from frame first */ 6219 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK; 6220 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT); 6221 h->seq_ctrl = cpu_to_le16(seq); 6222 6223 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) | 6224 (queue & TXFID_QUEUE_MASK); 6225 } 6226 } 6227 frameid |= queue & TXFID_QUEUE_MASK; 6228 6229 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */ 6230 if (ieee80211_is_beacon(h->frame_control)) 6231 mcl |= TXC_IGNOREPMQ; 6232 6233 txrate[0] = tx_info->control.rates; 6234 txrate[1] = txrate[0] + 1; 6235 6236 /* 6237 * if rate control algorithm didn't give us a fallback 6238 * rate, use the primary rate 6239 */ 6240 if (txrate[1]->idx < 0) 6241 txrate[1] = txrate[0]; 6242 6243 for (k = 0; k < hw->max_rates; k++) { 6244 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false; 6245 if (!is_mcs) { 6246 if ((txrate[k]->idx >= 0) 6247 && (txrate[k]->idx < 6248 hw->wiphy->bands[tx_info->band]->n_bitrates)) { 6249 rspec[k] = 6250 hw->wiphy->bands[tx_info->band]-> 6251 bitrates[txrate[k]->idx].hw_value; 6252 } else { 6253 rspec[k] = BRCM_RATE_1M; 6254 } 6255 } else { 6256 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band, 6257 NRATE_MCS_INUSE | txrate[k]->idx); 6258 } 6259 6260 /* 6261 * Currently only support same setting for primary and 6262 * fallback rates. Unify flags for each rate into a 6263 * single value for the frame 6264 */ 6265 use_rts |= 6266 txrate[k]-> 6267 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false; 6268 use_cts |= 6269 txrate[k]-> 6270 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false; 6271 6272 6273 /* 6274 * (1) RATE: 6275 * determine and validate primary rate 6276 * and fallback rates 6277 */ 6278 if (!rspec_active(rspec[k])) { 6279 rspec[k] = BRCM_RATE_1M; 6280 } else { 6281 if (!is_multicast_ether_addr(h->addr1)) { 6282 /* set tx antenna config */ 6283 brcms_c_antsel_antcfg_get(wlc->asi, false, 6284 false, 0, 0, &antcfg, &fbantcfg); 6285 } 6286 } 6287 } 6288 6289 phyctl1_stf = wlc->stf->ss_opmode; 6290 6291 if (wlc->pub->_n_enab & SUPPORT_11N) { 6292 for (k = 0; k < hw->max_rates; k++) { 6293 /* 6294 * apply siso/cdd to single stream mcs's or ofdm 6295 * if rspec is auto selected 6296 */ 6297 if (((is_mcs_rate(rspec[k]) && 6298 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) || 6299 is_ofdm_rate(rspec[k])) 6300 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY) 6301 || !(rspec[k] & RSPEC_OVERRIDE))) { 6302 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK); 6303 6304 /* For SISO MCS use STBC if possible */ 6305 if (is_mcs_rate(rspec[k]) 6306 && BRCMS_STF_SS_STBC_TX(wlc, scb)) { 6307 u8 stc; 6308 6309 /* Nss for single stream is always 1 */ 6310 stc = 1; 6311 rspec[k] |= (PHY_TXC1_MODE_STBC << 6312 RSPEC_STF_SHIFT) | 6313 (stc << RSPEC_STC_SHIFT); 6314 } else 6315 rspec[k] |= 6316 (phyctl1_stf << RSPEC_STF_SHIFT); 6317 } 6318 6319 /* 6320 * Is the phy configured to use 40MHZ frames? If 6321 * so then pick the desired txbw 6322 */ 6323 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) { 6324 /* default txbw is 20in40 SB */ 6325 mimo_ctlchbw = mimo_txbw = 6326 CHSPEC_SB_UPPER(wlc_phy_chanspec_get( 6327 wlc->band->pi)) 6328 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ; 6329 6330 if (is_mcs_rate(rspec[k])) { 6331 /* mcs 32 must be 40b/w DUP */ 6332 if ((rspec[k] & RSPEC_RATE_MASK) 6333 == 32) { 6334 mimo_txbw = 6335 PHY_TXC1_BW_40MHZ_DUP; 6336 /* use override */ 6337 } else if (wlc->mimo_40txbw != AUTO) 6338 mimo_txbw = wlc->mimo_40txbw; 6339 /* else check if dst is using 40 Mhz */ 6340 else if (scb->flags & SCB_IS40) 6341 mimo_txbw = PHY_TXC1_BW_40MHZ; 6342 } else if (is_ofdm_rate(rspec[k])) { 6343 if (wlc->ofdm_40txbw != AUTO) 6344 mimo_txbw = wlc->ofdm_40txbw; 6345 } else if (wlc->cck_40txbw != AUTO) { 6346 mimo_txbw = wlc->cck_40txbw; 6347 } 6348 } else { 6349 /* 6350 * mcs32 is 40 b/w only. 6351 * This is possible for probe packets on 6352 * a STA during SCAN 6353 */ 6354 if ((rspec[k] & RSPEC_RATE_MASK) == 32) 6355 /* mcs 0 */ 6356 rspec[k] = RSPEC_MIMORATE; 6357 6358 mimo_txbw = PHY_TXC1_BW_20MHZ; 6359 } 6360 6361 /* Set channel width */ 6362 rspec[k] &= ~RSPEC_BW_MASK; 6363 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k]))) 6364 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT); 6365 else 6366 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT); 6367 6368 /* Disable short GI, not supported yet */ 6369 rspec[k] &= ~RSPEC_SHORT_GI; 6370 6371 mimo_preamble_type = BRCMS_MM_PREAMBLE; 6372 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD) 6373 mimo_preamble_type = BRCMS_GF_PREAMBLE; 6374 6375 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS) 6376 && (!is_mcs_rate(rspec[k]))) { 6377 brcms_warn(wlc->hw->d11core, 6378 "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n", 6379 wlc->pub->unit, __func__); 6380 } 6381 6382 if (is_mcs_rate(rspec[k])) { 6383 preamble_type[k] = mimo_preamble_type; 6384 6385 /* 6386 * if SGI is selected, then forced mm 6387 * for single stream 6388 */ 6389 if ((rspec[k] & RSPEC_SHORT_GI) 6390 && is_single_stream(rspec[k] & 6391 RSPEC_RATE_MASK)) 6392 preamble_type[k] = BRCMS_MM_PREAMBLE; 6393 } 6394 6395 /* should be better conditionalized */ 6396 if (!is_mcs_rate(rspec[0]) 6397 && (tx_info->control.rates[0]. 6398 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)) 6399 preamble_type[k] = BRCMS_SHORT_PREAMBLE; 6400 } 6401 } else { 6402 for (k = 0; k < hw->max_rates; k++) { 6403 /* Set ctrlchbw as 20Mhz */ 6404 rspec[k] &= ~RSPEC_BW_MASK; 6405 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT); 6406 6407 /* for nphy, stf of ofdm frames must follow policies */ 6408 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) { 6409 rspec[k] &= ~RSPEC_STF_MASK; 6410 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT; 6411 } 6412 } 6413 } 6414 6415 /* Reset these for use with AMPDU's */ 6416 txrate[0]->count = 0; 6417 txrate[1]->count = 0; 6418 6419 /* (2) PROTECTION, may change rspec */ 6420 if ((ieee80211_is_data(h->frame_control) || 6421 ieee80211_is_mgmt(h->frame_control)) && 6422 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1)) 6423 use_rts = true; 6424 6425 /* (3) PLCP: determine PLCP header and MAC duration, 6426 * fill struct d11txh */ 6427 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp); 6428 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback); 6429 memcpy(&txh->FragPLCPFallback, 6430 plcp_fallback, sizeof(txh->FragPLCPFallback)); 6431 6432 /* Length field now put in CCK FBR CRC field */ 6433 if (is_cck_rate(rspec[1])) { 6434 txh->FragPLCPFallback[4] = phylen & 0xff; 6435 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8; 6436 } 6437 6438 /* MIMO-RATE: need validation ?? */ 6439 mainrates = is_ofdm_rate(rspec[0]) ? 6440 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) : 6441 plcp[0]; 6442 6443 /* DUR field for main rate */ 6444 if (!ieee80211_is_pspoll(h->frame_control) && 6445 !is_multicast_ether_addr(h->addr1) && !use_rifs) { 6446 durid = 6447 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0], 6448 next_frag_len); 6449 h->duration_id = cpu_to_le16(durid); 6450 } else if (use_rifs) { 6451 /* NAV protect to end of next max packet size */ 6452 durid = 6453 (u16) brcms_c_calc_frame_time(wlc, rspec[0], 6454 preamble_type[0], 6455 DOT11_MAX_FRAG_LEN); 6456 durid += RIFS_11N_TIME; 6457 h->duration_id = cpu_to_le16(durid); 6458 } 6459 6460 /* DUR field for fallback rate */ 6461 if (ieee80211_is_pspoll(h->frame_control)) 6462 txh->FragDurFallback = h->duration_id; 6463 else if (is_multicast_ether_addr(h->addr1) || use_rifs) 6464 txh->FragDurFallback = 0; 6465 else { 6466 durid = brcms_c_compute_frame_dur(wlc, rspec[1], 6467 preamble_type[1], next_frag_len); 6468 txh->FragDurFallback = cpu_to_le16(durid); 6469 } 6470 6471 /* (4) MAC-HDR: MacTxControlLow */ 6472 if (frag == 0) 6473 mcl |= TXC_STARTMSDU; 6474 6475 if (!is_multicast_ether_addr(h->addr1)) 6476 mcl |= TXC_IMMEDACK; 6477 6478 if (wlc->band->bandtype == BRCM_BAND_5G) 6479 mcl |= TXC_FREQBAND_5G; 6480 6481 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi))) 6482 mcl |= TXC_BW_40; 6483 6484 /* set AMIC bit if using hardware TKIP MIC */ 6485 if (hwtkmic) 6486 mcl |= TXC_AMIC; 6487 6488 txh->MacTxControlLow = cpu_to_le16(mcl); 6489 6490 /* MacTxControlHigh */ 6491 mch = 0; 6492 6493 /* Set fallback rate preamble type */ 6494 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) || 6495 (preamble_type[1] == BRCMS_GF_PREAMBLE)) { 6496 if (rspec2rate(rspec[1]) != BRCM_RATE_1M) 6497 mch |= TXC_PREAMBLE_DATA_FB_SHORT; 6498 } 6499 6500 /* MacFrameControl */ 6501 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16)); 6502 txh->TxFesTimeNormal = cpu_to_le16(0); 6503 6504 txh->TxFesTimeFallback = cpu_to_le16(0); 6505 6506 /* TxFrameRA */ 6507 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN); 6508 6509 /* TxFrameID */ 6510 txh->TxFrameID = cpu_to_le16(frameid); 6511 6512 /* 6513 * TxStatus, Note the case of recreating the first frag of a suppressed 6514 * frame then we may need to reset the retry cnt's via the status reg 6515 */ 6516 txh->TxStatus = cpu_to_le16(status); 6517 6518 /* 6519 * extra fields for ucode AMPDU aggregation, the new fields are added to 6520 * the END of previous structure so that it's compatible in driver. 6521 */ 6522 txh->MaxNMpdus = cpu_to_le16(0); 6523 txh->MaxABytes_MRT = cpu_to_le16(0); 6524 txh->MaxABytes_FBR = cpu_to_le16(0); 6525 txh->MinMBytes = cpu_to_le16(0); 6526 6527 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration, 6528 * furnish struct d11txh */ 6529 /* RTS PLCP header and RTS frame */ 6530 if (use_rts || use_cts) { 6531 if (use_rts && use_cts) 6532 use_cts = false; 6533 6534 for (k = 0; k < 2; k++) { 6535 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k], 6536 false, 6537 mimo_ctlchbw); 6538 } 6539 6540 if (!is_ofdm_rate(rts_rspec[0]) && 6541 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) || 6542 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) { 6543 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE; 6544 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT; 6545 } 6546 6547 if (!is_ofdm_rate(rts_rspec[1]) && 6548 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) || 6549 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) { 6550 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE; 6551 mch |= TXC_PREAMBLE_RTS_FB_SHORT; 6552 } 6553 6554 /* RTS/CTS additions to MacTxControlLow */ 6555 if (use_cts) { 6556 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS); 6557 } else { 6558 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS); 6559 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME); 6560 } 6561 6562 /* RTS PLCP header */ 6563 rts_plcp = txh->RTSPhyHeader; 6564 if (use_cts) 6565 rts_phylen = DOT11_CTS_LEN + FCS_LEN; 6566 else 6567 rts_phylen = DOT11_RTS_LEN + FCS_LEN; 6568 6569 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp); 6570 6571 /* fallback rate version of RTS PLCP header */ 6572 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen, 6573 rts_plcp_fallback); 6574 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback, 6575 sizeof(txh->RTSPLCPFallback)); 6576 6577 /* RTS frame fields... */ 6578 rts = (struct ieee80211_rts *)&txh->rts_frame; 6579 6580 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0], 6581 rspec[0], rts_preamble_type[0], 6582 preamble_type[0], phylen, false); 6583 rts->duration = cpu_to_le16(durid); 6584 /* fallback rate version of RTS DUR field */ 6585 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, 6586 rts_rspec[1], rspec[1], 6587 rts_preamble_type[1], 6588 preamble_type[1], phylen, false); 6589 txh->RTSDurFallback = cpu_to_le16(durid); 6590 6591 if (use_cts) { 6592 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL | 6593 IEEE80211_STYPE_CTS); 6594 6595 memcpy(&rts->ra, &h->addr2, ETH_ALEN); 6596 } else { 6597 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL | 6598 IEEE80211_STYPE_RTS); 6599 6600 memcpy(&rts->ra, &h->addr1, ETH_ALEN); 6601 memcpy(&rts->ta, &h->addr2, ETH_ALEN); 6602 } 6603 6604 /* mainrate 6605 * low 8 bits: main frag rate/mcs, 6606 * high 8 bits: rts/cts rate/mcs 6607 */ 6608 mainrates |= (is_ofdm_rate(rts_rspec[0]) ? 6609 D11A_PHY_HDR_GRATE( 6610 (struct ofdm_phy_hdr *) rts_plcp) : 6611 rts_plcp[0]) << 8; 6612 } else { 6613 memset(txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN); 6614 memset(&txh->rts_frame, 0, sizeof(struct ieee80211_rts)); 6615 memset(txh->RTSPLCPFallback, 0, sizeof(txh->RTSPLCPFallback)); 6616 txh->RTSDurFallback = 0; 6617 } 6618 6619 #ifdef SUPPORT_40MHZ 6620 /* add null delimiter count */ 6621 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec)) 6622 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 6623 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen); 6624 6625 #endif 6626 6627 /* 6628 * Now that RTS/RTS FB preamble types are updated, write 6629 * the final value 6630 */ 6631 txh->MacTxControlHigh = cpu_to_le16(mch); 6632 6633 /* 6634 * MainRates (both the rts and frag plcp rates have 6635 * been calculated now) 6636 */ 6637 txh->MainRates = cpu_to_le16(mainrates); 6638 6639 /* XtraFrameTypes */ 6640 xfts = frametype(rspec[1], wlc->mimoft); 6641 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT); 6642 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT); 6643 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) << 6644 XFTS_CHANNEL_SHIFT; 6645 txh->XtraFrameTypes = cpu_to_le16(xfts); 6646 6647 /* PhyTxControlWord */ 6648 phyctl = frametype(rspec[0], wlc->mimoft); 6649 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) || 6650 (preamble_type[0] == BRCMS_GF_PREAMBLE)) { 6651 if (rspec2rate(rspec[0]) != BRCM_RATE_1M) 6652 phyctl |= PHY_TXC_SHORT_HDR; 6653 } 6654 6655 /* phytxant is properly bit shifted */ 6656 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]); 6657 txh->PhyTxControlWord = cpu_to_le16(phyctl); 6658 6659 /* PhyTxControlWord_1 */ 6660 if (BRCMS_PHY_11N_CAP(wlc->band)) { 6661 u16 phyctl1 = 0; 6662 6663 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]); 6664 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1); 6665 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]); 6666 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1); 6667 6668 if (use_rts || use_cts) { 6669 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]); 6670 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1); 6671 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]); 6672 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1); 6673 } 6674 6675 /* 6676 * For mcs frames, if mixedmode(overloaded with long preamble) 6677 * is going to be set, fill in non-zero MModeLen and/or 6678 * MModeFbrLen it will be unnecessary if they are separated 6679 */ 6680 if (is_mcs_rate(rspec[0]) && 6681 (preamble_type[0] == BRCMS_MM_PREAMBLE)) { 6682 u16 mmodelen = 6683 brcms_c_calc_lsig_len(wlc, rspec[0], phylen); 6684 txh->MModeLen = cpu_to_le16(mmodelen); 6685 } 6686 6687 if (is_mcs_rate(rspec[1]) && 6688 (preamble_type[1] == BRCMS_MM_PREAMBLE)) { 6689 u16 mmodefbrlen = 6690 brcms_c_calc_lsig_len(wlc, rspec[1], phylen); 6691 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen); 6692 } 6693 } 6694 6695 ac = skb_get_queue_mapping(p); 6696 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) { 6697 uint frag_dur, dur, dur_fallback; 6698 6699 /* WME: Update TXOP threshold */ 6700 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) { 6701 frag_dur = 6702 brcms_c_calc_frame_time(wlc, rspec[0], 6703 preamble_type[0], phylen); 6704 6705 if (rts) { 6706 /* 1 RTS or CTS-to-self frame */ 6707 dur = 6708 brcms_c_calc_cts_time(wlc, rts_rspec[0], 6709 rts_preamble_type[0]); 6710 dur_fallback = 6711 brcms_c_calc_cts_time(wlc, rts_rspec[1], 6712 rts_preamble_type[1]); 6713 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */ 6714 dur += le16_to_cpu(rts->duration); 6715 dur_fallback += 6716 le16_to_cpu(txh->RTSDurFallback); 6717 } else if (use_rifs) { 6718 dur = frag_dur; 6719 dur_fallback = 0; 6720 } else { 6721 /* frame + SIFS + ACK */ 6722 dur = frag_dur; 6723 dur += 6724 brcms_c_compute_frame_dur(wlc, rspec[0], 6725 preamble_type[0], 0); 6726 6727 dur_fallback = 6728 brcms_c_calc_frame_time(wlc, rspec[1], 6729 preamble_type[1], 6730 phylen); 6731 dur_fallback += 6732 brcms_c_compute_frame_dur(wlc, rspec[1], 6733 preamble_type[1], 0); 6734 } 6735 /* NEED to set TxFesTimeNormal (hard) */ 6736 txh->TxFesTimeNormal = cpu_to_le16((u16) dur); 6737 /* 6738 * NEED to set fallback rate version of 6739 * TxFesTimeNormal (hard) 6740 */ 6741 txh->TxFesTimeFallback = 6742 cpu_to_le16((u16) dur_fallback); 6743 6744 /* 6745 * update txop byte threshold (txop minus intraframe 6746 * overhead) 6747 */ 6748 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) { 6749 uint newfragthresh; 6750 6751 newfragthresh = 6752 brcms_c_calc_frame_len(wlc, 6753 rspec[0], preamble_type[0], 6754 (wlc->edcf_txop[ac] - 6755 (dur - frag_dur))); 6756 /* range bound the fragthreshold */ 6757 if (newfragthresh < DOT11_MIN_FRAG_LEN) 6758 newfragthresh = 6759 DOT11_MIN_FRAG_LEN; 6760 else if (newfragthresh > 6761 wlc->usr_fragthresh) 6762 newfragthresh = 6763 wlc->usr_fragthresh; 6764 /* update the fragthresh and do txc update */ 6765 if (wlc->fragthresh[queue] != 6766 (u16) newfragthresh) 6767 wlc->fragthresh[queue] = 6768 (u16) newfragthresh; 6769 } else { 6770 brcms_warn(wlc->hw->d11core, 6771 "wl%d: %s txop invalid for rate %d\n", 6772 wlc->pub->unit, fifo_names[queue], 6773 rspec2rate(rspec[0])); 6774 } 6775 6776 if (dur > wlc->edcf_txop[ac]) 6777 brcms_warn(wlc->hw->d11core, 6778 "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n", 6779 wlc->pub->unit, __func__, 6780 fifo_names[queue], 6781 phylen, wlc->fragthresh[queue], 6782 dur, wlc->edcf_txop[ac]); 6783 } 6784 } 6785 6786 return 0; 6787 } 6788 6789 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb) 6790 { 6791 struct dma_pub *dma; 6792 int fifo, ret = -ENOSPC; 6793 struct d11txh *txh; 6794 u16 frameid = INVALIDFID; 6795 6796 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb)); 6797 dma = wlc->hw->di[fifo]; 6798 txh = (struct d11txh *)(skb->data); 6799 6800 if (dma->txavail == 0) { 6801 /* 6802 * We sometimes get a frame from mac80211 after stopping 6803 * the queues. This only ever seems to be a single frame 6804 * and is seems likely to be a race. TX_HEADROOM should 6805 * ensure that we have enough space to handle these stray 6806 * packets, so warn if there isn't. If we're out of space 6807 * in the tx ring and the tx queue isn't stopped then 6808 * we've really got a bug; warn loudly if that happens. 6809 */ 6810 brcms_warn(wlc->hw->d11core, 6811 "Received frame for tx with no space in DMA ring\n"); 6812 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw, 6813 skb_get_queue_mapping(skb))); 6814 return -ENOSPC; 6815 } 6816 6817 /* When a BC/MC frame is being committed to the BCMC fifo 6818 * via DMA (NOT PIO), update ucode or BSS info as appropriate. 6819 */ 6820 if (fifo == TX_BCMC_FIFO) 6821 frameid = le16_to_cpu(txh->TxFrameID); 6822 6823 /* Commit BCMC sequence number in the SHM frame ID location */ 6824 if (frameid != INVALIDFID) { 6825 /* 6826 * To inform the ucode of the last mcast frame posted 6827 * so that it can clear moredata bit 6828 */ 6829 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid); 6830 } 6831 6832 ret = brcms_c_txfifo(wlc, fifo, skb); 6833 /* 6834 * The only reason for brcms_c_txfifo to fail is because 6835 * there weren't any DMA descriptors, but we've already 6836 * checked for that. So if it does fail yell loudly. 6837 */ 6838 WARN_ON_ONCE(ret); 6839 6840 return ret; 6841 } 6842 6843 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu, 6844 struct ieee80211_hw *hw) 6845 { 6846 uint fifo; 6847 struct scb *scb = &wlc->pri_scb; 6848 6849 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu)); 6850 brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0); 6851 if (!brcms_c_tx(wlc, sdu)) 6852 return true; 6853 6854 /* packet discarded */ 6855 dev_kfree_skb_any(sdu); 6856 return false; 6857 } 6858 6859 int 6860 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p) 6861 { 6862 struct dma_pub *dma = wlc->hw->di[fifo]; 6863 int ret; 6864 u16 queue; 6865 6866 ret = dma_txfast(wlc, dma, p); 6867 if (ret < 0) 6868 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n"); 6869 6870 /* 6871 * Stop queue if DMA ring is full. Reserve some free descriptors, 6872 * as we sometimes receive a frame from mac80211 after the queues 6873 * are stopped. 6874 */ 6875 queue = skb_get_queue_mapping(p); 6876 if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO && 6877 !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue)) 6878 ieee80211_stop_queue(wlc->pub->ieee_hw, queue); 6879 6880 return ret; 6881 } 6882 6883 u32 6884 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec, 6885 bool use_rspec, u16 mimo_ctlchbw) 6886 { 6887 u32 rts_rspec = 0; 6888 6889 if (use_rspec) 6890 /* use frame rate as rts rate */ 6891 rts_rspec = rspec; 6892 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec)) 6893 /* Use 11Mbps as the g protection RTS target rate and fallback. 6894 * Use the brcms_basic_rate() lookup to find the best basic rate 6895 * under the target in case 11 Mbps is not Basic. 6896 * 6 and 9 Mbps are not usually selected by rate selection, but 6897 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11 6898 * is more robust. 6899 */ 6900 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M); 6901 else 6902 /* calculate RTS rate and fallback rate based on the frame rate 6903 * RTS must be sent at a basic rate since it is a 6904 * control frame, sec 9.6 of 802.11 spec 6905 */ 6906 rts_rspec = brcms_basic_rate(wlc, rspec); 6907 6908 if (BRCMS_PHY_11N_CAP(wlc->band)) { 6909 /* set rts txbw to correct side band */ 6910 rts_rspec &= ~RSPEC_BW_MASK; 6911 6912 /* 6913 * if rspec/rspec_fallback is 40MHz, then send RTS on both 6914 * 20MHz channel (DUP), otherwise send RTS on control channel 6915 */ 6916 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec)) 6917 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT); 6918 else 6919 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT); 6920 6921 /* pick siso/cdd as default for ofdm */ 6922 if (is_ofdm_rate(rts_rspec)) { 6923 rts_rspec &= ~RSPEC_STF_MASK; 6924 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT); 6925 } 6926 } 6927 return rts_rspec; 6928 } 6929 6930 /* Update beacon listen interval in shared memory */ 6931 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc) 6932 { 6933 /* wake up every DTIM is the default */ 6934 if (wlc->bcn_li_dtim == 1) 6935 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0); 6936 else 6937 brcms_b_write_shm(wlc->hw, M_BCN_LI, 6938 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn); 6939 } 6940 6941 static void 6942 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr, 6943 u32 *tsf_h_ptr) 6944 { 6945 struct bcma_device *core = wlc_hw->d11core; 6946 6947 /* read the tsf timer low, then high to get an atomic read */ 6948 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow)); 6949 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh)); 6950 } 6951 6952 /* 6953 * recover 64bit TSF value from the 16bit TSF value in the rx header 6954 * given the assumption that the TSF passed in header is within 65ms 6955 * of the current tsf. 6956 * 6957 * 6 5 4 4 3 2 1 6958 * 3.......6.......8.......0.......2.......4.......6.......8......0 6959 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->| 6960 * 6961 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The 6962 * tsf_l is filled in by brcms_b_recv, which is done earlier in the 6963 * receive call sequence after rx interrupt. Only the higher 16 bits 6964 * are used. Finally, the tsf_h is read from the tsf register. 6965 */ 6966 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc, 6967 struct d11rxhdr *rxh) 6968 { 6969 u32 tsf_h, tsf_l; 6970 u16 rx_tsf_0_15, rx_tsf_16_31; 6971 6972 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h); 6973 6974 rx_tsf_16_31 = (u16)(tsf_l >> 16); 6975 rx_tsf_0_15 = rxh->RxTSFTime; 6976 6977 /* 6978 * a greater tsf time indicates the low 16 bits of 6979 * tsf_l wrapped, so decrement the high 16 bits. 6980 */ 6981 if ((u16)tsf_l < rx_tsf_0_15) { 6982 rx_tsf_16_31 -= 1; 6983 if (rx_tsf_16_31 == 0xffff) 6984 tsf_h -= 1; 6985 } 6986 6987 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15); 6988 } 6989 6990 static void 6991 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh, 6992 struct sk_buff *p, 6993 struct ieee80211_rx_status *rx_status) 6994 { 6995 int channel; 6996 u32 rspec; 6997 unsigned char *plcp; 6998 6999 /* fill in TSF and flag its presence */ 7000 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh); 7001 rx_status->flag |= RX_FLAG_MACTIME_START; 7002 7003 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan); 7004 7005 rx_status->band = 7006 channel > 14 ? NL80211_BAND_5GHZ : NL80211_BAND_2GHZ; 7007 rx_status->freq = 7008 ieee80211_channel_to_frequency(channel, rx_status->band); 7009 7010 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh); 7011 7012 /* noise */ 7013 /* qual */ 7014 rx_status->antenna = 7015 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0; 7016 7017 plcp = p->data; 7018 7019 rspec = brcms_c_compute_rspec(rxh, plcp); 7020 if (is_mcs_rate(rspec)) { 7021 rx_status->rate_idx = rspec & RSPEC_RATE_MASK; 7022 rx_status->encoding = RX_ENC_HT; 7023 if (rspec_is40mhz(rspec)) 7024 rx_status->bw = RATE_INFO_BW_40; 7025 } else { 7026 switch (rspec2rate(rspec)) { 7027 case BRCM_RATE_1M: 7028 rx_status->rate_idx = 0; 7029 break; 7030 case BRCM_RATE_2M: 7031 rx_status->rate_idx = 1; 7032 break; 7033 case BRCM_RATE_5M5: 7034 rx_status->rate_idx = 2; 7035 break; 7036 case BRCM_RATE_11M: 7037 rx_status->rate_idx = 3; 7038 break; 7039 case BRCM_RATE_6M: 7040 rx_status->rate_idx = 4; 7041 break; 7042 case BRCM_RATE_9M: 7043 rx_status->rate_idx = 5; 7044 break; 7045 case BRCM_RATE_12M: 7046 rx_status->rate_idx = 6; 7047 break; 7048 case BRCM_RATE_18M: 7049 rx_status->rate_idx = 7; 7050 break; 7051 case BRCM_RATE_24M: 7052 rx_status->rate_idx = 8; 7053 break; 7054 case BRCM_RATE_36M: 7055 rx_status->rate_idx = 9; 7056 break; 7057 case BRCM_RATE_48M: 7058 rx_status->rate_idx = 10; 7059 break; 7060 case BRCM_RATE_54M: 7061 rx_status->rate_idx = 11; 7062 break; 7063 default: 7064 brcms_err(wlc->hw->d11core, 7065 "%s: Unknown rate\n", __func__); 7066 } 7067 7068 /* 7069 * For 5GHz, we should decrease the index as it is 7070 * a subset of the 2.4G rates. See bitrates field 7071 * of brcms_band_5GHz_nphy (in mac80211_if.c). 7072 */ 7073 if (rx_status->band == NL80211_BAND_5GHZ) 7074 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET; 7075 7076 /* Determine short preamble and rate_idx */ 7077 if (is_cck_rate(rspec)) { 7078 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH) 7079 rx_status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 7080 } else if (is_ofdm_rate(rspec)) { 7081 rx_status->enc_flags |= RX_ENC_FLAG_SHORTPRE; 7082 } else { 7083 brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n", 7084 __func__); 7085 } 7086 } 7087 7088 if (plcp3_issgi(plcp[3])) 7089 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 7090 7091 if (rxh->RxStatus1 & RXS_DECERR) { 7092 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC; 7093 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_PLCP_CRC\n", 7094 __func__); 7095 } 7096 if (rxh->RxStatus1 & RXS_FCSERR) { 7097 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 7098 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_FCS_CRC\n", 7099 __func__); 7100 } 7101 } 7102 7103 static void 7104 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh, 7105 struct sk_buff *p) 7106 { 7107 int len_mpdu; 7108 struct ieee80211_rx_status rx_status; 7109 struct ieee80211_hdr *hdr; 7110 7111 memset(&rx_status, 0, sizeof(rx_status)); 7112 prep_mac80211_status(wlc, rxh, p, &rx_status); 7113 7114 /* mac header+body length, exclude CRC and plcp header */ 7115 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN; 7116 skb_pull(p, D11_PHY_HDR_LEN); 7117 __skb_trim(p, len_mpdu); 7118 7119 /* unmute transmit */ 7120 if (wlc->hw->suspended_fifos) { 7121 hdr = (struct ieee80211_hdr *)p->data; 7122 if (ieee80211_is_beacon(hdr->frame_control)) 7123 brcms_b_mute(wlc->hw, false); 7124 } 7125 7126 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status)); 7127 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p); 7128 } 7129 7130 /* calculate frame duration for Mixed-mode L-SIG spoofing, return 7131 * number of bytes goes in the length field 7132 * 7133 * Formula given by HT PHY Spec v 1.13 7134 * len = 3(nsyms + nstream + 3) - 3 7135 */ 7136 u16 7137 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec, 7138 uint mac_len) 7139 { 7140 uint nsyms, len = 0, kNdps; 7141 7142 if (is_mcs_rate(ratespec)) { 7143 uint mcs = ratespec & RSPEC_RATE_MASK; 7144 int tot_streams = (mcs_2_txstreams(mcs) + 1) + 7145 rspec_stc(ratespec); 7146 7147 /* 7148 * the payload duration calculation matches that 7149 * of regular ofdm 7150 */ 7151 /* 1000Ndbps = kbps * 4 */ 7152 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 7153 rspec_issgi(ratespec)) * 4; 7154 7155 if (rspec_stc(ratespec) == 0) 7156 nsyms = 7157 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 7158 APHY_TAIL_NBITS) * 1000, kNdps); 7159 else 7160 /* STBC needs to have even number of symbols */ 7161 nsyms = 7162 2 * 7163 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 7164 APHY_TAIL_NBITS) * 1000, 2 * kNdps); 7165 7166 /* (+3) account for HT-SIG(2) and HT-STF(1) */ 7167 nsyms += (tot_streams + 3); 7168 /* 7169 * 3 bytes/symbol @ legacy 6Mbps rate 7170 * (-3) excluding service bits and tail bits 7171 */ 7172 len = (3 * nsyms) - 3; 7173 } 7174 7175 return (u16) len; 7176 } 7177 7178 static void 7179 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len) 7180 { 7181 const struct brcms_c_rateset *rs_dflt; 7182 struct brcms_c_rateset rs; 7183 u8 rate; 7184 u16 entry_ptr; 7185 u8 plcp[D11_PHY_HDR_LEN]; 7186 u16 dur, sifs; 7187 uint i; 7188 7189 sifs = get_sifs(wlc->band); 7190 7191 rs_dflt = brcms_c_rateset_get_hwrs(wlc); 7192 7193 brcms_c_rateset_copy(rs_dflt, &rs); 7194 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams); 7195 7196 /* 7197 * walk the phy rate table and update MAC core SHM 7198 * basic rate table entries 7199 */ 7200 for (i = 0; i < rs.count; i++) { 7201 rate = rs.rates[i] & BRCMS_RATE_MASK; 7202 7203 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate); 7204 7205 /* Calculate the Probe Response PLCP for the given rate */ 7206 brcms_c_compute_plcp(wlc, rate, frame_len, plcp); 7207 7208 /* 7209 * Calculate the duration of the Probe Response 7210 * frame plus SIFS for the MAC 7211 */ 7212 dur = (u16) brcms_c_calc_frame_time(wlc, rate, 7213 BRCMS_LONG_PREAMBLE, frame_len); 7214 dur += sifs; 7215 7216 /* Update the SHM Rate Table entry Probe Response values */ 7217 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS, 7218 (u16) (plcp[0] + (plcp[1] << 8))); 7219 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2, 7220 (u16) (plcp[2] + (plcp[3] << 8))); 7221 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur); 7222 } 7223 } 7224 7225 int brcms_c_get_header_len(void) 7226 { 7227 return TXOFF; 7228 } 7229 7230 static void brcms_c_beacon_write(struct brcms_c_info *wlc, 7231 struct sk_buff *beacon, u16 tim_offset, 7232 u16 dtim_period, bool bcn0, bool bcn1) 7233 { 7234 size_t len; 7235 struct ieee80211_tx_info *tx_info; 7236 struct brcms_hardware *wlc_hw = wlc->hw; 7237 struct ieee80211_hw *ieee_hw = brcms_c_pub(wlc)->ieee_hw; 7238 7239 /* Get tx_info */ 7240 tx_info = IEEE80211_SKB_CB(beacon); 7241 7242 len = min_t(size_t, beacon->len, BCN_TMPL_LEN); 7243 wlc->bcn_rspec = ieee80211_get_tx_rate(ieee_hw, tx_info)->hw_value; 7244 7245 brcms_c_compute_plcp(wlc, wlc->bcn_rspec, 7246 len + FCS_LEN - D11_PHY_HDR_LEN, beacon->data); 7247 7248 /* "Regular" and 16 MBSS but not for 4 MBSS */ 7249 /* Update the phytxctl for the beacon based on the rspec */ 7250 brcms_c_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec); 7251 7252 if (bcn0) { 7253 /* write the probe response into the template region */ 7254 brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, 7255 (len + 3) & ~3, beacon->data); 7256 7257 /* write beacon length to SCR */ 7258 brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len); 7259 } 7260 if (bcn1) { 7261 /* write the probe response into the template region */ 7262 brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, 7263 (len + 3) & ~3, beacon->data); 7264 7265 /* write beacon length to SCR */ 7266 brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len); 7267 } 7268 7269 if (tim_offset != 0) { 7270 brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON, 7271 tim_offset + D11B_PHY_HDR_LEN); 7272 brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, dtim_period); 7273 } else { 7274 brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON, 7275 len + D11B_PHY_HDR_LEN); 7276 brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, 0); 7277 } 7278 } 7279 7280 static void brcms_c_update_beacon_hw(struct brcms_c_info *wlc, 7281 struct sk_buff *beacon, u16 tim_offset, 7282 u16 dtim_period) 7283 { 7284 struct brcms_hardware *wlc_hw = wlc->hw; 7285 struct bcma_device *core = wlc_hw->d11core; 7286 7287 /* Hardware beaconing for this config */ 7288 u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD; 7289 7290 /* Check if both templates are in use, if so sched. an interrupt 7291 * that will call back into this routine 7292 */ 7293 if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid) 7294 /* clear any previous status */ 7295 bcma_write32(core, D11REGOFFS(macintstatus), MI_BCNTPL); 7296 7297 if (wlc->beacon_template_virgin) { 7298 wlc->beacon_template_virgin = false; 7299 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true, 7300 true); 7301 /* mark beacon0 valid */ 7302 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD); 7303 return; 7304 } 7305 7306 /* Check that after scheduling the interrupt both of the 7307 * templates are still busy. if not clear the int. & remask 7308 */ 7309 if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid) { 7310 wlc->defmacintmask |= MI_BCNTPL; 7311 return; 7312 } 7313 7314 if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN0VLD)) { 7315 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true, 7316 false); 7317 /* mark beacon0 valid */ 7318 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD); 7319 return; 7320 } 7321 if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN1VLD)) { 7322 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, 7323 false, true); 7324 /* mark beacon0 valid */ 7325 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN1VLD); 7326 } 7327 } 7328 7329 /* 7330 * Update all beacons for the system. 7331 */ 7332 void brcms_c_update_beacon(struct brcms_c_info *wlc) 7333 { 7334 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 7335 7336 if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP || 7337 bsscfg->type == BRCMS_TYPE_ADHOC)) { 7338 /* Clear the soft intmask */ 7339 wlc->defmacintmask &= ~MI_BCNTPL; 7340 if (!wlc->beacon) 7341 return; 7342 brcms_c_update_beacon_hw(wlc, wlc->beacon, 7343 wlc->beacon_tim_offset, 7344 wlc->beacon_dtim_period); 7345 } 7346 } 7347 7348 void brcms_c_set_new_beacon(struct brcms_c_info *wlc, struct sk_buff *beacon, 7349 u16 tim_offset, u16 dtim_period) 7350 { 7351 if (!beacon) 7352 return; 7353 if (wlc->beacon) 7354 dev_kfree_skb_any(wlc->beacon); 7355 wlc->beacon = beacon; 7356 7357 /* add PLCP */ 7358 skb_push(wlc->beacon, D11_PHY_HDR_LEN); 7359 wlc->beacon_tim_offset = tim_offset; 7360 wlc->beacon_dtim_period = dtim_period; 7361 brcms_c_update_beacon(wlc); 7362 } 7363 7364 void brcms_c_set_new_probe_resp(struct brcms_c_info *wlc, 7365 struct sk_buff *probe_resp) 7366 { 7367 if (!probe_resp) 7368 return; 7369 if (wlc->probe_resp) 7370 dev_kfree_skb_any(wlc->probe_resp); 7371 wlc->probe_resp = probe_resp; 7372 7373 /* add PLCP */ 7374 skb_push(wlc->probe_resp, D11_PHY_HDR_LEN); 7375 brcms_c_update_probe_resp(wlc, false); 7376 } 7377 7378 void brcms_c_enable_probe_resp(struct brcms_c_info *wlc, bool enable) 7379 { 7380 /* 7381 * prevent ucode from sending probe responses by setting the timeout 7382 * to 1, it can not send it in that time frame. 7383 */ 7384 wlc->prb_resp_timeout = enable ? BRCMS_PRB_RESP_TIMEOUT : 1; 7385 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout); 7386 /* TODO: if (enable) => also deactivate receiving of probe request */ 7387 } 7388 7389 /* Write ssid into shared memory */ 7390 static void 7391 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg) 7392 { 7393 u8 *ssidptr = cfg->SSID; 7394 u16 base = M_SSID; 7395 u8 ssidbuf[IEEE80211_MAX_SSID_LEN]; 7396 7397 /* padding the ssid with zero and copy it into shm */ 7398 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN); 7399 memcpy(ssidbuf, ssidptr, cfg->SSID_len); 7400 7401 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN); 7402 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len); 7403 } 7404 7405 static void 7406 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc, 7407 struct brcms_bss_cfg *cfg, 7408 struct sk_buff *probe_resp, 7409 bool suspend) 7410 { 7411 int len; 7412 7413 len = min_t(size_t, probe_resp->len, BCN_TMPL_LEN); 7414 7415 if (suspend) 7416 brcms_c_suspend_mac_and_wait(wlc); 7417 7418 /* write the probe response into the template region */ 7419 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE, 7420 (len + 3) & ~3, probe_resp->data); 7421 7422 /* write the length of the probe response frame (+PLCP/-FCS) */ 7423 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len); 7424 7425 /* write the SSID and SSID length */ 7426 brcms_c_shm_ssid_upd(wlc, cfg); 7427 7428 /* 7429 * Write PLCP headers and durations for probe response frames 7430 * at all rates. Use the actual frame length covered by the 7431 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table() 7432 * by subtracting the PLCP len and adding the FCS. 7433 */ 7434 brcms_c_mod_prb_rsp_rate_table(wlc, 7435 (u16)len + FCS_LEN - D11_PHY_HDR_LEN); 7436 7437 if (suspend) 7438 brcms_c_enable_mac(wlc); 7439 } 7440 7441 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend) 7442 { 7443 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 7444 7445 /* update AP or IBSS probe responses */ 7446 if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP || 7447 bsscfg->type == BRCMS_TYPE_ADHOC)) { 7448 if (!wlc->probe_resp) 7449 return; 7450 brcms_c_bss_update_probe_resp(wlc, bsscfg, wlc->probe_resp, 7451 suspend); 7452 } 7453 } 7454 7455 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo, 7456 uint *blocks) 7457 { 7458 if (fifo >= NFIFO) 7459 return -EINVAL; 7460 7461 *blocks = wlc_hw->xmtfifo_sz[fifo]; 7462 7463 return 0; 7464 } 7465 7466 void 7467 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset, 7468 const u8 *addr) 7469 { 7470 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr); 7471 if (match_reg_offset == RCM_BSSID_OFFSET) 7472 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN); 7473 } 7474 7475 /* 7476 * Flag 'scan in progress' to withhold dynamic phy calibration 7477 */ 7478 void brcms_c_scan_start(struct brcms_c_info *wlc) 7479 { 7480 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true); 7481 } 7482 7483 void brcms_c_scan_stop(struct brcms_c_info *wlc) 7484 { 7485 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false); 7486 } 7487 7488 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state) 7489 { 7490 wlc->pub->associated = state; 7491 } 7492 7493 /* 7494 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept 7495 * AMPDU traffic, packets pending in hardware have to be invalidated so that 7496 * when later on hardware releases them, they can be handled appropriately. 7497 */ 7498 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw, 7499 struct ieee80211_sta *sta, 7500 void (*dma_callback_fn)) 7501 { 7502 struct dma_pub *dmah; 7503 int i; 7504 for (i = 0; i < NFIFO; i++) { 7505 dmah = hw->di[i]; 7506 if (dmah != NULL) 7507 dma_walk_packets(dmah, dma_callback_fn, sta); 7508 } 7509 } 7510 7511 int brcms_c_get_curband(struct brcms_c_info *wlc) 7512 { 7513 return wlc->band->bandunit; 7514 } 7515 7516 bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc) 7517 { 7518 int i; 7519 7520 /* Kick DMA to send any pending AMPDU */ 7521 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++) 7522 if (wlc->hw->di[i]) 7523 dma_kick_tx(wlc->hw->di[i]); 7524 7525 return !brcms_txpktpendtot(wlc); 7526 } 7527 7528 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval) 7529 { 7530 wlc->bcn_li_bcn = interval; 7531 if (wlc->pub->up) 7532 brcms_c_bcn_li_upd(wlc); 7533 } 7534 7535 u64 brcms_c_tsf_get(struct brcms_c_info *wlc) 7536 { 7537 u32 tsf_h, tsf_l; 7538 u64 tsf; 7539 7540 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h); 7541 7542 tsf = tsf_h; 7543 tsf <<= 32; 7544 tsf |= tsf_l; 7545 7546 return tsf; 7547 } 7548 7549 void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf) 7550 { 7551 u32 tsf_h, tsf_l; 7552 7553 brcms_c_time_lock(wlc); 7554 7555 tsf_l = tsf; 7556 tsf_h = (tsf >> 32); 7557 7558 /* read the tsf timer low, then high to get an atomic read */ 7559 bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerlow), tsf_l); 7560 bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerhigh), tsf_h); 7561 7562 brcms_c_time_unlock(wlc); 7563 } 7564 7565 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr) 7566 { 7567 uint qdbm; 7568 7569 /* Remove override bit and clip to max qdbm value */ 7570 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff); 7571 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false); 7572 } 7573 7574 int brcms_c_get_tx_power(struct brcms_c_info *wlc) 7575 { 7576 uint qdbm; 7577 bool override; 7578 7579 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override); 7580 7581 /* Return qdbm units */ 7582 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR); 7583 } 7584 7585 /* Process received frames */ 7586 /* 7587 * Return true if more frames need to be processed. false otherwise. 7588 * Param 'bound' indicates max. # frames to process before break out. 7589 */ 7590 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p) 7591 { 7592 struct d11rxhdr *rxh; 7593 struct ieee80211_hdr *h; 7594 uint len; 7595 bool is_amsdu; 7596 7597 /* frame starts with rxhdr */ 7598 rxh = (struct d11rxhdr *) (p->data); 7599 7600 /* strip off rxhdr */ 7601 skb_pull(p, BRCMS_HWRXOFF); 7602 7603 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */ 7604 if (rxh->RxStatus1 & RXS_PBPRES) { 7605 if (p->len < 2) { 7606 brcms_err(wlc->hw->d11core, 7607 "wl%d: recv: rcvd runt of len %d\n", 7608 wlc->pub->unit, p->len); 7609 goto toss; 7610 } 7611 skb_pull(p, 2); 7612 } 7613 7614 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN); 7615 len = p->len; 7616 7617 if (rxh->RxStatus1 & RXS_FCSERR) { 7618 if (!(wlc->filter_flags & FIF_FCSFAIL)) 7619 goto toss; 7620 } 7621 7622 /* check received pkt has at least frame control field */ 7623 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control)) 7624 goto toss; 7625 7626 /* not supporting A-MSDU */ 7627 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK; 7628 if (is_amsdu) 7629 goto toss; 7630 7631 brcms_c_recvctl(wlc, rxh, p); 7632 return; 7633 7634 toss: 7635 brcmu_pkt_buf_free_skb(p); 7636 } 7637 7638 /* Process received frames */ 7639 /* 7640 * Return true if more frames need to be processed. false otherwise. 7641 * Param 'bound' indicates max. # frames to process before break out. 7642 */ 7643 static bool 7644 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound) 7645 { 7646 struct sk_buff *p; 7647 struct sk_buff *next = NULL; 7648 struct sk_buff_head recv_frames; 7649 7650 uint n = 0; 7651 uint bound_limit = bound ? RXBND : -1; 7652 bool morepending = false; 7653 7654 skb_queue_head_init(&recv_frames); 7655 7656 /* gather received frames */ 7657 do { 7658 /* !give others some time to run! */ 7659 if (n >= bound_limit) 7660 break; 7661 7662 morepending = dma_rx(wlc_hw->di[fifo], &recv_frames); 7663 n++; 7664 } while (morepending); 7665 7666 /* post more rbufs */ 7667 dma_rxfill(wlc_hw->di[fifo]); 7668 7669 /* process each frame */ 7670 skb_queue_walk_safe(&recv_frames, p, next) { 7671 struct d11rxhdr_le *rxh_le; 7672 struct d11rxhdr *rxh; 7673 7674 skb_unlink(p, &recv_frames); 7675 rxh_le = (struct d11rxhdr_le *)p->data; 7676 rxh = (struct d11rxhdr *)p->data; 7677 7678 /* fixup rx header endianness */ 7679 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize); 7680 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0); 7681 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1); 7682 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2); 7683 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3); 7684 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4); 7685 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5); 7686 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1); 7687 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2); 7688 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime); 7689 rxh->RxChan = le16_to_cpu(rxh_le->RxChan); 7690 7691 brcms_c_recv(wlc_hw->wlc, p); 7692 } 7693 7694 return morepending; 7695 } 7696 7697 /* second-level interrupt processing 7698 * Return true if another dpc needs to be re-scheduled. false otherwise. 7699 * Param 'bounded' indicates if applicable loops should be bounded. 7700 */ 7701 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded) 7702 { 7703 u32 macintstatus; 7704 struct brcms_hardware *wlc_hw = wlc->hw; 7705 struct bcma_device *core = wlc_hw->d11core; 7706 7707 if (brcms_deviceremoved(wlc)) { 7708 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 7709 __func__); 7710 brcms_down(wlc->wl); 7711 return false; 7712 } 7713 7714 /* grab and clear the saved software intstatus bits */ 7715 macintstatus = wlc->macintstatus; 7716 wlc->macintstatus = 0; 7717 7718 brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n", 7719 wlc_hw->unit, macintstatus); 7720 7721 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */ 7722 7723 /* tx status */ 7724 if (macintstatus & MI_TFS) { 7725 bool fatal; 7726 if (brcms_b_txstatus(wlc->hw, bounded, &fatal)) 7727 wlc->macintstatus |= MI_TFS; 7728 if (fatal) { 7729 brcms_err(core, "MI_TFS: fatal\n"); 7730 goto fatal; 7731 } 7732 } 7733 7734 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT)) 7735 brcms_c_tbtt(wlc); 7736 7737 /* ATIM window end */ 7738 if (macintstatus & MI_ATIMWINEND) { 7739 brcms_dbg_info(core, "end of ATIM window\n"); 7740 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid); 7741 wlc->qvalid = 0; 7742 } 7743 7744 /* 7745 * received data or control frame, MI_DMAINT is 7746 * indication of RX_FIFO interrupt 7747 */ 7748 if (macintstatus & MI_DMAINT) 7749 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded)) 7750 wlc->macintstatus |= MI_DMAINT; 7751 7752 /* noise sample collected */ 7753 if (macintstatus & MI_BG_NOISE) 7754 wlc_phy_noise_sample_intr(wlc_hw->band->pi); 7755 7756 if (macintstatus & MI_GP0) { 7757 brcms_err(core, "wl%d: PSM microcode watchdog fired at %d " 7758 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now); 7759 7760 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n", 7761 __func__, ai_get_chip_id(wlc_hw->sih), 7762 ai_get_chiprev(wlc_hw->sih)); 7763 brcms_fatal_error(wlc_hw->wlc->wl); 7764 } 7765 7766 /* gptimer timeout */ 7767 if (macintstatus & MI_TO) 7768 bcma_write32(core, D11REGOFFS(gptimer), 0); 7769 7770 if (macintstatus & MI_RFDISABLE) { 7771 brcms_dbg_info(core, "wl%d: BMAC Detected a change on the" 7772 " RF Disable Input\n", wlc_hw->unit); 7773 brcms_rfkill_set_hw_state(wlc->wl); 7774 } 7775 7776 /* BCN template is available */ 7777 if (macintstatus & MI_BCNTPL) 7778 brcms_c_update_beacon(wlc); 7779 7780 /* it isn't done and needs to be resched if macintstatus is non-zero */ 7781 return wlc->macintstatus != 0; 7782 7783 fatal: 7784 brcms_fatal_error(wlc_hw->wlc->wl); 7785 return wlc->macintstatus != 0; 7786 } 7787 7788 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx) 7789 { 7790 struct bcma_device *core = wlc->hw->d11core; 7791 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.chandef.chan; 7792 u16 chanspec; 7793 7794 brcms_dbg_info(core, "wl%d\n", wlc->pub->unit); 7795 7796 chanspec = ch20mhz_chspec(ch->hw_value); 7797 7798 brcms_b_init(wlc->hw, chanspec); 7799 7800 /* update beacon listen interval */ 7801 brcms_c_bcn_li_upd(wlc); 7802 7803 /* write ethernet address to core */ 7804 brcms_c_set_mac(wlc->bsscfg); 7805 brcms_c_set_bssid(wlc->bsscfg); 7806 7807 /* Update tsf_cfprep if associated and up */ 7808 if (wlc->pub->associated && wlc->pub->up) { 7809 u32 bi; 7810 7811 /* get beacon period and convert to uS */ 7812 bi = wlc->bsscfg->current_bss->beacon_period << 10; 7813 /* 7814 * update since init path would reset 7815 * to default value 7816 */ 7817 bcma_write32(core, D11REGOFFS(tsf_cfprep), 7818 bi << CFPREP_CBI_SHIFT); 7819 7820 /* Update maccontrol PM related bits */ 7821 brcms_c_set_ps_ctrl(wlc); 7822 } 7823 7824 brcms_c_bandinit_ordered(wlc, chanspec); 7825 7826 /* init probe response timeout */ 7827 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout); 7828 7829 /* init max burst txop (framebursting) */ 7830 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP, 7831 (wlc-> 7832 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP)); 7833 7834 /* initialize maximum allowed duty cycle */ 7835 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true); 7836 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true); 7837 7838 /* 7839 * Update some shared memory locations related to 7840 * max AMPDU size allowed to received 7841 */ 7842 brcms_c_ampdu_shm_upd(wlc->ampdu); 7843 7844 /* band-specific inits */ 7845 brcms_c_bsinit(wlc); 7846 7847 /* Enable EDCF mode (while the MAC is suspended) */ 7848 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF); 7849 brcms_c_edcf_setparams(wlc, false); 7850 7851 /* read the ucode version if we have not yet done so */ 7852 if (wlc->ucode_rev == 0) { 7853 u16 rev; 7854 u16 patch; 7855 7856 rev = brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR); 7857 patch = brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR); 7858 wlc->ucode_rev = (rev << NBITS(u16)) | patch; 7859 snprintf(wlc->wiphy->fw_version, 7860 sizeof(wlc->wiphy->fw_version), "%u.%u", rev, patch); 7861 } 7862 7863 /* ..now really unleash hell (allow the MAC out of suspend) */ 7864 brcms_c_enable_mac(wlc); 7865 7866 /* suspend the tx fifos and mute the phy for preism cac time */ 7867 if (mute_tx) 7868 brcms_b_mute(wlc->hw, true); 7869 7870 /* enable the RF Disable Delay timer */ 7871 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT); 7872 7873 /* 7874 * Initialize WME parameters; if they haven't been set by some other 7875 * mechanism (IOVar, etc) then read them from the hardware. 7876 */ 7877 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) { 7878 /* Uninitialized; read from HW */ 7879 int ac; 7880 7881 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 7882 wlc->wme_retries[ac] = 7883 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac)); 7884 } 7885 } 7886 7887 /* 7888 * The common driver entry routine. Error codes should be unique 7889 */ 7890 struct brcms_c_info * 7891 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit, 7892 bool piomode, uint *perr) 7893 { 7894 struct brcms_c_info *wlc; 7895 uint err = 0; 7896 uint i, j; 7897 struct brcms_pub *pub; 7898 7899 /* allocate struct brcms_c_info state and its substructures */ 7900 wlc = brcms_c_attach_malloc(unit, &err, 0); 7901 if (wlc == NULL) 7902 goto fail; 7903 wlc->wiphy = wl->wiphy; 7904 pub = wlc->pub; 7905 7906 #if defined(DEBUG) 7907 wlc_info_dbg = wlc; 7908 #endif 7909 7910 wlc->band = wlc->bandstate[0]; 7911 wlc->core = wlc->corestate; 7912 wlc->wl = wl; 7913 pub->unit = unit; 7914 pub->_piomode = piomode; 7915 wlc->bandinit_pending = false; 7916 wlc->beacon_template_virgin = true; 7917 7918 /* populate struct brcms_c_info with default values */ 7919 brcms_c_info_init(wlc, unit); 7920 7921 /* update sta/ap related parameters */ 7922 brcms_c_ap_upd(wlc); 7923 7924 /* 7925 * low level attach steps(all hw accesses go 7926 * inside, no more in rest of the attach) 7927 */ 7928 err = brcms_b_attach(wlc, core, unit, piomode); 7929 if (err) 7930 goto fail; 7931 7932 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF); 7933 7934 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band); 7935 7936 /* disable allowed duty cycle */ 7937 wlc->tx_duty_cycle_ofdm = 0; 7938 wlc->tx_duty_cycle_cck = 0; 7939 7940 brcms_c_stf_phy_chain_calc(wlc); 7941 7942 /* txchain 1: txant 0, txchain 2: txant 1 */ 7943 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1)) 7944 wlc->stf->txant = wlc->stf->hw_txchain - 1; 7945 7946 /* push to BMAC driver */ 7947 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain, 7948 wlc->stf->hw_rxchain); 7949 7950 /* pull up some info resulting from the low attach */ 7951 for (i = 0; i < NFIFO; i++) 7952 wlc->core->txavail[i] = wlc->hw->txavail[i]; 7953 7954 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN); 7955 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN); 7956 7957 for (j = 0; j < wlc->pub->_nbands; j++) { 7958 wlc->band = wlc->bandstate[j]; 7959 7960 if (!brcms_c_attach_stf_ant_init(wlc)) { 7961 err = 24; 7962 goto fail; 7963 } 7964 7965 /* default contention windows size limits */ 7966 wlc->band->CWmin = APHY_CWMIN; 7967 wlc->band->CWmax = PHY_CWMAX; 7968 7969 /* init gmode value */ 7970 if (wlc->band->bandtype == BRCM_BAND_2G) { 7971 wlc->band->gmode = GMODE_AUTO; 7972 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, 7973 wlc->band->gmode); 7974 } 7975 7976 /* init _n_enab supported mode */ 7977 if (BRCMS_PHY_11N_CAP(wlc->band)) { 7978 pub->_n_enab = SUPPORT_11N; 7979 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER, 7980 ((pub->_n_enab == 7981 SUPPORT_11N) ? WL_11N_2x2 : 7982 WL_11N_3x3)); 7983 } 7984 7985 /* init per-band default rateset, depend on band->gmode */ 7986 brcms_default_rateset(wlc, &wlc->band->defrateset); 7987 7988 /* fill in hw_rateset */ 7989 brcms_c_rateset_filter(&wlc->band->defrateset, 7990 &wlc->band->hw_rateset, false, 7991 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK, 7992 (bool) (wlc->pub->_n_enab & SUPPORT_11N)); 7993 } 7994 7995 /* 7996 * update antenna config due to 7997 * wlc->stf->txant/txchain/ant_rx_ovr change 7998 */ 7999 brcms_c_stf_phy_txant_upd(wlc); 8000 8001 /* attach each modules */ 8002 err = brcms_c_attach_module(wlc); 8003 if (err != 0) 8004 goto fail; 8005 8006 if (!brcms_c_timers_init(wlc, unit)) { 8007 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit, 8008 __func__); 8009 err = 32; 8010 goto fail; 8011 } 8012 8013 /* depend on rateset, gmode */ 8014 wlc->cmi = brcms_c_channel_mgr_attach(wlc); 8015 if (!wlc->cmi) { 8016 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed" 8017 "\n", unit, __func__); 8018 err = 33; 8019 goto fail; 8020 } 8021 8022 /* init default when all parameters are ready, i.e. ->rateset */ 8023 brcms_c_bss_default_init(wlc); 8024 8025 /* 8026 * Complete the wlc default state initializations.. 8027 */ 8028 8029 wlc->bsscfg->wlc = wlc; 8030 8031 wlc->mimoft = FT_HT; 8032 wlc->mimo_40txbw = AUTO; 8033 wlc->ofdm_40txbw = AUTO; 8034 wlc->cck_40txbw = AUTO; 8035 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G); 8036 8037 /* Set default values of SGI */ 8038 if (BRCMS_SGI_CAP_PHY(wlc)) { 8039 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 | 8040 BRCMS_N_SGI_40)); 8041 } else if (BRCMS_ISSSLPNPHY(wlc->band)) { 8042 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 | 8043 BRCMS_N_SGI_40)); 8044 } else { 8045 brcms_c_ht_update_sgi_rx(wlc, 0); 8046 } 8047 8048 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail); 8049 8050 if (perr) 8051 *perr = 0; 8052 8053 return wlc; 8054 8055 fail: 8056 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n", 8057 unit, __func__, err); 8058 if (wlc) 8059 brcms_c_detach(wlc); 8060 8061 if (perr) 8062 *perr = err; 8063 return NULL; 8064 } 8065