1*05491d2cSKalle Valo /*
2*05491d2cSKalle Valo * Copyright (c) 2011 Broadcom Corporation
3*05491d2cSKalle Valo *
4*05491d2cSKalle Valo * Permission to use, copy, modify, and/or distribute this software for any
5*05491d2cSKalle Valo * purpose with or without fee is hereby granted, provided that the above
6*05491d2cSKalle Valo * copyright notice and this permission notice appear in all copies.
7*05491d2cSKalle Valo *
8*05491d2cSKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*05491d2cSKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*05491d2cSKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11*05491d2cSKalle Valo * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*05491d2cSKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13*05491d2cSKalle Valo * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14*05491d2cSKalle Valo * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*05491d2cSKalle Valo */
16*05491d2cSKalle Valo
17*05491d2cSKalle Valo #ifndef _BRCM_AIUTILS_H_
18*05491d2cSKalle Valo #define _BRCM_AIUTILS_H_
19*05491d2cSKalle Valo
20*05491d2cSKalle Valo #include <linux/bcma/bcma.h>
21*05491d2cSKalle Valo
22*05491d2cSKalle Valo #include "types.h"
23*05491d2cSKalle Valo
24*05491d2cSKalle Valo /*
25*05491d2cSKalle Valo * SOC Interconnect Address Map.
26*05491d2cSKalle Valo * All regions may not exist on all chips.
27*05491d2cSKalle Valo */
28*05491d2cSKalle Valo /* each core gets 4Kbytes for registers */
29*05491d2cSKalle Valo #define SI_CORE_SIZE 0x1000
30*05491d2cSKalle Valo /*
31*05491d2cSKalle Valo * Max cores (this is arbitrary, for software
32*05491d2cSKalle Valo * convenience and could be changed if we
33*05491d2cSKalle Valo * make any larger chips
34*05491d2cSKalle Valo */
35*05491d2cSKalle Valo #define SI_MAXCORES 16
36*05491d2cSKalle Valo
37*05491d2cSKalle Valo /* Client Mode sb2pcitranslation2 size in bytes */
38*05491d2cSKalle Valo #define SI_PCI_DMA_SZ 0x40000000
39*05491d2cSKalle Valo
40*05491d2cSKalle Valo /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
41*05491d2cSKalle Valo #define SI_PCIE_DMA_H32 0x80000000
42*05491d2cSKalle Valo
43*05491d2cSKalle Valo /* chipcommon being the first core: */
44*05491d2cSKalle Valo #define SI_CC_IDX 0
45*05491d2cSKalle Valo
46*05491d2cSKalle Valo /* SOC Interconnect types (aka chip types) */
47*05491d2cSKalle Valo #define SOCI_AI 1
48*05491d2cSKalle Valo
49*05491d2cSKalle Valo /* A register that is common to all cores to
50*05491d2cSKalle Valo * communicate w/PMU regarding clock control.
51*05491d2cSKalle Valo */
52*05491d2cSKalle Valo #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
53*05491d2cSKalle Valo
54*05491d2cSKalle Valo /* clk_ctl_st register */
55*05491d2cSKalle Valo #define CCS_FORCEALP 0x00000001 /* force ALP request */
56*05491d2cSKalle Valo #define CCS_FORCEHT 0x00000002 /* force HT request */
57*05491d2cSKalle Valo #define CCS_FORCEILP 0x00000004 /* force ILP request */
58*05491d2cSKalle Valo #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
59*05491d2cSKalle Valo #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
60*05491d2cSKalle Valo #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
61*05491d2cSKalle Valo #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
62*05491d2cSKalle Valo #define CCS_ERSRC_REQ_SHIFT 8
63*05491d2cSKalle Valo #define CCS_ALPAVAIL 0x00010000 /* ALP is available */
64*05491d2cSKalle Valo #define CCS_HTAVAIL 0x00020000 /* HT is available */
65*05491d2cSKalle Valo #define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
66*05491d2cSKalle Valo #define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
67*05491d2cSKalle Valo #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
68*05491d2cSKalle Valo #define CCS_ERSRC_STS_SHIFT 24
69*05491d2cSKalle Valo
70*05491d2cSKalle Valo /* HT avail in chipc and pcmcia on 4328a0 */
71*05491d2cSKalle Valo #define CCS0_HTAVAIL 0x00010000
72*05491d2cSKalle Valo /* ALP avail in chipc and pcmcia on 4328a0 */
73*05491d2cSKalle Valo #define CCS0_ALPAVAIL 0x00020000
74*05491d2cSKalle Valo
75*05491d2cSKalle Valo /* Not really related to SOC Interconnect, but a couple of software
76*05491d2cSKalle Valo * conventions for the use the flash space:
77*05491d2cSKalle Valo */
78*05491d2cSKalle Valo
79*05491d2cSKalle Valo /* Minumum amount of flash we support */
80*05491d2cSKalle Valo #define FLASH_MIN 0x00020000 /* Minimum flash size */
81*05491d2cSKalle Valo
82*05491d2cSKalle Valo #define CC_SROM_OTP 0x800 /* SROM/OTP address space */
83*05491d2cSKalle Valo
84*05491d2cSKalle Valo /* gpiotimerval */
85*05491d2cSKalle Valo #define GPIO_ONTIME_SHIFT 16
86*05491d2cSKalle Valo
87*05491d2cSKalle Valo /* Fields in clkdiv */
88*05491d2cSKalle Valo #define CLKD_OTP 0x000f0000
89*05491d2cSKalle Valo #define CLKD_OTP_SHIFT 16
90*05491d2cSKalle Valo
91*05491d2cSKalle Valo /* dynamic clock control defines */
92*05491d2cSKalle Valo #define LPOMINFREQ 25000 /* low power oscillator min */
93*05491d2cSKalle Valo #define LPOMAXFREQ 43000 /* low power oscillator max */
94*05491d2cSKalle Valo #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
95*05491d2cSKalle Valo #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
96*05491d2cSKalle Valo #define PCIMINFREQ 25000000 /* 25 MHz */
97*05491d2cSKalle Valo #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
98*05491d2cSKalle Valo
99*05491d2cSKalle Valo #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
100*05491d2cSKalle Valo #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
101*05491d2cSKalle Valo
102*05491d2cSKalle Valo /* clkctl xtal what flags */
103*05491d2cSKalle Valo #define XTAL 0x1 /* primary crystal oscillator (2050) */
104*05491d2cSKalle Valo #define PLL 0x2 /* main chip pll */
105*05491d2cSKalle Valo
106*05491d2cSKalle Valo /* GPIO usage priorities */
107*05491d2cSKalle Valo #define GPIO_DRV_PRIORITY 0 /* Driver */
108*05491d2cSKalle Valo #define GPIO_APP_PRIORITY 1 /* Application */
109*05491d2cSKalle Valo #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
110*05491d2cSKalle Valo * reservation
111*05491d2cSKalle Valo */
112*05491d2cSKalle Valo
113*05491d2cSKalle Valo /* GPIO pull up/down */
114*05491d2cSKalle Valo #define GPIO_PULLUP 0
115*05491d2cSKalle Valo #define GPIO_PULLDN 1
116*05491d2cSKalle Valo
117*05491d2cSKalle Valo /* GPIO event regtype */
118*05491d2cSKalle Valo #define GPIO_REGEVT 0 /* GPIO register event */
119*05491d2cSKalle Valo #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
120*05491d2cSKalle Valo #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
121*05491d2cSKalle Valo
122*05491d2cSKalle Valo /* device path */
123*05491d2cSKalle Valo #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
124*05491d2cSKalle Valo
125*05491d2cSKalle Valo /* SI routine enumeration: to be used by update function with multiple hooks */
126*05491d2cSKalle Valo #define SI_DOATTACH 1
127*05491d2cSKalle Valo #define SI_PCIDOWN 2
128*05491d2cSKalle Valo #define SI_PCIUP 3
129*05491d2cSKalle Valo
130*05491d2cSKalle Valo /*
131*05491d2cSKalle Valo * Data structure to export all chip specific common variables
132*05491d2cSKalle Valo * public (read-only) portion of aiutils handle returned by si_attach()
133*05491d2cSKalle Valo */
134*05491d2cSKalle Valo struct si_pub {
135*05491d2cSKalle Valo int ccrev; /* chip common core rev */
136*05491d2cSKalle Valo u32 cccaps; /* chip common capabilities */
137*05491d2cSKalle Valo int pmurev; /* pmu core rev */
138*05491d2cSKalle Valo u32 pmucaps; /* pmu capabilities */
139*05491d2cSKalle Valo uint boardtype; /* board type */
140*05491d2cSKalle Valo uint boardvendor; /* board vendor */
141*05491d2cSKalle Valo uint chip; /* chip number */
142*05491d2cSKalle Valo uint chiprev; /* chip revision */
143*05491d2cSKalle Valo uint chippkg; /* chip package option */
144*05491d2cSKalle Valo };
145*05491d2cSKalle Valo
146*05491d2cSKalle Valo struct pci_dev;
147*05491d2cSKalle Valo
148*05491d2cSKalle Valo /* misc si info needed by some of the routines */
149*05491d2cSKalle Valo struct si_info {
150*05491d2cSKalle Valo struct si_pub pub; /* back plane public state (must be first) */
151*05491d2cSKalle Valo struct bcma_bus *icbus; /* handle to soc interconnect bus */
152*05491d2cSKalle Valo struct pci_dev *pcibus; /* handle to pci bus */
153*05491d2cSKalle Valo
154*05491d2cSKalle Valo u32 chipst; /* chip status */
155*05491d2cSKalle Valo };
156*05491d2cSKalle Valo
157*05491d2cSKalle Valo /*
158*05491d2cSKalle Valo * Many of the routines below take an 'sih' handle as their first arg.
159*05491d2cSKalle Valo * Allocate this by calling si_attach(). Free it by calling si_detach().
160*05491d2cSKalle Valo * At any one time, the sih is logically focused on one particular si core
161*05491d2cSKalle Valo * (the "current core").
162*05491d2cSKalle Valo * Use si_setcore() or si_setcoreidx() to change the association to another core
163*05491d2cSKalle Valo */
164*05491d2cSKalle Valo
165*05491d2cSKalle Valo
166*05491d2cSKalle Valo /* AMBA Interconnect exported externs */
167*05491d2cSKalle Valo u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
168*05491d2cSKalle Valo
169*05491d2cSKalle Valo /* === exported functions === */
170*05491d2cSKalle Valo struct si_pub *ai_attach(struct bcma_bus *pbus);
171*05491d2cSKalle Valo void ai_detach(struct si_pub *sih);
172*05491d2cSKalle Valo uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
173*05491d2cSKalle Valo void ai_clkctl_init(struct si_pub *sih);
174*05491d2cSKalle Valo u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
175*05491d2cSKalle Valo bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
176*05491d2cSKalle Valo bool ai_deviceremoved(struct si_pub *sih);
177*05491d2cSKalle Valo
178*05491d2cSKalle Valo /* Enable Ex-PA for 4313 */
179*05491d2cSKalle Valo void ai_epa_4313war(struct si_pub *sih);
180*05491d2cSKalle Valo
ai_get_cccaps(struct si_pub * sih)181*05491d2cSKalle Valo static inline u32 ai_get_cccaps(struct si_pub *sih)
182*05491d2cSKalle Valo {
183*05491d2cSKalle Valo return sih->cccaps;
184*05491d2cSKalle Valo }
185*05491d2cSKalle Valo
ai_get_pmurev(struct si_pub * sih)186*05491d2cSKalle Valo static inline int ai_get_pmurev(struct si_pub *sih)
187*05491d2cSKalle Valo {
188*05491d2cSKalle Valo return sih->pmurev;
189*05491d2cSKalle Valo }
190*05491d2cSKalle Valo
ai_get_pmucaps(struct si_pub * sih)191*05491d2cSKalle Valo static inline u32 ai_get_pmucaps(struct si_pub *sih)
192*05491d2cSKalle Valo {
193*05491d2cSKalle Valo return sih->pmucaps;
194*05491d2cSKalle Valo }
195*05491d2cSKalle Valo
ai_get_boardtype(struct si_pub * sih)196*05491d2cSKalle Valo static inline uint ai_get_boardtype(struct si_pub *sih)
197*05491d2cSKalle Valo {
198*05491d2cSKalle Valo return sih->boardtype;
199*05491d2cSKalle Valo }
200*05491d2cSKalle Valo
ai_get_boardvendor(struct si_pub * sih)201*05491d2cSKalle Valo static inline uint ai_get_boardvendor(struct si_pub *sih)
202*05491d2cSKalle Valo {
203*05491d2cSKalle Valo return sih->boardvendor;
204*05491d2cSKalle Valo }
205*05491d2cSKalle Valo
ai_get_chip_id(struct si_pub * sih)206*05491d2cSKalle Valo static inline uint ai_get_chip_id(struct si_pub *sih)
207*05491d2cSKalle Valo {
208*05491d2cSKalle Valo return sih->chip;
209*05491d2cSKalle Valo }
210*05491d2cSKalle Valo
ai_get_chiprev(struct si_pub * sih)211*05491d2cSKalle Valo static inline uint ai_get_chiprev(struct si_pub *sih)
212*05491d2cSKalle Valo {
213*05491d2cSKalle Valo return sih->chiprev;
214*05491d2cSKalle Valo }
215*05491d2cSKalle Valo
ai_get_chippkg(struct si_pub * sih)216*05491d2cSKalle Valo static inline uint ai_get_chippkg(struct si_pub *sih)
217*05491d2cSKalle Valo {
218*05491d2cSKalle Valo return sih->chippkg;
219*05491d2cSKalle Valo }
220*05491d2cSKalle Valo
221*05491d2cSKalle Valo #endif /* _BRCM_AIUTILS_H_ */
222