1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef BRCMFMAC_SDIO_H 18 #define BRCMFMAC_SDIO_H 19 20 #include <linux/skbuff.h> 21 #include <linux/firmware.h> 22 #include "firmware.h" 23 24 #define SDIO_FUNC_0 0 25 #define SDIO_FUNC_1 1 26 #define SDIO_FUNC_2 2 27 28 #define SDIOD_FBR_SIZE 0x100 29 30 /* io_en */ 31 #define SDIO_FUNC_ENABLE_1 0x02 32 #define SDIO_FUNC_ENABLE_2 0x04 33 34 /* io_rdys */ 35 #define SDIO_FUNC_READY_1 0x02 36 #define SDIO_FUNC_READY_2 0x04 37 38 /* intr_status */ 39 #define INTR_STATUS_FUNC1 0x2 40 #define INTR_STATUS_FUNC2 0x4 41 42 /* Maximum number of I/O funcs */ 43 #define SDIOD_MAX_IOFUNCS 7 44 45 /* mask of register map */ 46 #define REG_F0_REG_MASK 0x7FF 47 #define REG_F1_MISC_MASK 0x1FFFF 48 49 /* as of sdiod rev 0, supports 3 functions */ 50 #define SBSDIO_NUM_FUNCTION 3 51 52 /* function 0 vendor specific CCCR registers */ 53 54 #define SDIO_CCCR_BRCM_CARDCAP 0xf0 55 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT BIT(1) 56 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT BIT(2) 57 #define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC BIT(3) 58 59 #define SDIO_CCCR_BRCM_CARDCTRL 0xf1 60 #define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET BIT(1) 61 62 #define SDIO_CCCR_BRCM_SEPINT 0xf2 63 #define SDIO_CCCR_BRCM_SEPINT_MASK BIT(0) 64 #define SDIO_CCCR_BRCM_SEPINT_OE BIT(1) 65 #define SDIO_CCCR_BRCM_SEPINT_ACT_HI BIT(2) 66 67 /* function 1 miscellaneous registers */ 68 69 /* sprom command and status */ 70 #define SBSDIO_SPROM_CS 0x10000 71 /* sprom info register */ 72 #define SBSDIO_SPROM_INFO 0x10001 73 /* sprom indirect access data byte 0 */ 74 #define SBSDIO_SPROM_DATA_LOW 0x10002 75 /* sprom indirect access data byte 1 */ 76 #define SBSDIO_SPROM_DATA_HIGH 0x10003 77 /* sprom indirect access addr byte 0 */ 78 #define SBSDIO_SPROM_ADDR_LOW 0x10004 79 /* gpio select */ 80 #define SBSDIO_GPIO_SELECT 0x10005 81 /* gpio output */ 82 #define SBSDIO_GPIO_OUT 0x10006 83 /* gpio enable */ 84 #define SBSDIO_GPIO_EN 0x10007 85 /* rev < 7, watermark for sdio device */ 86 #define SBSDIO_WATERMARK 0x10008 87 /* control busy signal generation */ 88 #define SBSDIO_DEVICE_CTL 0x10009 89 90 /* SB Address Window Low (b15) */ 91 #define SBSDIO_FUNC1_SBADDRLOW 0x1000A 92 /* SB Address Window Mid (b23:b16) */ 93 #define SBSDIO_FUNC1_SBADDRMID 0x1000B 94 /* SB Address Window High (b31:b24) */ 95 #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C 96 /* Frame Control (frame term/abort) */ 97 #define SBSDIO_FUNC1_FRAMECTRL 0x1000D 98 /* ChipClockCSR (ALP/HT ctl/status) */ 99 #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E 100 /* SdioPullUp (on cmd, d0-d2) */ 101 #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F 102 /* Write Frame Byte Count Low */ 103 #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 104 /* Write Frame Byte Count High */ 105 #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A 106 /* Read Frame Byte Count Low */ 107 #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B 108 /* Read Frame Byte Count High */ 109 #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C 110 /* MesBusyCtl (rev 11) */ 111 #define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D 112 /* Sdio Core Rev 12 */ 113 #define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E 114 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1 115 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0 116 #define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2 117 #define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1 118 #define SBSDIO_FUNC1_SLEEPCSR 0x1001F 119 #define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1 120 #define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0 121 #define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1 122 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2 123 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1 124 125 #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ 126 #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */ 127 128 /* function 1 OCP space */ 129 130 /* sb offset addr is <= 15 bits, 32k */ 131 #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF 132 #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 133 /* with b15, maps to 32-bit SB access */ 134 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 135 136 /* Address bits from SBADDR regs */ 137 #define SBSDIO_SBWINDOW_MASK 0xffff8000 138 139 #define SDIOH_READ 0 /* Read request */ 140 #define SDIOH_WRITE 1 /* Write request */ 141 142 #define SDIOH_DATA_FIX 0 /* Fixed addressing */ 143 #define SDIOH_DATA_INC 1 /* Incremental addressing */ 144 145 /* internal return code */ 146 #define SUCCESS 0 147 #define ERROR 1 148 149 /* Packet alignment for most efficient SDIO (can change based on platform) */ 150 #define BRCMF_SDALIGN (1 << 6) 151 152 /* watchdog polling interval */ 153 #define BRCMF_WD_POLL msecs_to_jiffies(10) 154 155 /** 156 * enum brcmf_sdiod_state - the state of the bus. 157 * 158 * @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC. 159 * @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled. 160 * @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible. 161 */ 162 enum brcmf_sdiod_state { 163 BRCMF_SDIOD_DOWN, 164 BRCMF_SDIOD_DATA, 165 BRCMF_SDIOD_NOMEDIUM 166 }; 167 168 struct brcmf_sdreg { 169 int func; 170 int offset; 171 int value; 172 }; 173 174 struct brcmf_sdio; 175 struct brcmf_sdiod_freezer; 176 177 struct brcmf_sdio_dev { 178 struct sdio_func *func[SDIO_MAX_FUNCS]; 179 u8 num_funcs; /* Supported funcs on client */ 180 u32 sbwad; /* Save backplane window address */ 181 struct brcmf_sdio *bus; 182 struct device *dev; 183 struct brcmf_bus *bus_if; 184 struct brcmf_mp_device *settings; 185 bool oob_irq_requested; 186 bool sd_irq_requested; 187 bool irq_en; /* irq enable flags */ 188 spinlock_t irq_en_lock; 189 bool irq_wake; /* irq wake enable flags */ 190 bool sg_support; 191 uint max_request_size; 192 ushort max_segment_count; 193 uint max_segment_size; 194 uint txglomsz; 195 struct sg_table sgtable; 196 char fw_name[BRCMF_FW_NAME_LEN]; 197 char nvram_name[BRCMF_FW_NAME_LEN]; 198 bool wowl_enabled; 199 enum brcmf_sdiod_state state; 200 struct brcmf_sdiod_freezer *freezer; 201 }; 202 203 /* sdio core registers */ 204 struct sdpcmd_regs { 205 u32 corecontrol; /* 0x00, rev8 */ 206 u32 corestatus; /* rev8 */ 207 u32 PAD[1]; 208 u32 biststatus; /* rev8 */ 209 210 /* PCMCIA access */ 211 u16 pcmciamesportaladdr; /* 0x010, rev8 */ 212 u16 PAD[1]; 213 u16 pcmciamesportalmask; /* rev8 */ 214 u16 PAD[1]; 215 u16 pcmciawrframebc; /* rev8 */ 216 u16 PAD[1]; 217 u16 pcmciaunderflowtimer; /* rev8 */ 218 u16 PAD[1]; 219 220 /* interrupt */ 221 u32 intstatus; /* 0x020, rev8 */ 222 u32 hostintmask; /* rev8 */ 223 u32 intmask; /* rev8 */ 224 u32 sbintstatus; /* rev8 */ 225 u32 sbintmask; /* rev8 */ 226 u32 funcintmask; /* rev4 */ 227 u32 PAD[2]; 228 u32 tosbmailbox; /* 0x040, rev8 */ 229 u32 tohostmailbox; /* rev8 */ 230 u32 tosbmailboxdata; /* rev8 */ 231 u32 tohostmailboxdata; /* rev8 */ 232 233 /* synchronized access to registers in SDIO clock domain */ 234 u32 sdioaccess; /* 0x050, rev8 */ 235 u32 PAD[3]; 236 237 /* PCMCIA frame control */ 238 u8 pcmciaframectrl; /* 0x060, rev8 */ 239 u8 PAD[3]; 240 u8 pcmciawatermark; /* rev8 */ 241 u8 PAD[155]; 242 243 /* interrupt batching control */ 244 u32 intrcvlazy; /* 0x100, rev8 */ 245 u32 PAD[3]; 246 247 /* counters */ 248 u32 cmd52rd; /* 0x110, rev8 */ 249 u32 cmd52wr; /* rev8 */ 250 u32 cmd53rd; /* rev8 */ 251 u32 cmd53wr; /* rev8 */ 252 u32 abort; /* rev8 */ 253 u32 datacrcerror; /* rev8 */ 254 u32 rdoutofsync; /* rev8 */ 255 u32 wroutofsync; /* rev8 */ 256 u32 writebusy; /* rev8 */ 257 u32 readwait; /* rev8 */ 258 u32 readterm; /* rev8 */ 259 u32 writeterm; /* rev8 */ 260 u32 PAD[40]; 261 u32 clockctlstatus; /* rev8 */ 262 u32 PAD[7]; 263 264 u32 PAD[128]; /* DMA engines */ 265 266 /* SDIO/PCMCIA CIS region */ 267 char cis[512]; /* 0x400-0x5ff, rev6 */ 268 269 /* PCMCIA function control registers */ 270 char pcmciafcr[256]; /* 0x600-6ff, rev6 */ 271 u16 PAD[55]; 272 273 /* PCMCIA backplane access */ 274 u16 backplanecsr; /* 0x76E, rev6 */ 275 u16 backplaneaddr0; /* rev6 */ 276 u16 backplaneaddr1; /* rev6 */ 277 u16 backplaneaddr2; /* rev6 */ 278 u16 backplaneaddr3; /* rev6 */ 279 u16 backplanedata0; /* rev6 */ 280 u16 backplanedata1; /* rev6 */ 281 u16 backplanedata2; /* rev6 */ 282 u16 backplanedata3; /* rev6 */ 283 u16 PAD[31]; 284 285 /* sprom "size" & "blank" info */ 286 u16 spromstatus; /* 0x7BE, rev2 */ 287 u32 PAD[464]; 288 289 u16 PAD[0x80]; 290 }; 291 292 /* Register/deregister interrupt handler. */ 293 int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev); 294 void brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev); 295 296 /* SDIO device register access interface */ 297 /* Accessors for SDIO Function 0 */ 298 #define brcmf_sdiod_func0_rb(sdiodev, addr, r) \ 299 sdio_readb((sdiodev)->func[0], (addr), (r)) 300 301 #define brcmf_sdiod_func0_wb(sdiodev, addr, v, ret) \ 302 sdio_writeb((sdiodev)->func[0], (v), (addr), (ret)) 303 304 /* Accessors for SDIO Function 1 */ 305 #define brcmf_sdiod_readb(sdiodev, addr, r) \ 306 sdio_readb((sdiodev)->func[1], (addr), (r)) 307 308 #define brcmf_sdiod_writeb(sdiodev, addr, v, ret) \ 309 sdio_writeb((sdiodev)->func[1], (v), (addr), (ret)) 310 311 u32 brcmf_sdiod_readl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret); 312 void brcmf_sdiod_writel(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data, 313 int *ret); 314 315 /* Buffer transfer to/from device (client) core via cmd53. 316 * fn: function number 317 * flags: backplane width, address increment, sync/async 318 * buf: pointer to memory data buffer 319 * nbytes: number of bytes to transfer to/from buf 320 * pkt: pointer to packet associated with buf (if any) 321 * complete: callback function for command completion (async only) 322 * handle: handle for completion callback (first arg in callback) 323 * Returns 0 or error code. 324 * NOTE: Async operation is not currently supported. 325 */ 326 int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev, 327 struct sk_buff_head *pktq); 328 int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); 329 330 int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt); 331 int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); 332 int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev, 333 struct sk_buff_head *pktq, uint totlen); 334 335 /* Flags bits */ 336 337 /* Four-byte target (backplane) width (vs. two-byte) */ 338 #define SDIO_REQ_4BYTE 0x1 339 /* Fixed address (FIFO) (vs. incrementing address) */ 340 #define SDIO_REQ_FIXED 0x2 341 342 /* Read/write to memory block (F1, no FIFO) via CMD53 (sync only). 343 * rw: read or write (0/1) 344 * addr: direct SDIO address 345 * buf: pointer to memory data buffer 346 * nbytes: number of bytes to transfer to/from buf 347 * Returns 0 or error code. 348 */ 349 int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address, 350 u8 *data, uint size); 351 352 /* Issue an abort to the specified function */ 353 int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, u8 fn); 354 void brcmf_sdiod_sgtable_alloc(struct brcmf_sdio_dev *sdiodev); 355 void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev, 356 enum brcmf_sdiod_state state); 357 #ifdef CONFIG_PM_SLEEP 358 bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev); 359 void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev); 360 void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev); 361 void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev); 362 #else 363 static inline bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev) 364 { 365 return false; 366 } 367 static inline void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev) 368 { 369 } 370 static inline void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev) 371 { 372 } 373 static inline void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev) 374 { 375 } 376 #endif /* CONFIG_PM_SLEEP */ 377 378 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev); 379 void brcmf_sdio_remove(struct brcmf_sdio *bus); 380 void brcmf_sdio_isr(struct brcmf_sdio *bus); 381 382 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active); 383 void brcmf_sdio_wowl_config(struct device *dev, bool enabled); 384 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep); 385 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus); 386 387 #endif /* BRCMFMAC_SDIO_H */ 388