1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/types.h> 18 #include <linux/atomic.h> 19 #include <linux/kernel.h> 20 #include <linux/kthread.h> 21 #include <linux/printk.h> 22 #include <linux/pci_ids.h> 23 #include <linux/netdevice.h> 24 #include <linux/interrupt.h> 25 #include <linux/sched/signal.h> 26 #include <linux/mmc/sdio.h> 27 #include <linux/mmc/sdio_ids.h> 28 #include <linux/mmc/sdio_func.h> 29 #include <linux/mmc/card.h> 30 #include <linux/semaphore.h> 31 #include <linux/firmware.h> 32 #include <linux/module.h> 33 #include <linux/bcma/bcma.h> 34 #include <linux/debugfs.h> 35 #include <linux/vmalloc.h> 36 #include <asm/unaligned.h> 37 #include <defs.h> 38 #include <brcmu_wifi.h> 39 #include <brcmu_utils.h> 40 #include <brcm_hw_ids.h> 41 #include <soc.h> 42 #include "sdio.h" 43 #include "chip.h" 44 #include "firmware.h" 45 #include "core.h" 46 #include "common.h" 47 #include "bcdc.h" 48 49 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500) 50 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500) 51 52 #ifdef DEBUG 53 54 #define BRCMF_TRAP_INFO_SIZE 80 55 56 #define CBUF_LEN (128) 57 58 /* Device console log buffer state */ 59 #define CONSOLE_BUFFER_MAX 2024 60 61 struct rte_log_le { 62 __le32 buf; /* Can't be pointer on (64-bit) hosts */ 63 __le32 buf_size; 64 __le32 idx; 65 char *_buf_compat; /* Redundant pointer for backward compat. */ 66 }; 67 68 struct rte_console { 69 /* Virtual UART 70 * When there is no UART (e.g. Quickturn), 71 * the host should write a complete 72 * input line directly into cbuf and then write 73 * the length into vcons_in. 74 * This may also be used when there is a real UART 75 * (at risk of conflicting with 76 * the real UART). vcons_out is currently unused. 77 */ 78 uint vcons_in; 79 uint vcons_out; 80 81 /* Output (logging) buffer 82 * Console output is written to a ring buffer log_buf at index log_idx. 83 * The host may read the output when it sees log_idx advance. 84 * Output will be lost if the output wraps around faster than the host 85 * polls. 86 */ 87 struct rte_log_le log_le; 88 89 /* Console input line buffer 90 * Characters are read one at a time into cbuf 91 * until <CR> is received, then 92 * the buffer is processed as a command line. 93 * Also used for virtual UART. 94 */ 95 uint cbuf_idx; 96 char cbuf[CBUF_LEN]; 97 }; 98 99 #endif /* DEBUG */ 100 #include <chipcommon.h> 101 102 #include "bus.h" 103 #include "debug.h" 104 #include "tracepoint.h" 105 106 #define TXQLEN 2048 /* bulk tx queue length */ 107 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ 108 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ 109 #define PRIOMASK 7 110 111 #define TXRETRIES 2 /* # of retries for tx frames */ 112 113 #define BRCMF_RXBOUND 50 /* Default for max rx frames in 114 one scheduling */ 115 116 #define BRCMF_TXBOUND 20 /* Default for max tx frames in 117 one scheduling */ 118 119 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ 120 121 #define MEMBLOCK 2048 /* Block size used for downloading 122 of dongle image */ 123 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold 124 biggest possible glom */ 125 126 #define BRCMF_FIRSTREAD (1 << 6) 127 128 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */ 129 130 /* SBSDIO_DEVICE_CTL */ 131 132 /* 1: device will assert busy signal when receiving CMD53 */ 133 #define SBSDIO_DEVCTL_SETBUSY 0x01 134 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ 135 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 136 /* 1: mask all interrupts to host except the chipActive (rev 8) */ 137 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 138 /* 1: isolate internal sdio signals, put external pads in tri-state; requires 139 * sdio bus power cycle to clear (rev 9) */ 140 #define SBSDIO_DEVCTL_PADS_ISO 0x08 141 /* Force SD->SB reset mapping (rev 11) */ 142 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 143 /* Determined by CoreControl bit */ 144 #define SBSDIO_DEVCTL_RST_CORECTL 0x00 145 /* Force backplane reset */ 146 #define SBSDIO_DEVCTL_RST_BPRESET 0x10 147 /* Force no backplane reset */ 148 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 149 150 /* direct(mapped) cis space */ 151 152 /* MAPPED common CIS address */ 153 #define SBSDIO_CIS_BASE_COMMON 0x1000 154 /* maximum bytes in one CIS */ 155 #define SBSDIO_CIS_SIZE_LIMIT 0x200 156 /* cis offset addr is < 17 bits */ 157 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF 158 159 /* manfid tuple length, include tuple, link bytes */ 160 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 161 162 #define SD_REG(field) \ 163 (offsetof(struct sdpcmd_regs, field)) 164 165 /* SDIO function 1 register CHIPCLKCSR */ 166 /* Force ALP request to backplane */ 167 #define SBSDIO_FORCE_ALP 0x01 168 /* Force HT request to backplane */ 169 #define SBSDIO_FORCE_HT 0x02 170 /* Force ILP request to backplane */ 171 #define SBSDIO_FORCE_ILP 0x04 172 /* Make ALP ready (power up xtal) */ 173 #define SBSDIO_ALP_AVAIL_REQ 0x08 174 /* Make HT ready (power up PLL) */ 175 #define SBSDIO_HT_AVAIL_REQ 0x10 176 /* Squelch clock requests from HW */ 177 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 178 /* Status: ALP is ready */ 179 #define SBSDIO_ALP_AVAIL 0x40 180 /* Status: HT is ready */ 181 #define SBSDIO_HT_AVAIL 0x80 182 #define SBSDIO_CSR_MASK 0x1F 183 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 184 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 185 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 186 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 187 #define SBSDIO_CLKAV(regval, alponly) \ 188 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 189 190 /* intstatus */ 191 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 192 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 193 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 194 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 195 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 196 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 197 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 198 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 199 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 200 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 201 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 202 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 203 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 204 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 205 #define I_PC (1 << 10) /* descriptor error */ 206 #define I_PD (1 << 11) /* data error */ 207 #define I_DE (1 << 12) /* Descriptor protocol Error */ 208 #define I_RU (1 << 13) /* Receive descriptor Underflow */ 209 #define I_RO (1 << 14) /* Receive fifo Overflow */ 210 #define I_XU (1 << 15) /* Transmit fifo Underflow */ 211 #define I_RI (1 << 16) /* Receive Interrupt */ 212 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 213 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 214 #define I_XI (1 << 24) /* Transmit Interrupt */ 215 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 216 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 217 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 218 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 219 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ 220 #define I_SRESET (1 << 30) /* CCCR RES interrupt */ 221 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 222 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 223 #define I_DMA (I_RI | I_XI | I_ERRORS) 224 225 /* corecontrol */ 226 #define CC_CISRDY (1 << 0) /* CIS Ready */ 227 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ 228 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 229 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ 230 #define CC_XMTDATAAVAIL_MODE (1 << 4) 231 #define CC_XMTDATAAVAIL_CTRL (1 << 5) 232 233 /* SDA_FRAMECTRL */ 234 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 235 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 236 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ 237 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ 238 239 /* 240 * Software allocation of To SB Mailbox resources 241 */ 242 243 /* tosbmailbox bits corresponding to intstatus bits */ 244 #define SMB_NAK (1 << 0) /* Frame NAK */ 245 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ 246 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ 247 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ 248 249 /* tosbmailboxdata */ 250 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ 251 252 /* 253 * Software allocation of To Host Mailbox resources 254 */ 255 256 /* intstatus bits */ 257 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ 258 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ 259 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ 260 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ 261 262 /* tohostmailboxdata */ 263 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */ 264 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */ 265 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */ 266 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */ 267 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */ 268 269 #define HMB_DATA_FCDATA_MASK 0xff000000 270 #define HMB_DATA_FCDATA_SHIFT 24 271 272 #define HMB_DATA_VERSION_MASK 0x00ff0000 273 #define HMB_DATA_VERSION_SHIFT 16 274 275 /* 276 * Software-defined protocol header 277 */ 278 279 /* Current protocol version */ 280 #define SDPCM_PROT_VERSION 4 281 282 /* 283 * Shared structure between dongle and the host. 284 * The structure contains pointers to trap or assert information. 285 */ 286 #define SDPCM_SHARED_VERSION 0x0003 287 #define SDPCM_SHARED_VERSION_MASK 0x00FF 288 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 289 #define SDPCM_SHARED_ASSERT 0x0200 290 #define SDPCM_SHARED_TRAP 0x0400 291 292 /* Space for header read, limit for data packets */ 293 #define MAX_HDR_READ (1 << 6) 294 #define MAX_RX_DATASZ 2048 295 296 /* Bump up limit on waiting for HT to account for first startup; 297 * if the image is doing a CRC calculation before programming the PMU 298 * for HT availability, it could take a couple hundred ms more, so 299 * max out at a 1 second (1000000us). 300 */ 301 #undef PMU_MAX_TRANSITION_DLY 302 #define PMU_MAX_TRANSITION_DLY 1000000 303 304 /* Value for ChipClockCSR during initial setup */ 305 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ 306 SBSDIO_ALP_AVAIL_REQ) 307 308 /* Flags for SDH calls */ 309 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 310 311 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change 312 * when idle 313 */ 314 #define BRCMF_IDLE_INTERVAL 1 315 316 #define KSO_WAIT_US 50 317 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) 318 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5 319 320 /* 321 * Conversion of 802.1D priority to precedence level 322 */ 323 static uint prio2prec(u32 prio) 324 { 325 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ? 326 (prio^2) : prio; 327 } 328 329 #ifdef DEBUG 330 /* Device console log buffer state */ 331 struct brcmf_console { 332 uint count; /* Poll interval msec counter */ 333 uint log_addr; /* Log struct address (fixed) */ 334 struct rte_log_le log_le; /* Log struct (host copy) */ 335 uint bufsize; /* Size of log buffer */ 336 u8 *buf; /* Log buffer (host copy) */ 337 uint last; /* Last buffer read index */ 338 }; 339 340 struct brcmf_trap_info { 341 __le32 type; 342 __le32 epc; 343 __le32 cpsr; 344 __le32 spsr; 345 __le32 r0; /* a1 */ 346 __le32 r1; /* a2 */ 347 __le32 r2; /* a3 */ 348 __le32 r3; /* a4 */ 349 __le32 r4; /* v1 */ 350 __le32 r5; /* v2 */ 351 __le32 r6; /* v3 */ 352 __le32 r7; /* v4 */ 353 __le32 r8; /* v5 */ 354 __le32 r9; /* sb/v6 */ 355 __le32 r10; /* sl/v7 */ 356 __le32 r11; /* fp/v8 */ 357 __le32 r12; /* ip */ 358 __le32 r13; /* sp */ 359 __le32 r14; /* lr */ 360 __le32 pc; /* r15 */ 361 }; 362 #endif /* DEBUG */ 363 364 struct sdpcm_shared { 365 u32 flags; 366 u32 trap_addr; 367 u32 assert_exp_addr; 368 u32 assert_file_addr; 369 u32 assert_line; 370 u32 console_addr; /* Address of struct rte_console */ 371 u32 msgtrace_addr; 372 u8 tag[32]; 373 u32 brpt_addr; 374 }; 375 376 struct sdpcm_shared_le { 377 __le32 flags; 378 __le32 trap_addr; 379 __le32 assert_exp_addr; 380 __le32 assert_file_addr; 381 __le32 assert_line; 382 __le32 console_addr; /* Address of struct rte_console */ 383 __le32 msgtrace_addr; 384 u8 tag[32]; 385 __le32 brpt_addr; 386 }; 387 388 /* dongle SDIO bus specific header info */ 389 struct brcmf_sdio_hdrinfo { 390 u8 seq_num; 391 u8 channel; 392 u16 len; 393 u16 len_left; 394 u16 len_nxtfrm; 395 u8 dat_offset; 396 bool lastfrm; 397 u16 tail_pad; 398 }; 399 400 /* 401 * hold counter variables 402 */ 403 struct brcmf_sdio_count { 404 uint intrcount; /* Count of device interrupt callbacks */ 405 uint lastintrs; /* Count as of last watchdog timer */ 406 uint pollcnt; /* Count of active polls */ 407 uint regfails; /* Count of R_REG failures */ 408 uint tx_sderrs; /* Count of tx attempts with sd errors */ 409 uint fcqueued; /* Tx packets that got queued */ 410 uint rxrtx; /* Count of rtx requests (NAK to dongle) */ 411 uint rx_toolong; /* Receive frames too long to receive */ 412 uint rxc_errors; /* SDIO errors when reading control frames */ 413 uint rx_hdrfail; /* SDIO errors on header reads */ 414 uint rx_badhdr; /* Bad received headers (roosync?) */ 415 uint rx_badseq; /* Mismatched rx sequence number */ 416 uint fc_rcvd; /* Number of flow-control events received */ 417 uint fc_xoff; /* Number which turned on flow-control */ 418 uint fc_xon; /* Number which turned off flow-control */ 419 uint rxglomfail; /* Failed deglom attempts */ 420 uint rxglomframes; /* Number of glom frames (superframes) */ 421 uint rxglompkts; /* Number of packets from glom frames */ 422 uint f2rxhdrs; /* Number of header reads */ 423 uint f2rxdata; /* Number of frame data reads */ 424 uint f2txdata; /* Number of f2 frame writes */ 425 uint f1regdata; /* Number of f1 register accesses */ 426 uint tickcnt; /* Number of watchdog been schedule */ 427 ulong tx_ctlerrs; /* Err of sending ctrl frames */ 428 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ 429 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ 430 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ 431 ulong rx_readahead_cnt; /* packets where header read-ahead was used */ 432 }; 433 434 /* misc chip info needed by some of the routines */ 435 /* Private data for SDIO bus interaction */ 436 struct brcmf_sdio { 437 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ 438 struct brcmf_chip *ci; /* Chip info struct */ 439 struct brcmf_core *sdio_core; /* sdio core info struct */ 440 441 u32 hostintmask; /* Copy of Host Interrupt Mask */ 442 atomic_t intstatus; /* Intstatus bits (events) pending */ 443 atomic_t fcstate; /* State of dongle flow-control */ 444 445 uint blocksize; /* Block size of SDIO transfers */ 446 uint roundup; /* Max roundup limit */ 447 448 struct pktq txq; /* Queue length used for flow-control */ 449 u8 flowcontrol; /* per prio flow control bitmask */ 450 u8 tx_seq; /* Transmit sequence number (next) */ 451 u8 tx_max; /* Maximum transmit sequence allowed */ 452 453 u8 *hdrbuf; /* buffer for handling rx frame */ 454 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ 455 u8 rx_seq; /* Receive sequence number (expected) */ 456 struct brcmf_sdio_hdrinfo cur_read; 457 /* info of current read frame */ 458 bool rxskip; /* Skip receive (awaiting NAK ACK) */ 459 bool rxpending; /* Data frame pending in dongle */ 460 461 uint rxbound; /* Rx frames to read before resched */ 462 uint txbound; /* Tx frames to send before resched */ 463 uint txminmax; 464 465 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 466 struct sk_buff_head glom; /* Packet list for glommed superframe */ 467 468 u8 *rxbuf; /* Buffer for receiving control packets */ 469 uint rxblen; /* Allocated length of rxbuf */ 470 u8 *rxctl; /* Aligned pointer into rxbuf */ 471 u8 *rxctl_orig; /* pointer for freeing rxctl */ 472 uint rxlen; /* Length of valid data in buffer */ 473 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ 474 475 u8 sdpcm_ver; /* Bus protocol reported by dongle */ 476 477 bool intr; /* Use interrupts */ 478 bool poll; /* Use polling */ 479 atomic_t ipend; /* Device interrupt is pending */ 480 uint spurious; /* Count of spurious interrupts */ 481 uint pollrate; /* Ticks between device polls */ 482 uint polltick; /* Tick counter */ 483 484 #ifdef DEBUG 485 uint console_interval; 486 struct brcmf_console console; /* Console output polling support */ 487 uint console_addr; /* Console address from shared struct */ 488 #endif /* DEBUG */ 489 490 uint clkstate; /* State of sd and backplane clock(s) */ 491 s32 idletime; /* Control for activity timeout */ 492 s32 idlecount; /* Activity timeout counter */ 493 s32 idleclock; /* How to set bus driver when idle */ 494 bool rxflow_mode; /* Rx flow control mode */ 495 bool rxflow; /* Is rx flow control on */ 496 bool alp_only; /* Don't use HT clock (ALP only) */ 497 498 u8 *ctrl_frame_buf; 499 u16 ctrl_frame_len; 500 bool ctrl_frame_stat; 501 int ctrl_frame_err; 502 503 spinlock_t txq_lock; /* protect bus->txq */ 504 wait_queue_head_t ctrl_wait; 505 wait_queue_head_t dcmd_resp_wait; 506 507 struct timer_list timer; 508 struct completion watchdog_wait; 509 struct task_struct *watchdog_tsk; 510 bool wd_active; 511 512 struct workqueue_struct *brcmf_wq; 513 struct work_struct datawork; 514 bool dpc_triggered; 515 bool dpc_running; 516 517 bool txoff; /* Transmit flow-controlled */ 518 struct brcmf_sdio_count sdcnt; 519 bool sr_enabled; /* SaveRestore enabled */ 520 bool sleeping; 521 522 u8 tx_hdrlen; /* sdio bus header length for tx packet */ 523 bool txglom; /* host tx glomming enable flag */ 524 u16 head_align; /* buffer pointer alignment */ 525 u16 sgentry_align; /* scatter-gather buffer alignment */ 526 }; 527 528 /* clkstate */ 529 #define CLK_NONE 0 530 #define CLK_SDONLY 1 531 #define CLK_PENDING 2 532 #define CLK_AVAIL 3 533 534 #ifdef DEBUG 535 static int qcount[NUMPRIO]; 536 #endif /* DEBUG */ 537 538 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ 539 540 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) 541 542 /* Limit on rounding up frames */ 543 static const uint max_roundup = 512; 544 545 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 546 #define ALIGNMENT 8 547 #else 548 #define ALIGNMENT 4 549 #endif 550 551 enum brcmf_sdio_frmtype { 552 BRCMF_SDIO_FT_NORMAL, 553 BRCMF_SDIO_FT_SUPER, 554 BRCMF_SDIO_FT_SUB, 555 }; 556 557 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu)) 558 559 /* SDIO Pad drive strength to select value mappings */ 560 struct sdiod_drive_str { 561 u8 strength; /* Pad Drive Strength in mA */ 562 u8 sel; /* Chip-specific select value */ 563 }; 564 565 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ 566 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { 567 {32, 0x6}, 568 {26, 0x7}, 569 {22, 0x4}, 570 {16, 0x5}, 571 {12, 0x2}, 572 {8, 0x3}, 573 {4, 0x0}, 574 {0, 0x1} 575 }; 576 577 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ 578 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { 579 {6, 0x7}, 580 {5, 0x6}, 581 {4, 0x5}, 582 {3, 0x4}, 583 {2, 0x2}, 584 {1, 0x1}, 585 {0, 0x0} 586 }; 587 588 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ 589 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { 590 {3, 0x3}, 591 {2, 0x2}, 592 {1, 0x1}, 593 {0, 0x0} }; 594 595 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ 596 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { 597 {16, 0x7}, 598 {12, 0x5}, 599 {8, 0x3}, 600 {4, 0x1} 601 }; 602 603 BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt"); 604 BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin", 605 "brcmfmac43241b0-sdio.txt"); 606 BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin", 607 "brcmfmac43241b4-sdio.txt"); 608 BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin", 609 "brcmfmac43241b5-sdio.txt"); 610 BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt"); 611 BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt"); 612 BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt"); 613 BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt"); 614 BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt"); 615 BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt"); 616 BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt"); 617 BRCMF_FW_NVRAM_DEF(43430A0, "brcmfmac43430a0-sdio.bin", "brcmfmac43430a0-sdio.txt"); 618 /* Note the names are not postfixed with a1 for backward compatibility */ 619 BRCMF_FW_NVRAM_DEF(43430A1, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt"); 620 BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt"); 621 BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt"); 622 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-sdio.bin", "brcmfmac4356-sdio.txt"); 623 BRCMF_FW_NVRAM_DEF(4373, "brcmfmac4373-sdio.bin", "brcmfmac4373-sdio.txt"); 624 625 static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { 626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143), 627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0), 628 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4), 629 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5), 630 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329), 631 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330), 632 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334), 633 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340), 634 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340), 635 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335), 636 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362), 637 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), 638 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0), 639 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFE, 43430A1), 640 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455), 641 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354), 642 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 643 BRCMF_FW_NVRAM_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373) 644 }; 645 646 static void pkt_align(struct sk_buff *p, int len, int align) 647 { 648 uint datalign; 649 datalign = (unsigned long)(p->data); 650 datalign = roundup(datalign, (align)) - datalign; 651 if (datalign) 652 skb_pull(p, datalign); 653 __skb_trim(p, len); 654 } 655 656 /* To check if there's window offered */ 657 static bool data_ok(struct brcmf_sdio *bus) 658 { 659 return (u8)(bus->tx_max - bus->tx_seq) != 0 && 660 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0; 661 } 662 663 /* 664 * Reads a register in the SDIO hardware block. This block occupies a series of 665 * adresses on the 32 bit backplane bus. 666 */ 667 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset) 668 { 669 struct brcmf_core *core = bus->sdio_core; 670 int ret; 671 672 *regvar = brcmf_sdiod_readl(bus->sdiodev, core->base + offset, &ret); 673 674 return ret; 675 } 676 677 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) 678 { 679 struct brcmf_core *core = bus->sdio_core; 680 int ret; 681 682 brcmf_sdiod_writel(bus->sdiodev, core->base + reg_offset, regval, &ret); 683 684 return ret; 685 } 686 687 static int 688 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) 689 { 690 u8 wr_val = 0, rd_val, cmp_val, bmask; 691 int err = 0; 692 int err_cnt = 0; 693 int try_cnt = 0; 694 695 brcmf_dbg(TRACE, "Enter: on=%d\n", on); 696 697 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 698 /* 1st KSO write goes to AOS wake up core if device is asleep */ 699 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err); 700 701 if (on) { 702 /* device WAKEUP through KSO: 703 * write bit 0 & read back until 704 * both bits 0 (kso bit) & 1 (dev on status) are set 705 */ 706 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | 707 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; 708 bmask = cmp_val; 709 usleep_range(2000, 3000); 710 } else { 711 /* Put device to sleep, turn off KSO */ 712 cmp_val = 0; 713 /* only check for bit0, bit1(dev on status) may not 714 * get cleared right away 715 */ 716 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; 717 } 718 719 do { 720 /* reliable KSO bit set/clr: 721 * the sdiod sleep write access is synced to PMU 32khz clk 722 * just one write attempt may fail, 723 * read it back until it matches written value 724 */ 725 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 726 &err); 727 if (!err) { 728 if ((rd_val & bmask) == cmp_val) 729 break; 730 err_cnt = 0; 731 } 732 /* bail out upon subsequent access errors */ 733 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS)) 734 break; 735 736 udelay(KSO_WAIT_US); 737 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, 738 &err); 739 740 } while (try_cnt++ < MAX_KSO_ATTEMPTS); 741 742 if (try_cnt > 2) 743 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, 744 rd_val, err); 745 746 if (try_cnt > MAX_KSO_ATTEMPTS) 747 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); 748 749 return err; 750 } 751 752 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) 753 754 /* Turn backplane clock on or off */ 755 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) 756 { 757 int err; 758 u8 clkctl, clkreq, devctl; 759 unsigned long timeout; 760 761 brcmf_dbg(SDIO, "Enter\n"); 762 763 clkctl = 0; 764 765 if (bus->sr_enabled) { 766 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); 767 return 0; 768 } 769 770 if (on) { 771 /* Request HT Avail */ 772 clkreq = 773 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 774 775 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 776 clkreq, &err); 777 if (err) { 778 brcmf_err("HT Avail request error: %d\n", err); 779 return -EBADE; 780 } 781 782 /* Check current status */ 783 clkctl = brcmf_sdiod_readb(bus->sdiodev, 784 SBSDIO_FUNC1_CHIPCLKCSR, &err); 785 if (err) { 786 brcmf_err("HT Avail read error: %d\n", err); 787 return -EBADE; 788 } 789 790 /* Go to pending and await interrupt if appropriate */ 791 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { 792 /* Allow only clock-available interrupt */ 793 devctl = brcmf_sdiod_readb(bus->sdiodev, 794 SBSDIO_DEVICE_CTL, &err); 795 if (err) { 796 brcmf_err("Devctl error setting CA: %d\n", err); 797 return -EBADE; 798 } 799 800 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; 801 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 802 devctl, &err); 803 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); 804 bus->clkstate = CLK_PENDING; 805 806 return 0; 807 } else if (bus->clkstate == CLK_PENDING) { 808 /* Cancel CA-only interrupt filter */ 809 devctl = brcmf_sdiod_readb(bus->sdiodev, 810 SBSDIO_DEVICE_CTL, &err); 811 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 812 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 813 devctl, &err); 814 } 815 816 /* Otherwise, wait here (polling) for HT Avail */ 817 timeout = jiffies + 818 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); 819 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 820 clkctl = brcmf_sdiod_readb(bus->sdiodev, 821 SBSDIO_FUNC1_CHIPCLKCSR, 822 &err); 823 if (time_after(jiffies, timeout)) 824 break; 825 else 826 usleep_range(5000, 10000); 827 } 828 if (err) { 829 brcmf_err("HT Avail request error: %d\n", err); 830 return -EBADE; 831 } 832 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 833 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", 834 PMU_MAX_TRANSITION_DLY, clkctl); 835 return -EBADE; 836 } 837 838 /* Mark clock available */ 839 bus->clkstate = CLK_AVAIL; 840 brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); 841 842 #if defined(DEBUG) 843 if (!bus->alp_only) { 844 if (SBSDIO_ALPONLY(clkctl)) 845 brcmf_err("HT Clock should be on\n"); 846 } 847 #endif /* defined (DEBUG) */ 848 849 } else { 850 clkreq = 0; 851 852 if (bus->clkstate == CLK_PENDING) { 853 /* Cancel CA-only interrupt filter */ 854 devctl = brcmf_sdiod_readb(bus->sdiodev, 855 SBSDIO_DEVICE_CTL, &err); 856 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 857 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 858 devctl, &err); 859 } 860 861 bus->clkstate = CLK_SDONLY; 862 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 863 clkreq, &err); 864 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); 865 if (err) { 866 brcmf_err("Failed access turning clock off: %d\n", 867 err); 868 return -EBADE; 869 } 870 } 871 return 0; 872 } 873 874 /* Change idle/active SD state */ 875 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) 876 { 877 brcmf_dbg(SDIO, "Enter\n"); 878 879 if (on) 880 bus->clkstate = CLK_SDONLY; 881 else 882 bus->clkstate = CLK_NONE; 883 884 return 0; 885 } 886 887 /* Transition SD and backplane clock readiness */ 888 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) 889 { 890 #ifdef DEBUG 891 uint oldstate = bus->clkstate; 892 #endif /* DEBUG */ 893 894 brcmf_dbg(SDIO, "Enter\n"); 895 896 /* Early exit if we're already there */ 897 if (bus->clkstate == target) 898 return 0; 899 900 switch (target) { 901 case CLK_AVAIL: 902 /* Make sure SD clock is available */ 903 if (bus->clkstate == CLK_NONE) 904 brcmf_sdio_sdclk(bus, true); 905 /* Now request HT Avail on the backplane */ 906 brcmf_sdio_htclk(bus, true, pendok); 907 break; 908 909 case CLK_SDONLY: 910 /* Remove HT request, or bring up SD clock */ 911 if (bus->clkstate == CLK_NONE) 912 brcmf_sdio_sdclk(bus, true); 913 else if (bus->clkstate == CLK_AVAIL) 914 brcmf_sdio_htclk(bus, false, false); 915 else 916 brcmf_err("request for %d -> %d\n", 917 bus->clkstate, target); 918 break; 919 920 case CLK_NONE: 921 /* Make sure to remove HT request */ 922 if (bus->clkstate == CLK_AVAIL) 923 brcmf_sdio_htclk(bus, false, false); 924 /* Now remove the SD clock */ 925 brcmf_sdio_sdclk(bus, false); 926 break; 927 } 928 #ifdef DEBUG 929 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); 930 #endif /* DEBUG */ 931 932 return 0; 933 } 934 935 static int 936 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) 937 { 938 int err = 0; 939 u8 clkcsr; 940 941 brcmf_dbg(SDIO, "Enter: request %s currently %s\n", 942 (sleep ? "SLEEP" : "WAKE"), 943 (bus->sleeping ? "SLEEP" : "WAKE")); 944 945 /* If SR is enabled control bus state with KSO */ 946 if (bus->sr_enabled) { 947 /* Done if we're already in the requested state */ 948 if (sleep == bus->sleeping) 949 goto end; 950 951 /* Going to sleep */ 952 if (sleep) { 953 clkcsr = brcmf_sdiod_readb(bus->sdiodev, 954 SBSDIO_FUNC1_CHIPCLKCSR, 955 &err); 956 if ((clkcsr & SBSDIO_CSR_MASK) == 0) { 957 brcmf_dbg(SDIO, "no clock, set ALP\n"); 958 brcmf_sdiod_writeb(bus->sdiodev, 959 SBSDIO_FUNC1_CHIPCLKCSR, 960 SBSDIO_ALP_AVAIL_REQ, &err); 961 } 962 err = brcmf_sdio_kso_control(bus, false); 963 } else { 964 err = brcmf_sdio_kso_control(bus, true); 965 } 966 if (err) { 967 brcmf_err("error while changing bus sleep state %d\n", 968 err); 969 goto done; 970 } 971 } 972 973 end: 974 /* control clocks */ 975 if (sleep) { 976 if (!bus->sr_enabled) 977 brcmf_sdio_clkctl(bus, CLK_NONE, pendok); 978 } else { 979 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); 980 brcmf_sdio_wd_timer(bus, true); 981 } 982 bus->sleeping = sleep; 983 brcmf_dbg(SDIO, "new state %s\n", 984 (sleep ? "SLEEP" : "WAKE")); 985 done: 986 brcmf_dbg(SDIO, "Exit: err=%d\n", err); 987 return err; 988 989 } 990 991 #ifdef DEBUG 992 static inline bool brcmf_sdio_valid_shared_address(u32 addr) 993 { 994 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); 995 } 996 997 static int brcmf_sdio_readshared(struct brcmf_sdio *bus, 998 struct sdpcm_shared *sh) 999 { 1000 u32 addr = 0; 1001 int rv; 1002 u32 shaddr = 0; 1003 struct sdpcm_shared_le sh_le; 1004 __le32 addr_le; 1005 1006 sdio_claim_host(bus->sdiodev->func[1]); 1007 brcmf_sdio_bus_sleep(bus, false, false); 1008 1009 /* 1010 * Read last word in socram to determine 1011 * address of sdpcm_shared structure 1012 */ 1013 shaddr = bus->ci->rambase + bus->ci->ramsize - 4; 1014 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci)) 1015 shaddr -= bus->ci->srsize; 1016 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, 1017 (u8 *)&addr_le, 4); 1018 if (rv < 0) 1019 goto fail; 1020 1021 /* 1022 * Check if addr is valid. 1023 * NVRAM length at the end of memory should have been overwritten. 1024 */ 1025 addr = le32_to_cpu(addr_le); 1026 if (!brcmf_sdio_valid_shared_address(addr)) { 1027 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr); 1028 rv = -EINVAL; 1029 goto fail; 1030 } 1031 1032 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr); 1033 1034 /* Read hndrte_shared structure */ 1035 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, 1036 sizeof(struct sdpcm_shared_le)); 1037 if (rv < 0) 1038 goto fail; 1039 1040 sdio_release_host(bus->sdiodev->func[1]); 1041 1042 /* Endianness */ 1043 sh->flags = le32_to_cpu(sh_le.flags); 1044 sh->trap_addr = le32_to_cpu(sh_le.trap_addr); 1045 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); 1046 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); 1047 sh->assert_line = le32_to_cpu(sh_le.assert_line); 1048 sh->console_addr = le32_to_cpu(sh_le.console_addr); 1049 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); 1050 1051 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { 1052 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", 1053 SDPCM_SHARED_VERSION, 1054 sh->flags & SDPCM_SHARED_VERSION_MASK); 1055 return -EPROTO; 1056 } 1057 return 0; 1058 1059 fail: 1060 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n", 1061 rv, addr); 1062 sdio_release_host(bus->sdiodev->func[1]); 1063 return rv; 1064 } 1065 1066 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1067 { 1068 struct sdpcm_shared sh; 1069 1070 if (brcmf_sdio_readshared(bus, &sh) == 0) 1071 bus->console_addr = sh.console_addr; 1072 } 1073 #else 1074 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1075 { 1076 } 1077 #endif /* DEBUG */ 1078 1079 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) 1080 { 1081 u32 intstatus = 0; 1082 u32 hmb_data; 1083 u8 fcbits; 1084 int ret; 1085 1086 brcmf_dbg(SDIO, "Enter\n"); 1087 1088 /* Read mailbox data and ack that we did so */ 1089 ret = r_sdreg32(bus, &hmb_data, SD_REG(tohostmailboxdata)); 1090 1091 if (ret == 0) 1092 w_sdreg32(bus, SMB_INT_ACK, SD_REG(tosbmailbox)); 1093 bus->sdcnt.f1regdata += 2; 1094 1095 /* dongle indicates the firmware has halted/crashed */ 1096 if (hmb_data & HMB_DATA_FWHALT) 1097 brcmf_err("mailbox indicates firmware halted\n"); 1098 1099 /* Dongle recomposed rx frames, accept them again */ 1100 if (hmb_data & HMB_DATA_NAKHANDLED) { 1101 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", 1102 bus->rx_seq); 1103 if (!bus->rxskip) 1104 brcmf_err("unexpected NAKHANDLED!\n"); 1105 1106 bus->rxskip = false; 1107 intstatus |= I_HMB_FRAME_IND; 1108 } 1109 1110 /* 1111 * DEVREADY does not occur with gSPI. 1112 */ 1113 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { 1114 bus->sdpcm_ver = 1115 (hmb_data & HMB_DATA_VERSION_MASK) >> 1116 HMB_DATA_VERSION_SHIFT; 1117 if (bus->sdpcm_ver != SDPCM_PROT_VERSION) 1118 brcmf_err("Version mismatch, dongle reports %d, " 1119 "expecting %d\n", 1120 bus->sdpcm_ver, SDPCM_PROT_VERSION); 1121 else 1122 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", 1123 bus->sdpcm_ver); 1124 1125 /* 1126 * Retrieve console state address now that firmware should have 1127 * updated it. 1128 */ 1129 brcmf_sdio_get_console_addr(bus); 1130 } 1131 1132 /* 1133 * Flow Control has been moved into the RX headers and this out of band 1134 * method isn't used any more. 1135 * remaining backward compatible with older dongles. 1136 */ 1137 if (hmb_data & HMB_DATA_FC) { 1138 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> 1139 HMB_DATA_FCDATA_SHIFT; 1140 1141 if (fcbits & ~bus->flowcontrol) 1142 bus->sdcnt.fc_xoff++; 1143 1144 if (bus->flowcontrol & ~fcbits) 1145 bus->sdcnt.fc_xon++; 1146 1147 bus->sdcnt.fc_rcvd++; 1148 bus->flowcontrol = fcbits; 1149 } 1150 1151 /* Shouldn't be any others */ 1152 if (hmb_data & ~(HMB_DATA_DEVREADY | 1153 HMB_DATA_NAKHANDLED | 1154 HMB_DATA_FC | 1155 HMB_DATA_FWREADY | 1156 HMB_DATA_FWHALT | 1157 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) 1158 brcmf_err("Unknown mailbox data content: 0x%02x\n", 1159 hmb_data); 1160 1161 return intstatus; 1162 } 1163 1164 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) 1165 { 1166 uint retries = 0; 1167 u16 lastrbc; 1168 u8 hi, lo; 1169 int err; 1170 1171 brcmf_err("%sterminate frame%s\n", 1172 abort ? "abort command, " : "", 1173 rtx ? ", send NAK" : ""); 1174 1175 if (abort) 1176 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2); 1177 1178 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, 1179 &err); 1180 bus->sdcnt.f1regdata++; 1181 1182 /* Wait until the packet has been flushed (device/FIFO stable) */ 1183 for (lastrbc = retries = 0xffff; retries > 0; retries--) { 1184 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI, 1185 &err); 1186 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO, 1187 &err); 1188 bus->sdcnt.f1regdata += 2; 1189 1190 if ((hi == 0) && (lo == 0)) 1191 break; 1192 1193 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { 1194 brcmf_err("count growing: last 0x%04x now 0x%04x\n", 1195 lastrbc, (hi << 8) + lo); 1196 } 1197 lastrbc = (hi << 8) + lo; 1198 } 1199 1200 if (!retries) 1201 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); 1202 else 1203 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); 1204 1205 if (rtx) { 1206 bus->sdcnt.rxrtx++; 1207 err = w_sdreg32(bus, SMB_NAK, SD_REG(tosbmailbox)); 1208 1209 bus->sdcnt.f1regdata++; 1210 if (err == 0) 1211 bus->rxskip = true; 1212 } 1213 1214 /* Clear partial in any case */ 1215 bus->cur_read.len = 0; 1216 } 1217 1218 static void brcmf_sdio_txfail(struct brcmf_sdio *bus) 1219 { 1220 struct brcmf_sdio_dev *sdiodev = bus->sdiodev; 1221 u8 i, hi, lo; 1222 1223 /* On failure, abort the command and terminate the frame */ 1224 brcmf_err("sdio error, abort command and terminate frame\n"); 1225 bus->sdcnt.tx_sderrs++; 1226 1227 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2); 1228 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); 1229 bus->sdcnt.f1regdata++; 1230 1231 for (i = 0; i < 3; i++) { 1232 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); 1233 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); 1234 bus->sdcnt.f1regdata += 2; 1235 if ((hi == 0) && (lo == 0)) 1236 break; 1237 } 1238 } 1239 1240 /* return total length of buffer chain */ 1241 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) 1242 { 1243 struct sk_buff *p; 1244 uint total; 1245 1246 total = 0; 1247 skb_queue_walk(&bus->glom, p) 1248 total += p->len; 1249 return total; 1250 } 1251 1252 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) 1253 { 1254 struct sk_buff *cur, *next; 1255 1256 skb_queue_walk_safe(&bus->glom, cur, next) { 1257 skb_unlink(cur, &bus->glom); 1258 brcmu_pkt_buf_free_skb(cur); 1259 } 1260 } 1261 1262 /** 1263 * brcmfmac sdio bus specific header 1264 * This is the lowest layer header wrapped on the packets transmitted between 1265 * host and WiFi dongle which contains information needed for SDIO core and 1266 * firmware 1267 * 1268 * It consists of 3 parts: hardware header, hardware extension header and 1269 * software header 1270 * hardware header (frame tag) - 4 bytes 1271 * Byte 0~1: Frame length 1272 * Byte 2~3: Checksum, bit-wise inverse of frame length 1273 * hardware extension header - 8 bytes 1274 * Tx glom mode only, N/A for Rx or normal Tx 1275 * Byte 0~1: Packet length excluding hw frame tag 1276 * Byte 2: Reserved 1277 * Byte 3: Frame flags, bit 0: last frame indication 1278 * Byte 4~5: Reserved 1279 * Byte 6~7: Tail padding length 1280 * software header - 8 bytes 1281 * Byte 0: Rx/Tx sequence number 1282 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag 1283 * Byte 2: Length of next data frame, reserved for Tx 1284 * Byte 3: Data offset 1285 * Byte 4: Flow control bits, reserved for Tx 1286 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet 1287 * Byte 6~7: Reserved 1288 */ 1289 #define SDPCM_HWHDR_LEN 4 1290 #define SDPCM_HWEXT_LEN 8 1291 #define SDPCM_SWHDR_LEN 8 1292 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) 1293 /* software header */ 1294 #define SDPCM_SEQ_MASK 0x000000ff 1295 #define SDPCM_SEQ_WRAP 256 1296 #define SDPCM_CHANNEL_MASK 0x00000f00 1297 #define SDPCM_CHANNEL_SHIFT 8 1298 #define SDPCM_CONTROL_CHANNEL 0 /* Control */ 1299 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ 1300 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ 1301 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ 1302 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ 1303 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) 1304 #define SDPCM_NEXTLEN_MASK 0x00ff0000 1305 #define SDPCM_NEXTLEN_SHIFT 16 1306 #define SDPCM_DOFFSET_MASK 0xff000000 1307 #define SDPCM_DOFFSET_SHIFT 24 1308 #define SDPCM_FCMASK_MASK 0x000000ff 1309 #define SDPCM_WINDOW_MASK 0x0000ff00 1310 #define SDPCM_WINDOW_SHIFT 8 1311 1312 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) 1313 { 1314 u32 hdrvalue; 1315 hdrvalue = *(u32 *)swheader; 1316 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); 1317 } 1318 1319 static inline bool brcmf_sdio_fromevntchan(u8 *swheader) 1320 { 1321 u32 hdrvalue; 1322 u8 ret; 1323 1324 hdrvalue = *(u32 *)swheader; 1325 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT); 1326 1327 return (ret == SDPCM_EVENT_CHANNEL); 1328 } 1329 1330 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, 1331 struct brcmf_sdio_hdrinfo *rd, 1332 enum brcmf_sdio_frmtype type) 1333 { 1334 u16 len, checksum; 1335 u8 rx_seq, fc, tx_seq_max; 1336 u32 swheader; 1337 1338 trace_brcmf_sdpcm_hdr(SDPCM_RX, header); 1339 1340 /* hw header */ 1341 len = get_unaligned_le16(header); 1342 checksum = get_unaligned_le16(header + sizeof(u16)); 1343 /* All zero means no more to read */ 1344 if (!(len | checksum)) { 1345 bus->rxpending = false; 1346 return -ENODATA; 1347 } 1348 if ((u16)(~(len ^ checksum))) { 1349 brcmf_err("HW header checksum error\n"); 1350 bus->sdcnt.rx_badhdr++; 1351 brcmf_sdio_rxfail(bus, false, false); 1352 return -EIO; 1353 } 1354 if (len < SDPCM_HDRLEN) { 1355 brcmf_err("HW header length error\n"); 1356 return -EPROTO; 1357 } 1358 if (type == BRCMF_SDIO_FT_SUPER && 1359 (roundup(len, bus->blocksize) != rd->len)) { 1360 brcmf_err("HW superframe header length error\n"); 1361 return -EPROTO; 1362 } 1363 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { 1364 brcmf_err("HW subframe header length error\n"); 1365 return -EPROTO; 1366 } 1367 rd->len = len; 1368 1369 /* software header */ 1370 header += SDPCM_HWHDR_LEN; 1371 swheader = le32_to_cpu(*(__le32 *)header); 1372 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { 1373 brcmf_err("Glom descriptor found in superframe head\n"); 1374 rd->len = 0; 1375 return -EINVAL; 1376 } 1377 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); 1378 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; 1379 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && 1380 type != BRCMF_SDIO_FT_SUPER) { 1381 brcmf_err("HW header length too long\n"); 1382 bus->sdcnt.rx_toolong++; 1383 brcmf_sdio_rxfail(bus, false, false); 1384 rd->len = 0; 1385 return -EPROTO; 1386 } 1387 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { 1388 brcmf_err("Wrong channel for superframe\n"); 1389 rd->len = 0; 1390 return -EINVAL; 1391 } 1392 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && 1393 rd->channel != SDPCM_EVENT_CHANNEL) { 1394 brcmf_err("Wrong channel for subframe\n"); 1395 rd->len = 0; 1396 return -EINVAL; 1397 } 1398 rd->dat_offset = brcmf_sdio_getdatoffset(header); 1399 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { 1400 brcmf_err("seq %d: bad data offset\n", rx_seq); 1401 bus->sdcnt.rx_badhdr++; 1402 brcmf_sdio_rxfail(bus, false, false); 1403 rd->len = 0; 1404 return -ENXIO; 1405 } 1406 if (rd->seq_num != rx_seq) { 1407 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num); 1408 bus->sdcnt.rx_badseq++; 1409 rd->seq_num = rx_seq; 1410 } 1411 /* no need to check the reset for subframe */ 1412 if (type == BRCMF_SDIO_FT_SUB) 1413 return 0; 1414 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; 1415 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { 1416 /* only warm for NON glom packet */ 1417 if (rd->channel != SDPCM_GLOM_CHANNEL) 1418 brcmf_err("seq %d: next length error\n", rx_seq); 1419 rd->len_nxtfrm = 0; 1420 } 1421 swheader = le32_to_cpu(*(__le32 *)(header + 4)); 1422 fc = swheader & SDPCM_FCMASK_MASK; 1423 if (bus->flowcontrol != fc) { 1424 if (~bus->flowcontrol & fc) 1425 bus->sdcnt.fc_xoff++; 1426 if (bus->flowcontrol & ~fc) 1427 bus->sdcnt.fc_xon++; 1428 bus->sdcnt.fc_rcvd++; 1429 bus->flowcontrol = fc; 1430 } 1431 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; 1432 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { 1433 brcmf_err("seq %d: max tx seq number error\n", rx_seq); 1434 tx_seq_max = bus->tx_seq + 2; 1435 } 1436 bus->tx_max = tx_seq_max; 1437 1438 return 0; 1439 } 1440 1441 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) 1442 { 1443 *(__le16 *)header = cpu_to_le16(frm_length); 1444 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); 1445 } 1446 1447 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, 1448 struct brcmf_sdio_hdrinfo *hd_info) 1449 { 1450 u32 hdrval; 1451 u8 hdr_offset; 1452 1453 brcmf_sdio_update_hwhdr(header, hd_info->len); 1454 hdr_offset = SDPCM_HWHDR_LEN; 1455 1456 if (bus->txglom) { 1457 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); 1458 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1459 hdrval = (u16)hd_info->tail_pad << 16; 1460 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); 1461 hdr_offset += SDPCM_HWEXT_LEN; 1462 } 1463 1464 hdrval = hd_info->seq_num; 1465 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & 1466 SDPCM_CHANNEL_MASK; 1467 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & 1468 SDPCM_DOFFSET_MASK; 1469 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1470 *(((__le32 *)(header + hdr_offset)) + 1) = 0; 1471 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); 1472 } 1473 1474 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) 1475 { 1476 u16 dlen, totlen; 1477 u8 *dptr, num = 0; 1478 u16 sublen; 1479 struct sk_buff *pfirst, *pnext; 1480 1481 int errcode; 1482 u8 doff, sfdoff; 1483 1484 struct brcmf_sdio_hdrinfo rd_new; 1485 1486 /* If packets, issue read(s) and send up packet chain */ 1487 /* Return sequence numbers consumed? */ 1488 1489 brcmf_dbg(SDIO, "start: glomd %p glom %p\n", 1490 bus->glomd, skb_peek(&bus->glom)); 1491 1492 /* If there's a descriptor, generate the packet chain */ 1493 if (bus->glomd) { 1494 pfirst = pnext = NULL; 1495 dlen = (u16) (bus->glomd->len); 1496 dptr = bus->glomd->data; 1497 if (!dlen || (dlen & 1)) { 1498 brcmf_err("bad glomd len(%d), ignore descriptor\n", 1499 dlen); 1500 dlen = 0; 1501 } 1502 1503 for (totlen = num = 0; dlen; num++) { 1504 /* Get (and move past) next length */ 1505 sublen = get_unaligned_le16(dptr); 1506 dlen -= sizeof(u16); 1507 dptr += sizeof(u16); 1508 if ((sublen < SDPCM_HDRLEN) || 1509 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { 1510 brcmf_err("descriptor len %d bad: %d\n", 1511 num, sublen); 1512 pnext = NULL; 1513 break; 1514 } 1515 if (sublen % bus->sgentry_align) { 1516 brcmf_err("sublen %d not multiple of %d\n", 1517 sublen, bus->sgentry_align); 1518 } 1519 totlen += sublen; 1520 1521 /* For last frame, adjust read len so total 1522 is a block multiple */ 1523 if (!dlen) { 1524 sublen += 1525 (roundup(totlen, bus->blocksize) - totlen); 1526 totlen = roundup(totlen, bus->blocksize); 1527 } 1528 1529 /* Allocate/chain packet for next subframe */ 1530 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); 1531 if (pnext == NULL) { 1532 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", 1533 num, sublen); 1534 break; 1535 } 1536 skb_queue_tail(&bus->glom, pnext); 1537 1538 /* Adhere to start alignment requirements */ 1539 pkt_align(pnext, sublen, bus->sgentry_align); 1540 } 1541 1542 /* If all allocations succeeded, save packet chain 1543 in bus structure */ 1544 if (pnext) { 1545 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", 1546 totlen, num); 1547 if (BRCMF_GLOM_ON() && bus->cur_read.len && 1548 totlen != bus->cur_read.len) { 1549 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", 1550 bus->cur_read.len, totlen, rxseq); 1551 } 1552 pfirst = pnext = NULL; 1553 } else { 1554 brcmf_sdio_free_glom(bus); 1555 num = 0; 1556 } 1557 1558 /* Done with descriptor packet */ 1559 brcmu_pkt_buf_free_skb(bus->glomd); 1560 bus->glomd = NULL; 1561 bus->cur_read.len = 0; 1562 } 1563 1564 /* Ok -- either we just generated a packet chain, 1565 or had one from before */ 1566 if (!skb_queue_empty(&bus->glom)) { 1567 if (BRCMF_GLOM_ON()) { 1568 brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); 1569 skb_queue_walk(&bus->glom, pnext) { 1570 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", 1571 pnext, (u8 *) (pnext->data), 1572 pnext->len, pnext->len); 1573 } 1574 } 1575 1576 pfirst = skb_peek(&bus->glom); 1577 dlen = (u16) brcmf_sdio_glom_len(bus); 1578 1579 /* Do an SDIO read for the superframe. Configurable iovar to 1580 * read directly into the chained packet, or allocate a large 1581 * packet and and copy into the chain. 1582 */ 1583 sdio_claim_host(bus->sdiodev->func[1]); 1584 errcode = brcmf_sdiod_recv_chain(bus->sdiodev, 1585 &bus->glom, dlen); 1586 sdio_release_host(bus->sdiodev->func[1]); 1587 bus->sdcnt.f2rxdata++; 1588 1589 /* On failure, kill the superframe */ 1590 if (errcode < 0) { 1591 brcmf_err("glom read of %d bytes failed: %d\n", 1592 dlen, errcode); 1593 1594 sdio_claim_host(bus->sdiodev->func[1]); 1595 brcmf_sdio_rxfail(bus, true, false); 1596 bus->sdcnt.rxglomfail++; 1597 brcmf_sdio_free_glom(bus); 1598 sdio_release_host(bus->sdiodev->func[1]); 1599 return 0; 1600 } 1601 1602 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1603 pfirst->data, min_t(int, pfirst->len, 48), 1604 "SUPERFRAME:\n"); 1605 1606 rd_new.seq_num = rxseq; 1607 rd_new.len = dlen; 1608 sdio_claim_host(bus->sdiodev->func[1]); 1609 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, 1610 BRCMF_SDIO_FT_SUPER); 1611 sdio_release_host(bus->sdiodev->func[1]); 1612 bus->cur_read.len = rd_new.len_nxtfrm << 4; 1613 1614 /* Remove superframe header, remember offset */ 1615 skb_pull(pfirst, rd_new.dat_offset); 1616 sfdoff = rd_new.dat_offset; 1617 num = 0; 1618 1619 /* Validate all the subframe headers */ 1620 skb_queue_walk(&bus->glom, pnext) { 1621 /* leave when invalid subframe is found */ 1622 if (errcode) 1623 break; 1624 1625 rd_new.len = pnext->len; 1626 rd_new.seq_num = rxseq++; 1627 sdio_claim_host(bus->sdiodev->func[1]); 1628 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, 1629 BRCMF_SDIO_FT_SUB); 1630 sdio_release_host(bus->sdiodev->func[1]); 1631 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1632 pnext->data, 32, "subframe:\n"); 1633 1634 num++; 1635 } 1636 1637 if (errcode) { 1638 /* Terminate frame on error */ 1639 sdio_claim_host(bus->sdiodev->func[1]); 1640 brcmf_sdio_rxfail(bus, true, false); 1641 bus->sdcnt.rxglomfail++; 1642 brcmf_sdio_free_glom(bus); 1643 sdio_release_host(bus->sdiodev->func[1]); 1644 bus->cur_read.len = 0; 1645 return 0; 1646 } 1647 1648 /* Basic SD framing looks ok - process each packet (header) */ 1649 1650 skb_queue_walk_safe(&bus->glom, pfirst, pnext) { 1651 dptr = (u8 *) (pfirst->data); 1652 sublen = get_unaligned_le16(dptr); 1653 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); 1654 1655 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1656 dptr, pfirst->len, 1657 "Rx Subframe Data:\n"); 1658 1659 __skb_trim(pfirst, sublen); 1660 skb_pull(pfirst, doff); 1661 1662 if (pfirst->len == 0) { 1663 skb_unlink(pfirst, &bus->glom); 1664 brcmu_pkt_buf_free_skb(pfirst); 1665 continue; 1666 } 1667 1668 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1669 pfirst->data, 1670 min_t(int, pfirst->len, 32), 1671 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", 1672 bus->glom.qlen, pfirst, pfirst->data, 1673 pfirst->len, pfirst->next, 1674 pfirst->prev); 1675 skb_unlink(pfirst, &bus->glom); 1676 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN])) 1677 brcmf_rx_event(bus->sdiodev->dev, pfirst); 1678 else 1679 brcmf_rx_frame(bus->sdiodev->dev, pfirst, 1680 false); 1681 bus->sdcnt.rxglompkts++; 1682 } 1683 1684 bus->sdcnt.rxglomframes++; 1685 } 1686 return num; 1687 } 1688 1689 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, 1690 bool *pending) 1691 { 1692 DECLARE_WAITQUEUE(wait, current); 1693 int timeout = DCMD_RESP_TIMEOUT; 1694 1695 /* Wait until control frame is available */ 1696 add_wait_queue(&bus->dcmd_resp_wait, &wait); 1697 set_current_state(TASK_INTERRUPTIBLE); 1698 1699 while (!(*condition) && (!signal_pending(current) && timeout)) 1700 timeout = schedule_timeout(timeout); 1701 1702 if (signal_pending(current)) 1703 *pending = true; 1704 1705 set_current_state(TASK_RUNNING); 1706 remove_wait_queue(&bus->dcmd_resp_wait, &wait); 1707 1708 return timeout; 1709 } 1710 1711 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) 1712 { 1713 wake_up_interruptible(&bus->dcmd_resp_wait); 1714 1715 return 0; 1716 } 1717 static void 1718 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) 1719 { 1720 uint rdlen, pad; 1721 u8 *buf = NULL, *rbuf; 1722 int sdret; 1723 1724 brcmf_dbg(TRACE, "Enter\n"); 1725 1726 if (bus->rxblen) 1727 buf = vzalloc(bus->rxblen); 1728 if (!buf) 1729 goto done; 1730 1731 rbuf = bus->rxbuf; 1732 pad = ((unsigned long)rbuf % bus->head_align); 1733 if (pad) 1734 rbuf += (bus->head_align - pad); 1735 1736 /* Copy the already-read portion over */ 1737 memcpy(buf, hdr, BRCMF_FIRSTREAD); 1738 if (len <= BRCMF_FIRSTREAD) 1739 goto gotpkt; 1740 1741 /* Raise rdlen to next SDIO block to avoid tail command */ 1742 rdlen = len - BRCMF_FIRSTREAD; 1743 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { 1744 pad = bus->blocksize - (rdlen % bus->blocksize); 1745 if ((pad <= bus->roundup) && (pad < bus->blocksize) && 1746 ((len + pad) < bus->sdiodev->bus_if->maxctl)) 1747 rdlen += pad; 1748 } else if (rdlen % bus->head_align) { 1749 rdlen += bus->head_align - (rdlen % bus->head_align); 1750 } 1751 1752 /* Drop if the read is too big or it exceeds our maximum */ 1753 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { 1754 brcmf_err("%d-byte control read exceeds %d-byte buffer\n", 1755 rdlen, bus->sdiodev->bus_if->maxctl); 1756 brcmf_sdio_rxfail(bus, false, false); 1757 goto done; 1758 } 1759 1760 if ((len - doff) > bus->sdiodev->bus_if->maxctl) { 1761 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", 1762 len, len - doff, bus->sdiodev->bus_if->maxctl); 1763 bus->sdcnt.rx_toolong++; 1764 brcmf_sdio_rxfail(bus, false, false); 1765 goto done; 1766 } 1767 1768 /* Read remain of frame body */ 1769 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); 1770 bus->sdcnt.f2rxdata++; 1771 1772 /* Control frame failures need retransmission */ 1773 if (sdret < 0) { 1774 brcmf_err("read %d control bytes failed: %d\n", 1775 rdlen, sdret); 1776 bus->sdcnt.rxc_errors++; 1777 brcmf_sdio_rxfail(bus, true, true); 1778 goto done; 1779 } else 1780 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); 1781 1782 gotpkt: 1783 1784 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 1785 buf, len, "RxCtrl:\n"); 1786 1787 /* Point to valid data and indicate its length */ 1788 spin_lock_bh(&bus->rxctl_lock); 1789 if (bus->rxctl) { 1790 brcmf_err("last control frame is being processed.\n"); 1791 spin_unlock_bh(&bus->rxctl_lock); 1792 vfree(buf); 1793 goto done; 1794 } 1795 bus->rxctl = buf + doff; 1796 bus->rxctl_orig = buf; 1797 bus->rxlen = len - doff; 1798 spin_unlock_bh(&bus->rxctl_lock); 1799 1800 done: 1801 /* Awake any waiters */ 1802 brcmf_sdio_dcmd_resp_wake(bus); 1803 } 1804 1805 /* Pad read to blocksize for efficiency */ 1806 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) 1807 { 1808 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { 1809 *pad = bus->blocksize - (*rdlen % bus->blocksize); 1810 if (*pad <= bus->roundup && *pad < bus->blocksize && 1811 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) 1812 *rdlen += *pad; 1813 } else if (*rdlen % bus->head_align) { 1814 *rdlen += bus->head_align - (*rdlen % bus->head_align); 1815 } 1816 } 1817 1818 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) 1819 { 1820 struct sk_buff *pkt; /* Packet for event or data frames */ 1821 u16 pad; /* Number of pad bytes to read */ 1822 uint rxleft = 0; /* Remaining number of frames allowed */ 1823 int ret; /* Return code from calls */ 1824 uint rxcount = 0; /* Total frames read */ 1825 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; 1826 u8 head_read = 0; 1827 1828 brcmf_dbg(TRACE, "Enter\n"); 1829 1830 /* Not finished unless we encounter no more frames indication */ 1831 bus->rxpending = true; 1832 1833 for (rd->seq_num = bus->rx_seq, rxleft = maxframes; 1834 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; 1835 rd->seq_num++, rxleft--) { 1836 1837 /* Handle glomming separately */ 1838 if (bus->glomd || !skb_queue_empty(&bus->glom)) { 1839 u8 cnt; 1840 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", 1841 bus->glomd, skb_peek(&bus->glom)); 1842 cnt = brcmf_sdio_rxglom(bus, rd->seq_num); 1843 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); 1844 rd->seq_num += cnt - 1; 1845 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; 1846 continue; 1847 } 1848 1849 rd->len_left = rd->len; 1850 /* read header first for unknow frame length */ 1851 sdio_claim_host(bus->sdiodev->func[1]); 1852 if (!rd->len) { 1853 ret = brcmf_sdiod_recv_buf(bus->sdiodev, 1854 bus->rxhdr, BRCMF_FIRSTREAD); 1855 bus->sdcnt.f2rxhdrs++; 1856 if (ret < 0) { 1857 brcmf_err("RXHEADER FAILED: %d\n", 1858 ret); 1859 bus->sdcnt.rx_hdrfail++; 1860 brcmf_sdio_rxfail(bus, true, true); 1861 sdio_release_host(bus->sdiodev->func[1]); 1862 continue; 1863 } 1864 1865 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), 1866 bus->rxhdr, SDPCM_HDRLEN, 1867 "RxHdr:\n"); 1868 1869 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, 1870 BRCMF_SDIO_FT_NORMAL)) { 1871 sdio_release_host(bus->sdiodev->func[1]); 1872 if (!bus->rxpending) 1873 break; 1874 else 1875 continue; 1876 } 1877 1878 if (rd->channel == SDPCM_CONTROL_CHANNEL) { 1879 brcmf_sdio_read_control(bus, bus->rxhdr, 1880 rd->len, 1881 rd->dat_offset); 1882 /* prepare the descriptor for the next read */ 1883 rd->len = rd->len_nxtfrm << 4; 1884 rd->len_nxtfrm = 0; 1885 /* treat all packet as event if we don't know */ 1886 rd->channel = SDPCM_EVENT_CHANNEL; 1887 sdio_release_host(bus->sdiodev->func[1]); 1888 continue; 1889 } 1890 rd->len_left = rd->len > BRCMF_FIRSTREAD ? 1891 rd->len - BRCMF_FIRSTREAD : 0; 1892 head_read = BRCMF_FIRSTREAD; 1893 } 1894 1895 brcmf_sdio_pad(bus, &pad, &rd->len_left); 1896 1897 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + 1898 bus->head_align); 1899 if (!pkt) { 1900 /* Give up on data, request rtx of events */ 1901 brcmf_err("brcmu_pkt_buf_get_skb failed\n"); 1902 brcmf_sdio_rxfail(bus, false, 1903 RETRYCHAN(rd->channel)); 1904 sdio_release_host(bus->sdiodev->func[1]); 1905 continue; 1906 } 1907 skb_pull(pkt, head_read); 1908 pkt_align(pkt, rd->len_left, bus->head_align); 1909 1910 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); 1911 bus->sdcnt.f2rxdata++; 1912 sdio_release_host(bus->sdiodev->func[1]); 1913 1914 if (ret < 0) { 1915 brcmf_err("read %d bytes from channel %d failed: %d\n", 1916 rd->len, rd->channel, ret); 1917 brcmu_pkt_buf_free_skb(pkt); 1918 sdio_claim_host(bus->sdiodev->func[1]); 1919 brcmf_sdio_rxfail(bus, true, 1920 RETRYCHAN(rd->channel)); 1921 sdio_release_host(bus->sdiodev->func[1]); 1922 continue; 1923 } 1924 1925 if (head_read) { 1926 skb_push(pkt, head_read); 1927 memcpy(pkt->data, bus->rxhdr, head_read); 1928 head_read = 0; 1929 } else { 1930 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); 1931 rd_new.seq_num = rd->seq_num; 1932 sdio_claim_host(bus->sdiodev->func[1]); 1933 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, 1934 BRCMF_SDIO_FT_NORMAL)) { 1935 rd->len = 0; 1936 brcmu_pkt_buf_free_skb(pkt); 1937 } 1938 bus->sdcnt.rx_readahead_cnt++; 1939 if (rd->len != roundup(rd_new.len, 16)) { 1940 brcmf_err("frame length mismatch:read %d, should be %d\n", 1941 rd->len, 1942 roundup(rd_new.len, 16) >> 4); 1943 rd->len = 0; 1944 brcmf_sdio_rxfail(bus, true, true); 1945 sdio_release_host(bus->sdiodev->func[1]); 1946 brcmu_pkt_buf_free_skb(pkt); 1947 continue; 1948 } 1949 sdio_release_host(bus->sdiodev->func[1]); 1950 rd->len_nxtfrm = rd_new.len_nxtfrm; 1951 rd->channel = rd_new.channel; 1952 rd->dat_offset = rd_new.dat_offset; 1953 1954 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && 1955 BRCMF_DATA_ON()) && 1956 BRCMF_HDRS_ON(), 1957 bus->rxhdr, SDPCM_HDRLEN, 1958 "RxHdr:\n"); 1959 1960 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { 1961 brcmf_err("readahead on control packet %d?\n", 1962 rd_new.seq_num); 1963 /* Force retry w/normal header read */ 1964 rd->len = 0; 1965 sdio_claim_host(bus->sdiodev->func[1]); 1966 brcmf_sdio_rxfail(bus, false, true); 1967 sdio_release_host(bus->sdiodev->func[1]); 1968 brcmu_pkt_buf_free_skb(pkt); 1969 continue; 1970 } 1971 } 1972 1973 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1974 pkt->data, rd->len, "Rx Data:\n"); 1975 1976 /* Save superframe descriptor and allocate packet frame */ 1977 if (rd->channel == SDPCM_GLOM_CHANNEL) { 1978 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { 1979 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", 1980 rd->len); 1981 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1982 pkt->data, rd->len, 1983 "Glom Data:\n"); 1984 __skb_trim(pkt, rd->len); 1985 skb_pull(pkt, SDPCM_HDRLEN); 1986 bus->glomd = pkt; 1987 } else { 1988 brcmf_err("%s: glom superframe w/o " 1989 "descriptor!\n", __func__); 1990 sdio_claim_host(bus->sdiodev->func[1]); 1991 brcmf_sdio_rxfail(bus, false, false); 1992 sdio_release_host(bus->sdiodev->func[1]); 1993 } 1994 /* prepare the descriptor for the next read */ 1995 rd->len = rd->len_nxtfrm << 4; 1996 rd->len_nxtfrm = 0; 1997 /* treat all packet as event if we don't know */ 1998 rd->channel = SDPCM_EVENT_CHANNEL; 1999 continue; 2000 } 2001 2002 /* Fill in packet len and prio, deliver upward */ 2003 __skb_trim(pkt, rd->len); 2004 skb_pull(pkt, rd->dat_offset); 2005 2006 if (pkt->len == 0) 2007 brcmu_pkt_buf_free_skb(pkt); 2008 else if (rd->channel == SDPCM_EVENT_CHANNEL) 2009 brcmf_rx_event(bus->sdiodev->dev, pkt); 2010 else 2011 brcmf_rx_frame(bus->sdiodev->dev, pkt, 2012 false); 2013 2014 /* prepare the descriptor for the next read */ 2015 rd->len = rd->len_nxtfrm << 4; 2016 rd->len_nxtfrm = 0; 2017 /* treat all packet as event if we don't know */ 2018 rd->channel = SDPCM_EVENT_CHANNEL; 2019 } 2020 2021 rxcount = maxframes - rxleft; 2022 /* Message if we hit the limit */ 2023 if (!rxleft) 2024 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); 2025 else 2026 brcmf_dbg(DATA, "processed %d frames\n", rxcount); 2027 /* Back off rxseq if awaiting rtx, update rx_seq */ 2028 if (bus->rxskip) 2029 rd->seq_num--; 2030 bus->rx_seq = rd->seq_num; 2031 2032 return rxcount; 2033 } 2034 2035 static void 2036 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) 2037 { 2038 wake_up_interruptible(&bus->ctrl_wait); 2039 return; 2040 } 2041 2042 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) 2043 { 2044 struct brcmf_bus_stats *stats; 2045 u16 head_pad; 2046 u8 *dat_buf; 2047 2048 dat_buf = (u8 *)(pkt->data); 2049 2050 /* Check head padding */ 2051 head_pad = ((unsigned long)dat_buf % bus->head_align); 2052 if (head_pad) { 2053 if (skb_headroom(pkt) < head_pad) { 2054 stats = &bus->sdiodev->bus_if->stats; 2055 atomic_inc(&stats->pktcowed); 2056 if (skb_cow_head(pkt, head_pad)) { 2057 atomic_inc(&stats->pktcow_failed); 2058 return -ENOMEM; 2059 } 2060 head_pad = 0; 2061 } 2062 skb_push(pkt, head_pad); 2063 dat_buf = (u8 *)(pkt->data); 2064 } 2065 memset(dat_buf, 0, head_pad + bus->tx_hdrlen); 2066 return head_pad; 2067 } 2068 2069 /* 2070 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for 2071 * bus layer usage. 2072 */ 2073 /* flag marking a dummy skb added for DMA alignment requirement */ 2074 #define ALIGN_SKB_FLAG 0x8000 2075 /* bit mask of data length chopped from the previous packet */ 2076 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff 2077 2078 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, 2079 struct sk_buff_head *pktq, 2080 struct sk_buff *pkt, u16 total_len) 2081 { 2082 struct brcmf_sdio_dev *sdiodev; 2083 struct sk_buff *pkt_pad; 2084 u16 tail_pad, tail_chop, chain_pad; 2085 unsigned int blksize; 2086 bool lastfrm; 2087 int ntail, ret; 2088 2089 sdiodev = bus->sdiodev; 2090 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize; 2091 /* sg entry alignment should be a divisor of block size */ 2092 WARN_ON(blksize % bus->sgentry_align); 2093 2094 /* Check tail padding */ 2095 lastfrm = skb_queue_is_last(pktq, pkt); 2096 tail_pad = 0; 2097 tail_chop = pkt->len % bus->sgentry_align; 2098 if (tail_chop) 2099 tail_pad = bus->sgentry_align - tail_chop; 2100 chain_pad = (total_len + tail_pad) % blksize; 2101 if (lastfrm && chain_pad) 2102 tail_pad += blksize - chain_pad; 2103 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { 2104 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + 2105 bus->head_align); 2106 if (pkt_pad == NULL) 2107 return -ENOMEM; 2108 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); 2109 if (unlikely(ret < 0)) { 2110 kfree_skb(pkt_pad); 2111 return ret; 2112 } 2113 memcpy(pkt_pad->data, 2114 pkt->data + pkt->len - tail_chop, 2115 tail_chop); 2116 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; 2117 skb_trim(pkt, pkt->len - tail_chop); 2118 skb_trim(pkt_pad, tail_pad + tail_chop); 2119 __skb_queue_after(pktq, pkt, pkt_pad); 2120 } else { 2121 ntail = pkt->data_len + tail_pad - 2122 (pkt->end - pkt->tail); 2123 if (skb_cloned(pkt) || ntail > 0) 2124 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) 2125 return -ENOMEM; 2126 if (skb_linearize(pkt)) 2127 return -ENOMEM; 2128 __skb_put(pkt, tail_pad); 2129 } 2130 2131 return tail_pad; 2132 } 2133 2134 /** 2135 * brcmf_sdio_txpkt_prep - packet preparation for transmit 2136 * @bus: brcmf_sdio structure pointer 2137 * @pktq: packet list pointer 2138 * @chan: virtual channel to transmit the packet 2139 * 2140 * Processes to be applied to the packet 2141 * - Align data buffer pointer 2142 * - Align data buffer length 2143 * - Prepare header 2144 * Return: negative value if there is error 2145 */ 2146 static int 2147 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2148 uint chan) 2149 { 2150 u16 head_pad, total_len; 2151 struct sk_buff *pkt_next; 2152 u8 txseq; 2153 int ret; 2154 struct brcmf_sdio_hdrinfo hd_info = {0}; 2155 2156 txseq = bus->tx_seq; 2157 total_len = 0; 2158 skb_queue_walk(pktq, pkt_next) { 2159 /* alignment packet inserted in previous 2160 * loop cycle can be skipped as it is 2161 * already properly aligned and does not 2162 * need an sdpcm header. 2163 */ 2164 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) 2165 continue; 2166 2167 /* align packet data pointer */ 2168 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); 2169 if (ret < 0) 2170 return ret; 2171 head_pad = (u16)ret; 2172 if (head_pad) 2173 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); 2174 2175 total_len += pkt_next->len; 2176 2177 hd_info.len = pkt_next->len; 2178 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); 2179 if (bus->txglom && pktq->qlen > 1) { 2180 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, 2181 pkt_next, total_len); 2182 if (ret < 0) 2183 return ret; 2184 hd_info.tail_pad = (u16)ret; 2185 total_len += (u16)ret; 2186 } 2187 2188 hd_info.channel = chan; 2189 hd_info.dat_offset = head_pad + bus->tx_hdrlen; 2190 hd_info.seq_num = txseq++; 2191 2192 /* Now fill the header */ 2193 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); 2194 2195 if (BRCMF_BYTES_ON() && 2196 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || 2197 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) 2198 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, 2199 "Tx Frame:\n"); 2200 else if (BRCMF_HDRS_ON()) 2201 brcmf_dbg_hex_dump(true, pkt_next->data, 2202 head_pad + bus->tx_hdrlen, 2203 "Tx Header:\n"); 2204 } 2205 /* Hardware length tag of the first packet should be total 2206 * length of the chain (including padding) 2207 */ 2208 if (bus->txglom) 2209 brcmf_sdio_update_hwhdr(pktq->next->data, total_len); 2210 return 0; 2211 } 2212 2213 /** 2214 * brcmf_sdio_txpkt_postp - packet post processing for transmit 2215 * @bus: brcmf_sdio structure pointer 2216 * @pktq: packet list pointer 2217 * 2218 * Processes to be applied to the packet 2219 * - Remove head padding 2220 * - Remove tail padding 2221 */ 2222 static void 2223 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) 2224 { 2225 u8 *hdr; 2226 u32 dat_offset; 2227 u16 tail_pad; 2228 u16 dummy_flags, chop_len; 2229 struct sk_buff *pkt_next, *tmp, *pkt_prev; 2230 2231 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2232 dummy_flags = *(u16 *)(pkt_next->cb); 2233 if (dummy_flags & ALIGN_SKB_FLAG) { 2234 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; 2235 if (chop_len) { 2236 pkt_prev = pkt_next->prev; 2237 skb_put(pkt_prev, chop_len); 2238 } 2239 __skb_unlink(pkt_next, pktq); 2240 brcmu_pkt_buf_free_skb(pkt_next); 2241 } else { 2242 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; 2243 dat_offset = le32_to_cpu(*(__le32 *)hdr); 2244 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> 2245 SDPCM_DOFFSET_SHIFT; 2246 skb_pull(pkt_next, dat_offset); 2247 if (bus->txglom) { 2248 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); 2249 skb_trim(pkt_next, pkt_next->len - tail_pad); 2250 } 2251 } 2252 } 2253 } 2254 2255 /* Writes a HW/SW header into the packet and sends it. */ 2256 /* Assumes: (a) header space already there, (b) caller holds lock */ 2257 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2258 uint chan) 2259 { 2260 int ret; 2261 struct sk_buff *pkt_next, *tmp; 2262 2263 brcmf_dbg(TRACE, "Enter\n"); 2264 2265 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); 2266 if (ret) 2267 goto done; 2268 2269 sdio_claim_host(bus->sdiodev->func[1]); 2270 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); 2271 bus->sdcnt.f2txdata++; 2272 2273 if (ret < 0) 2274 brcmf_sdio_txfail(bus); 2275 2276 sdio_release_host(bus->sdiodev->func[1]); 2277 2278 done: 2279 brcmf_sdio_txpkt_postp(bus, pktq); 2280 if (ret == 0) 2281 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; 2282 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2283 __skb_unlink(pkt_next, pktq); 2284 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next, 2285 ret == 0); 2286 } 2287 return ret; 2288 } 2289 2290 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) 2291 { 2292 struct sk_buff *pkt; 2293 struct sk_buff_head pktq; 2294 u32 intstatus = 0; 2295 int ret = 0, prec_out, i; 2296 uint cnt = 0; 2297 u8 tx_prec_map, pkt_num; 2298 2299 brcmf_dbg(TRACE, "Enter\n"); 2300 2301 tx_prec_map = ~bus->flowcontrol; 2302 2303 /* Send frames until the limit or some other event */ 2304 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { 2305 pkt_num = 1; 2306 if (bus->txglom) 2307 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, 2308 bus->sdiodev->txglomsz); 2309 pkt_num = min_t(u32, pkt_num, 2310 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); 2311 __skb_queue_head_init(&pktq); 2312 spin_lock_bh(&bus->txq_lock); 2313 for (i = 0; i < pkt_num; i++) { 2314 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, 2315 &prec_out); 2316 if (pkt == NULL) 2317 break; 2318 __skb_queue_tail(&pktq, pkt); 2319 } 2320 spin_unlock_bh(&bus->txq_lock); 2321 if (i == 0) 2322 break; 2323 2324 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); 2325 2326 cnt += i; 2327 2328 /* In poll mode, need to check for other events */ 2329 if (!bus->intr) { 2330 /* Check device status, signal pending interrupt */ 2331 sdio_claim_host(bus->sdiodev->func[1]); 2332 ret = r_sdreg32(bus, &intstatus, SD_REG(intstatus)); 2333 sdio_release_host(bus->sdiodev->func[1]); 2334 bus->sdcnt.f2txdata++; 2335 if (ret != 0) 2336 break; 2337 if (intstatus & bus->hostintmask) 2338 atomic_set(&bus->ipend, 1); 2339 } 2340 } 2341 2342 /* Deflow-control stack if needed */ 2343 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && 2344 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { 2345 bus->txoff = false; 2346 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false); 2347 } 2348 2349 return cnt; 2350 } 2351 2352 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) 2353 { 2354 u8 doff; 2355 u16 pad; 2356 uint retries = 0; 2357 struct brcmf_sdio_hdrinfo hd_info = {0}; 2358 int ret; 2359 2360 brcmf_dbg(TRACE, "Enter\n"); 2361 2362 /* Back the pointer to make room for bus header */ 2363 frame -= bus->tx_hdrlen; 2364 len += bus->tx_hdrlen; 2365 2366 /* Add alignment padding (optional for ctl frames) */ 2367 doff = ((unsigned long)frame % bus->head_align); 2368 if (doff) { 2369 frame -= doff; 2370 len += doff; 2371 memset(frame + bus->tx_hdrlen, 0, doff); 2372 } 2373 2374 /* Round send length to next SDIO block */ 2375 pad = 0; 2376 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { 2377 pad = bus->blocksize - (len % bus->blocksize); 2378 if ((pad > bus->roundup) || (pad >= bus->blocksize)) 2379 pad = 0; 2380 } else if (len % bus->head_align) { 2381 pad = bus->head_align - (len % bus->head_align); 2382 } 2383 len += pad; 2384 2385 hd_info.len = len - pad; 2386 hd_info.channel = SDPCM_CONTROL_CHANNEL; 2387 hd_info.dat_offset = doff + bus->tx_hdrlen; 2388 hd_info.seq_num = bus->tx_seq; 2389 hd_info.lastfrm = true; 2390 hd_info.tail_pad = pad; 2391 brcmf_sdio_hdpack(bus, frame, &hd_info); 2392 2393 if (bus->txglom) 2394 brcmf_sdio_update_hwhdr(frame, len); 2395 2396 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 2397 frame, len, "Tx Frame:\n"); 2398 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && 2399 BRCMF_HDRS_ON(), 2400 frame, min_t(u16, len, 16), "TxHdr:\n"); 2401 2402 do { 2403 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); 2404 2405 if (ret < 0) 2406 brcmf_sdio_txfail(bus); 2407 else 2408 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; 2409 } while (ret < 0 && retries++ < TXRETRIES); 2410 2411 return ret; 2412 } 2413 2414 static void brcmf_sdio_bus_stop(struct device *dev) 2415 { 2416 u32 local_hostintmask; 2417 u8 saveclk; 2418 int err; 2419 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2420 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2421 struct brcmf_sdio *bus = sdiodev->bus; 2422 2423 brcmf_dbg(TRACE, "Enter\n"); 2424 2425 if (bus->watchdog_tsk) { 2426 send_sig(SIGTERM, bus->watchdog_tsk, 1); 2427 kthread_stop(bus->watchdog_tsk); 2428 bus->watchdog_tsk = NULL; 2429 } 2430 2431 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 2432 sdio_claim_host(sdiodev->func[1]); 2433 2434 /* Enable clock for device interrupts */ 2435 brcmf_sdio_bus_sleep(bus, false, false); 2436 2437 /* Disable and clear interrupts at the chip level also */ 2438 w_sdreg32(bus, 0, SD_REG(hostintmask)); 2439 local_hostintmask = bus->hostintmask; 2440 bus->hostintmask = 0; 2441 2442 /* Force backplane clocks to assure F2 interrupt propagates */ 2443 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2444 &err); 2445 if (!err) 2446 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2447 (saveclk | SBSDIO_FORCE_HT), &err); 2448 if (err) 2449 brcmf_err("Failed to force clock for F2: err %d\n", 2450 err); 2451 2452 /* Turn off the bus (F2), free any pending packets */ 2453 brcmf_dbg(INTR, "disable SDIO interrupts\n"); 2454 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); 2455 2456 /* Clear any pending interrupts now that F2 is disabled */ 2457 w_sdreg32(bus, local_hostintmask, SD_REG(intstatus)); 2458 2459 sdio_release_host(sdiodev->func[1]); 2460 } 2461 /* Clear the data packet queues */ 2462 brcmu_pktq_flush(&bus->txq, true, NULL, NULL); 2463 2464 /* Clear any held glomming stuff */ 2465 brcmu_pkt_buf_free_skb(bus->glomd); 2466 brcmf_sdio_free_glom(bus); 2467 2468 /* Clear rx control and wake any waiters */ 2469 spin_lock_bh(&bus->rxctl_lock); 2470 bus->rxlen = 0; 2471 spin_unlock_bh(&bus->rxctl_lock); 2472 brcmf_sdio_dcmd_resp_wake(bus); 2473 2474 /* Reset some F2 state stuff */ 2475 bus->rxskip = false; 2476 bus->tx_seq = bus->rx_seq = 0; 2477 } 2478 2479 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) 2480 { 2481 struct brcmf_sdio_dev *sdiodev; 2482 unsigned long flags; 2483 2484 sdiodev = bus->sdiodev; 2485 if (sdiodev->oob_irq_requested) { 2486 spin_lock_irqsave(&sdiodev->irq_en_lock, flags); 2487 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) { 2488 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr); 2489 sdiodev->irq_en = true; 2490 } 2491 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags); 2492 } 2493 } 2494 2495 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) 2496 { 2497 struct brcmf_core *buscore = bus->sdio_core; 2498 u32 addr; 2499 unsigned long val; 2500 int ret; 2501 2502 addr = buscore->base + SD_REG(intstatus); 2503 2504 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret); 2505 bus->sdcnt.f1regdata++; 2506 if (ret != 0) 2507 return ret; 2508 2509 val &= bus->hostintmask; 2510 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); 2511 2512 /* Clear interrupts */ 2513 if (val) { 2514 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret); 2515 bus->sdcnt.f1regdata++; 2516 atomic_or(val, &bus->intstatus); 2517 } 2518 2519 return ret; 2520 } 2521 2522 static void brcmf_sdio_dpc(struct brcmf_sdio *bus) 2523 { 2524 u32 newstatus = 0; 2525 unsigned long intstatus; 2526 uint txlimit = bus->txbound; /* Tx frames to send before resched */ 2527 uint framecnt; /* Temporary counter of tx/rx frames */ 2528 int err = 0; 2529 2530 brcmf_dbg(TRACE, "Enter\n"); 2531 2532 sdio_claim_host(bus->sdiodev->func[1]); 2533 2534 /* If waiting for HTAVAIL, check status */ 2535 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { 2536 u8 clkctl, devctl = 0; 2537 2538 #ifdef DEBUG 2539 /* Check for inconsistent device control */ 2540 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL, 2541 &err); 2542 #endif /* DEBUG */ 2543 2544 /* Read CSR, if clock on switch to AVAIL, else ignore */ 2545 clkctl = brcmf_sdiod_readb(bus->sdiodev, 2546 SBSDIO_FUNC1_CHIPCLKCSR, &err); 2547 2548 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", 2549 devctl, clkctl); 2550 2551 if (SBSDIO_HTAV(clkctl)) { 2552 devctl = brcmf_sdiod_readb(bus->sdiodev, 2553 SBSDIO_DEVICE_CTL, &err); 2554 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 2555 brcmf_sdiod_writeb(bus->sdiodev, 2556 SBSDIO_DEVICE_CTL, devctl, &err); 2557 bus->clkstate = CLK_AVAIL; 2558 } 2559 } 2560 2561 /* Make sure backplane clock is on */ 2562 brcmf_sdio_bus_sleep(bus, false, true); 2563 2564 /* Pending interrupt indicates new device status */ 2565 if (atomic_read(&bus->ipend) > 0) { 2566 atomic_set(&bus->ipend, 0); 2567 err = brcmf_sdio_intr_rstatus(bus); 2568 } 2569 2570 /* Start with leftover status bits */ 2571 intstatus = atomic_xchg(&bus->intstatus, 0); 2572 2573 /* Handle flow-control change: read new state in case our ack 2574 * crossed another change interrupt. If change still set, assume 2575 * FC ON for safety, let next loop through do the debounce. 2576 */ 2577 if (intstatus & I_HMB_FC_CHANGE) { 2578 intstatus &= ~I_HMB_FC_CHANGE; 2579 err = w_sdreg32(bus, I_HMB_FC_CHANGE, SD_REG(intstatus)); 2580 2581 err = r_sdreg32(bus, &newstatus, SD_REG(intstatus)); 2582 bus->sdcnt.f1regdata += 2; 2583 atomic_set(&bus->fcstate, 2584 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); 2585 intstatus |= (newstatus & bus->hostintmask); 2586 } 2587 2588 /* Handle host mailbox indication */ 2589 if (intstatus & I_HMB_HOST_INT) { 2590 intstatus &= ~I_HMB_HOST_INT; 2591 intstatus |= brcmf_sdio_hostmail(bus); 2592 } 2593 2594 sdio_release_host(bus->sdiodev->func[1]); 2595 2596 /* Generally don't ask for these, can get CRC errors... */ 2597 if (intstatus & I_WR_OOSYNC) { 2598 brcmf_err("Dongle reports WR_OOSYNC\n"); 2599 intstatus &= ~I_WR_OOSYNC; 2600 } 2601 2602 if (intstatus & I_RD_OOSYNC) { 2603 brcmf_err("Dongle reports RD_OOSYNC\n"); 2604 intstatus &= ~I_RD_OOSYNC; 2605 } 2606 2607 if (intstatus & I_SBINT) { 2608 brcmf_err("Dongle reports SBINT\n"); 2609 intstatus &= ~I_SBINT; 2610 } 2611 2612 /* Would be active due to wake-wlan in gSPI */ 2613 if (intstatus & I_CHIPACTIVE) { 2614 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n"); 2615 intstatus &= ~I_CHIPACTIVE; 2616 } 2617 2618 /* Ignore frame indications if rxskip is set */ 2619 if (bus->rxskip) 2620 intstatus &= ~I_HMB_FRAME_IND; 2621 2622 /* On frame indication, read available frames */ 2623 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { 2624 brcmf_sdio_readframes(bus, bus->rxbound); 2625 if (!bus->rxpending) 2626 intstatus &= ~I_HMB_FRAME_IND; 2627 } 2628 2629 /* Keep still-pending events for next scheduling */ 2630 if (intstatus) 2631 atomic_or(intstatus, &bus->intstatus); 2632 2633 brcmf_sdio_clrintr(bus); 2634 2635 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && 2636 data_ok(bus)) { 2637 sdio_claim_host(bus->sdiodev->func[1]); 2638 if (bus->ctrl_frame_stat) { 2639 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, 2640 bus->ctrl_frame_len); 2641 bus->ctrl_frame_err = err; 2642 wmb(); 2643 bus->ctrl_frame_stat = false; 2644 } 2645 sdio_release_host(bus->sdiodev->func[1]); 2646 brcmf_sdio_wait_event_wakeup(bus); 2647 } 2648 /* Send queued frames (limit 1 if rx may still be pending) */ 2649 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && 2650 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && 2651 data_ok(bus)) { 2652 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : 2653 txlimit; 2654 brcmf_sdio_sendfromq(bus, framecnt); 2655 } 2656 2657 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { 2658 brcmf_err("failed backplane access over SDIO, halting operation\n"); 2659 atomic_set(&bus->intstatus, 0); 2660 if (bus->ctrl_frame_stat) { 2661 sdio_claim_host(bus->sdiodev->func[1]); 2662 if (bus->ctrl_frame_stat) { 2663 bus->ctrl_frame_err = -ENODEV; 2664 wmb(); 2665 bus->ctrl_frame_stat = false; 2666 brcmf_sdio_wait_event_wakeup(bus); 2667 } 2668 sdio_release_host(bus->sdiodev->func[1]); 2669 } 2670 } else if (atomic_read(&bus->intstatus) || 2671 atomic_read(&bus->ipend) > 0 || 2672 (!atomic_read(&bus->fcstate) && 2673 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && 2674 data_ok(bus))) { 2675 bus->dpc_triggered = true; 2676 } 2677 } 2678 2679 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) 2680 { 2681 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2682 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2683 struct brcmf_sdio *bus = sdiodev->bus; 2684 2685 return &bus->txq; 2686 } 2687 2688 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) 2689 { 2690 struct sk_buff *p; 2691 int eprec = -1; /* precedence to evict from */ 2692 2693 /* Fast case, precedence queue is not full and we are also not 2694 * exceeding total queue length 2695 */ 2696 if (!pktq_pfull(q, prec) && !pktq_full(q)) { 2697 brcmu_pktq_penq(q, prec, pkt); 2698 return true; 2699 } 2700 2701 /* Determine precedence from which to evict packet, if any */ 2702 if (pktq_pfull(q, prec)) { 2703 eprec = prec; 2704 } else if (pktq_full(q)) { 2705 p = brcmu_pktq_peek_tail(q, &eprec); 2706 if (eprec > prec) 2707 return false; 2708 } 2709 2710 /* Evict if needed */ 2711 if (eprec >= 0) { 2712 /* Detect queueing to unconfigured precedence */ 2713 if (eprec == prec) 2714 return false; /* refuse newer (incoming) packet */ 2715 /* Evict packet according to discard policy */ 2716 p = brcmu_pktq_pdeq_tail(q, eprec); 2717 if (p == NULL) 2718 brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); 2719 brcmu_pkt_buf_free_skb(p); 2720 } 2721 2722 /* Enqueue */ 2723 p = brcmu_pktq_penq(q, prec, pkt); 2724 if (p == NULL) 2725 brcmf_err("brcmu_pktq_penq() failed\n"); 2726 2727 return p != NULL; 2728 } 2729 2730 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) 2731 { 2732 int ret = -EBADE; 2733 uint prec; 2734 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2735 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2736 struct brcmf_sdio *bus = sdiodev->bus; 2737 2738 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); 2739 if (sdiodev->state != BRCMF_SDIOD_DATA) 2740 return -EIO; 2741 2742 /* Add space for the header */ 2743 skb_push(pkt, bus->tx_hdrlen); 2744 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ 2745 2746 prec = prio2prec((pkt->priority & PRIOMASK)); 2747 2748 /* Check for existing queue, current flow-control, 2749 pending event, or pending clock */ 2750 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); 2751 bus->sdcnt.fcqueued++; 2752 2753 /* Priority based enq */ 2754 spin_lock_bh(&bus->txq_lock); 2755 /* reset bus_flags in packet cb */ 2756 *(u16 *)(pkt->cb) = 0; 2757 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { 2758 skb_pull(pkt, bus->tx_hdrlen); 2759 brcmf_err("out of bus->txq !!!\n"); 2760 ret = -ENOSR; 2761 } else { 2762 ret = 0; 2763 } 2764 2765 if (pktq_len(&bus->txq) >= TXHI) { 2766 bus->txoff = true; 2767 brcmf_proto_bcdc_txflowblock(dev, true); 2768 } 2769 spin_unlock_bh(&bus->txq_lock); 2770 2771 #ifdef DEBUG 2772 if (pktq_plen(&bus->txq, prec) > qcount[prec]) 2773 qcount[prec] = pktq_plen(&bus->txq, prec); 2774 #endif 2775 2776 brcmf_sdio_trigger_dpc(bus); 2777 return ret; 2778 } 2779 2780 #ifdef DEBUG 2781 #define CONSOLE_LINE_MAX 192 2782 2783 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) 2784 { 2785 struct brcmf_console *c = &bus->console; 2786 u8 line[CONSOLE_LINE_MAX], ch; 2787 u32 n, idx, addr; 2788 int rv; 2789 2790 /* Don't do anything until FWREADY updates console address */ 2791 if (bus->console_addr == 0) 2792 return 0; 2793 2794 /* Read console log struct */ 2795 addr = bus->console_addr + offsetof(struct rte_console, log_le); 2796 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, 2797 sizeof(c->log_le)); 2798 if (rv < 0) 2799 return rv; 2800 2801 /* Allocate console buffer (one time only) */ 2802 if (c->buf == NULL) { 2803 c->bufsize = le32_to_cpu(c->log_le.buf_size); 2804 c->buf = kmalloc(c->bufsize, GFP_ATOMIC); 2805 if (c->buf == NULL) 2806 return -ENOMEM; 2807 } 2808 2809 idx = le32_to_cpu(c->log_le.idx); 2810 2811 /* Protect against corrupt value */ 2812 if (idx > c->bufsize) 2813 return -EBADE; 2814 2815 /* Skip reading the console buffer if the index pointer 2816 has not moved */ 2817 if (idx == c->last) 2818 return 0; 2819 2820 /* Read the console buffer */ 2821 addr = le32_to_cpu(c->log_le.buf); 2822 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); 2823 if (rv < 0) 2824 return rv; 2825 2826 while (c->last != idx) { 2827 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { 2828 if (c->last == idx) { 2829 /* This would output a partial line. 2830 * Instead, back up 2831 * the buffer pointer and output this 2832 * line next time around. 2833 */ 2834 if (c->last >= n) 2835 c->last -= n; 2836 else 2837 c->last = c->bufsize - n; 2838 goto break2; 2839 } 2840 ch = c->buf[c->last]; 2841 c->last = (c->last + 1) % c->bufsize; 2842 if (ch == '\n') 2843 break; 2844 line[n] = ch; 2845 } 2846 2847 if (n > 0) { 2848 if (line[n - 1] == '\r') 2849 n--; 2850 line[n] = 0; 2851 pr_debug("CONSOLE: %s\n", line); 2852 } 2853 } 2854 break2: 2855 2856 return 0; 2857 } 2858 #endif /* DEBUG */ 2859 2860 static int 2861 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) 2862 { 2863 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2864 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2865 struct brcmf_sdio *bus = sdiodev->bus; 2866 int ret; 2867 2868 brcmf_dbg(TRACE, "Enter\n"); 2869 if (sdiodev->state != BRCMF_SDIOD_DATA) 2870 return -EIO; 2871 2872 /* Send from dpc */ 2873 bus->ctrl_frame_buf = msg; 2874 bus->ctrl_frame_len = msglen; 2875 wmb(); 2876 bus->ctrl_frame_stat = true; 2877 2878 brcmf_sdio_trigger_dpc(bus); 2879 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, 2880 CTL_DONE_TIMEOUT); 2881 ret = 0; 2882 if (bus->ctrl_frame_stat) { 2883 sdio_claim_host(bus->sdiodev->func[1]); 2884 if (bus->ctrl_frame_stat) { 2885 brcmf_dbg(SDIO, "ctrl_frame timeout\n"); 2886 bus->ctrl_frame_stat = false; 2887 ret = -ETIMEDOUT; 2888 } 2889 sdio_release_host(bus->sdiodev->func[1]); 2890 } 2891 if (!ret) { 2892 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", 2893 bus->ctrl_frame_err); 2894 rmb(); 2895 ret = bus->ctrl_frame_err; 2896 } 2897 2898 if (ret) 2899 bus->sdcnt.tx_ctlerrs++; 2900 else 2901 bus->sdcnt.tx_ctlpkts++; 2902 2903 return ret; 2904 } 2905 2906 #ifdef DEBUG 2907 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, 2908 struct sdpcm_shared *sh) 2909 { 2910 u32 addr, console_ptr, console_size, console_index; 2911 char *conbuf = NULL; 2912 __le32 sh_val; 2913 int rv; 2914 2915 /* obtain console information from device memory */ 2916 addr = sh->console_addr + offsetof(struct rte_console, log_le); 2917 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2918 (u8 *)&sh_val, sizeof(u32)); 2919 if (rv < 0) 2920 return rv; 2921 console_ptr = le32_to_cpu(sh_val); 2922 2923 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); 2924 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2925 (u8 *)&sh_val, sizeof(u32)); 2926 if (rv < 0) 2927 return rv; 2928 console_size = le32_to_cpu(sh_val); 2929 2930 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); 2931 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2932 (u8 *)&sh_val, sizeof(u32)); 2933 if (rv < 0) 2934 return rv; 2935 console_index = le32_to_cpu(sh_val); 2936 2937 /* allocate buffer for console data */ 2938 if (console_size <= CONSOLE_BUFFER_MAX) 2939 conbuf = vzalloc(console_size+1); 2940 2941 if (!conbuf) 2942 return -ENOMEM; 2943 2944 /* obtain the console data from device */ 2945 conbuf[console_size] = '\0'; 2946 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, 2947 console_size); 2948 if (rv < 0) 2949 goto done; 2950 2951 rv = seq_write(seq, conbuf + console_index, 2952 console_size - console_index); 2953 if (rv < 0) 2954 goto done; 2955 2956 if (console_index > 0) 2957 rv = seq_write(seq, conbuf, console_index - 1); 2958 2959 done: 2960 vfree(conbuf); 2961 return rv; 2962 } 2963 2964 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, 2965 struct sdpcm_shared *sh) 2966 { 2967 int error; 2968 struct brcmf_trap_info tr; 2969 2970 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { 2971 brcmf_dbg(INFO, "no trap in firmware\n"); 2972 return 0; 2973 } 2974 2975 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, 2976 sizeof(struct brcmf_trap_info)); 2977 if (error < 0) 2978 return error; 2979 2980 seq_printf(seq, 2981 "dongle trap info: type 0x%x @ epc 0x%08x\n" 2982 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 2983 " lr 0x%08x pc 0x%08x offset 0x%x\n" 2984 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 2985 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 2986 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 2987 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 2988 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 2989 le32_to_cpu(tr.pc), sh->trap_addr, 2990 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 2991 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 2992 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 2993 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 2994 2995 return 0; 2996 } 2997 2998 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, 2999 struct sdpcm_shared *sh) 3000 { 3001 int error = 0; 3002 char file[80] = "?"; 3003 char expr[80] = "<???>"; 3004 3005 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { 3006 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3007 return 0; 3008 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { 3009 brcmf_dbg(INFO, "no assert in dongle\n"); 3010 return 0; 3011 } 3012 3013 sdio_claim_host(bus->sdiodev->func[1]); 3014 if (sh->assert_file_addr != 0) { 3015 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3016 sh->assert_file_addr, (u8 *)file, 80); 3017 if (error < 0) 3018 return error; 3019 } 3020 if (sh->assert_exp_addr != 0) { 3021 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3022 sh->assert_exp_addr, (u8 *)expr, 80); 3023 if (error < 0) 3024 return error; 3025 } 3026 sdio_release_host(bus->sdiodev->func[1]); 3027 3028 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", 3029 file, sh->assert_line, expr); 3030 return 0; 3031 } 3032 3033 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3034 { 3035 int error; 3036 struct sdpcm_shared sh; 3037 3038 error = brcmf_sdio_readshared(bus, &sh); 3039 3040 if (error < 0) 3041 return error; 3042 3043 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) 3044 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3045 else if (sh.flags & SDPCM_SHARED_ASSERT) 3046 brcmf_err("assertion in dongle\n"); 3047 3048 if (sh.flags & SDPCM_SHARED_TRAP) 3049 brcmf_err("firmware trap in dongle\n"); 3050 3051 return 0; 3052 } 3053 3054 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) 3055 { 3056 int error = 0; 3057 struct sdpcm_shared sh; 3058 3059 error = brcmf_sdio_readshared(bus, &sh); 3060 if (error < 0) 3061 goto done; 3062 3063 error = brcmf_sdio_assert_info(seq, bus, &sh); 3064 if (error < 0) 3065 goto done; 3066 3067 error = brcmf_sdio_trap_info(seq, bus, &sh); 3068 if (error < 0) 3069 goto done; 3070 3071 error = brcmf_sdio_dump_console(seq, bus, &sh); 3072 3073 done: 3074 return error; 3075 } 3076 3077 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) 3078 { 3079 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3080 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; 3081 3082 return brcmf_sdio_died_dump(seq, bus); 3083 } 3084 3085 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) 3086 { 3087 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3088 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3089 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; 3090 3091 seq_printf(seq, 3092 "intrcount: %u\nlastintrs: %u\n" 3093 "pollcnt: %u\nregfails: %u\n" 3094 "tx_sderrs: %u\nfcqueued: %u\n" 3095 "rxrtx: %u\nrx_toolong: %u\n" 3096 "rxc_errors: %u\nrx_hdrfail: %u\n" 3097 "rx_badhdr: %u\nrx_badseq: %u\n" 3098 "fc_rcvd: %u\nfc_xoff: %u\n" 3099 "fc_xon: %u\nrxglomfail: %u\n" 3100 "rxglomframes: %u\nrxglompkts: %u\n" 3101 "f2rxhdrs: %u\nf2rxdata: %u\n" 3102 "f2txdata: %u\nf1regdata: %u\n" 3103 "tickcnt: %u\ntx_ctlerrs: %lu\n" 3104 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" 3105 "rx_ctlpkts: %lu\nrx_readahead: %lu\n", 3106 sdcnt->intrcount, sdcnt->lastintrs, 3107 sdcnt->pollcnt, sdcnt->regfails, 3108 sdcnt->tx_sderrs, sdcnt->fcqueued, 3109 sdcnt->rxrtx, sdcnt->rx_toolong, 3110 sdcnt->rxc_errors, sdcnt->rx_hdrfail, 3111 sdcnt->rx_badhdr, sdcnt->rx_badseq, 3112 sdcnt->fc_rcvd, sdcnt->fc_xoff, 3113 sdcnt->fc_xon, sdcnt->rxglomfail, 3114 sdcnt->rxglomframes, sdcnt->rxglompkts, 3115 sdcnt->f2rxhdrs, sdcnt->f2rxdata, 3116 sdcnt->f2txdata, sdcnt->f1regdata, 3117 sdcnt->tickcnt, sdcnt->tx_ctlerrs, 3118 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, 3119 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); 3120 3121 return 0; 3122 } 3123 3124 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) 3125 { 3126 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr; 3127 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 3128 3129 if (IS_ERR_OR_NULL(dentry)) 3130 return; 3131 3132 bus->console_interval = BRCMF_CONSOLE; 3133 3134 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); 3135 brcmf_debugfs_add_entry(drvr, "counters", 3136 brcmf_debugfs_sdio_count_read); 3137 debugfs_create_u32("console_interval", 0644, dentry, 3138 &bus->console_interval); 3139 } 3140 #else 3141 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3142 { 3143 return 0; 3144 } 3145 3146 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus) 3147 { 3148 } 3149 #endif /* DEBUG */ 3150 3151 static int 3152 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) 3153 { 3154 int timeleft; 3155 uint rxlen = 0; 3156 bool pending; 3157 u8 *buf; 3158 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3159 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3160 struct brcmf_sdio *bus = sdiodev->bus; 3161 3162 brcmf_dbg(TRACE, "Enter\n"); 3163 if (sdiodev->state != BRCMF_SDIOD_DATA) 3164 return -EIO; 3165 3166 /* Wait until control frame is available */ 3167 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); 3168 3169 spin_lock_bh(&bus->rxctl_lock); 3170 rxlen = bus->rxlen; 3171 memcpy(msg, bus->rxctl, min(msglen, rxlen)); 3172 bus->rxctl = NULL; 3173 buf = bus->rxctl_orig; 3174 bus->rxctl_orig = NULL; 3175 bus->rxlen = 0; 3176 spin_unlock_bh(&bus->rxctl_lock); 3177 vfree(buf); 3178 3179 if (rxlen) { 3180 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", 3181 rxlen, msglen); 3182 } else if (timeleft == 0) { 3183 brcmf_err("resumed on timeout\n"); 3184 brcmf_sdio_checkdied(bus); 3185 } else if (pending) { 3186 brcmf_dbg(CTL, "cancelled\n"); 3187 return -ERESTARTSYS; 3188 } else { 3189 brcmf_dbg(CTL, "resumed for unknown reason?\n"); 3190 brcmf_sdio_checkdied(bus); 3191 } 3192 3193 if (rxlen) 3194 bus->sdcnt.rx_ctlpkts++; 3195 else 3196 bus->sdcnt.rx_ctlerrs++; 3197 3198 return rxlen ? (int)rxlen : -ETIMEDOUT; 3199 } 3200 3201 #ifdef DEBUG 3202 static bool 3203 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3204 u8 *ram_data, uint ram_sz) 3205 { 3206 char *ram_cmp; 3207 int err; 3208 bool ret = true; 3209 int address; 3210 int offset; 3211 int len; 3212 3213 /* read back and verify */ 3214 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, 3215 ram_sz); 3216 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); 3217 /* do not proceed while no memory but */ 3218 if (!ram_cmp) 3219 return true; 3220 3221 address = ram_addr; 3222 offset = 0; 3223 while (offset < ram_sz) { 3224 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : 3225 ram_sz - offset; 3226 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); 3227 if (err) { 3228 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3229 err, len, address); 3230 ret = false; 3231 break; 3232 } else if (memcmp(ram_cmp, &ram_data[offset], len)) { 3233 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", 3234 offset, len); 3235 ret = false; 3236 break; 3237 } 3238 offset += len; 3239 address += len; 3240 } 3241 3242 kfree(ram_cmp); 3243 3244 return ret; 3245 } 3246 #else /* DEBUG */ 3247 static bool 3248 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3249 u8 *ram_data, uint ram_sz) 3250 { 3251 return true; 3252 } 3253 #endif /* DEBUG */ 3254 3255 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, 3256 const struct firmware *fw) 3257 { 3258 int err; 3259 3260 brcmf_dbg(TRACE, "Enter\n"); 3261 3262 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, 3263 (u8 *)fw->data, fw->size); 3264 if (err) 3265 brcmf_err("error %d on writing %d membytes at 0x%08x\n", 3266 err, (int)fw->size, bus->ci->rambase); 3267 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, 3268 (u8 *)fw->data, fw->size)) 3269 err = -EIO; 3270 3271 return err; 3272 } 3273 3274 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, 3275 void *vars, u32 varsz) 3276 { 3277 int address; 3278 int err; 3279 3280 brcmf_dbg(TRACE, "Enter\n"); 3281 3282 address = bus->ci->ramsize - varsz + bus->ci->rambase; 3283 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); 3284 if (err) 3285 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", 3286 err, varsz, address); 3287 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) 3288 err = -EIO; 3289 3290 return err; 3291 } 3292 3293 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, 3294 const struct firmware *fw, 3295 void *nvram, u32 nvlen) 3296 { 3297 int bcmerror; 3298 u32 rstvec; 3299 3300 sdio_claim_host(bus->sdiodev->func[1]); 3301 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 3302 3303 rstvec = get_unaligned_le32(fw->data); 3304 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); 3305 3306 bcmerror = brcmf_sdio_download_code_file(bus, fw); 3307 release_firmware(fw); 3308 if (bcmerror) { 3309 brcmf_err("dongle image file download failed\n"); 3310 brcmf_fw_nvram_free(nvram); 3311 goto err; 3312 } 3313 3314 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); 3315 brcmf_fw_nvram_free(nvram); 3316 if (bcmerror) { 3317 brcmf_err("dongle nvram file download failed\n"); 3318 goto err; 3319 } 3320 3321 /* Take arm out of reset */ 3322 if (!brcmf_chip_set_active(bus->ci, rstvec)) { 3323 brcmf_err("error getting out of ARM core reset\n"); 3324 goto err; 3325 } 3326 3327 err: 3328 brcmf_sdio_clkctl(bus, CLK_SDONLY, false); 3329 sdio_release_host(bus->sdiodev->func[1]); 3330 return bcmerror; 3331 } 3332 3333 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) 3334 { 3335 int err = 0; 3336 u8 val; 3337 3338 brcmf_dbg(TRACE, "Enter\n"); 3339 3340 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); 3341 if (err) { 3342 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); 3343 return; 3344 } 3345 3346 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; 3347 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); 3348 if (err) { 3349 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); 3350 return; 3351 } 3352 3353 /* Add CMD14 Support */ 3354 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, 3355 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | 3356 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT), 3357 &err); 3358 if (err) { 3359 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); 3360 return; 3361 } 3362 3363 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3364 SBSDIO_FORCE_HT, &err); 3365 if (err) { 3366 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); 3367 return; 3368 } 3369 3370 /* set flag */ 3371 bus->sr_enabled = true; 3372 brcmf_dbg(INFO, "SR enabled\n"); 3373 } 3374 3375 /* enable KSO bit */ 3376 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) 3377 { 3378 struct brcmf_core *core = bus->sdio_core; 3379 u8 val; 3380 int err = 0; 3381 3382 brcmf_dbg(TRACE, "Enter\n"); 3383 3384 /* KSO bit added in SDIO core rev 12 */ 3385 if (core->rev < 12) 3386 return 0; 3387 3388 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); 3389 if (err) { 3390 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); 3391 return err; 3392 } 3393 3394 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { 3395 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << 3396 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 3397 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 3398 val, &err); 3399 if (err) { 3400 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); 3401 return err; 3402 } 3403 } 3404 3405 return 0; 3406 } 3407 3408 3409 static int brcmf_sdio_bus_preinit(struct device *dev) 3410 { 3411 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3412 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3413 struct brcmf_sdio *bus = sdiodev->bus; 3414 struct brcmf_core *core = bus->sdio_core; 3415 uint pad_size; 3416 u32 value; 3417 int err; 3418 3419 /* the commands below use the terms tx and rx from 3420 * a device perspective, ie. bus:txglom affects the 3421 * bus transfers from device to host. 3422 */ 3423 if (core->rev < 12) { 3424 /* for sdio core rev < 12, disable txgloming */ 3425 value = 0; 3426 err = brcmf_iovar_data_set(dev, "bus:txglom", &value, 3427 sizeof(u32)); 3428 } else { 3429 /* otherwise, set txglomalign */ 3430 value = sdiodev->settings->bus.sdio.sd_sgentry_align; 3431 /* SDIO ADMA requires at least 32 bit alignment */ 3432 value = max_t(u32, value, ALIGNMENT); 3433 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value, 3434 sizeof(u32)); 3435 } 3436 3437 if (err < 0) 3438 goto done; 3439 3440 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 3441 if (sdiodev->sg_support) { 3442 bus->txglom = false; 3443 value = 1; 3444 pad_size = bus->sdiodev->func[2]->cur_blksize << 1; 3445 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", 3446 &value, sizeof(u32)); 3447 if (err < 0) { 3448 /* bus:rxglom is allowed to fail */ 3449 err = 0; 3450 } else { 3451 bus->txglom = true; 3452 bus->tx_hdrlen += SDPCM_HWEXT_LEN; 3453 } 3454 } 3455 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); 3456 3457 done: 3458 return err; 3459 } 3460 3461 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev) 3462 { 3463 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3464 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3465 struct brcmf_sdio *bus = sdiodev->bus; 3466 3467 return bus->ci->ramsize - bus->ci->srsize; 3468 } 3469 3470 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data, 3471 size_t mem_size) 3472 { 3473 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3474 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3475 struct brcmf_sdio *bus = sdiodev->bus; 3476 int err; 3477 int address; 3478 int offset; 3479 int len; 3480 3481 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase, 3482 mem_size); 3483 3484 address = bus->ci->rambase; 3485 offset = err = 0; 3486 sdio_claim_host(sdiodev->func[1]); 3487 while (offset < mem_size) { 3488 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK : 3489 mem_size - offset; 3490 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len); 3491 if (err) { 3492 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3493 err, len, address); 3494 goto done; 3495 } 3496 data += len; 3497 offset += len; 3498 address += len; 3499 } 3500 3501 done: 3502 sdio_release_host(sdiodev->func[1]); 3503 return err; 3504 } 3505 3506 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) 3507 { 3508 if (!bus->dpc_triggered) { 3509 bus->dpc_triggered = true; 3510 queue_work(bus->brcmf_wq, &bus->datawork); 3511 } 3512 } 3513 3514 void brcmf_sdio_isr(struct brcmf_sdio *bus) 3515 { 3516 brcmf_dbg(TRACE, "Enter\n"); 3517 3518 if (!bus) { 3519 brcmf_err("bus is null pointer, exiting\n"); 3520 return; 3521 } 3522 3523 /* Count the interrupt call */ 3524 bus->sdcnt.intrcount++; 3525 if (in_interrupt()) 3526 atomic_set(&bus->ipend, 1); 3527 else 3528 if (brcmf_sdio_intr_rstatus(bus)) { 3529 brcmf_err("failed backplane access\n"); 3530 } 3531 3532 /* Disable additional interrupts (is this needed now)? */ 3533 if (!bus->intr) 3534 brcmf_err("isr w/o interrupt configured!\n"); 3535 3536 bus->dpc_triggered = true; 3537 queue_work(bus->brcmf_wq, &bus->datawork); 3538 } 3539 3540 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) 3541 { 3542 brcmf_dbg(TIMER, "Enter\n"); 3543 3544 /* Poll period: check device if appropriate. */ 3545 if (!bus->sr_enabled && 3546 bus->poll && (++bus->polltick >= bus->pollrate)) { 3547 u32 intstatus = 0; 3548 3549 /* Reset poll tick */ 3550 bus->polltick = 0; 3551 3552 /* Check device if no interrupts */ 3553 if (!bus->intr || 3554 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { 3555 3556 if (!bus->dpc_triggered) { 3557 u8 devpend; 3558 3559 sdio_claim_host(bus->sdiodev->func[1]); 3560 devpend = brcmf_sdiod_func0_rb(bus->sdiodev, 3561 SDIO_CCCR_INTx, 3562 NULL); 3563 sdio_release_host(bus->sdiodev->func[1]); 3564 intstatus = devpend & (INTR_STATUS_FUNC1 | 3565 INTR_STATUS_FUNC2); 3566 } 3567 3568 /* If there is something, make like the ISR and 3569 schedule the DPC */ 3570 if (intstatus) { 3571 bus->sdcnt.pollcnt++; 3572 atomic_set(&bus->ipend, 1); 3573 3574 bus->dpc_triggered = true; 3575 queue_work(bus->brcmf_wq, &bus->datawork); 3576 } 3577 } 3578 3579 /* Update interrupt tracking */ 3580 bus->sdcnt.lastintrs = bus->sdcnt.intrcount; 3581 } 3582 #ifdef DEBUG 3583 /* Poll for console output periodically */ 3584 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() && 3585 bus->console_interval != 0) { 3586 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL); 3587 if (bus->console.count >= bus->console_interval) { 3588 bus->console.count -= bus->console_interval; 3589 sdio_claim_host(bus->sdiodev->func[1]); 3590 /* Make sure backplane clock is on */ 3591 brcmf_sdio_bus_sleep(bus, false, false); 3592 if (brcmf_sdio_readconsole(bus) < 0) 3593 /* stop on error */ 3594 bus->console_interval = 0; 3595 sdio_release_host(bus->sdiodev->func[1]); 3596 } 3597 } 3598 #endif /* DEBUG */ 3599 3600 /* On idle timeout clear activity flag and/or turn off clock */ 3601 if (!bus->dpc_triggered) { 3602 rmb(); 3603 if ((!bus->dpc_running) && (bus->idletime > 0) && 3604 (bus->clkstate == CLK_AVAIL)) { 3605 bus->idlecount++; 3606 if (bus->idlecount > bus->idletime) { 3607 brcmf_dbg(SDIO, "idle\n"); 3608 sdio_claim_host(bus->sdiodev->func[1]); 3609 brcmf_sdio_wd_timer(bus, false); 3610 bus->idlecount = 0; 3611 brcmf_sdio_bus_sleep(bus, true, false); 3612 sdio_release_host(bus->sdiodev->func[1]); 3613 } 3614 } else { 3615 bus->idlecount = 0; 3616 } 3617 } else { 3618 bus->idlecount = 0; 3619 } 3620 } 3621 3622 static void brcmf_sdio_dataworker(struct work_struct *work) 3623 { 3624 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, 3625 datawork); 3626 3627 bus->dpc_running = true; 3628 wmb(); 3629 while (READ_ONCE(bus->dpc_triggered)) { 3630 bus->dpc_triggered = false; 3631 brcmf_sdio_dpc(bus); 3632 bus->idlecount = 0; 3633 } 3634 bus->dpc_running = false; 3635 if (brcmf_sdiod_freezing(bus->sdiodev)) { 3636 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); 3637 brcmf_sdiod_try_freeze(bus->sdiodev); 3638 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 3639 } 3640 } 3641 3642 static void 3643 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, 3644 struct brcmf_chip *ci, u32 drivestrength) 3645 { 3646 const struct sdiod_drive_str *str_tab = NULL; 3647 u32 str_mask; 3648 u32 str_shift; 3649 u32 i; 3650 u32 drivestrength_sel = 0; 3651 u32 cc_data_temp; 3652 u32 addr; 3653 3654 if (!(ci->cc_caps & CC_CAP_PMU)) 3655 return; 3656 3657 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { 3658 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): 3659 str_tab = sdiod_drvstr_tab1_1v8; 3660 str_mask = 0x00003800; 3661 str_shift = 11; 3662 break; 3663 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): 3664 str_tab = sdiod_drvstr_tab6_1v8; 3665 str_mask = 0x00001800; 3666 str_shift = 11; 3667 break; 3668 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): 3669 /* note: 43143 does not support tristate */ 3670 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; 3671 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { 3672 str_tab = sdiod_drvstr_tab2_3v3; 3673 str_mask = 0x00000007; 3674 str_shift = 0; 3675 } else 3676 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", 3677 ci->name, drivestrength); 3678 break; 3679 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): 3680 str_tab = sdiod_drive_strength_tab5_1v8; 3681 str_mask = 0x00003800; 3682 str_shift = 11; 3683 break; 3684 default: 3685 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n", 3686 ci->name, ci->chiprev, ci->pmurev); 3687 break; 3688 } 3689 3690 if (str_tab != NULL) { 3691 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci); 3692 3693 for (i = 0; str_tab[i].strength != 0; i++) { 3694 if (drivestrength >= str_tab[i].strength) { 3695 drivestrength_sel = str_tab[i].sel; 3696 break; 3697 } 3698 } 3699 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); 3700 brcmf_sdiod_writel(sdiodev, addr, 1, NULL); 3701 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL); 3702 cc_data_temp &= ~str_mask; 3703 drivestrength_sel <<= str_shift; 3704 cc_data_temp |= drivestrength_sel; 3705 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL); 3706 3707 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", 3708 str_tab[i].strength, drivestrength, cc_data_temp); 3709 } 3710 } 3711 3712 static int brcmf_sdio_buscoreprep(void *ctx) 3713 { 3714 struct brcmf_sdio_dev *sdiodev = ctx; 3715 int err = 0; 3716 u8 clkval, clkset; 3717 3718 /* Try forcing SDIO core to do ALPAvail request only */ 3719 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; 3720 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3721 if (err) { 3722 brcmf_err("error writing for HT off\n"); 3723 return err; 3724 } 3725 3726 /* If register supported, wait for ALPAvail and then force ALP */ 3727 /* This may take up to 15 milliseconds */ 3728 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL); 3729 3730 if ((clkval & ~SBSDIO_AVBITS) != clkset) { 3731 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", 3732 clkset, clkval); 3733 return -EACCES; 3734 } 3735 3736 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3737 NULL)), 3738 !SBSDIO_ALPAV(clkval)), 3739 PMU_MAX_TRANSITION_DLY); 3740 3741 if (!SBSDIO_ALPAV(clkval)) { 3742 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", 3743 clkval); 3744 return -EBUSY; 3745 } 3746 3747 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; 3748 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3749 udelay(65); 3750 3751 /* Also, disable the extra SDIO pull-ups */ 3752 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); 3753 3754 return 0; 3755 } 3756 3757 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, 3758 u32 rstvec) 3759 { 3760 struct brcmf_sdio_dev *sdiodev = ctx; 3761 struct brcmf_core *core = sdiodev->bus->sdio_core; 3762 u32 reg_addr; 3763 3764 /* clear all interrupts */ 3765 reg_addr = core->base + SD_REG(intstatus); 3766 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL); 3767 3768 if (rstvec) 3769 /* Write reset vector to address 0 */ 3770 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, 3771 sizeof(rstvec)); 3772 } 3773 3774 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) 3775 { 3776 struct brcmf_sdio_dev *sdiodev = ctx; 3777 u32 val, rev; 3778 3779 val = brcmf_sdiod_readl(sdiodev, addr, NULL); 3780 if ((sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 || 3781 sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4339) && 3782 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) { 3783 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; 3784 if (rev >= 2) { 3785 val &= ~CID_ID_MASK; 3786 val |= BRCM_CC_4339_CHIP_ID; 3787 } 3788 } 3789 return val; 3790 } 3791 3792 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) 3793 { 3794 struct brcmf_sdio_dev *sdiodev = ctx; 3795 3796 brcmf_sdiod_writel(sdiodev, addr, val, NULL); 3797 } 3798 3799 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { 3800 .prepare = brcmf_sdio_buscoreprep, 3801 .activate = brcmf_sdio_buscore_activate, 3802 .read32 = brcmf_sdio_buscore_read32, 3803 .write32 = brcmf_sdio_buscore_write32, 3804 }; 3805 3806 static bool 3807 brcmf_sdio_probe_attach(struct brcmf_sdio *bus) 3808 { 3809 struct brcmf_sdio_dev *sdiodev; 3810 u8 clkctl = 0; 3811 int err = 0; 3812 int reg_addr; 3813 u32 reg_val; 3814 u32 drivestrength; 3815 3816 sdiodev = bus->sdiodev; 3817 sdio_claim_host(sdiodev->func[1]); 3818 3819 pr_debug("F1 signature read @0x18000000=0x%4x\n", 3820 brcmf_sdiod_readl(sdiodev, SI_ENUM_BASE, NULL)); 3821 3822 /* 3823 * Force PLL off until brcmf_chip_attach() 3824 * programs PLL control regs 3825 */ 3826 3827 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1, 3828 &err); 3829 if (!err) 3830 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3831 &err); 3832 3833 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { 3834 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", 3835 err, BRCMF_INIT_CLKCTL1, clkctl); 3836 goto fail; 3837 } 3838 3839 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops); 3840 if (IS_ERR(bus->ci)) { 3841 brcmf_err("brcmf_chip_attach failed!\n"); 3842 bus->ci = NULL; 3843 goto fail; 3844 } 3845 3846 /* Pick up the SDIO core info struct from chip.c */ 3847 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 3848 if (!bus->sdio_core) 3849 goto fail; 3850 3851 sdiodev->settings = brcmf_get_module_param(sdiodev->dev, 3852 BRCMF_BUSTYPE_SDIO, 3853 bus->ci->chip, 3854 bus->ci->chiprev); 3855 if (!sdiodev->settings) { 3856 brcmf_err("Failed to get device parameters\n"); 3857 goto fail; 3858 } 3859 /* platform specific configuration: 3860 * alignments must be at least 4 bytes for ADMA 3861 */ 3862 bus->head_align = ALIGNMENT; 3863 bus->sgentry_align = ALIGNMENT; 3864 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT) 3865 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align; 3866 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT) 3867 bus->sgentry_align = 3868 sdiodev->settings->bus.sdio.sd_sgentry_align; 3869 3870 /* allocate scatter-gather table. sg support 3871 * will be disabled upon allocation failure. 3872 */ 3873 brcmf_sdiod_sgtable_alloc(sdiodev); 3874 3875 #ifdef CONFIG_PM_SLEEP 3876 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ 3877 * is true or when platform data OOB irq is true). 3878 */ 3879 if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) && 3880 ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) || 3881 (sdiodev->settings->bus.sdio.oob_irq_supported))) 3882 sdiodev->bus_if->wowl_supported = true; 3883 #endif 3884 3885 if (brcmf_sdio_kso_init(bus)) { 3886 brcmf_err("error enabling KSO\n"); 3887 goto fail; 3888 } 3889 3890 if (sdiodev->settings->bus.sdio.drive_strength) 3891 drivestrength = sdiodev->settings->bus.sdio.drive_strength; 3892 else 3893 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; 3894 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength); 3895 3896 /* Set card control so an SDIO card reset does a WLAN backplane reset */ 3897 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err); 3898 if (err) 3899 goto fail; 3900 3901 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; 3902 3903 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); 3904 if (err) 3905 goto fail; 3906 3907 /* set PMUControl so a backplane reset does PMU state reload */ 3908 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol); 3909 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err); 3910 if (err) 3911 goto fail; 3912 3913 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); 3914 3915 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err); 3916 if (err) 3917 goto fail; 3918 3919 sdio_release_host(sdiodev->func[1]); 3920 3921 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); 3922 3923 /* allocate header buffer */ 3924 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); 3925 if (!bus->hdrbuf) 3926 return false; 3927 /* Locate an appropriately-aligned portion of hdrbuf */ 3928 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], 3929 bus->head_align); 3930 3931 /* Set the poll and/or interrupt flags */ 3932 bus->intr = true; 3933 bus->poll = false; 3934 if (bus->poll) 3935 bus->pollrate = 1; 3936 3937 return true; 3938 3939 fail: 3940 sdio_release_host(sdiodev->func[1]); 3941 return false; 3942 } 3943 3944 static int 3945 brcmf_sdio_watchdog_thread(void *data) 3946 { 3947 struct brcmf_sdio *bus = (struct brcmf_sdio *)data; 3948 int wait; 3949 3950 allow_signal(SIGTERM); 3951 /* Run until signal received */ 3952 brcmf_sdiod_freezer_count(bus->sdiodev); 3953 while (1) { 3954 if (kthread_should_stop()) 3955 break; 3956 brcmf_sdiod_freezer_uncount(bus->sdiodev); 3957 wait = wait_for_completion_interruptible(&bus->watchdog_wait); 3958 brcmf_sdiod_freezer_count(bus->sdiodev); 3959 brcmf_sdiod_try_freeze(bus->sdiodev); 3960 if (!wait) { 3961 brcmf_sdio_bus_watchdog(bus); 3962 /* Count the tick for reference */ 3963 bus->sdcnt.tickcnt++; 3964 reinit_completion(&bus->watchdog_wait); 3965 } else 3966 break; 3967 } 3968 return 0; 3969 } 3970 3971 static void 3972 brcmf_sdio_watchdog(struct timer_list *t) 3973 { 3974 struct brcmf_sdio *bus = from_timer(bus, t, timer); 3975 3976 if (bus->watchdog_tsk) { 3977 complete(&bus->watchdog_wait); 3978 /* Reschedule the watchdog */ 3979 if (bus->wd_active) 3980 mod_timer(&bus->timer, 3981 jiffies + BRCMF_WD_POLL); 3982 } 3983 } 3984 3985 static int brcmf_sdio_get_fwname(struct device *dev, u32 chip, u32 chiprev, 3986 u8 *fw_name) 3987 { 3988 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3989 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3990 int ret = 0; 3991 3992 if (sdiodev->fw_name[0] != '\0') 3993 strlcpy(fw_name, sdiodev->fw_name, BRCMF_FW_NAME_LEN); 3994 else 3995 ret = brcmf_fw_map_chip_to_name(chip, chiprev, 3996 brcmf_sdio_fwnames, 3997 ARRAY_SIZE(brcmf_sdio_fwnames), 3998 fw_name, NULL); 3999 4000 return ret; 4001 } 4002 4003 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = { 4004 .stop = brcmf_sdio_bus_stop, 4005 .preinit = brcmf_sdio_bus_preinit, 4006 .txdata = brcmf_sdio_bus_txdata, 4007 .txctl = brcmf_sdio_bus_txctl, 4008 .rxctl = brcmf_sdio_bus_rxctl, 4009 .gettxq = brcmf_sdio_bus_gettxq, 4010 .wowl_config = brcmf_sdio_wowl_config, 4011 .get_ramsize = brcmf_sdio_bus_get_ramsize, 4012 .get_memdump = brcmf_sdio_bus_get_memdump, 4013 .get_fwname = brcmf_sdio_get_fwname, 4014 }; 4015 4016 static void brcmf_sdio_firmware_callback(struct device *dev, int err, 4017 const struct firmware *code, 4018 void *nvram, u32 nvram_len) 4019 { 4020 struct brcmf_bus *bus_if; 4021 struct brcmf_sdio_dev *sdiodev; 4022 struct brcmf_sdio *bus; 4023 u8 saveclk; 4024 4025 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err); 4026 bus_if = dev_get_drvdata(dev); 4027 sdiodev = bus_if->bus_priv.sdio; 4028 if (err) 4029 goto fail; 4030 4031 if (!bus_if->drvr) 4032 return; 4033 4034 bus = sdiodev->bus; 4035 4036 /* try to download image and nvram to the dongle */ 4037 bus->alp_only = true; 4038 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); 4039 if (err) 4040 goto fail; 4041 bus->alp_only = false; 4042 4043 /* Start the watchdog timer */ 4044 bus->sdcnt.tickcnt = 0; 4045 brcmf_sdio_wd_timer(bus, true); 4046 4047 sdio_claim_host(sdiodev->func[1]); 4048 4049 /* Make sure backplane clock is on, needed to generate F2 interrupt */ 4050 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4051 if (bus->clkstate != CLK_AVAIL) 4052 goto release; 4053 4054 /* Force clocks on backplane to be sure F2 interrupt propagates */ 4055 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err); 4056 if (!err) { 4057 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 4058 (saveclk | SBSDIO_FORCE_HT), &err); 4059 } 4060 if (err) { 4061 brcmf_err("Failed to force clock for F2: err %d\n", err); 4062 goto release; 4063 } 4064 4065 /* Enable function 2 (frame transfers) */ 4066 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, 4067 SD_REG(tosbmailboxdata)); 4068 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]); 4069 4070 4071 brcmf_dbg(INFO, "enable F2: err=%d\n", err); 4072 4073 /* If F2 successfully enabled, set core and enable interrupts */ 4074 if (!err) { 4075 /* Set up the interrupt mask and enable interrupts */ 4076 bus->hostintmask = HOSTINTMASK; 4077 w_sdreg32(bus, bus->hostintmask, SD_REG(hostintmask)); 4078 4079 brcmf_sdiod_writeb(sdiodev, SBSDIO_WATERMARK, 8, &err); 4080 } else { 4081 /* Disable F2 again */ 4082 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]); 4083 goto release; 4084 } 4085 4086 if (brcmf_chip_sr_capable(bus->ci)) { 4087 brcmf_sdio_sr_init(bus); 4088 } else { 4089 /* Restore previous clock setting */ 4090 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 4091 saveclk, &err); 4092 } 4093 4094 if (err == 0) { 4095 /* Allow full data communication using DPC from now on. */ 4096 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 4097 4098 err = brcmf_sdiod_intr_register(sdiodev); 4099 if (err != 0) 4100 brcmf_err("intr register failed:%d\n", err); 4101 } 4102 4103 /* If we didn't come up, turn off backplane clock */ 4104 if (err != 0) 4105 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4106 4107 sdio_release_host(sdiodev->func[1]); 4108 4109 err = brcmf_bus_started(dev); 4110 if (err != 0) { 4111 brcmf_err("dongle is not responding\n"); 4112 goto fail; 4113 } 4114 return; 4115 4116 release: 4117 sdio_release_host(sdiodev->func[1]); 4118 fail: 4119 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); 4120 device_release_driver(&sdiodev->func[2]->dev); 4121 device_release_driver(dev); 4122 } 4123 4124 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) 4125 { 4126 int ret; 4127 struct brcmf_sdio *bus; 4128 struct workqueue_struct *wq; 4129 4130 brcmf_dbg(TRACE, "Enter\n"); 4131 4132 /* Allocate private bus interface state */ 4133 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC); 4134 if (!bus) 4135 goto fail; 4136 4137 bus->sdiodev = sdiodev; 4138 sdiodev->bus = bus; 4139 skb_queue_head_init(&bus->glom); 4140 bus->txbound = BRCMF_TXBOUND; 4141 bus->rxbound = BRCMF_RXBOUND; 4142 bus->txminmax = BRCMF_TXMINMAX; 4143 bus->tx_seq = SDPCM_SEQ_WRAP - 1; 4144 4145 /* single-threaded workqueue */ 4146 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM, 4147 dev_name(&sdiodev->func[1]->dev)); 4148 if (!wq) { 4149 brcmf_err("insufficient memory to create txworkqueue\n"); 4150 goto fail; 4151 } 4152 brcmf_sdiod_freezer_count(sdiodev); 4153 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); 4154 bus->brcmf_wq = wq; 4155 4156 /* attempt to attach to the dongle */ 4157 if (!(brcmf_sdio_probe_attach(bus))) { 4158 brcmf_err("brcmf_sdio_probe_attach failed\n"); 4159 goto fail; 4160 } 4161 4162 spin_lock_init(&bus->rxctl_lock); 4163 spin_lock_init(&bus->txq_lock); 4164 init_waitqueue_head(&bus->ctrl_wait); 4165 init_waitqueue_head(&bus->dcmd_resp_wait); 4166 4167 /* Set up the watchdog timer */ 4168 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0); 4169 /* Initialize watchdog thread */ 4170 init_completion(&bus->watchdog_wait); 4171 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, 4172 bus, "brcmf_wdog/%s", 4173 dev_name(&sdiodev->func[1]->dev)); 4174 if (IS_ERR(bus->watchdog_tsk)) { 4175 pr_warn("brcmf_watchdog thread failed to start\n"); 4176 bus->watchdog_tsk = NULL; 4177 } 4178 /* Initialize DPC thread */ 4179 bus->dpc_triggered = false; 4180 bus->dpc_running = false; 4181 4182 /* Assign bus interface call back */ 4183 bus->sdiodev->bus_if->dev = bus->sdiodev->dev; 4184 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops; 4185 bus->sdiodev->bus_if->chip = bus->ci->chip; 4186 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev; 4187 4188 /* default sdio bus header length for tx packet */ 4189 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 4190 4191 /* Attach to the common layer, reserve hdr space */ 4192 ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings); 4193 if (ret != 0) { 4194 brcmf_err("brcmf_attach failed\n"); 4195 goto fail; 4196 } 4197 4198 /* Query the F2 block size, set roundup accordingly */ 4199 bus->blocksize = bus->sdiodev->func[2]->cur_blksize; 4200 bus->roundup = min(max_roundup, bus->blocksize); 4201 4202 /* Allocate buffers */ 4203 if (bus->sdiodev->bus_if->maxctl) { 4204 bus->sdiodev->bus_if->maxctl += bus->roundup; 4205 bus->rxblen = 4206 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN), 4207 ALIGNMENT) + bus->head_align; 4208 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC); 4209 if (!(bus->rxbuf)) { 4210 brcmf_err("rxbuf allocation failed\n"); 4211 goto fail; 4212 } 4213 } 4214 4215 sdio_claim_host(bus->sdiodev->func[1]); 4216 4217 /* Disable F2 to clear any intermediate frame state on the dongle */ 4218 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]); 4219 4220 bus->rxflow = false; 4221 4222 /* Done with backplane-dependent accesses, can drop clock... */ 4223 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 4224 4225 sdio_release_host(bus->sdiodev->func[1]); 4226 4227 /* ...and initialize clock/power states */ 4228 bus->clkstate = CLK_SDONLY; 4229 bus->idletime = BRCMF_IDLE_INTERVAL; 4230 bus->idleclock = BRCMF_IDLE_ACTIVE; 4231 4232 /* SR state */ 4233 bus->sr_enabled = false; 4234 4235 brcmf_sdio_debugfs_create(bus); 4236 brcmf_dbg(INFO, "completed!!\n"); 4237 4238 ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev, 4239 brcmf_sdio_fwnames, 4240 ARRAY_SIZE(brcmf_sdio_fwnames), 4241 sdiodev->fw_name, sdiodev->nvram_name); 4242 if (ret) 4243 goto fail; 4244 4245 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM, 4246 sdiodev->fw_name, sdiodev->nvram_name, 4247 brcmf_sdio_firmware_callback); 4248 if (ret != 0) { 4249 brcmf_err("async firmware request failed: %d\n", ret); 4250 goto fail; 4251 } 4252 4253 return bus; 4254 4255 fail: 4256 brcmf_sdio_remove(bus); 4257 return NULL; 4258 } 4259 4260 /* Detach and free everything */ 4261 void brcmf_sdio_remove(struct brcmf_sdio *bus) 4262 { 4263 brcmf_dbg(TRACE, "Enter\n"); 4264 4265 if (bus) { 4266 /* De-register interrupt handler */ 4267 brcmf_sdiod_intr_unregister(bus->sdiodev); 4268 4269 brcmf_detach(bus->sdiodev->dev); 4270 4271 cancel_work_sync(&bus->datawork); 4272 if (bus->brcmf_wq) 4273 destroy_workqueue(bus->brcmf_wq); 4274 4275 if (bus->ci) { 4276 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 4277 sdio_claim_host(bus->sdiodev->func[1]); 4278 brcmf_sdio_wd_timer(bus, false); 4279 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4280 /* Leave the device in state where it is 4281 * 'passive'. This is done by resetting all 4282 * necessary cores. 4283 */ 4284 msleep(20); 4285 brcmf_chip_set_passive(bus->ci); 4286 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4287 sdio_release_host(bus->sdiodev->func[1]); 4288 } 4289 brcmf_chip_detach(bus->ci); 4290 } 4291 if (bus->sdiodev->settings) 4292 brcmf_release_module_param(bus->sdiodev->settings); 4293 4294 kfree(bus->rxbuf); 4295 kfree(bus->hdrbuf); 4296 kfree(bus); 4297 } 4298 4299 brcmf_dbg(TRACE, "Disconnected\n"); 4300 } 4301 4302 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active) 4303 { 4304 /* Totally stop the timer */ 4305 if (!active && bus->wd_active) { 4306 del_timer_sync(&bus->timer); 4307 bus->wd_active = false; 4308 return; 4309 } 4310 4311 /* don't start the wd until fw is loaded */ 4312 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) 4313 return; 4314 4315 if (active) { 4316 if (!bus->wd_active) { 4317 /* Create timer again when watchdog period is 4318 dynamically changed or in the first instance 4319 */ 4320 bus->timer.expires = jiffies + BRCMF_WD_POLL; 4321 add_timer(&bus->timer); 4322 bus->wd_active = true; 4323 } else { 4324 /* Re arm the timer, at last watchdog period */ 4325 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL); 4326 } 4327 } 4328 } 4329 4330 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) 4331 { 4332 int ret; 4333 4334 sdio_claim_host(bus->sdiodev->func[1]); 4335 ret = brcmf_sdio_bus_sleep(bus, sleep, false); 4336 sdio_release_host(bus->sdiodev->func[1]); 4337 4338 return ret; 4339 } 4340 4341