1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2010 Broadcom Corporation 4 */ 5 6 #include <linux/types.h> 7 #include <linux/atomic.h> 8 #include <linux/kernel.h> 9 #include <linux/kthread.h> 10 #include <linux/printk.h> 11 #include <linux/pci_ids.h> 12 #include <linux/netdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/sched/signal.h> 15 #include <linux/mmc/sdio.h> 16 #include <linux/mmc/sdio_ids.h> 17 #include <linux/mmc/sdio_func.h> 18 #include <linux/mmc/card.h> 19 #include <linux/mmc/core.h> 20 #include <linux/semaphore.h> 21 #include <linux/firmware.h> 22 #include <linux/module.h> 23 #include <linux/bcma/bcma.h> 24 #include <linux/debugfs.h> 25 #include <linux/vmalloc.h> 26 #include <linux/unaligned.h> 27 #include <defs.h> 28 #include <brcmu_wifi.h> 29 #include <brcmu_utils.h> 30 #include <brcm_hw_ids.h> 31 #include <soc.h> 32 #include "sdio.h" 33 #include "chip.h" 34 #include "firmware.h" 35 #include "core.h" 36 #include "common.h" 37 #include "bcdc.h" 38 39 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500) 40 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500) 41 42 /* watermark expressed in number of words */ 43 #define DEFAULT_F2_WATERMARK 0x8 44 #define CY_4373_F2_WATERMARK 0x40 45 #define CY_4373_F1_MESBUSYCTRL (CY_4373_F2_WATERMARK | SBSDIO_MESBUSYCTRL_ENAB) 46 #define CY_43012_F2_WATERMARK 0x60 47 #define CY_43012_MES_WATERMARK 0x50 48 #define CY_43012_MESBUSYCTRL (CY_43012_MES_WATERMARK | \ 49 SBSDIO_MESBUSYCTRL_ENAB) 50 #define CY_4339_F2_WATERMARK 48 51 #define CY_4339_MES_WATERMARK 80 52 #define CY_4339_MESBUSYCTRL (CY_4339_MES_WATERMARK | \ 53 SBSDIO_MESBUSYCTRL_ENAB) 54 #define CY_43455_F2_WATERMARK 0x60 55 #define CY_43455_MES_WATERMARK 0x50 56 #define CY_43455_MESBUSYCTRL (CY_43455_MES_WATERMARK | \ 57 SBSDIO_MESBUSYCTRL_ENAB) 58 #define CY_435X_F2_WATERMARK 0x40 59 #define CY_435X_F1_MESBUSYCTRL (CY_435X_F2_WATERMARK | \ 60 SBSDIO_MESBUSYCTRL_ENAB) 61 62 #ifdef DEBUG 63 64 #define BRCMF_TRAP_INFO_SIZE 80 65 66 #define CBUF_LEN (128) 67 68 /* Device console log buffer state */ 69 #define CONSOLE_BUFFER_MAX 2024 70 71 struct rte_log_le { 72 __le32 buf; /* Can't be pointer on (64-bit) hosts */ 73 __le32 buf_size; 74 __le32 idx; 75 char *_buf_compat; /* Redundant pointer for backward compat. */ 76 }; 77 78 struct rte_console { 79 /* Virtual UART 80 * When there is no UART (e.g. Quickturn), 81 * the host should write a complete 82 * input line directly into cbuf and then write 83 * the length into vcons_in. 84 * This may also be used when there is a real UART 85 * (at risk of conflicting with 86 * the real UART). vcons_out is currently unused. 87 */ 88 uint vcons_in; 89 uint vcons_out; 90 91 /* Output (logging) buffer 92 * Console output is written to a ring buffer log_buf at index log_idx. 93 * The host may read the output when it sees log_idx advance. 94 * Output will be lost if the output wraps around faster than the host 95 * polls. 96 */ 97 struct rte_log_le log_le; 98 99 /* Console input line buffer 100 * Characters are read one at a time into cbuf 101 * until <CR> is received, then 102 * the buffer is processed as a command line. 103 * Also used for virtual UART. 104 */ 105 uint cbuf_idx; 106 char cbuf[CBUF_LEN]; 107 }; 108 109 #endif /* DEBUG */ 110 #include <chipcommon.h> 111 112 #include "bus.h" 113 #include "debug.h" 114 #include "tracepoint.h" 115 116 #define TXQLEN 2048 /* bulk tx queue length */ 117 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ 118 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ 119 #define PRIOMASK 7 120 121 #define TXRETRIES 2 /* # of retries for tx frames */ 122 123 #define BRCMF_RXBOUND 50 /* Default for max rx frames in 124 one scheduling */ 125 126 #define BRCMF_TXBOUND 20 /* Default for max tx frames in 127 one scheduling */ 128 129 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ 130 131 #define MEMBLOCK 2048 /* Block size used for downloading 132 of dongle image */ 133 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold 134 biggest possible glom */ 135 136 #define BRCMF_FIRSTREAD (1 << 6) 137 138 /* SBSDIO_DEVICE_CTL */ 139 140 /* 1: device will assert busy signal when receiving CMD53 */ 141 #define SBSDIO_DEVCTL_SETBUSY 0x01 142 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ 143 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 144 /* 1: mask all interrupts to host except the chipActive (rev 8) */ 145 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 146 /* 1: isolate internal sdio signals, put external pads in tri-state; requires 147 * sdio bus power cycle to clear (rev 9) */ 148 #define SBSDIO_DEVCTL_PADS_ISO 0x08 149 /* 1: enable F2 Watermark */ 150 #define SBSDIO_DEVCTL_F2WM_ENAB 0x10 151 /* Force SD->SB reset mapping (rev 11) */ 152 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30 153 /* Determined by CoreControl bit */ 154 #define SBSDIO_DEVCTL_RST_CORECTL 0x00 155 /* Force backplane reset */ 156 #define SBSDIO_DEVCTL_RST_BPRESET 0x10 157 /* Force no backplane reset */ 158 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 159 160 /* direct(mapped) cis space */ 161 162 /* MAPPED common CIS address */ 163 #define SBSDIO_CIS_BASE_COMMON 0x1000 164 /* maximum bytes in one CIS */ 165 #define SBSDIO_CIS_SIZE_LIMIT 0x200 166 /* cis offset addr is < 17 bits */ 167 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF 168 169 /* manfid tuple length, include tuple, link bytes */ 170 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6 171 172 #define SD_REG(field) \ 173 (offsetof(struct sdpcmd_regs, field)) 174 175 /* SDIO function 1 register CHIPCLKCSR */ 176 /* Force ALP request to backplane */ 177 #define SBSDIO_FORCE_ALP 0x01 178 /* Force HT request to backplane */ 179 #define SBSDIO_FORCE_HT 0x02 180 /* Force ILP request to backplane */ 181 #define SBSDIO_FORCE_ILP 0x04 182 /* Make ALP ready (power up xtal) */ 183 #define SBSDIO_ALP_AVAIL_REQ 0x08 184 /* Make HT ready (power up PLL) */ 185 #define SBSDIO_HT_AVAIL_REQ 0x10 186 /* Squelch clock requests from HW */ 187 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 188 /* Status: ALP is ready */ 189 #define SBSDIO_ALP_AVAIL 0x40 190 /* Status: HT is ready */ 191 #define SBSDIO_HT_AVAIL 0x80 192 #define SBSDIO_CSR_MASK 0x1F 193 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 194 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 195 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 196 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 197 #define SBSDIO_CLKAV(regval, alponly) \ 198 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 199 200 /* intstatus */ 201 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 202 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 203 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 204 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 205 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 206 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 207 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 208 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 209 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 210 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 211 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 212 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 213 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 214 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 215 #define I_PC (1 << 10) /* descriptor error */ 216 #define I_PD (1 << 11) /* data error */ 217 #define I_DE (1 << 12) /* Descriptor protocol Error */ 218 #define I_RU (1 << 13) /* Receive descriptor Underflow */ 219 #define I_RO (1 << 14) /* Receive fifo Overflow */ 220 #define I_XU (1 << 15) /* Transmit fifo Underflow */ 221 #define I_RI (1 << 16) /* Receive Interrupt */ 222 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 223 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 224 #define I_XI (1 << 24) /* Transmit Interrupt */ 225 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 226 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 227 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 228 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 229 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ 230 #define I_SRESET (1 << 30) /* CCCR RES interrupt */ 231 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 232 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 233 #define I_DMA (I_RI | I_XI | I_ERRORS) 234 235 /* corecontrol */ 236 #define CC_CISRDY (1 << 0) /* CIS Ready */ 237 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */ 238 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 239 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ 240 #define CC_XMTDATAAVAIL_MODE (1 << 4) 241 #define CC_XMTDATAAVAIL_CTRL (1 << 5) 242 243 /* SDA_FRAMECTRL */ 244 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 245 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 246 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ 247 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ 248 249 /* 250 * Software allocation of To SB Mailbox resources 251 */ 252 253 /* tosbmailbox bits corresponding to intstatus bits */ 254 #define SMB_NAK (1 << 0) /* Frame NAK */ 255 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ 256 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ 257 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ 258 259 /* tosbmailboxdata */ 260 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ 261 262 /* 263 * Software allocation of To Host Mailbox resources 264 */ 265 266 /* intstatus bits */ 267 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ 268 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ 269 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ 270 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ 271 272 /* tohostmailboxdata */ 273 #define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */ 274 #define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */ 275 #define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */ 276 #define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */ 277 #define HMB_DATA_FWHALT 0x0010 /* firmware halted */ 278 279 #define HMB_DATA_FCDATA_MASK 0xff000000 280 #define HMB_DATA_FCDATA_SHIFT 24 281 282 #define HMB_DATA_VERSION_MASK 0x00ff0000 283 #define HMB_DATA_VERSION_SHIFT 16 284 285 /* 286 * Software-defined protocol header 287 */ 288 289 /* Current protocol version */ 290 #define SDPCM_PROT_VERSION 4 291 292 /* 293 * Shared structure between dongle and the host. 294 * The structure contains pointers to trap or assert information. 295 */ 296 #define SDPCM_SHARED_VERSION 0x0003 297 #define SDPCM_SHARED_VERSION_MASK 0x00FF 298 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 299 #define SDPCM_SHARED_ASSERT 0x0200 300 #define SDPCM_SHARED_TRAP 0x0400 301 302 /* Space for header read, limit for data packets */ 303 #define MAX_HDR_READ (1 << 6) 304 #define MAX_RX_DATASZ 2048 305 306 /* Bump up limit on waiting for HT to account for first startup; 307 * if the image is doing a CRC calculation before programming the PMU 308 * for HT availability, it could take a couple hundred ms more, so 309 * max out at a 1 second (1000000us). 310 */ 311 #undef PMU_MAX_TRANSITION_DLY 312 #define PMU_MAX_TRANSITION_DLY 1000000 313 314 /* Value for ChipClockCSR during initial setup */ 315 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ 316 SBSDIO_ALP_AVAIL_REQ) 317 318 /* Flags for SDH calls */ 319 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 320 321 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change 322 * when idle 323 */ 324 #define BRCMF_IDLE_INTERVAL 1 325 326 #define KSO_WAIT_US 50 327 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) 328 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5 329 330 #ifdef DEBUG 331 /* Device console log buffer state */ 332 struct brcmf_console { 333 uint count; /* Poll interval msec counter */ 334 uint log_addr; /* Log struct address (fixed) */ 335 struct rte_log_le log_le; /* Log struct (host copy) */ 336 uint bufsize; /* Size of log buffer */ 337 u8 *buf; /* Log buffer (host copy) */ 338 uint last; /* Last buffer read index */ 339 }; 340 341 struct brcmf_trap_info { 342 __le32 type; 343 __le32 epc; 344 __le32 cpsr; 345 __le32 spsr; 346 __le32 r0; /* a1 */ 347 __le32 r1; /* a2 */ 348 __le32 r2; /* a3 */ 349 __le32 r3; /* a4 */ 350 __le32 r4; /* v1 */ 351 __le32 r5; /* v2 */ 352 __le32 r6; /* v3 */ 353 __le32 r7; /* v4 */ 354 __le32 r8; /* v5 */ 355 __le32 r9; /* sb/v6 */ 356 __le32 r10; /* sl/v7 */ 357 __le32 r11; /* fp/v8 */ 358 __le32 r12; /* ip */ 359 __le32 r13; /* sp */ 360 __le32 r14; /* lr */ 361 __le32 pc; /* r15 */ 362 }; 363 #endif /* DEBUG */ 364 365 struct sdpcm_shared { 366 u32 flags; 367 u32 trap_addr; 368 u32 assert_exp_addr; 369 u32 assert_file_addr; 370 u32 assert_line; 371 u32 console_addr; /* Address of struct rte_console */ 372 u32 msgtrace_addr; 373 u8 tag[32]; 374 u32 brpt_addr; 375 }; 376 377 struct sdpcm_shared_le { 378 __le32 flags; 379 __le32 trap_addr; 380 __le32 assert_exp_addr; 381 __le32 assert_file_addr; 382 __le32 assert_line; 383 __le32 console_addr; /* Address of struct rte_console */ 384 __le32 msgtrace_addr; 385 u8 tag[32]; 386 __le32 brpt_addr; 387 }; 388 389 /* dongle SDIO bus specific header info */ 390 struct brcmf_sdio_hdrinfo { 391 u8 seq_num; 392 u8 channel; 393 u16 len; 394 u16 len_left; 395 u16 len_nxtfrm; 396 u8 dat_offset; 397 bool lastfrm; 398 u16 tail_pad; 399 }; 400 401 /* 402 * hold counter variables 403 */ 404 struct brcmf_sdio_count { 405 uint intrcount; /* Count of device interrupt callbacks */ 406 uint lastintrs; /* Count as of last watchdog timer */ 407 uint pollcnt; /* Count of active polls */ 408 uint regfails; /* Count of R_REG failures */ 409 uint tx_sderrs; /* Count of tx attempts with sd errors */ 410 uint fcqueued; /* Tx packets that got queued */ 411 uint rxrtx; /* Count of rtx requests (NAK to dongle) */ 412 uint rx_toolong; /* Receive frames too long to receive */ 413 uint rxc_errors; /* SDIO errors when reading control frames */ 414 uint rx_hdrfail; /* SDIO errors on header reads */ 415 uint rx_badhdr; /* Bad received headers (roosync?) */ 416 uint rx_badseq; /* Mismatched rx sequence number */ 417 uint fc_rcvd; /* Number of flow-control events received */ 418 uint fc_xoff; /* Number which turned on flow-control */ 419 uint fc_xon; /* Number which turned off flow-control */ 420 uint rxglomfail; /* Failed deglom attempts */ 421 uint rxglomframes; /* Number of glom frames (superframes) */ 422 uint rxglompkts; /* Number of packets from glom frames */ 423 uint f2rxhdrs; /* Number of header reads */ 424 uint f2rxdata; /* Number of frame data reads */ 425 uint f2txdata; /* Number of f2 frame writes */ 426 uint f1regdata; /* Number of f1 register accesses */ 427 uint tickcnt; /* Number of watchdog been schedule */ 428 ulong tx_ctlerrs; /* Err of sending ctrl frames */ 429 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ 430 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ 431 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ 432 ulong rx_readahead_cnt; /* packets where header read-ahead was used */ 433 }; 434 435 /* misc chip info needed by some of the routines */ 436 /* Private data for SDIO bus interaction */ 437 struct brcmf_sdio { 438 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ 439 struct brcmf_chip *ci; /* Chip info struct */ 440 struct brcmf_core *sdio_core; /* sdio core info struct */ 441 442 u32 hostintmask; /* Copy of Host Interrupt Mask */ 443 atomic_t intstatus; /* Intstatus bits (events) pending */ 444 atomic_t fcstate; /* State of dongle flow-control */ 445 446 uint blocksize; /* Block size of SDIO transfers */ 447 uint roundup; /* Max roundup limit */ 448 449 struct pktq txq; /* Queue length used for flow-control */ 450 u8 flowcontrol; /* per prio flow control bitmask */ 451 u8 tx_seq; /* Transmit sequence number (next) */ 452 u8 tx_max; /* Maximum transmit sequence allowed */ 453 454 u8 *hdrbuf; /* buffer for handling rx frame */ 455 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ 456 u8 rx_seq; /* Receive sequence number (expected) */ 457 struct brcmf_sdio_hdrinfo cur_read; 458 /* info of current read frame */ 459 bool rxskip; /* Skip receive (awaiting NAK ACK) */ 460 bool rxpending; /* Data frame pending in dongle */ 461 462 uint rxbound; /* Rx frames to read before resched */ 463 uint txbound; /* Tx frames to send before resched */ 464 uint txminmax; 465 466 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 467 struct sk_buff_head glom; /* Packet list for glommed superframe */ 468 469 u8 *rxbuf; /* Buffer for receiving control packets */ 470 uint rxblen; /* Allocated length of rxbuf */ 471 u8 *rxctl; /* Aligned pointer into rxbuf */ 472 u8 *rxctl_orig; /* pointer for freeing rxctl */ 473 uint rxlen; /* Length of valid data in buffer */ 474 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ 475 476 u8 sdpcm_ver; /* Bus protocol reported by dongle */ 477 478 bool intr; /* Use interrupts */ 479 bool poll; /* Use polling */ 480 atomic_t ipend; /* Device interrupt is pending */ 481 uint spurious; /* Count of spurious interrupts */ 482 uint pollrate; /* Ticks between device polls */ 483 uint polltick; /* Tick counter */ 484 485 #ifdef DEBUG 486 uint console_interval; 487 struct brcmf_console console; /* Console output polling support */ 488 uint console_addr; /* Console address from shared struct */ 489 #endif /* DEBUG */ 490 491 uint clkstate; /* State of sd and backplane clock(s) */ 492 s32 idletime; /* Control for activity timeout */ 493 s32 idlecount; /* Activity timeout counter */ 494 s32 idleclock; /* How to set bus driver when idle */ 495 bool rxflow_mode; /* Rx flow control mode */ 496 bool rxflow; /* Is rx flow control on */ 497 bool alp_only; /* Don't use HT clock (ALP only) */ 498 499 u8 *ctrl_frame_buf; 500 u16 ctrl_frame_len; 501 bool ctrl_frame_stat; 502 int ctrl_frame_err; 503 504 spinlock_t txq_lock; /* protect bus->txq */ 505 wait_queue_head_t ctrl_wait; 506 wait_queue_head_t dcmd_resp_wait; 507 508 struct timer_list timer; 509 struct completion watchdog_wait; 510 struct task_struct *watchdog_tsk; 511 bool wd_active; 512 513 struct workqueue_struct *brcmf_wq; 514 struct work_struct datawork; 515 bool dpc_triggered; 516 bool dpc_running; 517 518 bool txoff; /* Transmit flow-controlled */ 519 struct brcmf_sdio_count sdcnt; 520 bool sr_enabled; /* SaveRestore enabled */ 521 bool sleeping; 522 523 u8 tx_hdrlen; /* sdio bus header length for tx packet */ 524 bool txglom; /* host tx glomming enable flag */ 525 u16 head_align; /* buffer pointer alignment */ 526 u16 sgentry_align; /* scatter-gather buffer alignment */ 527 }; 528 529 /* clkstate */ 530 #define CLK_NONE 0 531 #define CLK_SDONLY 1 532 #define CLK_PENDING 2 533 #define CLK_AVAIL 3 534 535 #ifdef DEBUG 536 static int qcount[NUMPRIO]; 537 #endif /* DEBUG */ 538 539 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ 540 541 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) 542 543 /* Limit on rounding up frames */ 544 static const uint max_roundup = 512; 545 546 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 547 #define ALIGNMENT 8 548 #else 549 #define ALIGNMENT 4 550 #endif 551 552 enum brcmf_sdio_frmtype { 553 BRCMF_SDIO_FT_NORMAL, 554 BRCMF_SDIO_FT_SUPER, 555 BRCMF_SDIO_FT_SUB, 556 }; 557 558 #define SDIOD_DRVSTR_KEY(chip, pmu) (((unsigned int)(chip) << 16) | (pmu)) 559 560 /* SDIO Pad drive strength to select value mappings */ 561 struct sdiod_drive_str { 562 u8 strength; /* Pad Drive Strength in mA */ 563 u8 sel; /* Chip-specific select value */ 564 }; 565 566 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ 567 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { 568 {32, 0x6}, 569 {26, 0x7}, 570 {22, 0x4}, 571 {16, 0x5}, 572 {12, 0x2}, 573 {8, 0x3}, 574 {4, 0x0}, 575 {0, 0x1} 576 }; 577 578 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ 579 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { 580 {6, 0x7}, 581 {5, 0x6}, 582 {4, 0x5}, 583 {3, 0x4}, 584 {2, 0x2}, 585 {1, 0x1}, 586 {0, 0x0} 587 }; 588 589 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ 590 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { 591 {3, 0x3}, 592 {2, 0x2}, 593 {1, 0x1}, 594 {0, 0x0} }; 595 596 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ 597 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { 598 {16, 0x7}, 599 {12, 0x5}, 600 {8, 0x3}, 601 {4, 0x1} 602 }; 603 604 BRCMF_FW_DEF(43143, "brcmfmac43143-sdio"); 605 BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio"); 606 BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio"); 607 BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio"); 608 BRCMF_FW_DEF(4329, "brcmfmac4329-sdio"); 609 BRCMF_FW_DEF(4330, "brcmfmac4330-sdio"); 610 BRCMF_FW_DEF(4334, "brcmfmac4334-sdio"); 611 BRCMF_FW_DEF(43340, "brcmfmac43340-sdio"); 612 BRCMF_FW_DEF(4335, "brcmfmac4335-sdio"); 613 BRCMF_FW_DEF(43362, "brcmfmac43362-sdio"); 614 BRCMF_FW_DEF(4339, "brcmfmac4339-sdio"); 615 BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio"); 616 /* Note the names are not postfixed with a1 for backward compatibility */ 617 BRCMF_FW_CLM_DEF(43430A1, "brcmfmac43430-sdio"); 618 BRCMF_FW_DEF(43430B0, "brcmfmac43430b0-sdio"); 619 BRCMF_FW_CLM_DEF(43439, "brcmfmac43439-sdio"); 620 BRCMF_FW_CLM_DEF(43455, "brcmfmac43455-sdio"); 621 BRCMF_FW_DEF(43456, "brcmfmac43456-sdio"); 622 BRCMF_FW_CLM_DEF(4354, "brcmfmac4354-sdio"); 623 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-sdio"); 624 BRCMF_FW_DEF(4359, "brcmfmac4359-sdio"); 625 BRCMF_FW_CLM_DEF(4373, "brcmfmac4373-sdio"); 626 BRCMF_FW_CLM_DEF(43012, "brcmfmac43012-sdio"); 627 BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-sdio"); 628 629 /* firmware config files */ 630 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.txt"); 631 632 /* per-board firmware binaries */ 633 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.bin"); 634 635 static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { 636 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143), 637 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0), 638 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4), 639 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5), 640 BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329), 641 BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330), 642 BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334), 643 BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340), 644 BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340), 645 BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335), 646 BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362), 647 BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), 648 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0), 649 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000002, 43430A1), 650 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFC, 43430B0), 651 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456), 652 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455), 653 BRCMF_FW_ENTRY(BRCM_CC_43454_CHIP_ID, 0x00000040, 43455), 654 BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354), 655 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 656 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 657 BRCMF_FW_ENTRY(BRCM_CC_43751_CHIP_ID, 0xFFFFFFFF, 43752), 658 BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752), 659 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373), 660 BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012), 661 BRCMF_FW_ENTRY(CY_CC_43439_CHIP_ID, 0xFFFFFFFF, 43439), 662 }; 663 664 #define TXCTL_CREDITS 2 665 666 static void pkt_align(struct sk_buff *p, int len, int align) 667 { 668 uint datalign; 669 datalign = (unsigned long)(p->data); 670 datalign = roundup(datalign, (align)) - datalign; 671 if (datalign) 672 skb_pull(p, datalign); 673 __skb_trim(p, len); 674 } 675 676 /* To check if there's window offered */ 677 static bool data_ok(struct brcmf_sdio *bus) 678 { 679 u8 tx_rsv = 0; 680 681 /* Reserve TXCTL_CREDITS credits for txctl when it is ready to send */ 682 if (bus->ctrl_frame_stat) 683 tx_rsv = TXCTL_CREDITS; 684 685 return (bus->tx_max - bus->tx_seq - tx_rsv) != 0 && 686 ((bus->tx_max - bus->tx_seq - tx_rsv) & 0x80) == 0; 687 688 } 689 690 /* To check if there's window offered */ 691 static bool txctl_ok(struct brcmf_sdio *bus) 692 { 693 return (bus->tx_max - bus->tx_seq) != 0 && 694 ((bus->tx_max - bus->tx_seq) & 0x80) == 0; 695 } 696 697 static int 698 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) 699 { 700 u8 wr_val = 0, rd_val, cmp_val, bmask; 701 int err = 0; 702 int err_cnt = 0; 703 int try_cnt = 0; 704 705 brcmf_dbg(TRACE, "Enter: on=%d\n", on); 706 707 sdio_retune_crc_disable(bus->sdiodev->func1); 708 709 /* Cannot re-tune if device is asleep; defer till we're awake */ 710 if (on) 711 sdio_retune_hold_now(bus->sdiodev->func1); 712 713 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 714 /* 1st KSO write goes to AOS wake up core if device is asleep */ 715 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err); 716 717 /* In case of 43012 chip, the chip could go down immediately after 718 * KSO bit is cleared. So the further reads of KSO register could 719 * fail. Thereby just bailing out immediately after clearing KSO 720 * bit, to avoid polling of KSO bit. 721 */ 722 if (!on && bus->ci->chip == CY_CC_43012_CHIP_ID) 723 return err; 724 725 if (on) { 726 /* device WAKEUP through KSO: 727 * write bit 0 & read back until 728 * both bits 0 (kso bit) & 1 (dev on status) are set 729 */ 730 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | 731 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; 732 bmask = cmp_val; 733 usleep_range(2000, 3000); 734 } else { 735 /* Put device to sleep, turn off KSO */ 736 cmp_val = 0; 737 /* only check for bit0, bit1(dev on status) may not 738 * get cleared right away 739 */ 740 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; 741 } 742 743 do { 744 /* reliable KSO bit set/clr: 745 * the sdiod sleep write access is synced to PMU 32khz clk 746 * just one write attempt may fail, 747 * read it back until it matches written value 748 */ 749 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 750 &err); 751 if (!err) { 752 if ((rd_val & bmask) == cmp_val) 753 break; 754 err_cnt = 0; 755 } 756 /* bail out upon subsequent access errors */ 757 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS)) 758 break; 759 760 udelay(KSO_WAIT_US); 761 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, 762 &err); 763 764 } while (try_cnt++ < MAX_KSO_ATTEMPTS); 765 766 if (try_cnt > 2) 767 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, 768 rd_val, err); 769 770 if (try_cnt > MAX_KSO_ATTEMPTS) 771 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); 772 773 if (on) 774 sdio_retune_release(bus->sdiodev->func1); 775 776 sdio_retune_crc_enable(bus->sdiodev->func1); 777 778 return err; 779 } 780 781 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) 782 783 /* Turn backplane clock on or off */ 784 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) 785 { 786 int err; 787 u8 clkctl, clkreq, devctl; 788 unsigned long timeout; 789 790 brcmf_dbg(SDIO, "Enter\n"); 791 792 clkctl = 0; 793 794 if (bus->sr_enabled) { 795 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); 796 return 0; 797 } 798 799 if (on) { 800 /* Request HT Avail */ 801 clkreq = 802 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 803 804 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 805 clkreq, &err); 806 if (err) { 807 brcmf_err("HT Avail request error: %d\n", err); 808 return -EBADE; 809 } 810 811 /* Check current status */ 812 clkctl = brcmf_sdiod_readb(bus->sdiodev, 813 SBSDIO_FUNC1_CHIPCLKCSR, &err); 814 if (err) { 815 brcmf_err("HT Avail read error: %d\n", err); 816 return -EBADE; 817 } 818 819 /* Go to pending and await interrupt if appropriate */ 820 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { 821 /* Allow only clock-available interrupt */ 822 devctl = brcmf_sdiod_readb(bus->sdiodev, 823 SBSDIO_DEVICE_CTL, &err); 824 if (err) { 825 brcmf_err("Devctl error setting CA: %d\n", err); 826 return -EBADE; 827 } 828 829 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; 830 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 831 devctl, &err); 832 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); 833 bus->clkstate = CLK_PENDING; 834 835 return 0; 836 } else if (bus->clkstate == CLK_PENDING) { 837 /* Cancel CA-only interrupt filter */ 838 devctl = brcmf_sdiod_readb(bus->sdiodev, 839 SBSDIO_DEVICE_CTL, &err); 840 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 841 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 842 devctl, &err); 843 } 844 845 /* Otherwise, wait here (polling) for HT Avail */ 846 timeout = jiffies + 847 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); 848 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 849 clkctl = brcmf_sdiod_readb(bus->sdiodev, 850 SBSDIO_FUNC1_CHIPCLKCSR, 851 &err); 852 if (time_after(jiffies, timeout)) 853 break; 854 else 855 usleep_range(5000, 10000); 856 } 857 if (err) { 858 brcmf_err("HT Avail request error: %d\n", err); 859 return -EBADE; 860 } 861 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 862 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", 863 PMU_MAX_TRANSITION_DLY, clkctl); 864 return -EBADE; 865 } 866 867 /* Mark clock available */ 868 bus->clkstate = CLK_AVAIL; 869 brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); 870 871 #if defined(DEBUG) 872 if (!bus->alp_only) { 873 if (SBSDIO_ALPONLY(clkctl)) 874 brcmf_err("HT Clock should be on\n"); 875 } 876 #endif /* defined (DEBUG) */ 877 878 } else { 879 clkreq = 0; 880 881 if (bus->clkstate == CLK_PENDING) { 882 /* Cancel CA-only interrupt filter */ 883 devctl = brcmf_sdiod_readb(bus->sdiodev, 884 SBSDIO_DEVICE_CTL, &err); 885 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 886 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 887 devctl, &err); 888 } 889 890 bus->clkstate = CLK_SDONLY; 891 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 892 clkreq, &err); 893 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); 894 if (err) { 895 brcmf_err("Failed access turning clock off: %d\n", 896 err); 897 return -EBADE; 898 } 899 } 900 return 0; 901 } 902 903 /* Change idle/active SD state */ 904 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) 905 { 906 brcmf_dbg(SDIO, "Enter\n"); 907 908 if (on) 909 bus->clkstate = CLK_SDONLY; 910 else 911 bus->clkstate = CLK_NONE; 912 913 return 0; 914 } 915 916 /* Transition SD and backplane clock readiness */ 917 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) 918 { 919 #ifdef DEBUG 920 uint oldstate = bus->clkstate; 921 #endif /* DEBUG */ 922 923 brcmf_dbg(SDIO, "Enter\n"); 924 925 /* Early exit if we're already there */ 926 if (bus->clkstate == target) 927 return 0; 928 929 switch (target) { 930 case CLK_AVAIL: 931 /* Make sure SD clock is available */ 932 if (bus->clkstate == CLK_NONE) 933 brcmf_sdio_sdclk(bus, true); 934 /* Now request HT Avail on the backplane */ 935 brcmf_sdio_htclk(bus, true, pendok); 936 break; 937 938 case CLK_SDONLY: 939 /* Remove HT request, or bring up SD clock */ 940 if (bus->clkstate == CLK_NONE) 941 brcmf_sdio_sdclk(bus, true); 942 else if (bus->clkstate == CLK_AVAIL) 943 brcmf_sdio_htclk(bus, false, false); 944 else 945 brcmf_err("request for %d -> %d\n", 946 bus->clkstate, target); 947 break; 948 949 case CLK_NONE: 950 /* Make sure to remove HT request */ 951 if (bus->clkstate == CLK_AVAIL) 952 brcmf_sdio_htclk(bus, false, false); 953 /* Now remove the SD clock */ 954 brcmf_sdio_sdclk(bus, false); 955 break; 956 } 957 #ifdef DEBUG 958 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); 959 #endif /* DEBUG */ 960 961 return 0; 962 } 963 964 static int 965 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) 966 { 967 int err = 0; 968 u8 clkcsr; 969 970 brcmf_dbg(SDIO, "Enter: request %s currently %s\n", 971 (sleep ? "SLEEP" : "WAKE"), 972 (bus->sleeping ? "SLEEP" : "WAKE")); 973 974 /* If SR is enabled control bus state with KSO */ 975 if (bus->sr_enabled) { 976 /* Done if we're already in the requested state */ 977 if (sleep == bus->sleeping) 978 goto end; 979 980 /* Going to sleep */ 981 if (sleep) { 982 clkcsr = brcmf_sdiod_readb(bus->sdiodev, 983 SBSDIO_FUNC1_CHIPCLKCSR, 984 &err); 985 if ((clkcsr & SBSDIO_CSR_MASK) == 0) { 986 brcmf_dbg(SDIO, "no clock, set ALP\n"); 987 brcmf_sdiod_writeb(bus->sdiodev, 988 SBSDIO_FUNC1_CHIPCLKCSR, 989 SBSDIO_ALP_AVAIL_REQ, &err); 990 } 991 err = brcmf_sdio_kso_control(bus, false); 992 } else { 993 err = brcmf_sdio_kso_control(bus, true); 994 } 995 if (err) { 996 brcmf_err("error while changing bus sleep state %d\n", 997 err); 998 goto done; 999 } 1000 } 1001 1002 end: 1003 /* control clocks */ 1004 if (sleep) { 1005 if (!bus->sr_enabled) 1006 brcmf_sdio_clkctl(bus, CLK_NONE, pendok); 1007 } else { 1008 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); 1009 brcmf_sdio_wd_timer(bus, true); 1010 } 1011 bus->sleeping = sleep; 1012 brcmf_dbg(SDIO, "new state %s\n", 1013 (sleep ? "SLEEP" : "WAKE")); 1014 done: 1015 brcmf_dbg(SDIO, "Exit: err=%d\n", err); 1016 return err; 1017 1018 } 1019 1020 #ifdef DEBUG 1021 static inline bool brcmf_sdio_valid_shared_address(u32 addr) 1022 { 1023 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); 1024 } 1025 1026 static int brcmf_sdio_readshared(struct brcmf_sdio *bus, 1027 struct sdpcm_shared *sh) 1028 { 1029 u32 addr = 0; 1030 int rv; 1031 u32 shaddr = 0; 1032 struct sdpcm_shared_le sh_le; 1033 __le32 addr_le; 1034 1035 sdio_claim_host(bus->sdiodev->func1); 1036 brcmf_sdio_bus_sleep(bus, false, false); 1037 1038 /* 1039 * Read last word in socram to determine 1040 * address of sdpcm_shared structure 1041 */ 1042 shaddr = bus->ci->rambase + bus->ci->ramsize - 4; 1043 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci)) 1044 shaddr -= bus->ci->srsize; 1045 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, 1046 (u8 *)&addr_le, 4); 1047 if (rv < 0) 1048 goto fail; 1049 1050 /* 1051 * Check if addr is valid. 1052 * NVRAM length at the end of memory should have been overwritten. 1053 */ 1054 addr = le32_to_cpu(addr_le); 1055 if (!brcmf_sdio_valid_shared_address(addr)) { 1056 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr); 1057 rv = -EINVAL; 1058 goto fail; 1059 } 1060 1061 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr); 1062 1063 /* Read hndrte_shared structure */ 1064 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, 1065 sizeof(struct sdpcm_shared_le)); 1066 if (rv < 0) 1067 goto fail; 1068 1069 sdio_release_host(bus->sdiodev->func1); 1070 1071 /* Endianness */ 1072 sh->flags = le32_to_cpu(sh_le.flags); 1073 sh->trap_addr = le32_to_cpu(sh_le.trap_addr); 1074 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); 1075 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); 1076 sh->assert_line = le32_to_cpu(sh_le.assert_line); 1077 sh->console_addr = le32_to_cpu(sh_le.console_addr); 1078 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); 1079 1080 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { 1081 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", 1082 SDPCM_SHARED_VERSION, 1083 sh->flags & SDPCM_SHARED_VERSION_MASK); 1084 return -EPROTO; 1085 } 1086 return 0; 1087 1088 fail: 1089 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n", 1090 rv, addr); 1091 sdio_release_host(bus->sdiodev->func1); 1092 return rv; 1093 } 1094 1095 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1096 { 1097 struct sdpcm_shared sh; 1098 1099 if (brcmf_sdio_readshared(bus, &sh) == 0) 1100 bus->console_addr = sh.console_addr; 1101 } 1102 #else 1103 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1104 { 1105 } 1106 #endif /* DEBUG */ 1107 1108 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) 1109 { 1110 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1111 struct brcmf_core *core = bus->sdio_core; 1112 u32 intstatus = 0; 1113 u32 hmb_data; 1114 u8 fcbits; 1115 int ret; 1116 1117 brcmf_dbg(SDIO, "Enter\n"); 1118 1119 /* Read mailbox data and ack that we did so */ 1120 hmb_data = brcmf_sdiod_readl(sdiod, 1121 core->base + SD_REG(tohostmailboxdata), 1122 &ret); 1123 1124 if (!ret) 1125 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1126 SMB_INT_ACK, &ret); 1127 1128 bus->sdcnt.f1regdata += 2; 1129 1130 /* dongle indicates the firmware has halted/crashed */ 1131 if (hmb_data & HMB_DATA_FWHALT) { 1132 brcmf_dbg(SDIO, "mailbox indicates firmware halted\n"); 1133 brcmf_fw_crashed(&sdiod->func1->dev); 1134 } 1135 1136 /* Dongle recomposed rx frames, accept them again */ 1137 if (hmb_data & HMB_DATA_NAKHANDLED) { 1138 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", 1139 bus->rx_seq); 1140 if (!bus->rxskip) 1141 brcmf_err("unexpected NAKHANDLED!\n"); 1142 1143 bus->rxskip = false; 1144 intstatus |= I_HMB_FRAME_IND; 1145 } 1146 1147 /* 1148 * DEVREADY does not occur with gSPI. 1149 */ 1150 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { 1151 bus->sdpcm_ver = 1152 (hmb_data & HMB_DATA_VERSION_MASK) >> 1153 HMB_DATA_VERSION_SHIFT; 1154 if (bus->sdpcm_ver != SDPCM_PROT_VERSION) 1155 brcmf_err("Version mismatch, dongle reports %d, " 1156 "expecting %d\n", 1157 bus->sdpcm_ver, SDPCM_PROT_VERSION); 1158 else 1159 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", 1160 bus->sdpcm_ver); 1161 1162 /* 1163 * Retrieve console state address now that firmware should have 1164 * updated it. 1165 */ 1166 brcmf_sdio_get_console_addr(bus); 1167 } 1168 1169 /* 1170 * Flow Control has been moved into the RX headers and this out of band 1171 * method isn't used any more. 1172 * remaining backward compatible with older dongles. 1173 */ 1174 if (hmb_data & HMB_DATA_FC) { 1175 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> 1176 HMB_DATA_FCDATA_SHIFT; 1177 1178 if (fcbits & ~bus->flowcontrol) 1179 bus->sdcnt.fc_xoff++; 1180 1181 if (bus->flowcontrol & ~fcbits) 1182 bus->sdcnt.fc_xon++; 1183 1184 bus->sdcnt.fc_rcvd++; 1185 bus->flowcontrol = fcbits; 1186 } 1187 1188 /* Shouldn't be any others */ 1189 if (hmb_data & ~(HMB_DATA_DEVREADY | 1190 HMB_DATA_NAKHANDLED | 1191 HMB_DATA_FC | 1192 HMB_DATA_FWREADY | 1193 HMB_DATA_FWHALT | 1194 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) 1195 brcmf_err("Unknown mailbox data content: 0x%02x\n", 1196 hmb_data); 1197 1198 return intstatus; 1199 } 1200 1201 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) 1202 { 1203 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1204 struct brcmf_core *core = bus->sdio_core; 1205 uint retries = 0; 1206 u16 lastrbc; 1207 u8 hi, lo; 1208 int err; 1209 1210 brcmf_err("%sterminate frame%s\n", 1211 abort ? "abort command, " : "", 1212 rtx ? ", send NAK" : ""); 1213 1214 if (abort) 1215 brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2); 1216 1217 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, 1218 &err); 1219 bus->sdcnt.f1regdata++; 1220 1221 /* Wait until the packet has been flushed (device/FIFO stable) */ 1222 for (lastrbc = retries = 0xffff; retries > 0; retries--) { 1223 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI, 1224 &err); 1225 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO, 1226 &err); 1227 bus->sdcnt.f1regdata += 2; 1228 1229 if ((hi == 0) && (lo == 0)) 1230 break; 1231 1232 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { 1233 brcmf_err("count growing: last 0x%04x now 0x%04x\n", 1234 lastrbc, (hi << 8) + lo); 1235 } 1236 lastrbc = (hi << 8) + lo; 1237 } 1238 1239 if (!retries) 1240 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); 1241 else 1242 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); 1243 1244 if (rtx) { 1245 bus->sdcnt.rxrtx++; 1246 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1247 SMB_NAK, &err); 1248 1249 bus->sdcnt.f1regdata++; 1250 if (err == 0) 1251 bus->rxskip = true; 1252 } 1253 1254 /* Clear partial in any case */ 1255 bus->cur_read.len = 0; 1256 } 1257 1258 static void brcmf_sdio_txfail(struct brcmf_sdio *bus) 1259 { 1260 struct brcmf_sdio_dev *sdiodev = bus->sdiodev; 1261 u8 i, hi, lo; 1262 1263 /* On failure, abort the command and terminate the frame */ 1264 brcmf_err("sdio error, abort command and terminate frame\n"); 1265 bus->sdcnt.tx_sderrs++; 1266 1267 brcmf_sdiod_abort(sdiodev, sdiodev->func2); 1268 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); 1269 bus->sdcnt.f1regdata++; 1270 1271 for (i = 0; i < 3; i++) { 1272 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); 1273 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); 1274 bus->sdcnt.f1regdata += 2; 1275 if ((hi == 0) && (lo == 0)) 1276 break; 1277 } 1278 } 1279 1280 /* return total length of buffer chain */ 1281 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) 1282 { 1283 struct sk_buff *p; 1284 uint total; 1285 1286 total = 0; 1287 skb_queue_walk(&bus->glom, p) 1288 total += p->len; 1289 return total; 1290 } 1291 1292 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) 1293 { 1294 struct sk_buff *cur, *next; 1295 1296 skb_queue_walk_safe(&bus->glom, cur, next) { 1297 skb_unlink(cur, &bus->glom); 1298 brcmu_pkt_buf_free_skb(cur); 1299 } 1300 } 1301 1302 /* 1303 * brcmfmac sdio bus specific header 1304 * This is the lowest layer header wrapped on the packets transmitted between 1305 * host and WiFi dongle which contains information needed for SDIO core and 1306 * firmware 1307 * 1308 * It consists of 3 parts: hardware header, hardware extension header and 1309 * software header 1310 * hardware header (frame tag) - 4 bytes 1311 * Byte 0~1: Frame length 1312 * Byte 2~3: Checksum, bit-wise inverse of frame length 1313 * hardware extension header - 8 bytes 1314 * Tx glom mode only, N/A for Rx or normal Tx 1315 * Byte 0~1: Packet length excluding hw frame tag 1316 * Byte 2: Reserved 1317 * Byte 3: Frame flags, bit 0: last frame indication 1318 * Byte 4~5: Reserved 1319 * Byte 6~7: Tail padding length 1320 * software header - 8 bytes 1321 * Byte 0: Rx/Tx sequence number 1322 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag 1323 * Byte 2: Length of next data frame, reserved for Tx 1324 * Byte 3: Data offset 1325 * Byte 4: Flow control bits, reserved for Tx 1326 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet 1327 * Byte 6~7: Reserved 1328 */ 1329 #define SDPCM_HWHDR_LEN 4 1330 #define SDPCM_HWEXT_LEN 8 1331 #define SDPCM_SWHDR_LEN 8 1332 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) 1333 /* software header */ 1334 #define SDPCM_SEQ_MASK 0x000000ff 1335 #define SDPCM_SEQ_WRAP 256 1336 #define SDPCM_CHANNEL_MASK 0x00000f00 1337 #define SDPCM_CHANNEL_SHIFT 8 1338 #define SDPCM_CONTROL_CHANNEL 0 /* Control */ 1339 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ 1340 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ 1341 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ 1342 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ 1343 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) 1344 #define SDPCM_NEXTLEN_MASK 0x00ff0000 1345 #define SDPCM_NEXTLEN_SHIFT 16 1346 #define SDPCM_DOFFSET_MASK 0xff000000 1347 #define SDPCM_DOFFSET_SHIFT 24 1348 #define SDPCM_FCMASK_MASK 0x000000ff 1349 #define SDPCM_WINDOW_MASK 0x0000ff00 1350 #define SDPCM_WINDOW_SHIFT 8 1351 1352 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) 1353 { 1354 u32 hdrvalue; 1355 hdrvalue = le32_to_cpu(*(__le32 *)swheader); 1356 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); 1357 } 1358 1359 static inline bool brcmf_sdio_fromevntchan(u8 *swheader) 1360 { 1361 u32 hdrvalue; 1362 u8 ret; 1363 1364 hdrvalue = le32_to_cpu(*(__le32 *)swheader); 1365 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT); 1366 1367 return (ret == SDPCM_EVENT_CHANNEL); 1368 } 1369 1370 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, 1371 struct brcmf_sdio_hdrinfo *rd, 1372 enum brcmf_sdio_frmtype type) 1373 { 1374 u16 len, checksum; 1375 u8 rx_seq, fc, tx_seq_max; 1376 u32 swheader; 1377 1378 trace_brcmf_sdpcm_hdr(SDPCM_RX, header); 1379 1380 /* hw header */ 1381 len = get_unaligned_le16(header); 1382 checksum = get_unaligned_le16(header + sizeof(u16)); 1383 /* All zero means no more to read */ 1384 if (!(len | checksum)) { 1385 bus->rxpending = false; 1386 return -ENODATA; 1387 } 1388 if ((u16)(~(len ^ checksum))) { 1389 brcmf_err("HW header checksum error\n"); 1390 bus->sdcnt.rx_badhdr++; 1391 brcmf_sdio_rxfail(bus, false, false); 1392 return -EIO; 1393 } 1394 if (len < SDPCM_HDRLEN) { 1395 brcmf_err("HW header length error\n"); 1396 return -EPROTO; 1397 } 1398 if (type == BRCMF_SDIO_FT_SUPER && 1399 (roundup(len, bus->blocksize) != rd->len)) { 1400 brcmf_err("HW superframe header length error\n"); 1401 return -EPROTO; 1402 } 1403 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { 1404 brcmf_err("HW subframe header length error\n"); 1405 return -EPROTO; 1406 } 1407 rd->len = len; 1408 1409 /* software header */ 1410 header += SDPCM_HWHDR_LEN; 1411 swheader = le32_to_cpu(*(__le32 *)header); 1412 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { 1413 brcmf_err("Glom descriptor found in superframe head\n"); 1414 rd->len = 0; 1415 return -EINVAL; 1416 } 1417 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); 1418 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; 1419 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && 1420 type != BRCMF_SDIO_FT_SUPER) { 1421 brcmf_err("HW header length too long\n"); 1422 bus->sdcnt.rx_toolong++; 1423 brcmf_sdio_rxfail(bus, false, false); 1424 rd->len = 0; 1425 return -EPROTO; 1426 } 1427 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { 1428 brcmf_err("Wrong channel for superframe\n"); 1429 rd->len = 0; 1430 return -EINVAL; 1431 } 1432 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && 1433 rd->channel != SDPCM_EVENT_CHANNEL) { 1434 brcmf_err("Wrong channel for subframe\n"); 1435 rd->len = 0; 1436 return -EINVAL; 1437 } 1438 rd->dat_offset = brcmf_sdio_getdatoffset(header); 1439 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { 1440 brcmf_err("seq %d: bad data offset\n", rx_seq); 1441 bus->sdcnt.rx_badhdr++; 1442 brcmf_sdio_rxfail(bus, false, false); 1443 rd->len = 0; 1444 return -ENXIO; 1445 } 1446 if (rd->seq_num != rx_seq) { 1447 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num); 1448 bus->sdcnt.rx_badseq++; 1449 rd->seq_num = rx_seq; 1450 } 1451 /* no need to check the reset for subframe */ 1452 if (type == BRCMF_SDIO_FT_SUB) 1453 return 0; 1454 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; 1455 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { 1456 /* only warm for NON glom packet */ 1457 if (rd->channel != SDPCM_GLOM_CHANNEL) 1458 brcmf_err("seq %d: next length error\n", rx_seq); 1459 rd->len_nxtfrm = 0; 1460 } 1461 swheader = le32_to_cpu(*(__le32 *)(header + 4)); 1462 fc = swheader & SDPCM_FCMASK_MASK; 1463 if (bus->flowcontrol != fc) { 1464 if (~bus->flowcontrol & fc) 1465 bus->sdcnt.fc_xoff++; 1466 if (bus->flowcontrol & ~fc) 1467 bus->sdcnt.fc_xon++; 1468 bus->sdcnt.fc_rcvd++; 1469 bus->flowcontrol = fc; 1470 } 1471 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; 1472 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { 1473 brcmf_err("seq %d: max tx seq number error\n", rx_seq); 1474 tx_seq_max = bus->tx_seq + 2; 1475 } 1476 bus->tx_max = tx_seq_max; 1477 1478 return 0; 1479 } 1480 1481 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) 1482 { 1483 *(__le16 *)header = cpu_to_le16(frm_length); 1484 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); 1485 } 1486 1487 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, 1488 struct brcmf_sdio_hdrinfo *hd_info) 1489 { 1490 u32 hdrval; 1491 u8 hdr_offset; 1492 1493 brcmf_sdio_update_hwhdr(header, hd_info->len); 1494 hdr_offset = SDPCM_HWHDR_LEN; 1495 1496 if (bus->txglom) { 1497 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); 1498 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1499 hdrval = (u16)hd_info->tail_pad << 16; 1500 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); 1501 hdr_offset += SDPCM_HWEXT_LEN; 1502 } 1503 1504 hdrval = hd_info->seq_num; 1505 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & 1506 SDPCM_CHANNEL_MASK; 1507 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & 1508 SDPCM_DOFFSET_MASK; 1509 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1510 *(((__le32 *)(header + hdr_offset)) + 1) = 0; 1511 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); 1512 } 1513 1514 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) 1515 { 1516 u16 dlen, totlen; 1517 u8 *dptr, num = 0; 1518 u16 sublen; 1519 struct sk_buff *pfirst, *pnext; 1520 1521 int errcode; 1522 u8 doff; 1523 1524 struct brcmf_sdio_hdrinfo rd_new; 1525 1526 /* If packets, issue read(s) and send up packet chain */ 1527 /* Return sequence numbers consumed? */ 1528 1529 brcmf_dbg(SDIO, "start: glomd %p glom %p\n", 1530 bus->glomd, skb_peek(&bus->glom)); 1531 1532 /* If there's a descriptor, generate the packet chain */ 1533 if (bus->glomd) { 1534 pfirst = pnext = NULL; 1535 dlen = (u16) (bus->glomd->len); 1536 dptr = bus->glomd->data; 1537 if (!dlen || (dlen & 1)) { 1538 brcmf_err("bad glomd len(%d), ignore descriptor\n", 1539 dlen); 1540 dlen = 0; 1541 } 1542 1543 for (totlen = num = 0; dlen; num++) { 1544 /* Get (and move past) next length */ 1545 sublen = get_unaligned_le16(dptr); 1546 dlen -= sizeof(u16); 1547 dptr += sizeof(u16); 1548 if ((sublen < SDPCM_HDRLEN) || 1549 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { 1550 brcmf_err("descriptor len %d bad: %d\n", 1551 num, sublen); 1552 pnext = NULL; 1553 break; 1554 } 1555 if (sublen % bus->sgentry_align) { 1556 brcmf_err("sublen %d not multiple of %d\n", 1557 sublen, bus->sgentry_align); 1558 } 1559 totlen += sublen; 1560 1561 /* For last frame, adjust read len so total 1562 is a block multiple */ 1563 if (!dlen) { 1564 sublen += 1565 (roundup(totlen, bus->blocksize) - totlen); 1566 totlen = roundup(totlen, bus->blocksize); 1567 } 1568 1569 /* Allocate/chain packet for next subframe */ 1570 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); 1571 if (pnext == NULL) { 1572 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", 1573 num, sublen); 1574 break; 1575 } 1576 skb_queue_tail(&bus->glom, pnext); 1577 1578 /* Adhere to start alignment requirements */ 1579 pkt_align(pnext, sublen, bus->sgentry_align); 1580 } 1581 1582 /* If all allocations succeeded, save packet chain 1583 in bus structure */ 1584 if (pnext) { 1585 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", 1586 totlen, num); 1587 if (BRCMF_GLOM_ON() && bus->cur_read.len && 1588 totlen != bus->cur_read.len) { 1589 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", 1590 bus->cur_read.len, totlen, rxseq); 1591 } 1592 pfirst = pnext = NULL; 1593 } else { 1594 brcmf_sdio_free_glom(bus); 1595 num = 0; 1596 } 1597 1598 /* Done with descriptor packet */ 1599 brcmu_pkt_buf_free_skb(bus->glomd); 1600 bus->glomd = NULL; 1601 bus->cur_read.len = 0; 1602 } 1603 1604 /* Ok -- either we just generated a packet chain, 1605 or had one from before */ 1606 if (!skb_queue_empty(&bus->glom)) { 1607 if (BRCMF_GLOM_ON()) { 1608 brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); 1609 skb_queue_walk(&bus->glom, pnext) { 1610 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", 1611 pnext, (u8 *) (pnext->data), 1612 pnext->len, pnext->len); 1613 } 1614 } 1615 1616 pfirst = skb_peek(&bus->glom); 1617 dlen = (u16) brcmf_sdio_glom_len(bus); 1618 1619 /* Do an SDIO read for the superframe. Configurable iovar to 1620 * read directly into the chained packet, or allocate a large 1621 * packet and copy into the chain. 1622 */ 1623 sdio_claim_host(bus->sdiodev->func1); 1624 errcode = brcmf_sdiod_recv_chain(bus->sdiodev, 1625 &bus->glom, dlen); 1626 sdio_release_host(bus->sdiodev->func1); 1627 bus->sdcnt.f2rxdata++; 1628 1629 /* On failure, kill the superframe */ 1630 if (errcode < 0) { 1631 brcmf_err("glom read of %d bytes failed: %d\n", 1632 dlen, errcode); 1633 1634 sdio_claim_host(bus->sdiodev->func1); 1635 brcmf_sdio_rxfail(bus, true, false); 1636 bus->sdcnt.rxglomfail++; 1637 brcmf_sdio_free_glom(bus); 1638 sdio_release_host(bus->sdiodev->func1); 1639 return 0; 1640 } 1641 1642 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1643 pfirst->data, min_t(int, pfirst->len, 48), 1644 "SUPERFRAME:\n"); 1645 1646 rd_new.seq_num = rxseq; 1647 rd_new.len = dlen; 1648 sdio_claim_host(bus->sdiodev->func1); 1649 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, 1650 BRCMF_SDIO_FT_SUPER); 1651 sdio_release_host(bus->sdiodev->func1); 1652 bus->cur_read.len = rd_new.len_nxtfrm << 4; 1653 1654 /* Remove superframe header, remember offset */ 1655 skb_pull(pfirst, rd_new.dat_offset); 1656 num = 0; 1657 1658 /* Validate all the subframe headers */ 1659 skb_queue_walk(&bus->glom, pnext) { 1660 /* leave when invalid subframe is found */ 1661 if (errcode) 1662 break; 1663 1664 rd_new.len = pnext->len; 1665 rd_new.seq_num = rxseq++; 1666 sdio_claim_host(bus->sdiodev->func1); 1667 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, 1668 BRCMF_SDIO_FT_SUB); 1669 sdio_release_host(bus->sdiodev->func1); 1670 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1671 pnext->data, 32, "subframe:\n"); 1672 1673 num++; 1674 } 1675 1676 if (errcode) { 1677 /* Terminate frame on error */ 1678 sdio_claim_host(bus->sdiodev->func1); 1679 brcmf_sdio_rxfail(bus, true, false); 1680 bus->sdcnt.rxglomfail++; 1681 brcmf_sdio_free_glom(bus); 1682 sdio_release_host(bus->sdiodev->func1); 1683 bus->cur_read.len = 0; 1684 return 0; 1685 } 1686 1687 /* Basic SD framing looks ok - process each packet (header) */ 1688 1689 skb_queue_walk_safe(&bus->glom, pfirst, pnext) { 1690 dptr = (u8 *) (pfirst->data); 1691 sublen = get_unaligned_le16(dptr); 1692 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); 1693 1694 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1695 dptr, pfirst->len, 1696 "Rx Subframe Data:\n"); 1697 1698 __skb_trim(pfirst, sublen); 1699 skb_pull(pfirst, doff); 1700 1701 if (pfirst->len == 0) { 1702 skb_unlink(pfirst, &bus->glom); 1703 brcmu_pkt_buf_free_skb(pfirst); 1704 continue; 1705 } 1706 1707 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1708 pfirst->data, 1709 min_t(int, pfirst->len, 32), 1710 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", 1711 bus->glom.qlen, pfirst, pfirst->data, 1712 pfirst->len, pfirst->next, 1713 pfirst->prev); 1714 skb_unlink(pfirst, &bus->glom); 1715 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN])) 1716 brcmf_rx_event(bus->sdiodev->dev, pfirst); 1717 else 1718 brcmf_rx_frame(bus->sdiodev->dev, pfirst, 1719 false, false); 1720 bus->sdcnt.rxglompkts++; 1721 } 1722 1723 bus->sdcnt.rxglomframes++; 1724 } 1725 return num; 1726 } 1727 1728 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, 1729 bool *pending) 1730 { 1731 DECLARE_WAITQUEUE(wait, current); 1732 int timeout = DCMD_RESP_TIMEOUT; 1733 1734 /* Wait until control frame is available */ 1735 add_wait_queue(&bus->dcmd_resp_wait, &wait); 1736 set_current_state(TASK_INTERRUPTIBLE); 1737 1738 while (!(*condition) && (!signal_pending(current) && timeout)) 1739 timeout = schedule_timeout(timeout); 1740 1741 if (signal_pending(current)) 1742 *pending = true; 1743 1744 set_current_state(TASK_RUNNING); 1745 remove_wait_queue(&bus->dcmd_resp_wait, &wait); 1746 1747 return timeout; 1748 } 1749 1750 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) 1751 { 1752 wake_up_interruptible(&bus->dcmd_resp_wait); 1753 1754 return 0; 1755 } 1756 static void 1757 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) 1758 { 1759 uint rdlen, pad; 1760 u8 *buf = NULL, *rbuf; 1761 int sdret; 1762 1763 brcmf_dbg(SDIO, "Enter\n"); 1764 if (bus->rxblen) 1765 buf = vzalloc(bus->rxblen); 1766 if (!buf) 1767 goto done; 1768 1769 rbuf = bus->rxbuf; 1770 pad = ((unsigned long)rbuf % bus->head_align); 1771 if (pad) 1772 rbuf += (bus->head_align - pad); 1773 1774 /* Copy the already-read portion over */ 1775 memcpy(buf, hdr, BRCMF_FIRSTREAD); 1776 if (len <= BRCMF_FIRSTREAD) 1777 goto gotpkt; 1778 1779 /* Raise rdlen to next SDIO block to avoid tail command */ 1780 rdlen = len - BRCMF_FIRSTREAD; 1781 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { 1782 pad = bus->blocksize - (rdlen % bus->blocksize); 1783 if ((pad <= bus->roundup) && (pad < bus->blocksize) && 1784 ((len + pad) < bus->sdiodev->bus_if->maxctl)) 1785 rdlen += pad; 1786 } else if (rdlen % bus->head_align) { 1787 rdlen += bus->head_align - (rdlen % bus->head_align); 1788 } 1789 1790 /* Drop if the read is too big or it exceeds our maximum */ 1791 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { 1792 brcmf_err("%d-byte control read exceeds %d-byte buffer\n", 1793 rdlen, bus->sdiodev->bus_if->maxctl); 1794 brcmf_sdio_rxfail(bus, false, false); 1795 goto done; 1796 } 1797 1798 if ((len - doff) > bus->sdiodev->bus_if->maxctl) { 1799 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", 1800 len, len - doff, bus->sdiodev->bus_if->maxctl); 1801 bus->sdcnt.rx_toolong++; 1802 brcmf_sdio_rxfail(bus, false, false); 1803 goto done; 1804 } 1805 1806 /* Read remain of frame body */ 1807 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); 1808 bus->sdcnt.f2rxdata++; 1809 1810 /* Control frame failures need retransmission */ 1811 if (sdret < 0) { 1812 brcmf_err("read %d control bytes failed: %d\n", 1813 rdlen, sdret); 1814 bus->sdcnt.rxc_errors++; 1815 brcmf_sdio_rxfail(bus, true, true); 1816 goto done; 1817 } else 1818 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); 1819 1820 gotpkt: 1821 1822 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 1823 buf, len, "RxCtrl:\n"); 1824 1825 /* Point to valid data and indicate its length */ 1826 spin_lock_bh(&bus->rxctl_lock); 1827 if (bus->rxctl) { 1828 brcmf_err("last control frame is being processed.\n"); 1829 spin_unlock_bh(&bus->rxctl_lock); 1830 goto done; 1831 } 1832 bus->rxctl = buf + doff; 1833 bus->rxctl_orig = buf; 1834 bus->rxlen = len - doff; 1835 spin_unlock_bh(&bus->rxctl_lock); 1836 buf = NULL; 1837 1838 done: 1839 /* Awake any waiters */ 1840 brcmf_sdio_dcmd_resp_wake(bus); 1841 vfree(buf); 1842 } 1843 1844 /* Pad read to blocksize for efficiency */ 1845 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) 1846 { 1847 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { 1848 *pad = bus->blocksize - (*rdlen % bus->blocksize); 1849 if (*pad <= bus->roundup && *pad < bus->blocksize && 1850 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) 1851 *rdlen += *pad; 1852 } else if (*rdlen % bus->head_align) { 1853 *rdlen += bus->head_align - (*rdlen % bus->head_align); 1854 } 1855 } 1856 1857 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) 1858 { 1859 struct sk_buff *pkt; /* Packet for event or data frames */ 1860 u16 pad; /* Number of pad bytes to read */ 1861 uint rxleft = 0; /* Remaining number of frames allowed */ 1862 int ret; /* Return code from calls */ 1863 uint rxcount = 0; /* Total frames read */ 1864 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; 1865 u8 head_read = 0; 1866 1867 brcmf_dbg(SDIO, "Enter\n"); 1868 1869 /* Not finished unless we encounter no more frames indication */ 1870 bus->rxpending = true; 1871 1872 for (rd->seq_num = bus->rx_seq, rxleft = maxframes; 1873 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; 1874 rd->seq_num++, rxleft--) { 1875 1876 /* Handle glomming separately */ 1877 if (bus->glomd || !skb_queue_empty(&bus->glom)) { 1878 u8 cnt; 1879 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", 1880 bus->glomd, skb_peek(&bus->glom)); 1881 cnt = brcmf_sdio_rxglom(bus, rd->seq_num); 1882 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); 1883 rd->seq_num += cnt - 1; 1884 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; 1885 continue; 1886 } 1887 1888 rd->len_left = rd->len; 1889 /* read header first for unknown frame length */ 1890 sdio_claim_host(bus->sdiodev->func1); 1891 if (!rd->len) { 1892 ret = brcmf_sdiod_recv_buf(bus->sdiodev, 1893 bus->rxhdr, BRCMF_FIRSTREAD); 1894 bus->sdcnt.f2rxhdrs++; 1895 if (ret < 0) { 1896 brcmf_err("RXHEADER FAILED: %d\n", 1897 ret); 1898 bus->sdcnt.rx_hdrfail++; 1899 brcmf_sdio_rxfail(bus, true, true); 1900 sdio_release_host(bus->sdiodev->func1); 1901 continue; 1902 } 1903 1904 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), 1905 bus->rxhdr, SDPCM_HDRLEN, 1906 "RxHdr:\n"); 1907 1908 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, 1909 BRCMF_SDIO_FT_NORMAL)) { 1910 sdio_release_host(bus->sdiodev->func1); 1911 if (!bus->rxpending) 1912 break; 1913 else 1914 continue; 1915 } 1916 1917 if (rd->channel == SDPCM_CONTROL_CHANNEL) { 1918 brcmf_sdio_read_control(bus, bus->rxhdr, 1919 rd->len, 1920 rd->dat_offset); 1921 /* prepare the descriptor for the next read */ 1922 rd->len = rd->len_nxtfrm << 4; 1923 rd->len_nxtfrm = 0; 1924 /* treat all packet as event if we don't know */ 1925 rd->channel = SDPCM_EVENT_CHANNEL; 1926 sdio_release_host(bus->sdiodev->func1); 1927 continue; 1928 } 1929 rd->len_left = rd->len > BRCMF_FIRSTREAD ? 1930 rd->len - BRCMF_FIRSTREAD : 0; 1931 head_read = BRCMF_FIRSTREAD; 1932 } 1933 1934 brcmf_sdio_pad(bus, &pad, &rd->len_left); 1935 1936 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + 1937 bus->head_align); 1938 if (!pkt) { 1939 /* Give up on data, request rtx of events */ 1940 brcmf_err("brcmu_pkt_buf_get_skb failed\n"); 1941 brcmf_sdio_rxfail(bus, false, 1942 RETRYCHAN(rd->channel)); 1943 sdio_release_host(bus->sdiodev->func1); 1944 continue; 1945 } 1946 skb_pull(pkt, head_read); 1947 pkt_align(pkt, rd->len_left, bus->head_align); 1948 1949 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); 1950 bus->sdcnt.f2rxdata++; 1951 sdio_release_host(bus->sdiodev->func1); 1952 1953 if (ret < 0) { 1954 brcmf_err("read %d bytes from channel %d failed: %d\n", 1955 rd->len, rd->channel, ret); 1956 brcmu_pkt_buf_free_skb(pkt); 1957 sdio_claim_host(bus->sdiodev->func1); 1958 brcmf_sdio_rxfail(bus, true, 1959 RETRYCHAN(rd->channel)); 1960 sdio_release_host(bus->sdiodev->func1); 1961 continue; 1962 } 1963 1964 if (head_read) { 1965 skb_push(pkt, head_read); 1966 memcpy(pkt->data, bus->rxhdr, head_read); 1967 head_read = 0; 1968 } else { 1969 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); 1970 rd_new.seq_num = rd->seq_num; 1971 sdio_claim_host(bus->sdiodev->func1); 1972 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, 1973 BRCMF_SDIO_FT_NORMAL)) { 1974 rd->len = 0; 1975 brcmf_sdio_rxfail(bus, true, true); 1976 sdio_release_host(bus->sdiodev->func1); 1977 brcmu_pkt_buf_free_skb(pkt); 1978 continue; 1979 } 1980 bus->sdcnt.rx_readahead_cnt++; 1981 if (rd->len != roundup(rd_new.len, 16)) { 1982 brcmf_err("frame length mismatch:read %d, should be %d\n", 1983 rd->len, 1984 roundup(rd_new.len, 16) >> 4); 1985 rd->len = 0; 1986 brcmf_sdio_rxfail(bus, true, true); 1987 sdio_release_host(bus->sdiodev->func1); 1988 brcmu_pkt_buf_free_skb(pkt); 1989 continue; 1990 } 1991 sdio_release_host(bus->sdiodev->func1); 1992 rd->len_nxtfrm = rd_new.len_nxtfrm; 1993 rd->channel = rd_new.channel; 1994 rd->dat_offset = rd_new.dat_offset; 1995 1996 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && 1997 BRCMF_DATA_ON()) && 1998 BRCMF_HDRS_ON(), 1999 bus->rxhdr, SDPCM_HDRLEN, 2000 "RxHdr:\n"); 2001 2002 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { 2003 brcmf_err("readahead on control packet %d?\n", 2004 rd_new.seq_num); 2005 /* Force retry w/normal header read */ 2006 rd->len = 0; 2007 sdio_claim_host(bus->sdiodev->func1); 2008 brcmf_sdio_rxfail(bus, false, true); 2009 sdio_release_host(bus->sdiodev->func1); 2010 brcmu_pkt_buf_free_skb(pkt); 2011 continue; 2012 } 2013 } 2014 2015 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 2016 pkt->data, rd->len, "Rx Data:\n"); 2017 2018 /* Save superframe descriptor and allocate packet frame */ 2019 if (rd->channel == SDPCM_GLOM_CHANNEL) { 2020 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { 2021 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", 2022 rd->len); 2023 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 2024 pkt->data, rd->len, 2025 "Glom Data:\n"); 2026 __skb_trim(pkt, rd->len); 2027 skb_pull(pkt, SDPCM_HDRLEN); 2028 bus->glomd = pkt; 2029 } else { 2030 brcmf_err("%s: glom superframe w/o " 2031 "descriptor!\n", __func__); 2032 sdio_claim_host(bus->sdiodev->func1); 2033 brcmf_sdio_rxfail(bus, false, false); 2034 sdio_release_host(bus->sdiodev->func1); 2035 } 2036 /* prepare the descriptor for the next read */ 2037 rd->len = rd->len_nxtfrm << 4; 2038 rd->len_nxtfrm = 0; 2039 /* treat all packet as event if we don't know */ 2040 rd->channel = SDPCM_EVENT_CHANNEL; 2041 continue; 2042 } 2043 2044 /* Fill in packet len and prio, deliver upward */ 2045 __skb_trim(pkt, rd->len); 2046 skb_pull(pkt, rd->dat_offset); 2047 2048 if (pkt->len == 0) 2049 brcmu_pkt_buf_free_skb(pkt); 2050 else if (rd->channel == SDPCM_EVENT_CHANNEL) 2051 brcmf_rx_event(bus->sdiodev->dev, pkt); 2052 else 2053 brcmf_rx_frame(bus->sdiodev->dev, pkt, 2054 false, false); 2055 2056 /* prepare the descriptor for the next read */ 2057 rd->len = rd->len_nxtfrm << 4; 2058 rd->len_nxtfrm = 0; 2059 /* treat all packet as event if we don't know */ 2060 rd->channel = SDPCM_EVENT_CHANNEL; 2061 } 2062 2063 rxcount = maxframes - rxleft; 2064 /* Message if we hit the limit */ 2065 if (!rxleft) 2066 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); 2067 else 2068 brcmf_dbg(DATA, "processed %d frames\n", rxcount); 2069 /* Back off rxseq if awaiting rtx, update rx_seq */ 2070 if (bus->rxskip) 2071 rd->seq_num--; 2072 bus->rx_seq = rd->seq_num; 2073 2074 return rxcount; 2075 } 2076 2077 static void 2078 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) 2079 { 2080 wake_up_interruptible(&bus->ctrl_wait); 2081 return; 2082 } 2083 2084 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) 2085 { 2086 struct brcmf_bus_stats *stats; 2087 u16 head_pad; 2088 u8 *dat_buf; 2089 2090 dat_buf = (u8 *)(pkt->data); 2091 2092 /* Check head padding */ 2093 head_pad = ((unsigned long)dat_buf % bus->head_align); 2094 if (head_pad) { 2095 if (skb_headroom(pkt) < head_pad) { 2096 stats = &bus->sdiodev->bus_if->stats; 2097 atomic_inc(&stats->pktcowed); 2098 if (skb_cow_head(pkt, head_pad)) { 2099 atomic_inc(&stats->pktcow_failed); 2100 return -ENOMEM; 2101 } 2102 head_pad = 0; 2103 } 2104 skb_push(pkt, head_pad); 2105 dat_buf = (u8 *)(pkt->data); 2106 } 2107 memset(dat_buf, 0, head_pad + bus->tx_hdrlen); 2108 return head_pad; 2109 } 2110 2111 /* 2112 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for 2113 * bus layer usage. 2114 */ 2115 /* flag marking a dummy skb added for DMA alignment requirement */ 2116 #define ALIGN_SKB_FLAG 0x8000 2117 /* bit mask of data length chopped from the previous packet */ 2118 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff 2119 2120 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, 2121 struct sk_buff_head *pktq, 2122 struct sk_buff *pkt, u16 total_len) 2123 { 2124 struct brcmf_sdio_dev *sdiodev; 2125 struct sk_buff *pkt_pad; 2126 u16 tail_pad, tail_chop, chain_pad; 2127 unsigned int blksize; 2128 bool lastfrm; 2129 int ntail, ret; 2130 2131 sdiodev = bus->sdiodev; 2132 blksize = sdiodev->func2->cur_blksize; 2133 /* sg entry alignment should be a divisor of block size */ 2134 WARN_ON(blksize % bus->sgentry_align); 2135 2136 /* Check tail padding */ 2137 lastfrm = skb_queue_is_last(pktq, pkt); 2138 tail_pad = 0; 2139 tail_chop = pkt->len % bus->sgentry_align; 2140 if (tail_chop) 2141 tail_pad = bus->sgentry_align - tail_chop; 2142 chain_pad = (total_len + tail_pad) % blksize; 2143 if (lastfrm && chain_pad) 2144 tail_pad += blksize - chain_pad; 2145 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { 2146 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + 2147 bus->head_align); 2148 if (pkt_pad == NULL) 2149 return -ENOMEM; 2150 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); 2151 if (unlikely(ret < 0)) { 2152 kfree_skb(pkt_pad); 2153 return ret; 2154 } 2155 memcpy(pkt_pad->data, 2156 pkt->data + pkt->len - tail_chop, 2157 tail_chop); 2158 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; 2159 skb_trim(pkt, pkt->len - tail_chop); 2160 skb_trim(pkt_pad, tail_pad + tail_chop); 2161 __skb_queue_after(pktq, pkt, pkt_pad); 2162 } else { 2163 ntail = pkt->data_len + tail_pad - 2164 (pkt->end - pkt->tail); 2165 if (skb_cloned(pkt) || ntail > 0) 2166 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) 2167 return -ENOMEM; 2168 if (skb_linearize(pkt)) 2169 return -ENOMEM; 2170 __skb_put(pkt, tail_pad); 2171 } 2172 2173 return tail_pad; 2174 } 2175 2176 /** 2177 * brcmf_sdio_txpkt_prep - packet preparation for transmit 2178 * @bus: brcmf_sdio structure pointer 2179 * @pktq: packet list pointer 2180 * @chan: virtual channel to transmit the packet 2181 * 2182 * Processes to be applied to the packet 2183 * - Align data buffer pointer 2184 * - Align data buffer length 2185 * - Prepare header 2186 * Return: negative value if there is error 2187 */ 2188 static int 2189 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2190 uint chan) 2191 { 2192 u16 head_pad, total_len; 2193 struct sk_buff *pkt_next; 2194 u8 txseq; 2195 int ret; 2196 struct brcmf_sdio_hdrinfo hd_info = {0}; 2197 2198 txseq = bus->tx_seq; 2199 total_len = 0; 2200 skb_queue_walk(pktq, pkt_next) { 2201 /* alignment packet inserted in previous 2202 * loop cycle can be skipped as it is 2203 * already properly aligned and does not 2204 * need an sdpcm header. 2205 */ 2206 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) 2207 continue; 2208 2209 /* align packet data pointer */ 2210 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); 2211 if (ret < 0) 2212 return ret; 2213 head_pad = (u16)ret; 2214 if (head_pad) 2215 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); 2216 2217 total_len += pkt_next->len; 2218 2219 hd_info.len = pkt_next->len; 2220 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); 2221 if (bus->txglom && pktq->qlen > 1) { 2222 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, 2223 pkt_next, total_len); 2224 if (ret < 0) 2225 return ret; 2226 hd_info.tail_pad = (u16)ret; 2227 total_len += (u16)ret; 2228 } 2229 2230 hd_info.channel = chan; 2231 hd_info.dat_offset = head_pad + bus->tx_hdrlen; 2232 hd_info.seq_num = txseq++; 2233 2234 /* Now fill the header */ 2235 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); 2236 2237 if (BRCMF_BYTES_ON() && 2238 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || 2239 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) 2240 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, 2241 "Tx Frame:\n"); 2242 else if (BRCMF_HDRS_ON()) 2243 brcmf_dbg_hex_dump(true, pkt_next->data, 2244 head_pad + bus->tx_hdrlen, 2245 "Tx Header:\n"); 2246 } 2247 /* Hardware length tag of the first packet should be total 2248 * length of the chain (including padding) 2249 */ 2250 if (bus->txglom) 2251 brcmf_sdio_update_hwhdr(__skb_peek(pktq)->data, total_len); 2252 return 0; 2253 } 2254 2255 /** 2256 * brcmf_sdio_txpkt_postp - packet post processing for transmit 2257 * @bus: brcmf_sdio structure pointer 2258 * @pktq: packet list pointer 2259 * 2260 * Processes to be applied to the packet 2261 * - Remove head padding 2262 * - Remove tail padding 2263 */ 2264 static void 2265 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) 2266 { 2267 u8 *hdr; 2268 u32 dat_offset; 2269 u16 tail_pad; 2270 u16 dummy_flags, chop_len; 2271 struct sk_buff *pkt_next, *tmp, *pkt_prev; 2272 2273 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2274 dummy_flags = *(u16 *)(pkt_next->cb); 2275 if (dummy_flags & ALIGN_SKB_FLAG) { 2276 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; 2277 if (chop_len) { 2278 pkt_prev = pkt_next->prev; 2279 skb_put(pkt_prev, chop_len); 2280 } 2281 __skb_unlink(pkt_next, pktq); 2282 brcmu_pkt_buf_free_skb(pkt_next); 2283 } else { 2284 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; 2285 dat_offset = le32_to_cpu(*(__le32 *)hdr); 2286 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> 2287 SDPCM_DOFFSET_SHIFT; 2288 skb_pull(pkt_next, dat_offset); 2289 if (bus->txglom) { 2290 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); 2291 skb_trim(pkt_next, pkt_next->len - tail_pad); 2292 } 2293 } 2294 } 2295 } 2296 2297 /* Writes a HW/SW header into the packet and sends it. */ 2298 /* Assumes: (a) header space already there, (b) caller holds lock */ 2299 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2300 uint chan) 2301 { 2302 int ret; 2303 struct sk_buff *pkt_next, *tmp; 2304 2305 brcmf_dbg(TRACE, "Enter\n"); 2306 2307 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); 2308 if (ret) 2309 goto done; 2310 2311 sdio_claim_host(bus->sdiodev->func1); 2312 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); 2313 bus->sdcnt.f2txdata++; 2314 2315 if (ret < 0) 2316 brcmf_sdio_txfail(bus); 2317 2318 sdio_release_host(bus->sdiodev->func1); 2319 2320 done: 2321 brcmf_sdio_txpkt_postp(bus, pktq); 2322 if (ret == 0) 2323 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; 2324 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2325 __skb_unlink(pkt_next, pktq); 2326 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next, 2327 ret == 0); 2328 } 2329 return ret; 2330 } 2331 2332 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) 2333 { 2334 struct sk_buff *pkt; 2335 struct sk_buff_head pktq; 2336 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2337 u32 intstatus = 0; 2338 int ret = 0, prec_out, i; 2339 uint cnt = 0; 2340 u8 tx_prec_map, pkt_num; 2341 2342 brcmf_dbg(TRACE, "Enter\n"); 2343 2344 tx_prec_map = ~bus->flowcontrol; 2345 2346 /* Send frames until the limit or some other event */ 2347 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { 2348 pkt_num = 1; 2349 if (bus->txglom) 2350 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, 2351 bus->sdiodev->txglomsz); 2352 pkt_num = min_t(u32, pkt_num, 2353 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); 2354 __skb_queue_head_init(&pktq); 2355 spin_lock_bh(&bus->txq_lock); 2356 for (i = 0; i < pkt_num; i++) { 2357 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, 2358 &prec_out); 2359 if (pkt == NULL) 2360 break; 2361 __skb_queue_tail(&pktq, pkt); 2362 } 2363 spin_unlock_bh(&bus->txq_lock); 2364 if (i == 0) 2365 break; 2366 2367 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); 2368 2369 cnt += i; 2370 2371 /* In poll mode, need to check for other events */ 2372 if (!bus->intr) { 2373 /* Check device status, signal pending interrupt */ 2374 sdio_claim_host(bus->sdiodev->func1); 2375 intstatus = brcmf_sdiod_readl(bus->sdiodev, 2376 intstat_addr, &ret); 2377 sdio_release_host(bus->sdiodev->func1); 2378 2379 bus->sdcnt.f2txdata++; 2380 if (ret != 0) 2381 break; 2382 if (intstatus & bus->hostintmask) 2383 atomic_set(&bus->ipend, 1); 2384 } 2385 } 2386 2387 /* Deflow-control stack if needed */ 2388 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && 2389 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { 2390 bus->txoff = false; 2391 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false); 2392 } 2393 2394 return cnt; 2395 } 2396 2397 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) 2398 { 2399 u8 doff; 2400 u16 pad; 2401 uint retries = 0; 2402 struct brcmf_sdio_hdrinfo hd_info = {0}; 2403 int ret; 2404 2405 brcmf_dbg(SDIO, "Enter\n"); 2406 2407 /* Back the pointer to make room for bus header */ 2408 frame -= bus->tx_hdrlen; 2409 len += bus->tx_hdrlen; 2410 2411 /* Add alignment padding (optional for ctl frames) */ 2412 doff = ((unsigned long)frame % bus->head_align); 2413 if (doff) { 2414 frame -= doff; 2415 len += doff; 2416 memset(frame + bus->tx_hdrlen, 0, doff); 2417 } 2418 2419 /* Round send length to next SDIO block */ 2420 pad = 0; 2421 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { 2422 pad = bus->blocksize - (len % bus->blocksize); 2423 if ((pad > bus->roundup) || (pad >= bus->blocksize)) 2424 pad = 0; 2425 } else if (len % bus->head_align) { 2426 pad = bus->head_align - (len % bus->head_align); 2427 } 2428 len += pad; 2429 2430 hd_info.len = len - pad; 2431 hd_info.channel = SDPCM_CONTROL_CHANNEL; 2432 hd_info.dat_offset = doff + bus->tx_hdrlen; 2433 hd_info.seq_num = bus->tx_seq; 2434 hd_info.lastfrm = true; 2435 hd_info.tail_pad = pad; 2436 brcmf_sdio_hdpack(bus, frame, &hd_info); 2437 2438 if (bus->txglom) 2439 brcmf_sdio_update_hwhdr(frame, len); 2440 2441 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 2442 frame, len, "Tx Frame:\n"); 2443 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && 2444 BRCMF_HDRS_ON(), 2445 frame, min_t(u16, len, 16), "TxHdr:\n"); 2446 2447 do { 2448 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); 2449 2450 if (ret < 0) 2451 brcmf_sdio_txfail(bus); 2452 else 2453 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; 2454 } while (ret < 0 && retries++ < TXRETRIES); 2455 2456 return ret; 2457 } 2458 2459 static bool brcmf_chip_is_ulp(struct brcmf_chip *ci) 2460 { 2461 if (ci->chip == CY_CC_43012_CHIP_ID) 2462 return true; 2463 else 2464 return false; 2465 } 2466 2467 static void brcmf_sdio_bus_stop(struct device *dev) 2468 { 2469 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2470 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2471 struct brcmf_sdio *bus = sdiodev->bus; 2472 struct brcmf_core *core = bus->sdio_core; 2473 u32 local_hostintmask; 2474 u8 saveclk, bpreq; 2475 int err; 2476 2477 brcmf_dbg(TRACE, "Enter\n"); 2478 2479 if (bus->watchdog_tsk) { 2480 get_task_struct(bus->watchdog_tsk); 2481 send_sig(SIGTERM, bus->watchdog_tsk, 1); 2482 kthread_stop_put(bus->watchdog_tsk); 2483 bus->watchdog_tsk = NULL; 2484 } 2485 2486 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 2487 sdio_claim_host(sdiodev->func1); 2488 2489 /* Enable clock for device interrupts */ 2490 brcmf_sdio_bus_sleep(bus, false, false); 2491 2492 /* Disable and clear interrupts at the chip level also */ 2493 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask), 2494 0, NULL); 2495 2496 local_hostintmask = bus->hostintmask; 2497 bus->hostintmask = 0; 2498 2499 /* Force backplane clocks to assure F2 interrupt propagates */ 2500 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2501 &err); 2502 if (!err) { 2503 bpreq = saveclk; 2504 bpreq |= brcmf_chip_is_ulp(bus->ci) ? 2505 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT; 2506 brcmf_sdiod_writeb(sdiodev, 2507 SBSDIO_FUNC1_CHIPCLKCSR, 2508 bpreq, &err); 2509 } 2510 if (err) 2511 brcmf_err("Failed to force clock for F2: err %d\n", 2512 err); 2513 2514 /* Turn off the bus (F2), free any pending packets */ 2515 brcmf_dbg(INTR, "disable SDIO interrupts\n"); 2516 sdio_disable_func(sdiodev->func2); 2517 2518 /* Clear any pending interrupts now that F2 is disabled */ 2519 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus), 2520 local_hostintmask, NULL); 2521 2522 sdio_release_host(sdiodev->func1); 2523 } 2524 /* Clear the data packet queues */ 2525 brcmu_pktq_flush(&bus->txq, true, NULL, NULL); 2526 2527 /* Clear any held glomming stuff */ 2528 brcmu_pkt_buf_free_skb(bus->glomd); 2529 brcmf_sdio_free_glom(bus); 2530 2531 /* Clear rx control and wake any waiters */ 2532 spin_lock_bh(&bus->rxctl_lock); 2533 bus->rxlen = 0; 2534 spin_unlock_bh(&bus->rxctl_lock); 2535 brcmf_sdio_dcmd_resp_wake(bus); 2536 2537 /* Reset some F2 state stuff */ 2538 bus->rxskip = false; 2539 bus->tx_seq = bus->rx_seq = 0; 2540 } 2541 2542 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) 2543 { 2544 struct brcmf_sdio_dev *sdiodev; 2545 unsigned long flags; 2546 2547 sdiodev = bus->sdiodev; 2548 if (sdiodev->oob_irq_requested) { 2549 spin_lock_irqsave(&sdiodev->irq_en_lock, flags); 2550 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) { 2551 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr); 2552 sdiodev->irq_en = true; 2553 } 2554 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags); 2555 } 2556 } 2557 2558 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) 2559 { 2560 struct brcmf_core *core = bus->sdio_core; 2561 u32 addr; 2562 unsigned long val; 2563 int ret; 2564 2565 addr = core->base + SD_REG(intstatus); 2566 2567 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret); 2568 bus->sdcnt.f1regdata++; 2569 if (ret != 0) 2570 return ret; 2571 2572 val &= bus->hostintmask; 2573 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); 2574 2575 /* Clear interrupts */ 2576 if (val) { 2577 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret); 2578 bus->sdcnt.f1regdata++; 2579 atomic_or(val, &bus->intstatus); 2580 } 2581 2582 return ret; 2583 } 2584 2585 static void brcmf_sdio_dpc(struct brcmf_sdio *bus) 2586 { 2587 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 2588 u32 newstatus = 0; 2589 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2590 unsigned long intstatus; 2591 uint txlimit = bus->txbound; /* Tx frames to send before resched */ 2592 uint framecnt; /* Temporary counter of tx/rx frames */ 2593 int err = 0; 2594 2595 brcmf_dbg(SDIO, "Enter\n"); 2596 2597 sdio_claim_host(bus->sdiodev->func1); 2598 2599 /* If waiting for HTAVAIL, check status */ 2600 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { 2601 u8 clkctl, devctl = 0; 2602 2603 #ifdef DEBUG 2604 /* Check for inconsistent device control */ 2605 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL, 2606 &err); 2607 #endif /* DEBUG */ 2608 2609 /* Read CSR, if clock on switch to AVAIL, else ignore */ 2610 clkctl = brcmf_sdiod_readb(bus->sdiodev, 2611 SBSDIO_FUNC1_CHIPCLKCSR, &err); 2612 2613 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", 2614 devctl, clkctl); 2615 2616 if (SBSDIO_HTAV(clkctl)) { 2617 devctl = brcmf_sdiod_readb(bus->sdiodev, 2618 SBSDIO_DEVICE_CTL, &err); 2619 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 2620 brcmf_sdiod_writeb(bus->sdiodev, 2621 SBSDIO_DEVICE_CTL, devctl, &err); 2622 bus->clkstate = CLK_AVAIL; 2623 } 2624 } 2625 2626 /* Make sure backplane clock is on */ 2627 brcmf_sdio_bus_sleep(bus, false, true); 2628 2629 /* Pending interrupt indicates new device status */ 2630 if (atomic_read(&bus->ipend) > 0) { 2631 atomic_set(&bus->ipend, 0); 2632 err = brcmf_sdio_intr_rstatus(bus); 2633 } 2634 2635 /* Start with leftover status bits */ 2636 intstatus = atomic_xchg(&bus->intstatus, 0); 2637 2638 /* Handle flow-control change: read new state in case our ack 2639 * crossed another change interrupt. If change still set, assume 2640 * FC ON for safety, let next loop through do the debounce. 2641 */ 2642 if (intstatus & I_HMB_FC_CHANGE) { 2643 intstatus &= ~I_HMB_FC_CHANGE; 2644 brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err); 2645 2646 newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err); 2647 2648 bus->sdcnt.f1regdata += 2; 2649 atomic_set(&bus->fcstate, 2650 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); 2651 intstatus |= (newstatus & bus->hostintmask); 2652 } 2653 2654 /* Handle host mailbox indication */ 2655 if (intstatus & I_HMB_HOST_INT) { 2656 intstatus &= ~I_HMB_HOST_INT; 2657 intstatus |= brcmf_sdio_hostmail(bus); 2658 } 2659 2660 sdio_release_host(bus->sdiodev->func1); 2661 2662 /* Generally don't ask for these, can get CRC errors... */ 2663 if (intstatus & I_WR_OOSYNC) { 2664 brcmf_err("Dongle reports WR_OOSYNC\n"); 2665 intstatus &= ~I_WR_OOSYNC; 2666 } 2667 2668 if (intstatus & I_RD_OOSYNC) { 2669 brcmf_err("Dongle reports RD_OOSYNC\n"); 2670 intstatus &= ~I_RD_OOSYNC; 2671 } 2672 2673 if (intstatus & I_SBINT) { 2674 brcmf_err("Dongle reports SBINT\n"); 2675 intstatus &= ~I_SBINT; 2676 } 2677 2678 /* Would be active due to wake-wlan in gSPI */ 2679 if (intstatus & I_CHIPACTIVE) { 2680 brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n"); 2681 intstatus &= ~I_CHIPACTIVE; 2682 } 2683 2684 /* Ignore frame indications if rxskip is set */ 2685 if (bus->rxskip) 2686 intstatus &= ~I_HMB_FRAME_IND; 2687 2688 /* On frame indication, read available frames */ 2689 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { 2690 brcmf_sdio_readframes(bus, bus->rxbound); 2691 if (!bus->rxpending) 2692 intstatus &= ~I_HMB_FRAME_IND; 2693 } 2694 2695 /* Keep still-pending events for next scheduling */ 2696 if (intstatus) 2697 atomic_or(intstatus, &bus->intstatus); 2698 2699 brcmf_sdio_clrintr(bus); 2700 2701 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && 2702 txctl_ok(bus)) { 2703 sdio_claim_host(bus->sdiodev->func1); 2704 if (bus->ctrl_frame_stat) { 2705 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, 2706 bus->ctrl_frame_len); 2707 bus->ctrl_frame_err = err; 2708 wmb(); 2709 bus->ctrl_frame_stat = false; 2710 if (err) 2711 brcmf_err("sdio ctrlframe tx failed err=%d\n", 2712 err); 2713 } 2714 sdio_release_host(bus->sdiodev->func1); 2715 brcmf_sdio_wait_event_wakeup(bus); 2716 } 2717 /* Send queued frames (limit 1 if rx may still be pending) */ 2718 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && 2719 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && 2720 data_ok(bus)) { 2721 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : 2722 txlimit; 2723 brcmf_sdio_sendfromq(bus, framecnt); 2724 } 2725 2726 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { 2727 brcmf_err("failed backplane access over SDIO, halting operation\n"); 2728 atomic_set(&bus->intstatus, 0); 2729 if (bus->ctrl_frame_stat) { 2730 sdio_claim_host(bus->sdiodev->func1); 2731 if (bus->ctrl_frame_stat) { 2732 bus->ctrl_frame_err = -ENODEV; 2733 wmb(); 2734 bus->ctrl_frame_stat = false; 2735 brcmf_sdio_wait_event_wakeup(bus); 2736 } 2737 sdio_release_host(bus->sdiodev->func1); 2738 } 2739 } else if (atomic_read(&bus->intstatus) || 2740 atomic_read(&bus->ipend) > 0 || 2741 (!atomic_read(&bus->fcstate) && 2742 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && 2743 data_ok(bus))) { 2744 bus->dpc_triggered = true; 2745 } 2746 } 2747 2748 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) 2749 { 2750 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2751 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2752 struct brcmf_sdio *bus = sdiodev->bus; 2753 2754 return &bus->txq; 2755 } 2756 2757 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) 2758 { 2759 struct sk_buff *p; 2760 int eprec = -1; /* precedence to evict from */ 2761 2762 /* Fast case, precedence queue is not full and we are also not 2763 * exceeding total queue length 2764 */ 2765 if (!pktq_pfull(q, prec) && !pktq_full(q)) { 2766 brcmu_pktq_penq(q, prec, pkt); 2767 return true; 2768 } 2769 2770 /* Determine precedence from which to evict packet, if any */ 2771 if (pktq_pfull(q, prec)) { 2772 eprec = prec; 2773 } else if (pktq_full(q)) { 2774 p = brcmu_pktq_peek_tail(q, &eprec); 2775 if (eprec > prec) 2776 return false; 2777 } 2778 2779 /* Evict if needed */ 2780 if (eprec >= 0) { 2781 /* Detect queueing to unconfigured precedence */ 2782 if (eprec == prec) 2783 return false; /* refuse newer (incoming) packet */ 2784 /* Evict packet according to discard policy */ 2785 p = brcmu_pktq_pdeq_tail(q, eprec); 2786 if (p == NULL) 2787 brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); 2788 brcmu_pkt_buf_free_skb(p); 2789 } 2790 2791 /* Enqueue */ 2792 p = brcmu_pktq_penq(q, prec, pkt); 2793 if (p == NULL) 2794 brcmf_err("brcmu_pktq_penq() failed\n"); 2795 2796 return p != NULL; 2797 } 2798 2799 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) 2800 { 2801 int ret = -EBADE; 2802 uint prec; 2803 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2804 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2805 struct brcmf_sdio *bus = sdiodev->bus; 2806 2807 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); 2808 if (sdiodev->state != BRCMF_SDIOD_DATA) 2809 return -EIO; 2810 2811 /* Add space for the header */ 2812 skb_push(pkt, bus->tx_hdrlen); 2813 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ 2814 2815 /* In WLAN, priority is always set by the AP using WMM parameters 2816 * and this need not always follow the standard 802.1d priority. 2817 * Based on AP WMM config, map from 802.1d priority to corresponding 2818 * precedence level. 2819 */ 2820 prec = brcmf_map_prio_to_prec(bus_if->drvr->config, 2821 (pkt->priority & PRIOMASK)); 2822 2823 /* Check for existing queue, current flow-control, 2824 pending event, or pending clock */ 2825 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); 2826 bus->sdcnt.fcqueued++; 2827 2828 /* Priority based enq */ 2829 spin_lock_bh(&bus->txq_lock); 2830 /* reset bus_flags in packet cb */ 2831 *(u16 *)(pkt->cb) = 0; 2832 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { 2833 skb_pull(pkt, bus->tx_hdrlen); 2834 brcmf_err("out of bus->txq !!!\n"); 2835 ret = -ENOSR; 2836 } else { 2837 ret = 0; 2838 } 2839 2840 if (pktq_len(&bus->txq) >= TXHI) { 2841 bus->txoff = true; 2842 brcmf_proto_bcdc_txflowblock(dev, true); 2843 } 2844 spin_unlock_bh(&bus->txq_lock); 2845 2846 #ifdef DEBUG 2847 if (pktq_plen(&bus->txq, prec) > qcount[prec]) 2848 qcount[prec] = pktq_plen(&bus->txq, prec); 2849 #endif 2850 2851 brcmf_sdio_trigger_dpc(bus); 2852 return ret; 2853 } 2854 2855 #ifdef DEBUG 2856 #define CONSOLE_LINE_MAX 192 2857 2858 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) 2859 { 2860 struct brcmf_console *c = &bus->console; 2861 u8 line[CONSOLE_LINE_MAX], ch; 2862 u32 n, idx, addr; 2863 int rv; 2864 2865 /* Don't do anything until FWREADY updates console address */ 2866 if (bus->console_addr == 0) 2867 return 0; 2868 2869 /* Read console log struct */ 2870 addr = bus->console_addr + offsetof(struct rte_console, log_le); 2871 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, 2872 sizeof(c->log_le)); 2873 if (rv < 0) 2874 return rv; 2875 2876 /* Allocate console buffer (one time only) */ 2877 if (c->buf == NULL) { 2878 c->bufsize = le32_to_cpu(c->log_le.buf_size); 2879 c->buf = kmalloc(c->bufsize, GFP_ATOMIC); 2880 if (c->buf == NULL) 2881 return -ENOMEM; 2882 } 2883 2884 idx = le32_to_cpu(c->log_le.idx); 2885 2886 /* Protect against corrupt value */ 2887 if (idx > c->bufsize) 2888 return -EBADE; 2889 2890 /* Skip reading the console buffer if the index pointer 2891 has not moved */ 2892 if (idx == c->last) 2893 return 0; 2894 2895 /* Read the console buffer */ 2896 addr = le32_to_cpu(c->log_le.buf); 2897 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); 2898 if (rv < 0) 2899 return rv; 2900 2901 while (c->last != idx) { 2902 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { 2903 if (c->last == idx) { 2904 /* This would output a partial line. 2905 * Instead, back up 2906 * the buffer pointer and output this 2907 * line next time around. 2908 */ 2909 if (c->last >= n) 2910 c->last -= n; 2911 else 2912 c->last = c->bufsize - n; 2913 goto break2; 2914 } 2915 ch = c->buf[c->last]; 2916 c->last = (c->last + 1) % c->bufsize; 2917 if (ch == '\n') 2918 break; 2919 line[n] = ch; 2920 } 2921 2922 if (n > 0) { 2923 if (line[n - 1] == '\r') 2924 n--; 2925 line[n] = 0; 2926 pr_debug("CONSOLE: %s\n", line); 2927 } 2928 } 2929 break2: 2930 2931 return 0; 2932 } 2933 #endif /* DEBUG */ 2934 2935 static int 2936 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) 2937 { 2938 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2939 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2940 struct brcmf_sdio *bus = sdiodev->bus; 2941 int ret; 2942 2943 brcmf_dbg(TRACE, "Enter\n"); 2944 if (sdiodev->state != BRCMF_SDIOD_DATA) 2945 return -EIO; 2946 2947 /* Send from dpc */ 2948 bus->ctrl_frame_buf = msg; 2949 bus->ctrl_frame_len = msglen; 2950 wmb(); 2951 bus->ctrl_frame_stat = true; 2952 2953 brcmf_sdio_trigger_dpc(bus); 2954 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, 2955 CTL_DONE_TIMEOUT); 2956 ret = 0; 2957 if (bus->ctrl_frame_stat) { 2958 sdio_claim_host(bus->sdiodev->func1); 2959 if (bus->ctrl_frame_stat) { 2960 brcmf_dbg(SDIO, "ctrl_frame timeout\n"); 2961 bus->ctrl_frame_stat = false; 2962 ret = -ETIMEDOUT; 2963 } 2964 sdio_release_host(bus->sdiodev->func1); 2965 } 2966 if (!ret) { 2967 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", 2968 bus->ctrl_frame_err); 2969 rmb(); 2970 ret = bus->ctrl_frame_err; 2971 } 2972 2973 if (ret) 2974 bus->sdcnt.tx_ctlerrs++; 2975 else 2976 bus->sdcnt.tx_ctlpkts++; 2977 2978 return ret; 2979 } 2980 2981 #ifdef DEBUG 2982 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, 2983 struct sdpcm_shared *sh) 2984 { 2985 u32 addr, console_ptr, console_size, console_index; 2986 char *conbuf = NULL; 2987 __le32 sh_val; 2988 int rv; 2989 2990 /* obtain console information from device memory */ 2991 addr = sh->console_addr + offsetof(struct rte_console, log_le); 2992 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2993 (u8 *)&sh_val, sizeof(u32)); 2994 if (rv < 0) 2995 return rv; 2996 console_ptr = le32_to_cpu(sh_val); 2997 2998 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); 2999 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 3000 (u8 *)&sh_val, sizeof(u32)); 3001 if (rv < 0) 3002 return rv; 3003 console_size = le32_to_cpu(sh_val); 3004 3005 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); 3006 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 3007 (u8 *)&sh_val, sizeof(u32)); 3008 if (rv < 0) 3009 return rv; 3010 console_index = le32_to_cpu(sh_val); 3011 3012 /* allocate buffer for console data */ 3013 if (console_size <= CONSOLE_BUFFER_MAX) 3014 conbuf = vzalloc(console_size+1); 3015 3016 if (!conbuf) 3017 return -ENOMEM; 3018 3019 /* obtain the console data from device */ 3020 conbuf[console_size] = '\0'; 3021 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, 3022 console_size); 3023 if (rv < 0) 3024 goto done; 3025 3026 rv = seq_write(seq, conbuf + console_index, 3027 console_size - console_index); 3028 if (rv < 0) 3029 goto done; 3030 3031 if (console_index > 0) 3032 rv = seq_write(seq, conbuf, console_index - 1); 3033 3034 done: 3035 vfree(conbuf); 3036 return rv; 3037 } 3038 3039 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, 3040 struct sdpcm_shared *sh) 3041 { 3042 int error; 3043 struct brcmf_trap_info tr; 3044 3045 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { 3046 brcmf_dbg(INFO, "no trap in firmware\n"); 3047 return 0; 3048 } 3049 3050 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, 3051 sizeof(struct brcmf_trap_info)); 3052 if (error < 0) 3053 return error; 3054 3055 if (seq) 3056 seq_printf(seq, 3057 "dongle trap info: type 0x%x @ epc 0x%08x\n" 3058 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3059 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3060 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3061 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3062 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3063 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3064 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3065 le32_to_cpu(tr.pc), sh->trap_addr, 3066 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3067 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3068 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3069 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3070 else 3071 pr_debug("dongle trap info: type 0x%x @ epc 0x%08x\n" 3072 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3073 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3074 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3075 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3076 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3077 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3078 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3079 le32_to_cpu(tr.pc), sh->trap_addr, 3080 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3081 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3082 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3083 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3084 return 0; 3085 } 3086 3087 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, 3088 struct sdpcm_shared *sh) 3089 { 3090 int error = 0; 3091 char file[80] = "?"; 3092 char expr[80] = "<???>"; 3093 3094 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { 3095 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3096 return 0; 3097 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { 3098 brcmf_dbg(INFO, "no assert in dongle\n"); 3099 return 0; 3100 } 3101 3102 sdio_claim_host(bus->sdiodev->func1); 3103 if (sh->assert_file_addr != 0) { 3104 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3105 sh->assert_file_addr, (u8 *)file, 80); 3106 if (error < 0) 3107 return error; 3108 } 3109 if (sh->assert_exp_addr != 0) { 3110 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3111 sh->assert_exp_addr, (u8 *)expr, 80); 3112 if (error < 0) 3113 return error; 3114 } 3115 sdio_release_host(bus->sdiodev->func1); 3116 3117 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", 3118 file, sh->assert_line, expr); 3119 return 0; 3120 } 3121 3122 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3123 { 3124 int error; 3125 struct sdpcm_shared sh; 3126 3127 error = brcmf_sdio_readshared(bus, &sh); 3128 3129 if (error < 0) 3130 return error; 3131 3132 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) 3133 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3134 else if (sh.flags & SDPCM_SHARED_ASSERT) 3135 brcmf_err("assertion in dongle\n"); 3136 3137 if (sh.flags & SDPCM_SHARED_TRAP) { 3138 brcmf_err("firmware trap in dongle\n"); 3139 brcmf_sdio_trap_info(NULL, bus, &sh); 3140 } 3141 3142 return 0; 3143 } 3144 3145 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) 3146 { 3147 int error = 0; 3148 struct sdpcm_shared sh; 3149 3150 error = brcmf_sdio_readshared(bus, &sh); 3151 if (error < 0) 3152 goto done; 3153 3154 error = brcmf_sdio_assert_info(seq, bus, &sh); 3155 if (error < 0) 3156 goto done; 3157 3158 error = brcmf_sdio_trap_info(seq, bus, &sh); 3159 if (error < 0) 3160 goto done; 3161 3162 error = brcmf_sdio_dump_console(seq, bus, &sh); 3163 3164 done: 3165 return error; 3166 } 3167 3168 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) 3169 { 3170 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3171 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; 3172 3173 return brcmf_sdio_died_dump(seq, bus); 3174 } 3175 3176 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) 3177 { 3178 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3179 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3180 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; 3181 3182 seq_printf(seq, 3183 "intrcount: %u\nlastintrs: %u\n" 3184 "pollcnt: %u\nregfails: %u\n" 3185 "tx_sderrs: %u\nfcqueued: %u\n" 3186 "rxrtx: %u\nrx_toolong: %u\n" 3187 "rxc_errors: %u\nrx_hdrfail: %u\n" 3188 "rx_badhdr: %u\nrx_badseq: %u\n" 3189 "fc_rcvd: %u\nfc_xoff: %u\n" 3190 "fc_xon: %u\nrxglomfail: %u\n" 3191 "rxglomframes: %u\nrxglompkts: %u\n" 3192 "f2rxhdrs: %u\nf2rxdata: %u\n" 3193 "f2txdata: %u\nf1regdata: %u\n" 3194 "tickcnt: %u\ntx_ctlerrs: %lu\n" 3195 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" 3196 "rx_ctlpkts: %lu\nrx_readahead: %lu\n", 3197 sdcnt->intrcount, sdcnt->lastintrs, 3198 sdcnt->pollcnt, sdcnt->regfails, 3199 sdcnt->tx_sderrs, sdcnt->fcqueued, 3200 sdcnt->rxrtx, sdcnt->rx_toolong, 3201 sdcnt->rxc_errors, sdcnt->rx_hdrfail, 3202 sdcnt->rx_badhdr, sdcnt->rx_badseq, 3203 sdcnt->fc_rcvd, sdcnt->fc_xoff, 3204 sdcnt->fc_xon, sdcnt->rxglomfail, 3205 sdcnt->rxglomframes, sdcnt->rxglompkts, 3206 sdcnt->f2rxhdrs, sdcnt->f2rxdata, 3207 sdcnt->f2txdata, sdcnt->f1regdata, 3208 sdcnt->tickcnt, sdcnt->tx_ctlerrs, 3209 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, 3210 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); 3211 3212 return 0; 3213 } 3214 3215 static void brcmf_sdio_debugfs_create(struct device *dev) 3216 { 3217 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3218 struct brcmf_pub *drvr = bus_if->drvr; 3219 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3220 struct brcmf_sdio *bus = sdiodev->bus; 3221 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 3222 3223 if (IS_ERR_OR_NULL(dentry)) 3224 return; 3225 3226 bus->console_interval = BRCMF_CONSOLE; 3227 3228 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); 3229 brcmf_debugfs_add_entry(drvr, "counters", 3230 brcmf_debugfs_sdio_count_read); 3231 debugfs_create_u32("console_interval", 0644, dentry, 3232 &bus->console_interval); 3233 } 3234 #else 3235 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3236 { 3237 return 0; 3238 } 3239 3240 static void brcmf_sdio_debugfs_create(struct device *dev) 3241 { 3242 } 3243 #endif /* DEBUG */ 3244 3245 static int 3246 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) 3247 { 3248 int timeleft; 3249 uint rxlen = 0; 3250 bool pending; 3251 u8 *buf; 3252 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3253 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3254 struct brcmf_sdio *bus = sdiodev->bus; 3255 3256 brcmf_dbg(TRACE, "Enter\n"); 3257 if (sdiodev->state != BRCMF_SDIOD_DATA) 3258 return -EIO; 3259 3260 /* Wait until control frame is available */ 3261 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); 3262 3263 spin_lock_bh(&bus->rxctl_lock); 3264 rxlen = bus->rxlen; 3265 memcpy(msg, bus->rxctl, min(msglen, rxlen)); 3266 bus->rxctl = NULL; 3267 buf = bus->rxctl_orig; 3268 bus->rxctl_orig = NULL; 3269 bus->rxlen = 0; 3270 spin_unlock_bh(&bus->rxctl_lock); 3271 vfree(buf); 3272 3273 if (rxlen) { 3274 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", 3275 rxlen, msglen); 3276 } else if (timeleft == 0) { 3277 brcmf_err("resumed on timeout\n"); 3278 brcmf_sdio_checkdied(bus); 3279 } else if (pending) { 3280 brcmf_dbg(CTL, "cancelled\n"); 3281 return -ERESTARTSYS; 3282 } else { 3283 brcmf_dbg(CTL, "resumed for unknown reason?\n"); 3284 brcmf_sdio_checkdied(bus); 3285 } 3286 3287 if (rxlen) 3288 bus->sdcnt.rx_ctlpkts++; 3289 else 3290 bus->sdcnt.rx_ctlerrs++; 3291 3292 return rxlen ? (int)rxlen : -ETIMEDOUT; 3293 } 3294 3295 #ifdef DEBUG 3296 static bool 3297 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3298 u8 *ram_data, uint ram_sz) 3299 { 3300 char *ram_cmp; 3301 int err; 3302 bool ret = true; 3303 int address; 3304 int offset; 3305 int len; 3306 3307 /* read back and verify */ 3308 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, 3309 ram_sz); 3310 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); 3311 /* do not proceed while no memory but */ 3312 if (!ram_cmp) 3313 return true; 3314 3315 address = ram_addr; 3316 offset = 0; 3317 while (offset < ram_sz) { 3318 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : 3319 ram_sz - offset; 3320 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); 3321 if (err) { 3322 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3323 err, len, address); 3324 ret = false; 3325 break; 3326 } else if (memcmp(ram_cmp, &ram_data[offset], len)) { 3327 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", 3328 offset, len); 3329 ret = false; 3330 break; 3331 } 3332 offset += len; 3333 address += len; 3334 } 3335 3336 kfree(ram_cmp); 3337 3338 return ret; 3339 } 3340 #else /* DEBUG */ 3341 static bool 3342 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3343 u8 *ram_data, uint ram_sz) 3344 { 3345 return true; 3346 } 3347 #endif /* DEBUG */ 3348 3349 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, 3350 const struct firmware *fw) 3351 { 3352 int err; 3353 3354 brcmf_dbg(TRACE, "Enter\n"); 3355 3356 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, 3357 (u8 *)fw->data, fw->size); 3358 if (err) 3359 brcmf_err("error %d on writing %d membytes at 0x%08x\n", 3360 err, (int)fw->size, bus->ci->rambase); 3361 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, 3362 (u8 *)fw->data, fw->size)) 3363 err = -EIO; 3364 3365 return err; 3366 } 3367 3368 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, 3369 void *vars, u32 varsz) 3370 { 3371 int address; 3372 int err; 3373 3374 brcmf_dbg(TRACE, "Enter\n"); 3375 3376 address = bus->ci->ramsize - varsz + bus->ci->rambase; 3377 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); 3378 if (err) 3379 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", 3380 err, varsz, address); 3381 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) 3382 err = -EIO; 3383 3384 return err; 3385 } 3386 3387 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, 3388 const struct firmware *fw, 3389 void *nvram, u32 nvlen) 3390 { 3391 int bcmerror; 3392 u32 rstvec; 3393 3394 sdio_claim_host(bus->sdiodev->func1); 3395 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 3396 3397 rstvec = get_unaligned_le32(fw->data); 3398 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); 3399 3400 bcmerror = brcmf_sdio_download_code_file(bus, fw); 3401 release_firmware(fw); 3402 if (bcmerror) { 3403 brcmf_err("dongle image file download failed\n"); 3404 brcmf_fw_nvram_free(nvram); 3405 goto err; 3406 } 3407 3408 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); 3409 brcmf_fw_nvram_free(nvram); 3410 if (bcmerror) { 3411 brcmf_err("dongle nvram file download failed\n"); 3412 goto err; 3413 } 3414 3415 /* Take arm out of reset */ 3416 if (!brcmf_chip_set_active(bus->ci, rstvec)) { 3417 brcmf_err("error getting out of ARM core reset\n"); 3418 bcmerror = -EIO; 3419 goto err; 3420 } 3421 3422 err: 3423 brcmf_sdio_clkctl(bus, CLK_SDONLY, false); 3424 sdio_release_host(bus->sdiodev->func1); 3425 return bcmerror; 3426 } 3427 3428 static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus) 3429 { 3430 if (bus->ci->chip == BRCM_CC_43751_CHIP_ID || 3431 bus->ci->chip == BRCM_CC_43752_CHIP_ID || 3432 bus->ci->chip == CY_CC_43012_CHIP_ID) 3433 return true; 3434 else 3435 return false; 3436 } 3437 3438 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) 3439 { 3440 int err = 0; 3441 u8 val; 3442 u8 wakeupctrl; 3443 u8 cardcap; 3444 u8 chipclkcsr; 3445 3446 brcmf_dbg(TRACE, "Enter\n"); 3447 3448 if (brcmf_chip_is_ulp(bus->ci)) { 3449 wakeupctrl = SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT; 3450 chipclkcsr = SBSDIO_HT_AVAIL_REQ; 3451 } else { 3452 wakeupctrl = SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; 3453 chipclkcsr = SBSDIO_FORCE_HT; 3454 } 3455 3456 if (brcmf_sdio_aos_no_decode(bus)) { 3457 cardcap = SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC; 3458 } else { 3459 cardcap = (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | 3460 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT); 3461 } 3462 3463 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); 3464 if (err) { 3465 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); 3466 return; 3467 } 3468 val |= 1 << wakeupctrl; 3469 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); 3470 if (err) { 3471 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); 3472 return; 3473 } 3474 3475 /* Add CMD14 Support */ 3476 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, 3477 cardcap, 3478 &err); 3479 if (err) { 3480 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); 3481 return; 3482 } 3483 3484 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3485 chipclkcsr, &err); 3486 if (err) { 3487 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); 3488 return; 3489 } 3490 3491 /* set flag */ 3492 bus->sr_enabled = true; 3493 brcmf_dbg(INFO, "SR enabled\n"); 3494 } 3495 3496 /* enable KSO bit */ 3497 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) 3498 { 3499 struct brcmf_core *core = bus->sdio_core; 3500 u8 val; 3501 int err = 0; 3502 3503 brcmf_dbg(TRACE, "Enter\n"); 3504 3505 /* KSO bit added in SDIO core rev 12 */ 3506 if (core->rev < 12) 3507 return 0; 3508 3509 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); 3510 if (err) { 3511 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); 3512 return err; 3513 } 3514 3515 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { 3516 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << 3517 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 3518 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 3519 val, &err); 3520 if (err) { 3521 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); 3522 return err; 3523 } 3524 } 3525 3526 return 0; 3527 } 3528 3529 3530 static int brcmf_sdio_bus_preinit(struct device *dev) 3531 { 3532 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3533 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3534 struct brcmf_sdio *bus = sdiodev->bus; 3535 struct brcmf_core *core = bus->sdio_core; 3536 u32 value; 3537 __le32 iovar; 3538 int err; 3539 3540 /* maxctl provided by common layer */ 3541 if (WARN_ON(!bus_if->maxctl)) 3542 return -EINVAL; 3543 3544 /* Allocate control receive buffer */ 3545 bus_if->maxctl += bus->roundup; 3546 value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT); 3547 value += bus->head_align; 3548 bus->rxbuf = kmalloc(value, GFP_ATOMIC); 3549 if (bus->rxbuf) 3550 bus->rxblen = value; 3551 3552 /* the commands below use the terms tx and rx from 3553 * a device perspective, ie. bus:txglom affects the 3554 * bus transfers from device to host. 3555 */ 3556 if (core->rev < 12) { 3557 /* for sdio core rev < 12, disable txgloming */ 3558 iovar = 0; 3559 err = brcmf_iovar_data_set(dev, "bus:txglom", &iovar, 3560 sizeof(iovar)); 3561 } else { 3562 /* otherwise, set txglomalign */ 3563 value = sdiodev->settings->bus.sdio.sd_sgentry_align; 3564 /* SDIO ADMA requires at least 32 bit alignment */ 3565 iovar = cpu_to_le32(max_t(u32, value, ALIGNMENT)); 3566 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &iovar, 3567 sizeof(iovar)); 3568 } 3569 3570 if (err < 0) 3571 goto done; 3572 3573 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 3574 if (sdiodev->sg_support) { 3575 bus->txglom = false; 3576 iovar = cpu_to_le32(1); 3577 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", 3578 &iovar, sizeof(iovar)); 3579 if (err < 0) { 3580 /* bus:rxglom is allowed to fail */ 3581 err = 0; 3582 } else { 3583 bus->txglom = true; 3584 bus->tx_hdrlen += SDPCM_HWEXT_LEN; 3585 } 3586 } 3587 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); 3588 3589 done: 3590 return err; 3591 } 3592 3593 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev) 3594 { 3595 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3596 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3597 struct brcmf_sdio *bus = sdiodev->bus; 3598 3599 return bus->ci->ramsize - bus->ci->srsize; 3600 } 3601 3602 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data, 3603 size_t mem_size) 3604 { 3605 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3606 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3607 struct brcmf_sdio *bus = sdiodev->bus; 3608 int err; 3609 int address; 3610 int offset; 3611 int len; 3612 3613 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase, 3614 mem_size); 3615 3616 address = bus->ci->rambase; 3617 offset = err = 0; 3618 sdio_claim_host(sdiodev->func1); 3619 while (offset < mem_size) { 3620 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK : 3621 mem_size - offset; 3622 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len); 3623 if (err) { 3624 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3625 err, len, address); 3626 goto done; 3627 } 3628 data += len; 3629 offset += len; 3630 address += len; 3631 } 3632 3633 done: 3634 sdio_release_host(sdiodev->func1); 3635 return err; 3636 } 3637 3638 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) 3639 { 3640 if (!bus->dpc_triggered) { 3641 bus->dpc_triggered = true; 3642 queue_work(bus->brcmf_wq, &bus->datawork); 3643 } 3644 } 3645 3646 void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr) 3647 { 3648 brcmf_dbg(TRACE, "Enter\n"); 3649 3650 if (!bus) { 3651 brcmf_err("bus is null pointer, exiting\n"); 3652 return; 3653 } 3654 3655 /* Count the interrupt call */ 3656 bus->sdcnt.intrcount++; 3657 if (in_isr) 3658 atomic_set(&bus->ipend, 1); 3659 else 3660 if (brcmf_sdio_intr_rstatus(bus)) { 3661 brcmf_err("failed backplane access\n"); 3662 } 3663 3664 /* Disable additional interrupts (is this needed now)? */ 3665 if (!bus->intr) 3666 brcmf_err("isr w/o interrupt configured!\n"); 3667 3668 bus->dpc_triggered = true; 3669 queue_work(bus->brcmf_wq, &bus->datawork); 3670 } 3671 3672 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) 3673 { 3674 brcmf_dbg(TIMER, "Enter\n"); 3675 3676 /* Poll period: check device if appropriate. */ 3677 if (!bus->sr_enabled && 3678 bus->poll && (++bus->polltick >= bus->pollrate)) { 3679 u32 intstatus = 0; 3680 3681 /* Reset poll tick */ 3682 bus->polltick = 0; 3683 3684 /* Check device if no interrupts */ 3685 if (!bus->intr || 3686 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { 3687 3688 if (!bus->dpc_triggered) { 3689 u8 devpend; 3690 3691 sdio_claim_host(bus->sdiodev->func1); 3692 devpend = brcmf_sdiod_func0_rb(bus->sdiodev, 3693 SDIO_CCCR_INTx, NULL); 3694 sdio_release_host(bus->sdiodev->func1); 3695 intstatus = devpend & (INTR_STATUS_FUNC1 | 3696 INTR_STATUS_FUNC2); 3697 } 3698 3699 /* If there is something, make like the ISR and 3700 schedule the DPC */ 3701 if (intstatus) { 3702 bus->sdcnt.pollcnt++; 3703 atomic_set(&bus->ipend, 1); 3704 3705 bus->dpc_triggered = true; 3706 queue_work(bus->brcmf_wq, &bus->datawork); 3707 } 3708 } 3709 3710 /* Update interrupt tracking */ 3711 bus->sdcnt.lastintrs = bus->sdcnt.intrcount; 3712 } 3713 #ifdef DEBUG 3714 /* Poll for console output periodically */ 3715 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() && 3716 bus->console_interval != 0) { 3717 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL); 3718 if (bus->console.count >= bus->console_interval) { 3719 bus->console.count -= bus->console_interval; 3720 sdio_claim_host(bus->sdiodev->func1); 3721 /* Make sure backplane clock is on */ 3722 brcmf_sdio_bus_sleep(bus, false, false); 3723 if (brcmf_sdio_readconsole(bus) < 0) 3724 /* stop on error */ 3725 bus->console_interval = 0; 3726 sdio_release_host(bus->sdiodev->func1); 3727 } 3728 } 3729 #endif /* DEBUG */ 3730 3731 /* On idle timeout clear activity flag and/or turn off clock */ 3732 if (!bus->dpc_triggered) { 3733 rmb(); 3734 if ((!bus->dpc_running) && (bus->idletime > 0) && 3735 (bus->clkstate == CLK_AVAIL)) { 3736 bus->idlecount++; 3737 if (bus->idlecount > bus->idletime) { 3738 brcmf_dbg(SDIO, "idle\n"); 3739 sdio_claim_host(bus->sdiodev->func1); 3740 #ifdef DEBUG 3741 if (!BRCMF_FWCON_ON() || 3742 bus->console_interval == 0) 3743 #endif 3744 brcmf_sdio_wd_timer(bus, false); 3745 bus->idlecount = 0; 3746 brcmf_sdio_bus_sleep(bus, true, false); 3747 sdio_release_host(bus->sdiodev->func1); 3748 } 3749 } else { 3750 bus->idlecount = 0; 3751 } 3752 } else { 3753 bus->idlecount = 0; 3754 } 3755 } 3756 3757 static void brcmf_sdio_dataworker(struct work_struct *work) 3758 { 3759 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, 3760 datawork); 3761 3762 bus->dpc_running = true; 3763 wmb(); 3764 while (READ_ONCE(bus->dpc_triggered)) { 3765 bus->dpc_triggered = false; 3766 brcmf_sdio_dpc(bus); 3767 bus->idlecount = 0; 3768 } 3769 bus->dpc_running = false; 3770 if (brcmf_sdiod_freezing(bus->sdiodev)) { 3771 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); 3772 brcmf_sdiod_try_freeze(bus->sdiodev); 3773 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 3774 } 3775 } 3776 3777 static void 3778 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, 3779 struct brcmf_chip *ci, u32 drivestrength) 3780 { 3781 const struct sdiod_drive_str *str_tab = NULL; 3782 u32 str_mask; 3783 u32 str_shift; 3784 u32 i; 3785 u32 drivestrength_sel = 0; 3786 u32 cc_data_temp; 3787 u32 addr; 3788 3789 if (!(ci->cc_caps & CC_CAP_PMU)) 3790 return; 3791 3792 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { 3793 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): 3794 str_tab = sdiod_drvstr_tab1_1v8; 3795 str_mask = 0x00003800; 3796 str_shift = 11; 3797 break; 3798 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): 3799 str_tab = sdiod_drvstr_tab6_1v8; 3800 str_mask = 0x00001800; 3801 str_shift = 11; 3802 break; 3803 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): 3804 /* note: 43143 does not support tristate */ 3805 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; 3806 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { 3807 str_tab = sdiod_drvstr_tab2_3v3; 3808 str_mask = 0x00000007; 3809 str_shift = 0; 3810 } else 3811 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", 3812 ci->name, drivestrength); 3813 break; 3814 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): 3815 str_tab = sdiod_drive_strength_tab5_1v8; 3816 str_mask = 0x00003800; 3817 str_shift = 11; 3818 break; 3819 default: 3820 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n", 3821 ci->name, ci->chiprev, ci->pmurev); 3822 break; 3823 } 3824 3825 if (str_tab != NULL) { 3826 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci); 3827 3828 for (i = 0; str_tab[i].strength != 0; i++) { 3829 if (drivestrength >= str_tab[i].strength) { 3830 drivestrength_sel = str_tab[i].sel; 3831 break; 3832 } 3833 } 3834 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); 3835 brcmf_sdiod_writel(sdiodev, addr, 1, NULL); 3836 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL); 3837 cc_data_temp &= ~str_mask; 3838 drivestrength_sel <<= str_shift; 3839 cc_data_temp |= drivestrength_sel; 3840 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL); 3841 3842 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", 3843 str_tab[i].strength, drivestrength, cc_data_temp); 3844 } 3845 } 3846 3847 static int brcmf_sdio_buscoreprep(void *ctx) 3848 { 3849 struct brcmf_sdio_dev *sdiodev = ctx; 3850 int err = 0; 3851 u8 clkval, clkset; 3852 3853 /* Try forcing SDIO core to do ALPAvail request only */ 3854 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; 3855 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3856 if (err) { 3857 brcmf_err("error writing for HT off\n"); 3858 return err; 3859 } 3860 3861 /* If register supported, wait for ALPAvail and then force ALP */ 3862 /* This may take up to 15 milliseconds */ 3863 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL); 3864 3865 if ((clkval & ~SBSDIO_AVBITS) != clkset) { 3866 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", 3867 clkset, clkval); 3868 return -EACCES; 3869 } 3870 3871 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3872 NULL)), 3873 !SBSDIO_ALPAV(clkval)), 3874 PMU_MAX_TRANSITION_DLY); 3875 3876 if (!SBSDIO_ALPAV(clkval)) { 3877 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", 3878 clkval); 3879 return -EBUSY; 3880 } 3881 3882 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; 3883 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3884 udelay(65); 3885 3886 /* Also, disable the extra SDIO pull-ups */ 3887 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); 3888 3889 return 0; 3890 } 3891 3892 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, 3893 u32 rstvec) 3894 { 3895 struct brcmf_sdio_dev *sdiodev = ctx; 3896 struct brcmf_core *core = sdiodev->bus->sdio_core; 3897 u32 reg_addr; 3898 3899 /* clear all interrupts */ 3900 reg_addr = core->base + SD_REG(intstatus); 3901 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL); 3902 3903 if (rstvec) 3904 /* Write reset vector to address 0 */ 3905 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, 3906 sizeof(rstvec)); 3907 } 3908 3909 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) 3910 { 3911 struct brcmf_sdio_dev *sdiodev = ctx; 3912 u32 val, rev; 3913 3914 val = brcmf_sdiod_readl(sdiodev, addr, NULL); 3915 3916 /* 3917 * this is a bit of special handling if reading the chipcommon chipid 3918 * register. The 4339 is a next-gen of the 4335. It uses the same 3919 * SDIO device id as 4335 and the chipid register returns 4335 as well. 3920 * It can be identified as 4339 by looking at the chip revision. It 3921 * is corrected here so the chip.c module has the right info. 3922 */ 3923 if (addr == CORE_CC_REG(SI_ENUM_BASE_DEFAULT, chipid) && 3924 (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 || 3925 sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) { 3926 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; 3927 if (rev >= 2) { 3928 val &= ~CID_ID_MASK; 3929 val |= BRCM_CC_4339_CHIP_ID; 3930 } 3931 } 3932 3933 return val; 3934 } 3935 3936 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) 3937 { 3938 struct brcmf_sdio_dev *sdiodev = ctx; 3939 3940 brcmf_sdiod_writel(sdiodev, addr, val, NULL); 3941 } 3942 3943 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { 3944 .prepare = brcmf_sdio_buscoreprep, 3945 .activate = brcmf_sdio_buscore_activate, 3946 .read32 = brcmf_sdio_buscore_read32, 3947 .write32 = brcmf_sdio_buscore_write32, 3948 }; 3949 3950 static int 3951 brcmf_sdio_probe_attach(struct brcmf_sdio *bus) 3952 { 3953 struct brcmf_sdio_dev *sdiodev; 3954 u8 clkctl = 0; 3955 int err = 0; 3956 int reg_addr; 3957 u32 reg_val; 3958 u32 drivestrength; 3959 u32 enum_base; 3960 int ret = -EBADE; 3961 3962 sdiodev = bus->sdiodev; 3963 sdio_claim_host(sdiodev->func1); 3964 3965 enum_base = brcmf_chip_enum_base(sdiodev->func1->device); 3966 3967 pr_debug("F1 signature read @0x%08x=0x%4x\n", enum_base, 3968 brcmf_sdiod_readl(sdiodev, enum_base, NULL)); 3969 3970 /* 3971 * Force PLL off until brcmf_chip_attach() 3972 * programs PLL control regs 3973 */ 3974 3975 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1, 3976 &err); 3977 if (!err) 3978 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3979 &err); 3980 3981 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { 3982 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", 3983 err, BRCMF_INIT_CLKCTL1, clkctl); 3984 goto fail; 3985 } 3986 3987 bus->ci = brcmf_chip_attach(sdiodev, sdiodev->func1->device, 3988 &brcmf_sdio_buscore_ops); 3989 if (IS_ERR(bus->ci)) { 3990 brcmf_err("brcmf_chip_attach failed!\n"); 3991 bus->ci = NULL; 3992 goto fail; 3993 } 3994 3995 /* Pick up the SDIO core info struct from chip.c */ 3996 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 3997 if (!bus->sdio_core) 3998 goto fail; 3999 4000 /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */ 4001 sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON); 4002 if (!sdiodev->cc_core) 4003 goto fail; 4004 4005 sdiodev->settings = brcmf_get_module_param(sdiodev->dev, 4006 BRCMF_BUSTYPE_SDIO, 4007 bus->ci->chip, 4008 bus->ci->chiprev); 4009 if (IS_ERR_OR_NULL(sdiodev->settings)) { 4010 brcmf_err("Failed to get device parameters\n"); 4011 ret = PTR_ERR_OR_ZERO(sdiodev->settings); 4012 goto fail; 4013 } 4014 /* platform specific configuration: 4015 * alignments must be at least 4 bytes for ADMA 4016 */ 4017 bus->head_align = ALIGNMENT; 4018 bus->sgentry_align = ALIGNMENT; 4019 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT) 4020 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align; 4021 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT) 4022 bus->sgentry_align = 4023 sdiodev->settings->bus.sdio.sd_sgentry_align; 4024 4025 /* allocate scatter-gather table. sg support 4026 * will be disabled upon allocation failure. 4027 */ 4028 brcmf_sdiod_sgtable_alloc(sdiodev); 4029 4030 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ 4031 * is true or when platform data OOB irq is true). 4032 */ 4033 if (IS_ENABLED(CONFIG_PM_SLEEP) && 4034 (sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) && 4035 ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) || 4036 (sdiodev->settings->bus.sdio.oob_irq_supported))) 4037 sdiodev->bus_if->wowl_supported = true; 4038 4039 if (brcmf_sdio_kso_init(bus)) { 4040 brcmf_err("error enabling KSO\n"); 4041 goto fail; 4042 } 4043 4044 if (sdiodev->settings->bus.sdio.drive_strength) 4045 drivestrength = sdiodev->settings->bus.sdio.drive_strength; 4046 else 4047 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; 4048 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength); 4049 4050 /* Set card control so an SDIO card reset does a WLAN backplane reset */ 4051 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err); 4052 if (err) 4053 goto fail; 4054 4055 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; 4056 4057 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); 4058 if (err) 4059 goto fail; 4060 4061 /* set PMUControl so a backplane reset does PMU state reload */ 4062 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol); 4063 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err); 4064 if (err) 4065 goto fail; 4066 4067 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); 4068 4069 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err); 4070 if (err) 4071 goto fail; 4072 4073 sdio_release_host(sdiodev->func1); 4074 4075 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); 4076 4077 /* allocate header buffer */ 4078 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); 4079 if (!bus->hdrbuf) 4080 return -ENOMEM; 4081 /* Locate an appropriately-aligned portion of hdrbuf */ 4082 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], 4083 bus->head_align); 4084 4085 /* Set the poll and/or interrupt flags */ 4086 bus->intr = true; 4087 bus->poll = false; 4088 if (bus->poll) 4089 bus->pollrate = 1; 4090 4091 return 0; 4092 4093 fail: 4094 sdio_release_host(sdiodev->func1); 4095 return ret; 4096 } 4097 4098 static int 4099 brcmf_sdio_watchdog_thread(void *data) 4100 { 4101 struct brcmf_sdio *bus = (struct brcmf_sdio *)data; 4102 int wait; 4103 4104 allow_signal(SIGTERM); 4105 /* Run until signal received */ 4106 brcmf_sdiod_freezer_count(bus->sdiodev); 4107 while (1) { 4108 if (kthread_should_stop()) 4109 break; 4110 brcmf_sdiod_freezer_uncount(bus->sdiodev); 4111 wait = wait_for_completion_interruptible(&bus->watchdog_wait); 4112 brcmf_sdiod_freezer_count(bus->sdiodev); 4113 brcmf_sdiod_try_freeze(bus->sdiodev); 4114 if (!wait) { 4115 brcmf_sdio_bus_watchdog(bus); 4116 /* Count the tick for reference */ 4117 bus->sdcnt.tickcnt++; 4118 reinit_completion(&bus->watchdog_wait); 4119 } else 4120 break; 4121 } 4122 return 0; 4123 } 4124 4125 static void 4126 brcmf_sdio_watchdog(struct timer_list *t) 4127 { 4128 struct brcmf_sdio *bus = timer_container_of(bus, t, timer); 4129 4130 if (bus->watchdog_tsk) { 4131 complete(&bus->watchdog_wait); 4132 /* Reschedule the watchdog */ 4133 if (bus->wd_active) 4134 mod_timer(&bus->timer, 4135 jiffies + BRCMF_WD_POLL); 4136 } 4137 } 4138 4139 static int brcmf_sdio_get_blob(struct device *dev, const struct firmware **fw, 4140 enum brcmf_blob_type type) 4141 { 4142 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4143 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 4144 4145 switch (type) { 4146 case BRCMF_BLOB_CLM: 4147 *fw = sdiodev->clm_fw; 4148 sdiodev->clm_fw = NULL; 4149 break; 4150 default: 4151 return -ENOENT; 4152 } 4153 4154 if (!*fw) 4155 return -ENOENT; 4156 4157 return 0; 4158 } 4159 4160 static int brcmf_sdio_bus_reset(struct device *dev) 4161 { 4162 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4163 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 4164 4165 brcmf_dbg(SDIO, "Enter\n"); 4166 4167 /* start by unregistering irqs */ 4168 brcmf_sdiod_intr_unregister(sdiodev); 4169 4170 brcmf_sdiod_remove(sdiodev); 4171 4172 /* reset the adapter */ 4173 sdio_claim_host(sdiodev->func1); 4174 mmc_hw_reset(sdiodev->func1->card); 4175 sdio_release_host(sdiodev->func1); 4176 4177 brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_DOWN); 4178 return 0; 4179 } 4180 4181 static void brcmf_sdio_bus_remove(struct device *dev) 4182 { 4183 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4184 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio; 4185 4186 device_release_driver(&sdiod->func2->dev); 4187 device_release_driver(&sdiod->func1->dev); 4188 } 4189 4190 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = { 4191 .stop = brcmf_sdio_bus_stop, 4192 .preinit = brcmf_sdio_bus_preinit, 4193 .txdata = brcmf_sdio_bus_txdata, 4194 .txctl = brcmf_sdio_bus_txctl, 4195 .rxctl = brcmf_sdio_bus_rxctl, 4196 .gettxq = brcmf_sdio_bus_gettxq, 4197 .wowl_config = brcmf_sdio_wowl_config, 4198 .get_ramsize = brcmf_sdio_bus_get_ramsize, 4199 .get_memdump = brcmf_sdio_bus_get_memdump, 4200 .get_blob = brcmf_sdio_get_blob, 4201 .debugfs_create = brcmf_sdio_debugfs_create, 4202 .reset = brcmf_sdio_bus_reset, 4203 .remove = brcmf_sdio_bus_remove, 4204 }; 4205 4206 #define BRCMF_SDIO_FW_CODE 0 4207 #define BRCMF_SDIO_FW_NVRAM 1 4208 #define BRCMF_SDIO_FW_CLM 2 4209 4210 static void brcmf_sdio_firmware_callback(struct device *dev, int err, 4211 struct brcmf_fw_request *fwreq) 4212 { 4213 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4214 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio; 4215 struct brcmf_sdio *bus = sdiod->bus; 4216 struct brcmf_core *core = bus->sdio_core; 4217 const struct firmware *code; 4218 void *nvram; 4219 u32 nvram_len; 4220 u8 saveclk, bpreq; 4221 u8 devctl; 4222 4223 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err); 4224 4225 if (err) 4226 goto fail; 4227 4228 code = fwreq->items[BRCMF_SDIO_FW_CODE].binary; 4229 nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data; 4230 nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len; 4231 sdiod->clm_fw = fwreq->items[BRCMF_SDIO_FW_CLM].binary; 4232 kfree(fwreq); 4233 4234 /* try to download image and nvram to the dongle */ 4235 bus->alp_only = true; 4236 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); 4237 if (err) 4238 goto fail; 4239 bus->alp_only = false; 4240 4241 /* Start the watchdog timer */ 4242 bus->sdcnt.tickcnt = 0; 4243 brcmf_sdio_wd_timer(bus, true); 4244 4245 sdio_claim_host(sdiod->func1); 4246 4247 /* Make sure backplane clock is on, needed to generate F2 interrupt */ 4248 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4249 if (bus->clkstate != CLK_AVAIL) 4250 goto release; 4251 4252 /* Force clocks on backplane to be sure F2 interrupt propagates */ 4253 saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err); 4254 if (!err) { 4255 bpreq = saveclk; 4256 bpreq |= brcmf_chip_is_ulp(bus->ci) ? 4257 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT; 4258 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4259 bpreq, &err); 4260 } 4261 if (err) { 4262 brcmf_err("Failed to force clock for F2: err %d\n", err); 4263 goto release; 4264 } 4265 4266 /* Enable function 2 (frame transfers) */ 4267 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata), 4268 SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL); 4269 4270 err = sdio_enable_func(sdiod->func2); 4271 4272 brcmf_dbg(INFO, "enable F2: err=%d\n", err); 4273 4274 /* If F2 successfully enabled, set core and enable interrupts */ 4275 if (!err) { 4276 /* Set up the interrupt mask and enable interrupts */ 4277 bus->hostintmask = HOSTINTMASK; 4278 brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask), 4279 bus->hostintmask, NULL); 4280 4281 switch (sdiod->func1->device) { 4282 case SDIO_DEVICE_ID_BROADCOM_43751: 4283 case SDIO_DEVICE_ID_BROADCOM_43752: 4284 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373: 4285 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4286 CY_4373_F2_WATERMARK); 4287 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4288 CY_4373_F2_WATERMARK, &err); 4289 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4290 &err); 4291 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4292 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4293 &err); 4294 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4295 CY_4373_F1_MESBUSYCTRL, &err); 4296 break; 4297 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012: 4298 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4299 CY_43012_F2_WATERMARK); 4300 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4301 CY_43012_F2_WATERMARK, &err); 4302 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4303 &err); 4304 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4305 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4306 &err); 4307 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4308 CY_43012_MESBUSYCTRL, &err); 4309 break; 4310 case SDIO_DEVICE_ID_BROADCOM_4329: 4311 case SDIO_DEVICE_ID_BROADCOM_4339: 4312 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4313 CY_4339_F2_WATERMARK); 4314 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4315 CY_4339_F2_WATERMARK, &err); 4316 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4317 &err); 4318 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4319 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4320 &err); 4321 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4322 CY_4339_MESBUSYCTRL, &err); 4323 break; 4324 case SDIO_DEVICE_ID_BROADCOM_43455: 4325 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4326 CY_43455_F2_WATERMARK); 4327 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4328 CY_43455_F2_WATERMARK, &err); 4329 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4330 &err); 4331 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4332 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4333 &err); 4334 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4335 CY_43455_MESBUSYCTRL, &err); 4336 break; 4337 case SDIO_DEVICE_ID_BROADCOM_4359: 4338 case SDIO_DEVICE_ID_BROADCOM_4354: 4339 case SDIO_DEVICE_ID_BROADCOM_4356: 4340 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4341 CY_435X_F2_WATERMARK); 4342 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4343 CY_435X_F2_WATERMARK, &err); 4344 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4345 &err); 4346 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4347 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4348 &err); 4349 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4350 CY_435X_F1_MESBUSYCTRL, &err); 4351 break; 4352 default: 4353 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4354 DEFAULT_F2_WATERMARK, &err); 4355 break; 4356 } 4357 } else { 4358 /* Disable F2 again */ 4359 sdio_disable_func(sdiod->func2); 4360 goto checkdied; 4361 } 4362 4363 if (brcmf_chip_sr_capable(bus->ci)) { 4364 brcmf_sdio_sr_init(bus); 4365 } else { 4366 /* Restore previous clock setting */ 4367 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4368 saveclk, &err); 4369 } 4370 4371 if (err == 0) { 4372 /* Assign bus interface call back */ 4373 sdiod->bus_if->dev = sdiod->dev; 4374 sdiod->bus_if->ops = &brcmf_sdio_bus_ops; 4375 sdiod->bus_if->chip = bus->ci->chip; 4376 sdiod->bus_if->chiprev = bus->ci->chiprev; 4377 4378 /* Allow full data communication using DPC from now on. */ 4379 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 4380 4381 err = brcmf_sdiod_intr_register(sdiod); 4382 if (err != 0) 4383 brcmf_err("intr register failed:%d\n", err); 4384 } 4385 4386 /* If we didn't come up, turn off backplane clock */ 4387 if (err != 0) { 4388 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4389 goto checkdied; 4390 } 4391 4392 sdio_release_host(sdiod->func1); 4393 4394 err = brcmf_alloc(sdiod->dev, sdiod->settings); 4395 if (err) { 4396 brcmf_err("brcmf_alloc failed\n"); 4397 goto claim; 4398 } 4399 4400 /* Attach to the common layer, reserve hdr space */ 4401 err = brcmf_attach(sdiod->dev); 4402 if (err != 0) { 4403 brcmf_err("brcmf_attach failed\n"); 4404 goto free; 4405 } 4406 4407 /* ready */ 4408 return; 4409 4410 free: 4411 brcmf_free(sdiod->dev); 4412 claim: 4413 sdio_claim_host(sdiod->func1); 4414 checkdied: 4415 brcmf_sdio_checkdied(bus); 4416 release: 4417 sdio_release_host(sdiod->func1); 4418 fail: 4419 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); 4420 device_release_driver(&sdiod->func2->dev); 4421 device_release_driver(dev); 4422 } 4423 4424 static struct brcmf_fw_request * 4425 brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus) 4426 { 4427 struct brcmf_fw_request *fwreq; 4428 struct brcmf_fw_name fwnames[] = { 4429 { ".bin", bus->sdiodev->fw_name }, 4430 { ".txt", bus->sdiodev->nvram_name }, 4431 { ".clm_blob", bus->sdiodev->clm_name }, 4432 }; 4433 4434 fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev, 4435 brcmf_sdio_fwnames, 4436 ARRAY_SIZE(brcmf_sdio_fwnames), 4437 fwnames, ARRAY_SIZE(fwnames)); 4438 if (!fwreq) 4439 return NULL; 4440 4441 fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 4442 fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 4443 fwreq->items[BRCMF_SDIO_FW_CLM].type = BRCMF_FW_TYPE_BINARY; 4444 fwreq->items[BRCMF_SDIO_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL; 4445 fwreq->board_types[0] = bus->sdiodev->settings->board_type; 4446 4447 return fwreq; 4448 } 4449 4450 int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) 4451 { 4452 int ret; 4453 struct brcmf_sdio *bus; 4454 struct workqueue_struct *wq; 4455 struct brcmf_fw_request *fwreq; 4456 4457 brcmf_dbg(TRACE, "Enter\n"); 4458 4459 /* Allocate private bus interface state */ 4460 bus = kzalloc_obj(*bus, GFP_ATOMIC); 4461 if (!bus) { 4462 ret = -ENOMEM; 4463 goto fail; 4464 } 4465 4466 bus->sdiodev = sdiodev; 4467 sdiodev->bus = bus; 4468 skb_queue_head_init(&bus->glom); 4469 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); 4470 bus->txbound = BRCMF_TXBOUND; 4471 bus->rxbound = BRCMF_RXBOUND; 4472 bus->txminmax = BRCMF_TXMINMAX; 4473 bus->tx_seq = SDPCM_SEQ_WRAP - 1; 4474 4475 /* single-threaded workqueue */ 4476 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM | WQ_HIGHPRI, 4477 dev_name(&sdiodev->func1->dev)); 4478 if (!wq) { 4479 brcmf_err("insufficient memory to create txworkqueue\n"); 4480 ret = -ENOMEM; 4481 goto fail; 4482 } 4483 brcmf_sdiod_freezer_count(sdiodev); 4484 bus->brcmf_wq = wq; 4485 4486 /* attempt to attach to the dongle */ 4487 ret = brcmf_sdio_probe_attach(bus); 4488 if (ret < 0) { 4489 brcmf_err("brcmf_sdio_probe_attach failed\n"); 4490 goto fail; 4491 } 4492 4493 spin_lock_init(&bus->rxctl_lock); 4494 spin_lock_init(&bus->txq_lock); 4495 init_waitqueue_head(&bus->ctrl_wait); 4496 init_waitqueue_head(&bus->dcmd_resp_wait); 4497 4498 /* Set up the watchdog timer */ 4499 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0); 4500 /* Initialize watchdog thread */ 4501 init_completion(&bus->watchdog_wait); 4502 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, 4503 bus, "brcmf_wdog/%s", 4504 dev_name(&sdiodev->func1->dev)); 4505 if (IS_ERR(bus->watchdog_tsk)) { 4506 pr_warn("brcmf_watchdog thread failed to start\n"); 4507 bus->watchdog_tsk = NULL; 4508 } 4509 /* Initialize DPC thread */ 4510 bus->dpc_triggered = false; 4511 bus->dpc_running = false; 4512 4513 /* default sdio bus header length for tx packet */ 4514 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 4515 4516 /* Query the F2 block size, set roundup accordingly */ 4517 bus->blocksize = bus->sdiodev->func2->cur_blksize; 4518 bus->roundup = min(max_roundup, bus->blocksize); 4519 4520 sdio_claim_host(bus->sdiodev->func1); 4521 4522 /* Disable F2 to clear any intermediate frame state on the dongle */ 4523 sdio_disable_func(bus->sdiodev->func2); 4524 4525 bus->rxflow = false; 4526 4527 /* Done with backplane-dependent accesses, can drop clock... */ 4528 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 4529 4530 sdio_release_host(bus->sdiodev->func1); 4531 4532 /* ...and initialize clock/power states */ 4533 bus->clkstate = CLK_SDONLY; 4534 bus->idletime = BRCMF_IDLE_INTERVAL; 4535 bus->idleclock = BRCMF_IDLE_ACTIVE; 4536 4537 /* SR state */ 4538 bus->sr_enabled = false; 4539 4540 brcmf_dbg(INFO, "completed!!\n"); 4541 4542 fwreq = brcmf_sdio_prepare_fw_request(bus); 4543 if (!fwreq) { 4544 ret = -ENOMEM; 4545 goto fail; 4546 } 4547 4548 ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq, 4549 brcmf_sdio_firmware_callback); 4550 if (ret != 0) { 4551 brcmf_err("async firmware request failed: %d\n", ret); 4552 kfree(fwreq); 4553 goto fail; 4554 } 4555 4556 return 0; 4557 4558 fail: 4559 brcmf_sdio_remove(bus); 4560 sdiodev->bus = NULL; 4561 return ret; 4562 } 4563 4564 void brcmf_sdio_cancel_datawork(struct brcmf_sdio *bus) 4565 { 4566 if (bus) 4567 cancel_work_sync(&bus->datawork); 4568 } 4569 4570 /* Detach and free everything */ 4571 void brcmf_sdio_remove(struct brcmf_sdio *bus) 4572 { 4573 brcmf_dbg(TRACE, "Enter\n"); 4574 4575 if (bus) { 4576 /* Stop watchdog task */ 4577 if (bus->watchdog_tsk) { 4578 get_task_struct(bus->watchdog_tsk); 4579 send_sig(SIGTERM, bus->watchdog_tsk, 1); 4580 kthread_stop_put(bus->watchdog_tsk); 4581 bus->watchdog_tsk = NULL; 4582 } 4583 4584 /* De-register interrupt handler */ 4585 brcmf_sdiod_intr_unregister(bus->sdiodev); 4586 4587 brcmf_detach(bus->sdiodev->dev); 4588 brcmf_free(bus->sdiodev->dev); 4589 4590 cancel_work_sync(&bus->datawork); 4591 if (bus->brcmf_wq) 4592 destroy_workqueue(bus->brcmf_wq); 4593 4594 if (bus->ci) { 4595 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 4596 sdio_claim_host(bus->sdiodev->func1); 4597 brcmf_sdio_wd_timer(bus, false); 4598 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4599 /* Leave the device in state where it is 4600 * 'passive'. This is done by resetting all 4601 * necessary cores. 4602 */ 4603 msleep(20); 4604 brcmf_chip_set_passive(bus->ci); 4605 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4606 sdio_release_host(bus->sdiodev->func1); 4607 } 4608 brcmf_chip_detach(bus->ci); 4609 } 4610 if (bus->sdiodev->settings) 4611 brcmf_release_module_param(bus->sdiodev->settings); 4612 4613 release_firmware(bus->sdiodev->clm_fw); 4614 bus->sdiodev->clm_fw = NULL; 4615 kfree(bus->rxbuf); 4616 kfree(bus->hdrbuf); 4617 kfree(bus); 4618 } 4619 4620 brcmf_dbg(TRACE, "Disconnected\n"); 4621 } 4622 4623 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active) 4624 { 4625 /* Totally stop the timer */ 4626 if (!active && bus->wd_active) { 4627 timer_delete_sync(&bus->timer); 4628 bus->wd_active = false; 4629 return; 4630 } 4631 4632 /* don't start the wd until fw is loaded */ 4633 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) 4634 return; 4635 4636 if (active) { 4637 if (!bus->wd_active) { 4638 /* Create timer again when watchdog period is 4639 dynamically changed or in the first instance 4640 */ 4641 bus->timer.expires = jiffies + BRCMF_WD_POLL; 4642 add_timer(&bus->timer); 4643 bus->wd_active = true; 4644 } else { 4645 /* Re arm the timer, at last watchdog period */ 4646 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL); 4647 } 4648 } 4649 } 4650 4651 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) 4652 { 4653 int ret; 4654 4655 sdio_claim_host(bus->sdiodev->func1); 4656 ret = brcmf_sdio_bus_sleep(bus, sleep, false); 4657 sdio_release_host(bus->sdiodev->func1); 4658 4659 return ret; 4660 } 4661