1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2014 Broadcom Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/firmware.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/bcma/bcma.h> 14 #include <linux/sched.h> 15 #include <linux/sched/signal.h> 16 #include <linux/kthread.h> 17 #include <linux/io.h> 18 #include <linux/random.h> 19 #include <asm/unaligned.h> 20 21 #include <soc.h> 22 #include <chipcommon.h> 23 #include <brcmu_utils.h> 24 #include <brcmu_wifi.h> 25 #include <brcm_hw_ids.h> 26 27 /* Custom brcmf_err() that takes bus arg and passes it further */ 28 #define brcmf_err(bus, fmt, ...) \ 29 do { \ 30 if (IS_ENABLED(CONFIG_BRCMDBG) || \ 31 IS_ENABLED(CONFIG_BRCM_TRACING) || \ 32 net_ratelimit()) \ 33 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \ 34 } while (0) 35 36 #include "debug.h" 37 #include "bus.h" 38 #include "commonring.h" 39 #include "msgbuf.h" 40 #include "pcie.h" 41 #include "firmware.h" 42 #include "chip.h" 43 #include "core.h" 44 #include "common.h" 45 46 47 enum brcmf_pcie_state { 48 BRCMFMAC_PCIE_STATE_DOWN, 49 BRCMFMAC_PCIE_STATE_UP 50 }; 51 52 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie"); 53 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie"); 54 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie"); 55 BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie"); 56 BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie"); 57 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie"); 58 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie"); 59 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie"); 60 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie"); 61 BRCMF_FW_DEF(4359C, "brcmfmac4359c-pcie"); 62 BRCMF_FW_CLM_DEF(4364B2, "brcmfmac4364b2-pcie"); 63 BRCMF_FW_CLM_DEF(4364B3, "brcmfmac4364b3-pcie"); 64 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie"); 65 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie"); 66 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie"); 67 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie"); 68 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie"); 69 BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie"); 70 BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie"); 71 BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie"); 72 BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie"); 73 74 /* firmware config files */ 75 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt"); 76 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt"); 77 78 /* per-board firmware binaries */ 79 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin"); 80 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob"); 81 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txcap_blob"); 82 83 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 84 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 85 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C), 86 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 87 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 88 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C), 89 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x000007FF, 4355), 90 BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0xFFFFF800, 4355C1), /* rev ID 12/C2 seen */ 91 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 92 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 93 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 94 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 95 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 96 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0x000001FF, 4359), 97 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFE00, 4359C), 98 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0x0000000F, 4364B2), /* 3 */ 99 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFF0, 4364B3), /* 4 */ 100 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B), 101 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C), 102 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 103 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 104 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), 105 BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C), 106 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 107 BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */ 108 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */ 109 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */ 110 BRCMF_FW_ENTRY(BRCM_CC_4387_CHIP_ID, 0xFFFFFFFF, 4387C2), /* revision ID 7 */ 111 }; 112 113 #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */ 114 115 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 116 117 /* backplane addres space accessed by BAR0 */ 118 #define BRCMF_PCIE_BAR0_WINDOW 0x80 119 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 120 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 121 122 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 123 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 124 125 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 126 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 127 128 #define BRCMF_PCIE_REG_INTSTATUS 0x90 129 #define BRCMF_PCIE_REG_INTMASK 0x94 130 #define BRCMF_PCIE_REG_SBMBX 0x98 131 132 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 133 134 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 135 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 136 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 137 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 138 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 139 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140 140 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144 141 142 #define BRCMF_PCIE_64_PCIE2REG_INTMASK 0xC14 143 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT 0xC30 144 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK 0xC34 145 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0 0xA20 146 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1 0xA24 147 148 #define BRCMF_PCIE2_INTA 0x01 149 #define BRCMF_PCIE2_INTB 0x02 150 151 #define BRCMF_PCIE_INT_0 0x01 152 #define BRCMF_PCIE_INT_1 0x02 153 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 154 BRCMF_PCIE_INT_1) 155 156 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 157 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 158 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 159 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 160 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 161 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 162 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 163 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 164 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 165 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 166 167 #define BRCMF_PCIE_MB_INT_FN0 (BRCMF_PCIE_MB_INT_FN0_0 | \ 168 BRCMF_PCIE_MB_INT_FN0_1) 169 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 170 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 171 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 172 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 173 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 174 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 175 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 176 BRCMF_PCIE_MB_INT_D2H3_DB1) 177 178 #define BRCMF_PCIE_64_MB_INT_D2H0_DB0 0x1 179 #define BRCMF_PCIE_64_MB_INT_D2H0_DB1 0x2 180 #define BRCMF_PCIE_64_MB_INT_D2H1_DB0 0x4 181 #define BRCMF_PCIE_64_MB_INT_D2H1_DB1 0x8 182 #define BRCMF_PCIE_64_MB_INT_D2H2_DB0 0x10 183 #define BRCMF_PCIE_64_MB_INT_D2H2_DB1 0x20 184 #define BRCMF_PCIE_64_MB_INT_D2H3_DB0 0x40 185 #define BRCMF_PCIE_64_MB_INT_D2H3_DB1 0x80 186 #define BRCMF_PCIE_64_MB_INT_D2H4_DB0 0x100 187 #define BRCMF_PCIE_64_MB_INT_D2H4_DB1 0x200 188 #define BRCMF_PCIE_64_MB_INT_D2H5_DB0 0x400 189 #define BRCMF_PCIE_64_MB_INT_D2H5_DB1 0x800 190 #define BRCMF_PCIE_64_MB_INT_D2H6_DB0 0x1000 191 #define BRCMF_PCIE_64_MB_INT_D2H6_DB1 0x2000 192 #define BRCMF_PCIE_64_MB_INT_D2H7_DB0 0x4000 193 #define BRCMF_PCIE_64_MB_INT_D2H7_DB1 0x8000 194 195 #define BRCMF_PCIE_64_MB_INT_D2H_DB (BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \ 196 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \ 197 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \ 198 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \ 199 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \ 200 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \ 201 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \ 202 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \ 203 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \ 204 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \ 205 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \ 206 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \ 207 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \ 208 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \ 209 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \ 210 BRCMF_PCIE_64_MB_INT_D2H7_DB1) 211 212 #define BRCMF_PCIE_SHARED_VERSION_7 7 213 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 214 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7 215 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 216 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 217 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 218 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000 219 220 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 221 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 222 223 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 224 #define BRCMF_SHARED_RING_BASE_OFFSET 52 225 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 226 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 227 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 228 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 229 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 230 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 231 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 232 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 233 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 234 235 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 236 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 237 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 238 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 239 240 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 241 #define BRCMF_RING_MAX_ITEM_OFFSET 4 242 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 243 #define BRCMF_RING_MEM_SZ 16 244 #define BRCMF_RING_STATE_SZ 8 245 246 #define BRCMF_DEF_MAX_RXBUFPOST 255 247 248 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 249 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 250 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 251 252 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 253 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 254 255 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 256 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 257 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 258 #define BRCMF_D2H_DEV_FWHALT 0x10000000 259 260 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 261 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 262 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 263 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 264 265 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 266 267 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 268 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 269 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 270 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 271 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 272 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 273 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 274 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 275 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 276 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 277 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 278 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 279 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 280 281 /* Magic number at a magic location to find RAM size */ 282 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 283 #define BRCMF_RAMSIZE_OFFSET 0x6c 284 285 286 struct brcmf_pcie_console { 287 u32 base_addr; 288 u32 buf_addr; 289 u32 bufsize; 290 u32 read_idx; 291 u8 log_str[256]; 292 u8 log_idx; 293 }; 294 295 struct brcmf_pcie_shared_info { 296 u32 tcm_base_address; 297 u32 flags; 298 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 299 struct brcmf_pcie_ringbuf *flowrings; 300 u16 max_rxbufpost; 301 u16 max_flowrings; 302 u16 max_submissionrings; 303 u16 max_completionrings; 304 u32 rx_dataoffset; 305 u32 htod_mb_data_addr; 306 u32 dtoh_mb_data_addr; 307 u32 ring_info_addr; 308 struct brcmf_pcie_console console; 309 void *scratch; 310 dma_addr_t scratch_dmahandle; 311 void *ringupd; 312 dma_addr_t ringupd_dmahandle; 313 u8 version; 314 }; 315 316 struct brcmf_pcie_core_info { 317 u32 base; 318 u32 wrapbase; 319 }; 320 321 #define BRCMF_OTP_MAX_PARAM_LEN 16 322 323 struct brcmf_otp_params { 324 char module[BRCMF_OTP_MAX_PARAM_LEN]; 325 char vendor[BRCMF_OTP_MAX_PARAM_LEN]; 326 char version[BRCMF_OTP_MAX_PARAM_LEN]; 327 bool valid; 328 }; 329 330 struct brcmf_pciedev_info { 331 enum brcmf_pcie_state state; 332 bool in_irq; 333 struct pci_dev *pdev; 334 char fw_name[BRCMF_FW_NAME_LEN]; 335 char nvram_name[BRCMF_FW_NAME_LEN]; 336 char clm_name[BRCMF_FW_NAME_LEN]; 337 char txcap_name[BRCMF_FW_NAME_LEN]; 338 const struct firmware *clm_fw; 339 const struct firmware *txcap_fw; 340 const struct brcmf_pcie_reginfo *reginfo; 341 void __iomem *regs; 342 void __iomem *tcm; 343 u32 ram_base; 344 u32 ram_size; 345 struct brcmf_chip *ci; 346 u32 coreid; 347 struct brcmf_pcie_shared_info shared; 348 wait_queue_head_t mbdata_resp_wait; 349 bool mbdata_completed; 350 bool irq_allocated; 351 bool wowl_enabled; 352 u8 dma_idx_sz; 353 void *idxbuf; 354 u32 idxbuf_sz; 355 dma_addr_t idxbuf_dmahandle; 356 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 357 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 358 u16 value); 359 struct brcmf_mp_device *settings; 360 struct brcmf_otp_params otp; 361 #ifdef DEBUG 362 u32 console_interval; 363 bool console_active; 364 struct timer_list timer; 365 #endif 366 }; 367 368 struct brcmf_pcie_ringbuf { 369 struct brcmf_commonring commonring; 370 dma_addr_t dma_handle; 371 u32 w_idx_addr; 372 u32 r_idx_addr; 373 struct brcmf_pciedev_info *devinfo; 374 u8 id; 375 }; 376 377 /** 378 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info 379 * 380 * @ringmem: dongle memory pointer to ring memory location 381 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers 382 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers 383 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers 384 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers 385 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers 386 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers 387 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers 388 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers 389 * @max_flowrings: maximum number of tx flow rings supported. 390 * @max_submissionrings: maximum number of submission rings(h2d) supported. 391 * @max_completionrings: maximum number of completion rings(d2h) supported. 392 */ 393 struct brcmf_pcie_dhi_ringinfo { 394 __le32 ringmem; 395 __le32 h2d_w_idx_ptr; 396 __le32 h2d_r_idx_ptr; 397 __le32 d2h_w_idx_ptr; 398 __le32 d2h_r_idx_ptr; 399 struct msgbuf_buf_addr h2d_w_idx_hostaddr; 400 struct msgbuf_buf_addr h2d_r_idx_hostaddr; 401 struct msgbuf_buf_addr d2h_w_idx_hostaddr; 402 struct msgbuf_buf_addr d2h_r_idx_hostaddr; 403 __le16 max_flowrings; 404 __le16 max_submissionrings; 405 __le16 max_completionrings; 406 }; 407 408 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 409 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 410 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 411 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 412 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 413 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 414 }; 415 416 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = { 417 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 418 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 419 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 420 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7, 421 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7 422 }; 423 424 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 425 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 426 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 427 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 428 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 429 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 430 }; 431 432 struct brcmf_pcie_reginfo { 433 u32 intmask; 434 u32 mailboxint; 435 u32 mailboxmask; 436 u32 h2d_mailbox_0; 437 u32 h2d_mailbox_1; 438 u32 int_d2h_db; 439 u32 int_fn0; 440 }; 441 442 static const struct brcmf_pcie_reginfo brcmf_reginfo_default = { 443 .intmask = BRCMF_PCIE_PCIE2REG_INTMASK, 444 .mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT, 445 .mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 446 .h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 447 .h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 448 .int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB, 449 .int_fn0 = BRCMF_PCIE_MB_INT_FN0, 450 }; 451 452 static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = { 453 .intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK, 454 .mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT, 455 .mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK, 456 .h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0, 457 .h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1, 458 .int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB, 459 .int_fn0 = 0, 460 }; 461 462 static void brcmf_pcie_setup(struct device *dev, int ret, 463 struct brcmf_fw_request *fwreq); 464 static struct brcmf_fw_request * 465 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo); 466 static void 467 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active); 468 static void brcmf_pcie_debugfs_create(struct device *dev); 469 470 static u16 471 brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 472 { 473 void __iomem *address = devinfo->regs + reg_offset; 474 475 return ioread16(address); 476 } 477 478 static u32 479 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 480 { 481 void __iomem *address = devinfo->regs + reg_offset; 482 483 return (ioread32(address)); 484 } 485 486 487 static void 488 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 489 u32 value) 490 { 491 void __iomem *address = devinfo->regs + reg_offset; 492 493 iowrite32(value, address); 494 } 495 496 497 static u8 498 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 499 { 500 void __iomem *address = devinfo->tcm + mem_offset; 501 502 return (ioread8(address)); 503 } 504 505 506 static u16 507 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 508 { 509 void __iomem *address = devinfo->tcm + mem_offset; 510 511 return (ioread16(address)); 512 } 513 514 515 static void 516 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 517 u16 value) 518 { 519 void __iomem *address = devinfo->tcm + mem_offset; 520 521 iowrite16(value, address); 522 } 523 524 525 static u16 526 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 527 { 528 u16 *address = devinfo->idxbuf + mem_offset; 529 530 return (*(address)); 531 } 532 533 534 static void 535 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 536 u16 value) 537 { 538 u16 *address = devinfo->idxbuf + mem_offset; 539 540 *(address) = value; 541 } 542 543 544 static u32 545 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 546 { 547 void __iomem *address = devinfo->tcm + mem_offset; 548 549 return (ioread32(address)); 550 } 551 552 553 static void 554 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 555 u32 value) 556 { 557 void __iomem *address = devinfo->tcm + mem_offset; 558 559 iowrite32(value, address); 560 } 561 562 563 static u32 564 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 565 { 566 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 567 568 return (ioread32(addr)); 569 } 570 571 572 static void 573 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 574 u32 value) 575 { 576 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 577 578 iowrite32(value, addr); 579 } 580 581 582 static void 583 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 584 void *dstaddr, u32 len) 585 { 586 void __iomem *address = devinfo->tcm + mem_offset; 587 __le32 *dst32; 588 __le16 *dst16; 589 u8 *dst8; 590 591 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 592 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 593 dst8 = (u8 *)dstaddr; 594 while (len) { 595 *dst8 = ioread8(address); 596 address++; 597 dst8++; 598 len--; 599 } 600 } else { 601 len = len / 2; 602 dst16 = (__le16 *)dstaddr; 603 while (len) { 604 *dst16 = cpu_to_le16(ioread16(address)); 605 address += 2; 606 dst16++; 607 len--; 608 } 609 } 610 } else { 611 len = len / 4; 612 dst32 = (__le32 *)dstaddr; 613 while (len) { 614 *dst32 = cpu_to_le32(ioread32(address)); 615 address += 4; 616 dst32++; 617 len--; 618 } 619 } 620 } 621 622 623 #define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \ 624 CHIPCREGOFFS(reg)) 625 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 626 CHIPCREGOFFS(reg), value) 627 628 629 static void 630 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 631 { 632 const struct pci_dev *pdev = devinfo->pdev; 633 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 634 struct brcmf_core *core; 635 u32 bar0_win; 636 637 core = brcmf_chip_get_core(devinfo->ci, coreid); 638 if (core) { 639 bar0_win = core->base; 640 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 641 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 642 &bar0_win) == 0) { 643 if (bar0_win != core->base) { 644 bar0_win = core->base; 645 pci_write_config_dword(pdev, 646 BRCMF_PCIE_BAR0_WINDOW, 647 bar0_win); 648 } 649 } 650 } else { 651 brcmf_err(bus, "Unsupported core selected %x\n", coreid); 652 } 653 } 654 655 656 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 657 { 658 struct brcmf_core *core; 659 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 660 BRCMF_PCIE_CFGREG_PM_CSR, 661 BRCMF_PCIE_CFGREG_MSI_CAP, 662 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 663 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 664 BRCMF_PCIE_CFGREG_MSI_DATA, 665 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 666 BRCMF_PCIE_CFGREG_RBAR_CTRL, 667 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 668 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 669 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 670 u32 i; 671 u32 val; 672 u32 lsc; 673 674 if (!devinfo->ci) 675 return; 676 677 /* Disable ASPM */ 678 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 679 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 680 &lsc); 681 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 682 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 683 val); 684 685 /* Watchdog reset */ 686 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 687 WRITECC32(devinfo, watchdog, 4); 688 msleep(100); 689 690 /* Restore ASPM */ 691 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 692 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 693 lsc); 694 695 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 696 if (core->rev <= 13) { 697 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 698 brcmf_pcie_write_reg32(devinfo, 699 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 700 cfg_offset[i]); 701 val = brcmf_pcie_read_reg32(devinfo, 702 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 703 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 704 cfg_offset[i], val); 705 brcmf_pcie_write_reg32(devinfo, 706 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 707 val); 708 } 709 } 710 } 711 712 713 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 714 { 715 u32 config; 716 717 /* BAR1 window may not be sized properly */ 718 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 719 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 720 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 721 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 722 723 device_wakeup_enable(&devinfo->pdev->dev); 724 } 725 726 727 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 728 { 729 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 730 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 731 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 732 5); 733 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 734 0); 735 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 736 7); 737 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 738 0); 739 } 740 return 0; 741 } 742 743 744 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 745 u32 resetintr) 746 { 747 struct brcmf_core *core; 748 749 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 750 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 751 brcmf_chip_resetcore(core, 0, 0, 0); 752 } 753 754 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 755 return -EIO; 756 return 0; 757 } 758 759 760 static int 761 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 762 { 763 struct brcmf_pcie_shared_info *shared; 764 struct brcmf_core *core; 765 u32 addr; 766 u32 cur_htod_mb_data; 767 u32 i; 768 769 shared = &devinfo->shared; 770 addr = shared->htod_mb_data_addr; 771 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 772 773 if (cur_htod_mb_data != 0) 774 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 775 cur_htod_mb_data); 776 777 i = 0; 778 while (cur_htod_mb_data != 0) { 779 msleep(10); 780 i++; 781 if (i > 100) 782 return -EIO; 783 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 784 } 785 786 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 787 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 788 789 /* Send mailbox interrupt twice as a hardware workaround */ 790 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 791 if (core->rev <= 13) 792 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 793 794 return 0; 795 } 796 797 798 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 799 { 800 struct brcmf_pcie_shared_info *shared; 801 u32 addr; 802 u32 dtoh_mb_data; 803 804 shared = &devinfo->shared; 805 addr = shared->dtoh_mb_data_addr; 806 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 807 808 if (!dtoh_mb_data) 809 return; 810 811 brcmf_pcie_write_tcm32(devinfo, addr, 0); 812 813 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 814 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 815 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 816 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 817 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 818 } 819 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 820 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 821 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 822 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 823 devinfo->mbdata_completed = true; 824 wake_up(&devinfo->mbdata_resp_wait); 825 } 826 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) { 827 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n"); 828 brcmf_fw_crashed(&devinfo->pdev->dev); 829 } 830 } 831 832 833 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 834 { 835 struct brcmf_pcie_shared_info *shared; 836 struct brcmf_pcie_console *console; 837 u32 addr; 838 839 shared = &devinfo->shared; 840 console = &shared->console; 841 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 842 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 843 844 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 845 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 846 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 847 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 848 849 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 850 console->base_addr, console->buf_addr, console->bufsize); 851 } 852 853 /** 854 * brcmf_pcie_bus_console_read - reads firmware messages 855 * 856 * @devinfo: pointer to the device data structure 857 * @error: specifies if error has occurred (prints messages unconditionally) 858 */ 859 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo, 860 bool error) 861 { 862 struct pci_dev *pdev = devinfo->pdev; 863 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 864 struct brcmf_pcie_console *console; 865 u32 addr; 866 u8 ch; 867 u32 newidx; 868 869 if (!error && !BRCMF_FWCON_ON()) 870 return; 871 872 console = &devinfo->shared.console; 873 if (!console->base_addr) 874 return; 875 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 876 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 877 while (newidx != console->read_idx) { 878 addr = console->buf_addr + console->read_idx; 879 ch = brcmf_pcie_read_tcm8(devinfo, addr); 880 console->read_idx++; 881 if (console->read_idx == console->bufsize) 882 console->read_idx = 0; 883 if (ch == '\r') 884 continue; 885 console->log_str[console->log_idx] = ch; 886 console->log_idx++; 887 if ((ch != '\n') && 888 (console->log_idx == (sizeof(console->log_str) - 2))) { 889 ch = '\n'; 890 console->log_str[console->log_idx] = ch; 891 console->log_idx++; 892 } 893 if (ch == '\n') { 894 console->log_str[console->log_idx] = 0; 895 if (error) 896 __brcmf_err(bus, __func__, "CONSOLE: %s", 897 console->log_str); 898 else 899 pr_debug("CONSOLE: %s", console->log_str); 900 console->log_idx = 0; 901 } 902 } 903 } 904 905 906 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 907 { 908 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0); 909 } 910 911 912 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 913 { 914 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 915 devinfo->reginfo->int_d2h_db | 916 devinfo->reginfo->int_fn0); 917 } 918 919 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo) 920 { 921 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1) 922 brcmf_pcie_write_reg32(devinfo, 923 devinfo->reginfo->h2d_mailbox_1, 1); 924 } 925 926 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 927 { 928 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 929 930 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) { 931 brcmf_pcie_intr_disable(devinfo); 932 brcmf_dbg(PCIE, "Enter\n"); 933 return IRQ_WAKE_THREAD; 934 } 935 return IRQ_NONE; 936 } 937 938 939 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 940 { 941 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 942 u32 status; 943 944 devinfo->in_irq = true; 945 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint); 946 brcmf_dbg(PCIE, "Enter %x\n", status); 947 if (status) { 948 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, 949 status); 950 if (status & devinfo->reginfo->int_fn0) 951 brcmf_pcie_handle_mb_data(devinfo); 952 if (status & devinfo->reginfo->int_d2h_db) { 953 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 954 brcmf_proto_msgbuf_rx_trigger( 955 &devinfo->pdev->dev); 956 } 957 } 958 brcmf_pcie_bus_console_read(devinfo, false); 959 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 960 brcmf_pcie_intr_enable(devinfo); 961 devinfo->in_irq = false; 962 return IRQ_HANDLED; 963 } 964 965 966 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 967 { 968 struct pci_dev *pdev = devinfo->pdev; 969 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 970 971 brcmf_pcie_intr_disable(devinfo); 972 973 brcmf_dbg(PCIE, "Enter\n"); 974 975 pci_enable_msi(pdev); 976 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 977 brcmf_pcie_isr_thread, IRQF_SHARED, 978 "brcmf_pcie_intr", devinfo)) { 979 pci_disable_msi(pdev); 980 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq); 981 return -EIO; 982 } 983 devinfo->irq_allocated = true; 984 return 0; 985 } 986 987 988 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 989 { 990 struct pci_dev *pdev = devinfo->pdev; 991 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 992 u32 status; 993 u32 count; 994 995 if (!devinfo->irq_allocated) 996 return; 997 998 brcmf_pcie_intr_disable(devinfo); 999 free_irq(pdev->irq, devinfo); 1000 pci_disable_msi(pdev); 1001 1002 msleep(50); 1003 count = 0; 1004 while ((devinfo->in_irq) && (count < 20)) { 1005 msleep(50); 1006 count++; 1007 } 1008 if (devinfo->in_irq) 1009 brcmf_err(bus, "Still in IRQ (processing) !!!\n"); 1010 1011 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint); 1012 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status); 1013 1014 devinfo->irq_allocated = false; 1015 } 1016 1017 1018 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 1019 { 1020 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1021 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1022 struct brcmf_commonring *commonring = &ring->commonring; 1023 1024 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1025 return -EIO; 1026 1027 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 1028 commonring->w_ptr, ring->id); 1029 1030 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 1031 1032 return 0; 1033 } 1034 1035 1036 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 1037 { 1038 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1039 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1040 struct brcmf_commonring *commonring = &ring->commonring; 1041 1042 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1043 return -EIO; 1044 1045 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 1046 commonring->r_ptr, ring->id); 1047 1048 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 1049 1050 return 0; 1051 } 1052 1053 1054 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 1055 { 1056 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1057 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1058 1059 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1060 return -EIO; 1061 1062 brcmf_dbg(PCIE, "RING !\n"); 1063 /* Any arbitrary value will do, lets use 1 */ 1064 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1); 1065 1066 return 0; 1067 } 1068 1069 1070 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 1071 { 1072 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1073 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1074 struct brcmf_commonring *commonring = &ring->commonring; 1075 1076 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1077 return -EIO; 1078 1079 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 1080 1081 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 1082 commonring->w_ptr, ring->id); 1083 1084 return 0; 1085 } 1086 1087 1088 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 1089 { 1090 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1091 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1092 struct brcmf_commonring *commonring = &ring->commonring; 1093 1094 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1095 return -EIO; 1096 1097 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 1098 1099 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 1100 commonring->r_ptr, ring->id); 1101 1102 return 0; 1103 } 1104 1105 1106 static void * 1107 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 1108 u32 size, u32 tcm_dma_phys_addr, 1109 dma_addr_t *dma_handle) 1110 { 1111 void *ring; 1112 u64 address; 1113 1114 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 1115 GFP_KERNEL); 1116 if (!ring) 1117 return NULL; 1118 1119 address = (u64)*dma_handle; 1120 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 1121 address & 0xffffffff); 1122 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 1123 1124 return (ring); 1125 } 1126 1127 1128 static struct brcmf_pcie_ringbuf * 1129 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 1130 u32 tcm_ring_phys_addr) 1131 { 1132 void *dma_buf; 1133 dma_addr_t dma_handle; 1134 struct brcmf_pcie_ringbuf *ring; 1135 u32 size; 1136 u32 addr; 1137 const u32 *ring_itemsize_array; 1138 1139 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7) 1140 ring_itemsize_array = brcmf_ring_itemsize_pre_v7; 1141 else 1142 ring_itemsize_array = brcmf_ring_itemsize; 1143 1144 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id]; 1145 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 1146 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 1147 &dma_handle); 1148 if (!dma_buf) 1149 return NULL; 1150 1151 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 1152 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 1153 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 1154 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]); 1155 1156 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 1157 if (!ring) { 1158 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 1159 dma_handle); 1160 return NULL; 1161 } 1162 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 1163 ring_itemsize_array[ring_id], dma_buf); 1164 ring->dma_handle = dma_handle; 1165 ring->devinfo = devinfo; 1166 brcmf_commonring_register_cb(&ring->commonring, 1167 brcmf_pcie_ring_mb_ring_bell, 1168 brcmf_pcie_ring_mb_update_rptr, 1169 brcmf_pcie_ring_mb_update_wptr, 1170 brcmf_pcie_ring_mb_write_rptr, 1171 brcmf_pcie_ring_mb_write_wptr, ring); 1172 1173 return (ring); 1174 } 1175 1176 1177 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1178 struct brcmf_pcie_ringbuf *ring) 1179 { 1180 void *dma_buf; 1181 u32 size; 1182 1183 if (!ring) 1184 return; 1185 1186 dma_buf = ring->commonring.buf_addr; 1187 if (dma_buf) { 1188 size = ring->commonring.depth * ring->commonring.item_len; 1189 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1190 } 1191 kfree(ring); 1192 } 1193 1194 1195 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1196 { 1197 u32 i; 1198 1199 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1200 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1201 devinfo->shared.commonrings[i]); 1202 devinfo->shared.commonrings[i] = NULL; 1203 } 1204 kfree(devinfo->shared.flowrings); 1205 devinfo->shared.flowrings = NULL; 1206 if (devinfo->idxbuf) { 1207 dma_free_coherent(&devinfo->pdev->dev, 1208 devinfo->idxbuf_sz, 1209 devinfo->idxbuf, 1210 devinfo->idxbuf_dmahandle); 1211 devinfo->idxbuf = NULL; 1212 } 1213 } 1214 1215 1216 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1217 { 1218 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1219 struct brcmf_pcie_ringbuf *ring; 1220 struct brcmf_pcie_ringbuf *rings; 1221 u32 d2h_w_idx_ptr; 1222 u32 d2h_r_idx_ptr; 1223 u32 h2d_w_idx_ptr; 1224 u32 h2d_r_idx_ptr; 1225 u32 ring_mem_ptr; 1226 u32 i; 1227 u64 address; 1228 u32 bufsz; 1229 u8 idx_offset; 1230 struct brcmf_pcie_dhi_ringinfo ringinfo; 1231 u16 max_flowrings; 1232 u16 max_submissionrings; 1233 u16 max_completionrings; 1234 1235 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr, 1236 sizeof(ringinfo)); 1237 if (devinfo->shared.version >= 6) { 1238 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings); 1239 max_flowrings = le16_to_cpu(ringinfo.max_flowrings); 1240 max_completionrings = le16_to_cpu(ringinfo.max_completionrings); 1241 } else { 1242 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings); 1243 max_flowrings = max_submissionrings - 1244 BRCMF_NROF_H2D_COMMON_MSGRINGS; 1245 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS; 1246 } 1247 if (max_flowrings > 512) { 1248 brcmf_err(bus, "invalid max_flowrings(%d)\n", max_flowrings); 1249 return -EIO; 1250 } 1251 1252 if (devinfo->dma_idx_sz != 0) { 1253 bufsz = (max_submissionrings + max_completionrings) * 1254 devinfo->dma_idx_sz * 2; 1255 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1256 &devinfo->idxbuf_dmahandle, 1257 GFP_KERNEL); 1258 if (!devinfo->idxbuf) 1259 devinfo->dma_idx_sz = 0; 1260 } 1261 1262 if (devinfo->dma_idx_sz == 0) { 1263 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr); 1264 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr); 1265 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr); 1266 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr); 1267 idx_offset = sizeof(u32); 1268 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1269 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1270 brcmf_dbg(PCIE, "Using TCM indices\n"); 1271 } else { 1272 memset(devinfo->idxbuf, 0, bufsz); 1273 devinfo->idxbuf_sz = bufsz; 1274 idx_offset = devinfo->dma_idx_sz; 1275 devinfo->write_ptr = brcmf_pcie_write_idx; 1276 devinfo->read_ptr = brcmf_pcie_read_idx; 1277 1278 h2d_w_idx_ptr = 0; 1279 address = (u64)devinfo->idxbuf_dmahandle; 1280 ringinfo.h2d_w_idx_hostaddr.low_addr = 1281 cpu_to_le32(address & 0xffffffff); 1282 ringinfo.h2d_w_idx_hostaddr.high_addr = 1283 cpu_to_le32(address >> 32); 1284 1285 h2d_r_idx_ptr = h2d_w_idx_ptr + 1286 max_submissionrings * idx_offset; 1287 address += max_submissionrings * idx_offset; 1288 ringinfo.h2d_r_idx_hostaddr.low_addr = 1289 cpu_to_le32(address & 0xffffffff); 1290 ringinfo.h2d_r_idx_hostaddr.high_addr = 1291 cpu_to_le32(address >> 32); 1292 1293 d2h_w_idx_ptr = h2d_r_idx_ptr + 1294 max_submissionrings * idx_offset; 1295 address += max_submissionrings * idx_offset; 1296 ringinfo.d2h_w_idx_hostaddr.low_addr = 1297 cpu_to_le32(address & 0xffffffff); 1298 ringinfo.d2h_w_idx_hostaddr.high_addr = 1299 cpu_to_le32(address >> 32); 1300 1301 d2h_r_idx_ptr = d2h_w_idx_ptr + 1302 max_completionrings * idx_offset; 1303 address += max_completionrings * idx_offset; 1304 ringinfo.d2h_r_idx_hostaddr.low_addr = 1305 cpu_to_le32(address & 0xffffffff); 1306 ringinfo.d2h_r_idx_hostaddr.high_addr = 1307 cpu_to_le32(address >> 32); 1308 1309 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr, 1310 &ringinfo, sizeof(ringinfo)); 1311 brcmf_dbg(PCIE, "Using host memory indices\n"); 1312 } 1313 1314 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem); 1315 1316 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1317 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1318 if (!ring) 1319 goto fail; 1320 ring->w_idx_addr = h2d_w_idx_ptr; 1321 ring->r_idx_addr = h2d_r_idx_ptr; 1322 ring->id = i; 1323 devinfo->shared.commonrings[i] = ring; 1324 1325 h2d_w_idx_ptr += idx_offset; 1326 h2d_r_idx_ptr += idx_offset; 1327 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1328 } 1329 1330 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1331 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1332 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1333 if (!ring) 1334 goto fail; 1335 ring->w_idx_addr = d2h_w_idx_ptr; 1336 ring->r_idx_addr = d2h_r_idx_ptr; 1337 ring->id = i; 1338 devinfo->shared.commonrings[i] = ring; 1339 1340 d2h_w_idx_ptr += idx_offset; 1341 d2h_r_idx_ptr += idx_offset; 1342 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1343 } 1344 1345 devinfo->shared.max_flowrings = max_flowrings; 1346 devinfo->shared.max_submissionrings = max_submissionrings; 1347 devinfo->shared.max_completionrings = max_completionrings; 1348 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL); 1349 if (!rings) 1350 goto fail; 1351 1352 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings); 1353 1354 for (i = 0; i < max_flowrings; i++) { 1355 ring = &rings[i]; 1356 ring->devinfo = devinfo; 1357 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART; 1358 brcmf_commonring_register_cb(&ring->commonring, 1359 brcmf_pcie_ring_mb_ring_bell, 1360 brcmf_pcie_ring_mb_update_rptr, 1361 brcmf_pcie_ring_mb_update_wptr, 1362 brcmf_pcie_ring_mb_write_rptr, 1363 brcmf_pcie_ring_mb_write_wptr, 1364 ring); 1365 ring->w_idx_addr = h2d_w_idx_ptr; 1366 ring->r_idx_addr = h2d_r_idx_ptr; 1367 h2d_w_idx_ptr += idx_offset; 1368 h2d_r_idx_ptr += idx_offset; 1369 } 1370 devinfo->shared.flowrings = rings; 1371 1372 return 0; 1373 1374 fail: 1375 brcmf_err(bus, "Allocating ring buffers failed\n"); 1376 brcmf_pcie_release_ringbuffers(devinfo); 1377 return -ENOMEM; 1378 } 1379 1380 1381 static void 1382 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1383 { 1384 if (devinfo->shared.scratch) 1385 dma_free_coherent(&devinfo->pdev->dev, 1386 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1387 devinfo->shared.scratch, 1388 devinfo->shared.scratch_dmahandle); 1389 if (devinfo->shared.ringupd) 1390 dma_free_coherent(&devinfo->pdev->dev, 1391 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1392 devinfo->shared.ringupd, 1393 devinfo->shared.ringupd_dmahandle); 1394 } 1395 1396 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1397 { 1398 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1399 u64 address; 1400 u32 addr; 1401 1402 devinfo->shared.scratch = 1403 dma_alloc_coherent(&devinfo->pdev->dev, 1404 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1405 &devinfo->shared.scratch_dmahandle, 1406 GFP_KERNEL); 1407 if (!devinfo->shared.scratch) 1408 goto fail; 1409 1410 addr = devinfo->shared.tcm_base_address + 1411 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1412 address = (u64)devinfo->shared.scratch_dmahandle; 1413 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1414 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1415 addr = devinfo->shared.tcm_base_address + 1416 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1417 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1418 1419 devinfo->shared.ringupd = 1420 dma_alloc_coherent(&devinfo->pdev->dev, 1421 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1422 &devinfo->shared.ringupd_dmahandle, 1423 GFP_KERNEL); 1424 if (!devinfo->shared.ringupd) 1425 goto fail; 1426 1427 addr = devinfo->shared.tcm_base_address + 1428 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1429 address = (u64)devinfo->shared.ringupd_dmahandle; 1430 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1431 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1432 addr = devinfo->shared.tcm_base_address + 1433 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1434 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1435 return 0; 1436 1437 fail: 1438 brcmf_err(bus, "Allocating scratch buffers failed\n"); 1439 brcmf_pcie_release_scratchbuffers(devinfo); 1440 return -ENOMEM; 1441 } 1442 1443 1444 static void brcmf_pcie_down(struct device *dev) 1445 { 1446 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1447 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie; 1448 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 1449 1450 brcmf_pcie_fwcon_timer(devinfo, false); 1451 } 1452 1453 static int brcmf_pcie_preinit(struct device *dev) 1454 { 1455 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1456 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1457 1458 brcmf_dbg(PCIE, "Enter\n"); 1459 1460 brcmf_pcie_intr_enable(buspub->devinfo); 1461 brcmf_pcie_hostready(buspub->devinfo); 1462 1463 return 0; 1464 } 1465 1466 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1467 { 1468 return 0; 1469 } 1470 1471 1472 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1473 uint len) 1474 { 1475 return 0; 1476 } 1477 1478 1479 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1480 uint len) 1481 { 1482 return 0; 1483 } 1484 1485 1486 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1487 { 1488 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1489 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1490 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1491 1492 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1493 devinfo->wowl_enabled = enabled; 1494 } 1495 1496 1497 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1498 { 1499 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1500 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1501 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1502 1503 return devinfo->ci->ramsize - devinfo->ci->srsize; 1504 } 1505 1506 1507 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1508 { 1509 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1510 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1511 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1512 1513 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1514 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1515 return 0; 1516 } 1517 1518 static int brcmf_pcie_get_blob(struct device *dev, const struct firmware **fw, 1519 enum brcmf_blob_type type) 1520 { 1521 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1522 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1523 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1524 1525 switch (type) { 1526 case BRCMF_BLOB_CLM: 1527 *fw = devinfo->clm_fw; 1528 devinfo->clm_fw = NULL; 1529 break; 1530 case BRCMF_BLOB_TXCAP: 1531 *fw = devinfo->txcap_fw; 1532 devinfo->txcap_fw = NULL; 1533 break; 1534 default: 1535 return -ENOENT; 1536 } 1537 1538 if (!*fw) 1539 return -ENOENT; 1540 1541 return 0; 1542 } 1543 1544 static int brcmf_pcie_reset(struct device *dev) 1545 { 1546 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1547 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1548 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1549 struct brcmf_fw_request *fwreq; 1550 int err; 1551 1552 brcmf_pcie_intr_disable(devinfo); 1553 1554 brcmf_pcie_bus_console_read(devinfo, true); 1555 1556 brcmf_detach(dev); 1557 1558 brcmf_pcie_release_irq(devinfo); 1559 brcmf_pcie_release_scratchbuffers(devinfo); 1560 brcmf_pcie_release_ringbuffers(devinfo); 1561 brcmf_pcie_reset_device(devinfo); 1562 1563 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 1564 if (!fwreq) { 1565 dev_err(dev, "Failed to prepare FW request\n"); 1566 return -ENOMEM; 1567 } 1568 1569 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup); 1570 if (err) { 1571 dev_err(dev, "Failed to prepare FW request\n"); 1572 kfree(fwreq); 1573 } 1574 1575 return err; 1576 } 1577 1578 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1579 .preinit = brcmf_pcie_preinit, 1580 .txdata = brcmf_pcie_tx, 1581 .stop = brcmf_pcie_down, 1582 .txctl = brcmf_pcie_tx_ctlpkt, 1583 .rxctl = brcmf_pcie_rx_ctlpkt, 1584 .wowl_config = brcmf_pcie_wowl_config, 1585 .get_ramsize = brcmf_pcie_get_ramsize, 1586 .get_memdump = brcmf_pcie_get_memdump, 1587 .get_blob = brcmf_pcie_get_blob, 1588 .reset = brcmf_pcie_reset, 1589 .debugfs_create = brcmf_pcie_debugfs_create, 1590 }; 1591 1592 1593 static void 1594 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1595 u32 data_len) 1596 { 1597 __le32 *field; 1598 u32 newsize; 1599 1600 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1601 return; 1602 1603 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1604 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1605 return; 1606 field++; 1607 newsize = le32_to_cpup(field); 1608 1609 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1610 newsize); 1611 devinfo->ci->ramsize = newsize; 1612 } 1613 1614 1615 static int 1616 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1617 u32 sharedram_addr) 1618 { 1619 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1620 struct brcmf_pcie_shared_info *shared; 1621 u32 addr; 1622 1623 shared = &devinfo->shared; 1624 shared->tcm_base_address = sharedram_addr; 1625 1626 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1627 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK); 1628 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version); 1629 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1630 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1631 brcmf_err(bus, "Unsupported PCIE version %d\n", 1632 shared->version); 1633 return -EINVAL; 1634 } 1635 1636 /* check firmware support dma indicies */ 1637 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1638 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1639 devinfo->dma_idx_sz = sizeof(u16); 1640 else 1641 devinfo->dma_idx_sz = sizeof(u32); 1642 } 1643 1644 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1645 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1646 if (shared->max_rxbufpost == 0) 1647 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1648 1649 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1650 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1651 1652 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1653 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1654 1655 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1656 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1657 1658 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1659 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1660 1661 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1662 shared->max_rxbufpost, shared->rx_dataoffset); 1663 1664 brcmf_pcie_bus_console_init(devinfo); 1665 brcmf_pcie_bus_console_read(devinfo, false); 1666 1667 return 0; 1668 } 1669 1670 struct brcmf_random_seed_footer { 1671 __le32 length; 1672 __le32 magic; 1673 }; 1674 1675 #define BRCMF_RANDOM_SEED_MAGIC 0xfeedc0de 1676 #define BRCMF_RANDOM_SEED_LENGTH 0x100 1677 1678 static noinline_for_stack void 1679 brcmf_pcie_provide_random_bytes(struct brcmf_pciedev_info *devinfo, u32 address) 1680 { 1681 u8 randbuf[BRCMF_RANDOM_SEED_LENGTH]; 1682 1683 get_random_bytes(randbuf, BRCMF_RANDOM_SEED_LENGTH); 1684 memcpy_toio(devinfo->tcm + address, randbuf, BRCMF_RANDOM_SEED_LENGTH); 1685 } 1686 1687 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1688 const struct firmware *fw, void *nvram, 1689 u32 nvram_len) 1690 { 1691 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1692 u32 sharedram_addr; 1693 u32 sharedram_addr_written; 1694 u32 loop_counter; 1695 int err; 1696 u32 address; 1697 u32 resetintr; 1698 1699 brcmf_dbg(PCIE, "Halt ARM.\n"); 1700 err = brcmf_pcie_enter_download_state(devinfo); 1701 if (err) 1702 return err; 1703 1704 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1705 memcpy_toio(devinfo->tcm + devinfo->ci->rambase, 1706 (void *)fw->data, fw->size); 1707 1708 resetintr = get_unaligned_le32(fw->data); 1709 release_firmware(fw); 1710 1711 /* reset last 4 bytes of RAM address. to be used for shared 1712 * area. This identifies when FW is running 1713 */ 1714 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1715 1716 if (nvram) { 1717 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1718 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1719 nvram_len; 1720 memcpy_toio(devinfo->tcm + address, nvram, nvram_len); 1721 brcmf_fw_nvram_free(nvram); 1722 1723 if (devinfo->otp.valid) { 1724 size_t rand_len = BRCMF_RANDOM_SEED_LENGTH; 1725 struct brcmf_random_seed_footer footer = { 1726 .length = cpu_to_le32(rand_len), 1727 .magic = cpu_to_le32(BRCMF_RANDOM_SEED_MAGIC), 1728 }; 1729 1730 /* Some Apple chips/firmwares expect a buffer of random 1731 * data to be present before NVRAM 1732 */ 1733 brcmf_dbg(PCIE, "Download random seed\n"); 1734 1735 address -= sizeof(footer); 1736 memcpy_toio(devinfo->tcm + address, &footer, 1737 sizeof(footer)); 1738 1739 address -= rand_len; 1740 brcmf_pcie_provide_random_bytes(devinfo, address); 1741 } 1742 } else { 1743 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1744 devinfo->nvram_name); 1745 } 1746 1747 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1748 devinfo->ci->ramsize - 1749 4); 1750 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1751 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1752 if (err) 1753 return err; 1754 1755 brcmf_dbg(PCIE, "Wait for FW init\n"); 1756 sharedram_addr = sharedram_addr_written; 1757 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1758 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1759 msleep(50); 1760 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1761 devinfo->ci->ramsize - 1762 4); 1763 loop_counter--; 1764 } 1765 if (sharedram_addr == sharedram_addr_written) { 1766 brcmf_err(bus, "FW failed to initialize\n"); 1767 return -ENODEV; 1768 } 1769 if (sharedram_addr < devinfo->ci->rambase || 1770 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) { 1771 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n", 1772 sharedram_addr); 1773 return -ENODEV; 1774 } 1775 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1776 1777 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1778 } 1779 1780 1781 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1782 { 1783 struct pci_dev *pdev = devinfo->pdev; 1784 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1785 int err; 1786 phys_addr_t bar0_addr, bar1_addr; 1787 ulong bar1_size; 1788 1789 err = pci_enable_device(pdev); 1790 if (err) { 1791 brcmf_err(bus, "pci_enable_device failed err=%d\n", err); 1792 return err; 1793 } 1794 1795 pci_set_master(pdev); 1796 1797 /* Bar-0 mapped address */ 1798 bar0_addr = pci_resource_start(pdev, 0); 1799 /* Bar-1 mapped address */ 1800 bar1_addr = pci_resource_start(pdev, 2); 1801 /* read Bar-1 mapped memory range */ 1802 bar1_size = pci_resource_len(pdev, 2); 1803 if ((bar1_size == 0) || (bar1_addr == 0)) { 1804 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1805 bar1_size, (unsigned long long)bar1_addr); 1806 return -EINVAL; 1807 } 1808 1809 devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1810 devinfo->tcm = ioremap(bar1_addr, bar1_size); 1811 1812 if (!devinfo->regs || !devinfo->tcm) { 1813 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs, 1814 devinfo->tcm); 1815 return -EINVAL; 1816 } 1817 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1818 devinfo->regs, (unsigned long long)bar0_addr); 1819 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1820 devinfo->tcm, (unsigned long long)bar1_addr, 1821 (unsigned int)bar1_size); 1822 1823 return 0; 1824 } 1825 1826 1827 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1828 { 1829 if (devinfo->tcm) 1830 iounmap(devinfo->tcm); 1831 if (devinfo->regs) 1832 iounmap(devinfo->regs); 1833 1834 pci_disable_device(devinfo->pdev); 1835 } 1836 1837 1838 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1839 { 1840 u32 ret_addr; 1841 1842 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1843 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1844 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1845 1846 return ret_addr; 1847 } 1848 1849 1850 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1851 { 1852 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1853 1854 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1855 return brcmf_pcie_read_reg32(devinfo, addr); 1856 } 1857 1858 1859 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1860 { 1861 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1862 1863 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1864 brcmf_pcie_write_reg32(devinfo, addr, value); 1865 } 1866 1867 1868 static int brcmf_pcie_buscoreprep(void *ctx) 1869 { 1870 return brcmf_pcie_get_resource(ctx); 1871 } 1872 1873 1874 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1875 { 1876 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1877 struct brcmf_core *core; 1878 u32 val, reg; 1879 1880 devinfo->ci = chip; 1881 brcmf_pcie_reset_device(devinfo); 1882 1883 /* reginfo is not ready yet */ 1884 core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2); 1885 if (core->rev >= 64) 1886 reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT; 1887 else 1888 reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT; 1889 1890 val = brcmf_pcie_read_reg32(devinfo, reg); 1891 if (val != 0xffffffff) 1892 brcmf_pcie_write_reg32(devinfo, reg, val); 1893 1894 return 0; 1895 } 1896 1897 1898 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1899 u32 rstvec) 1900 { 1901 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1902 1903 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1904 } 1905 1906 1907 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1908 .prepare = brcmf_pcie_buscoreprep, 1909 .reset = brcmf_pcie_buscore_reset, 1910 .activate = brcmf_pcie_buscore_activate, 1911 .read32 = brcmf_pcie_buscore_read32, 1912 .write32 = brcmf_pcie_buscore_write32, 1913 }; 1914 1915 #define BRCMF_OTP_SYS_VENDOR 0x15 1916 #define BRCMF_OTP_BRCM_CIS 0x80 1917 1918 #define BRCMF_OTP_VENDOR_HDR 0x00000008 1919 1920 static int 1921 brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info *devinfo, 1922 u8 *data, size_t size) 1923 { 1924 int idx = 4; 1925 const char *chip_params; 1926 const char *board_params; 1927 const char *p; 1928 1929 /* 4-byte header and two empty strings */ 1930 if (size < 6) 1931 return -EINVAL; 1932 1933 if (get_unaligned_le32(data) != BRCMF_OTP_VENDOR_HDR) 1934 return -EINVAL; 1935 1936 chip_params = &data[idx]; 1937 1938 /* Skip first string, including terminator */ 1939 idx += strnlen(chip_params, size - idx) + 1; 1940 if (idx >= size) 1941 return -EINVAL; 1942 1943 board_params = &data[idx]; 1944 1945 /* Skip to terminator of second string */ 1946 idx += strnlen(board_params, size - idx); 1947 if (idx >= size) 1948 return -EINVAL; 1949 1950 /* At this point both strings are guaranteed NUL-terminated */ 1951 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n", 1952 chip_params, board_params); 1953 1954 p = skip_spaces(board_params); 1955 while (*p) { 1956 char tag = *p++; 1957 const char *end; 1958 size_t len; 1959 1960 if (*p++ != '=') /* implicit NUL check */ 1961 return -EINVAL; 1962 1963 /* *p might be NUL here, if so end == p and len == 0 */ 1964 end = strchrnul(p, ' '); 1965 len = end - p; 1966 1967 /* leave 1 byte for NUL in destination string */ 1968 if (len > (BRCMF_OTP_MAX_PARAM_LEN - 1)) 1969 return -EINVAL; 1970 1971 /* Copy len characters plus a NUL terminator */ 1972 switch (tag) { 1973 case 'M': 1974 strscpy(devinfo->otp.module, p, len + 1); 1975 break; 1976 case 'V': 1977 strscpy(devinfo->otp.vendor, p, len + 1); 1978 break; 1979 case 'm': 1980 strscpy(devinfo->otp.version, p, len + 1); 1981 break; 1982 } 1983 1984 /* Skip to next arg, if any */ 1985 p = skip_spaces(end); 1986 } 1987 1988 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n", 1989 devinfo->otp.module, devinfo->otp.vendor, 1990 devinfo->otp.version); 1991 1992 if (!devinfo->otp.module[0] || 1993 !devinfo->otp.vendor[0] || 1994 !devinfo->otp.version[0]) 1995 return -EINVAL; 1996 1997 devinfo->otp.valid = true; 1998 return 0; 1999 } 2000 2001 static int 2002 brcmf_pcie_parse_otp(struct brcmf_pciedev_info *devinfo, u8 *otp, size_t size) 2003 { 2004 int p = 0; 2005 int ret = -EINVAL; 2006 2007 brcmf_dbg(PCIE, "parse_otp size=%zd\n", size); 2008 2009 while (p < (size - 1)) { 2010 u8 type = otp[p]; 2011 u8 length = otp[p + 1]; 2012 2013 if (type == 0) 2014 break; 2015 2016 if ((p + 2 + length) > size) 2017 break; 2018 2019 switch (type) { 2020 case BRCMF_OTP_SYS_VENDOR: 2021 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n", 2022 p, length); 2023 ret = brcmf_pcie_parse_otp_sys_vendor(devinfo, 2024 &otp[p + 2], 2025 length); 2026 break; 2027 case BRCMF_OTP_BRCM_CIS: 2028 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n", 2029 p, length); 2030 break; 2031 default: 2032 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n", 2033 p, length, type); 2034 break; 2035 } 2036 2037 p += 2 + length; 2038 } 2039 2040 return ret; 2041 } 2042 2043 static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo) 2044 { 2045 const struct pci_dev *pdev = devinfo->pdev; 2046 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 2047 u32 coreid, base, words, idx, sromctl; 2048 u16 *otp; 2049 struct brcmf_core *core; 2050 int ret; 2051 2052 switch (devinfo->ci->chip) { 2053 case BRCM_CC_4355_CHIP_ID: 2054 coreid = BCMA_CORE_CHIPCOMMON; 2055 base = 0x8c0; 2056 words = 0xb2; 2057 break; 2058 case BRCM_CC_4364_CHIP_ID: 2059 coreid = BCMA_CORE_CHIPCOMMON; 2060 base = 0x8c0; 2061 words = 0x1a0; 2062 break; 2063 case BRCM_CC_4377_CHIP_ID: 2064 case BRCM_CC_4378_CHIP_ID: 2065 coreid = BCMA_CORE_GCI; 2066 base = 0x1120; 2067 words = 0x170; 2068 break; 2069 case BRCM_CC_4387_CHIP_ID: 2070 coreid = BCMA_CORE_GCI; 2071 base = 0x113c; 2072 words = 0x170; 2073 break; 2074 default: 2075 /* OTP not supported on this chip */ 2076 return 0; 2077 } 2078 2079 core = brcmf_chip_get_core(devinfo->ci, coreid); 2080 if (!core) { 2081 brcmf_err(bus, "No OTP core\n"); 2082 return -ENODEV; 2083 } 2084 2085 if (coreid == BCMA_CORE_CHIPCOMMON) { 2086 /* Chips with OTP accessed via ChipCommon need additional 2087 * handling to access the OTP 2088 */ 2089 brcmf_pcie_select_core(devinfo, coreid); 2090 sromctl = READCC32(devinfo, sromcontrol); 2091 2092 if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) { 2093 /* Chip lacks OTP, try without it... */ 2094 brcmf_err(bus, 2095 "OTP unavailable, using default firmware\n"); 2096 return 0; 2097 } 2098 2099 /* Map OTP to shadow area */ 2100 WRITECC32(devinfo, sromcontrol, 2101 sromctl | BCMA_CC_SROM_CONTROL_OTPSEL); 2102 } 2103 2104 otp = kcalloc(words, sizeof(u16), GFP_KERNEL); 2105 if (!otp) 2106 return -ENOMEM; 2107 2108 /* Map bus window to SROM/OTP shadow area in core */ 2109 base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base); 2110 2111 brcmf_dbg(PCIE, "OTP data:\n"); 2112 for (idx = 0; idx < words; idx++) { 2113 otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx); 2114 brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]); 2115 } 2116 2117 if (coreid == BCMA_CORE_CHIPCOMMON) { 2118 brcmf_pcie_select_core(devinfo, coreid); 2119 WRITECC32(devinfo, sromcontrol, sromctl); 2120 } 2121 2122 ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words); 2123 kfree(otp); 2124 2125 return ret; 2126 } 2127 2128 #define BRCMF_PCIE_FW_CODE 0 2129 #define BRCMF_PCIE_FW_NVRAM 1 2130 #define BRCMF_PCIE_FW_CLM 2 2131 #define BRCMF_PCIE_FW_TXCAP 3 2132 2133 static void brcmf_pcie_setup(struct device *dev, int ret, 2134 struct brcmf_fw_request *fwreq) 2135 { 2136 const struct firmware *fw; 2137 void *nvram; 2138 struct brcmf_bus *bus; 2139 struct brcmf_pciedev *pcie_bus_dev; 2140 struct brcmf_pciedev_info *devinfo; 2141 struct brcmf_commonring **flowrings; 2142 u32 i, nvram_len; 2143 2144 bus = dev_get_drvdata(dev); 2145 pcie_bus_dev = bus->bus_priv.pcie; 2146 devinfo = pcie_bus_dev->devinfo; 2147 2148 /* check firmware loading result */ 2149 if (ret) 2150 goto fail; 2151 2152 brcmf_pcie_attach(devinfo); 2153 2154 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary; 2155 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data; 2156 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len; 2157 devinfo->clm_fw = fwreq->items[BRCMF_PCIE_FW_CLM].binary; 2158 devinfo->txcap_fw = fwreq->items[BRCMF_PCIE_FW_TXCAP].binary; 2159 kfree(fwreq); 2160 2161 ret = brcmf_chip_get_raminfo(devinfo->ci); 2162 if (ret) { 2163 brcmf_err(bus, "Failed to get RAM info\n"); 2164 release_firmware(fw); 2165 brcmf_fw_nvram_free(nvram); 2166 goto fail; 2167 } 2168 2169 /* Some of the firmwares have the size of the memory of the device 2170 * defined inside the firmware. This is because part of the memory in 2171 * the device is shared and the devision is determined by FW. Parse 2172 * the firmware and adjust the chip memory size now. 2173 */ 2174 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 2175 2176 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 2177 if (ret) 2178 goto fail; 2179 2180 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2181 2182 ret = brcmf_pcie_init_ringbuffers(devinfo); 2183 if (ret) 2184 goto fail; 2185 2186 ret = brcmf_pcie_init_scratchbuffers(devinfo); 2187 if (ret) 2188 goto fail; 2189 2190 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2191 ret = brcmf_pcie_request_irq(devinfo); 2192 if (ret) 2193 goto fail; 2194 2195 /* hook the commonrings in the bus structure. */ 2196 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 2197 bus->msgbuf->commonrings[i] = 2198 &devinfo->shared.commonrings[i]->commonring; 2199 2200 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings), 2201 GFP_KERNEL); 2202 if (!flowrings) 2203 goto fail; 2204 2205 for (i = 0; i < devinfo->shared.max_flowrings; i++) 2206 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 2207 bus->msgbuf->flowrings = flowrings; 2208 2209 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 2210 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 2211 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings; 2212 2213 init_waitqueue_head(&devinfo->mbdata_resp_wait); 2214 2215 ret = brcmf_attach(&devinfo->pdev->dev); 2216 if (ret) 2217 goto fail; 2218 2219 brcmf_pcie_bus_console_read(devinfo, false); 2220 2221 brcmf_pcie_fwcon_timer(devinfo, true); 2222 2223 return; 2224 2225 fail: 2226 brcmf_err(bus, "Dongle setup failed\n"); 2227 brcmf_pcie_bus_console_read(devinfo, true); 2228 brcmf_fw_crashed(dev); 2229 device_release_driver(dev); 2230 } 2231 2232 static struct brcmf_fw_request * 2233 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo) 2234 { 2235 struct brcmf_fw_request *fwreq; 2236 struct brcmf_fw_name fwnames[] = { 2237 { ".bin", devinfo->fw_name }, 2238 { ".txt", devinfo->nvram_name }, 2239 { ".clm_blob", devinfo->clm_name }, 2240 { ".txcap_blob", devinfo->txcap_name }, 2241 }; 2242 2243 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, 2244 brcmf_pcie_fwnames, 2245 ARRAY_SIZE(brcmf_pcie_fwnames), 2246 fwnames, ARRAY_SIZE(fwnames)); 2247 if (!fwreq) 2248 return NULL; 2249 2250 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 2251 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 2252 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL; 2253 fwreq->items[BRCMF_PCIE_FW_CLM].type = BRCMF_FW_TYPE_BINARY; 2254 fwreq->items[BRCMF_PCIE_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL; 2255 fwreq->items[BRCMF_PCIE_FW_TXCAP].type = BRCMF_FW_TYPE_BINARY; 2256 fwreq->items[BRCMF_PCIE_FW_TXCAP].flags = BRCMF_FW_REQF_OPTIONAL; 2257 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */ 2258 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1; 2259 fwreq->bus_nr = devinfo->pdev->bus->number; 2260 2261 /* Apple platforms with fancy firmware/NVRAM selection */ 2262 if (devinfo->settings->board_type && 2263 devinfo->settings->antenna_sku && 2264 devinfo->otp.valid) { 2265 const struct brcmf_otp_params *otp = &devinfo->otp; 2266 struct device *dev = &devinfo->pdev->dev; 2267 const char **bt = fwreq->board_types; 2268 2269 brcmf_dbg(PCIE, "Apple board: %s\n", 2270 devinfo->settings->board_type); 2271 2272 /* Example: apple,shikoku-RASP-m-6.11-X3 */ 2273 bt[0] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s-%s", 2274 devinfo->settings->board_type, 2275 otp->module, otp->vendor, otp->version, 2276 devinfo->settings->antenna_sku); 2277 bt[1] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s", 2278 devinfo->settings->board_type, 2279 otp->module, otp->vendor, otp->version); 2280 bt[2] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s", 2281 devinfo->settings->board_type, 2282 otp->module, otp->vendor); 2283 bt[3] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", 2284 devinfo->settings->board_type, 2285 otp->module); 2286 bt[4] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", 2287 devinfo->settings->board_type, 2288 devinfo->settings->antenna_sku); 2289 bt[5] = devinfo->settings->board_type; 2290 2291 if (!bt[0] || !bt[1] || !bt[2] || !bt[3] || !bt[4]) { 2292 kfree(fwreq); 2293 return NULL; 2294 } 2295 } else { 2296 brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type); 2297 fwreq->board_types[0] = devinfo->settings->board_type; 2298 } 2299 2300 return fwreq; 2301 } 2302 2303 #ifdef DEBUG 2304 static void 2305 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active) 2306 { 2307 if (!active) { 2308 if (devinfo->console_active) { 2309 del_timer_sync(&devinfo->timer); 2310 devinfo->console_active = false; 2311 } 2312 return; 2313 } 2314 2315 /* don't start the timer */ 2316 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP || 2317 !devinfo->console_interval || !BRCMF_FWCON_ON()) 2318 return; 2319 2320 if (!devinfo->console_active) { 2321 devinfo->timer.expires = jiffies + devinfo->console_interval; 2322 add_timer(&devinfo->timer); 2323 devinfo->console_active = true; 2324 } else { 2325 /* Reschedule the timer */ 2326 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval); 2327 } 2328 } 2329 2330 static void 2331 brcmf_pcie_fwcon(struct timer_list *t) 2332 { 2333 struct brcmf_pciedev_info *devinfo = from_timer(devinfo, t, timer); 2334 2335 if (!devinfo->console_active) 2336 return; 2337 2338 brcmf_pcie_bus_console_read(devinfo, false); 2339 2340 /* Reschedule the timer if console interval is not zero */ 2341 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval); 2342 } 2343 2344 static int brcmf_pcie_console_interval_get(void *data, u64 *val) 2345 { 2346 struct brcmf_pciedev_info *devinfo = data; 2347 2348 *val = devinfo->console_interval; 2349 2350 return 0; 2351 } 2352 2353 static int brcmf_pcie_console_interval_set(void *data, u64 val) 2354 { 2355 struct brcmf_pciedev_info *devinfo = data; 2356 2357 if (val > MAX_CONSOLE_INTERVAL) 2358 return -EINVAL; 2359 2360 devinfo->console_interval = val; 2361 2362 if (!val && devinfo->console_active) 2363 brcmf_pcie_fwcon_timer(devinfo, false); 2364 else if (val) 2365 brcmf_pcie_fwcon_timer(devinfo, true); 2366 2367 return 0; 2368 } 2369 2370 DEFINE_SIMPLE_ATTRIBUTE(brcmf_pcie_console_interval_fops, 2371 brcmf_pcie_console_interval_get, 2372 brcmf_pcie_console_interval_set, 2373 "%llu\n"); 2374 2375 static void brcmf_pcie_debugfs_create(struct device *dev) 2376 { 2377 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2378 struct brcmf_pub *drvr = bus_if->drvr; 2379 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie; 2380 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 2381 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 2382 2383 if (IS_ERR_OR_NULL(dentry)) 2384 return; 2385 2386 devinfo->console_interval = BRCMF_CONSOLE; 2387 2388 debugfs_create_file("console_interval", 0644, dentry, devinfo, 2389 &brcmf_pcie_console_interval_fops); 2390 } 2391 2392 #else 2393 void brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active) 2394 { 2395 } 2396 2397 static void brcmf_pcie_debugfs_create(struct device *dev) 2398 { 2399 } 2400 #endif 2401 2402 /* Forward declaration for pci_match_id() call */ 2403 static const struct pci_device_id brcmf_pcie_devid_table[]; 2404 2405 static int 2406 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2407 { 2408 int ret; 2409 struct brcmf_fw_request *fwreq; 2410 struct brcmf_pciedev_info *devinfo; 2411 struct brcmf_pciedev *pcie_bus_dev; 2412 struct brcmf_core *core; 2413 struct brcmf_bus *bus; 2414 2415 if (!id) { 2416 id = pci_match_id(brcmf_pcie_devid_table, pdev); 2417 if (!id) { 2418 pci_err(pdev, "Error could not find pci_device_id for %x:%x\n", pdev->vendor, pdev->device); 2419 return -ENODEV; 2420 } 2421 } 2422 2423 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); 2424 2425 ret = -ENOMEM; 2426 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 2427 if (devinfo == NULL) 2428 return ret; 2429 2430 devinfo->pdev = pdev; 2431 pcie_bus_dev = NULL; 2432 devinfo->ci = brcmf_chip_attach(devinfo, pdev->device, 2433 &brcmf_pcie_buscore_ops); 2434 if (IS_ERR(devinfo->ci)) { 2435 ret = PTR_ERR(devinfo->ci); 2436 devinfo->ci = NULL; 2437 goto fail; 2438 } 2439 2440 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 2441 if (core->rev >= 64) 2442 devinfo->reginfo = &brcmf_reginfo_64; 2443 else 2444 devinfo->reginfo = &brcmf_reginfo_default; 2445 2446 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 2447 if (pcie_bus_dev == NULL) { 2448 ret = -ENOMEM; 2449 goto fail; 2450 } 2451 2452 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 2453 BRCMF_BUSTYPE_PCIE, 2454 devinfo->ci->chip, 2455 devinfo->ci->chiprev); 2456 if (!devinfo->settings) { 2457 ret = -ENOMEM; 2458 goto fail; 2459 } 2460 2461 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 2462 if (!bus) { 2463 ret = -ENOMEM; 2464 goto fail; 2465 } 2466 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 2467 if (!bus->msgbuf) { 2468 ret = -ENOMEM; 2469 kfree(bus); 2470 goto fail; 2471 } 2472 2473 /* hook it all together. */ 2474 pcie_bus_dev->devinfo = devinfo; 2475 pcie_bus_dev->bus = bus; 2476 bus->dev = &pdev->dev; 2477 bus->bus_priv.pcie = pcie_bus_dev; 2478 bus->ops = &brcmf_pcie_bus_ops; 2479 bus->proto_type = BRCMF_PROTO_MSGBUF; 2480 bus->fwvid = id->driver_data; 2481 bus->chip = devinfo->coreid; 2482 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 2483 dev_set_drvdata(&pdev->dev, bus); 2484 2485 ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings); 2486 if (ret) 2487 goto fail_bus; 2488 2489 ret = brcmf_pcie_read_otp(devinfo); 2490 if (ret) { 2491 brcmf_err(bus, "failed to parse OTP\n"); 2492 goto fail_brcmf; 2493 } 2494 2495 #ifdef DEBUG 2496 /* Set up the fwcon timer */ 2497 timer_setup(&devinfo->timer, brcmf_pcie_fwcon, 0); 2498 #endif 2499 2500 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 2501 if (!fwreq) { 2502 ret = -ENOMEM; 2503 goto fail_brcmf; 2504 } 2505 2506 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup); 2507 if (ret < 0) { 2508 kfree(fwreq); 2509 goto fail_brcmf; 2510 } 2511 return 0; 2512 2513 fail_brcmf: 2514 brcmf_free(&devinfo->pdev->dev); 2515 fail_bus: 2516 kfree(bus->msgbuf); 2517 kfree(bus); 2518 fail: 2519 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device); 2520 brcmf_pcie_release_resource(devinfo); 2521 if (devinfo->ci) 2522 brcmf_chip_detach(devinfo->ci); 2523 if (devinfo->settings) 2524 brcmf_release_module_param(devinfo->settings); 2525 kfree(pcie_bus_dev); 2526 kfree(devinfo); 2527 return ret; 2528 } 2529 2530 2531 static void 2532 brcmf_pcie_remove(struct pci_dev *pdev) 2533 { 2534 struct brcmf_pciedev_info *devinfo; 2535 struct brcmf_bus *bus; 2536 2537 brcmf_dbg(PCIE, "Enter\n"); 2538 2539 bus = dev_get_drvdata(&pdev->dev); 2540 if (bus == NULL) 2541 return; 2542 2543 devinfo = bus->bus_priv.pcie->devinfo; 2544 brcmf_pcie_bus_console_read(devinfo, false); 2545 brcmf_pcie_fwcon_timer(devinfo, false); 2546 2547 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2548 if (devinfo->ci) 2549 brcmf_pcie_intr_disable(devinfo); 2550 2551 brcmf_detach(&pdev->dev); 2552 brcmf_free(&pdev->dev); 2553 2554 kfree(bus->bus_priv.pcie); 2555 kfree(bus->msgbuf->flowrings); 2556 kfree(bus->msgbuf); 2557 kfree(bus); 2558 2559 brcmf_pcie_release_irq(devinfo); 2560 brcmf_pcie_release_scratchbuffers(devinfo); 2561 brcmf_pcie_release_ringbuffers(devinfo); 2562 brcmf_pcie_reset_device(devinfo); 2563 brcmf_pcie_release_resource(devinfo); 2564 release_firmware(devinfo->clm_fw); 2565 release_firmware(devinfo->txcap_fw); 2566 2567 if (devinfo->ci) 2568 brcmf_chip_detach(devinfo->ci); 2569 if (devinfo->settings) 2570 brcmf_release_module_param(devinfo->settings); 2571 2572 kfree(devinfo); 2573 dev_set_drvdata(&pdev->dev, NULL); 2574 } 2575 2576 2577 #ifdef CONFIG_PM 2578 2579 2580 static int brcmf_pcie_pm_enter_D3(struct device *dev) 2581 { 2582 struct brcmf_pciedev_info *devinfo; 2583 struct brcmf_bus *bus; 2584 2585 brcmf_dbg(PCIE, "Enter\n"); 2586 2587 bus = dev_get_drvdata(dev); 2588 devinfo = bus->bus_priv.pcie->devinfo; 2589 2590 brcmf_pcie_fwcon_timer(devinfo, false); 2591 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 2592 2593 devinfo->mbdata_completed = false; 2594 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 2595 2596 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 2597 BRCMF_PCIE_MBDATA_TIMEOUT); 2598 if (!devinfo->mbdata_completed) { 2599 brcmf_err(bus, "Timeout on response for entering D3 substate\n"); 2600 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2601 return -EIO; 2602 } 2603 2604 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2605 2606 return 0; 2607 } 2608 2609 2610 static int brcmf_pcie_pm_leave_D3(struct device *dev) 2611 { 2612 struct brcmf_pciedev_info *devinfo; 2613 struct brcmf_bus *bus; 2614 struct pci_dev *pdev; 2615 int err; 2616 2617 brcmf_dbg(PCIE, "Enter\n"); 2618 2619 bus = dev_get_drvdata(dev); 2620 devinfo = bus->bus_priv.pcie->devinfo; 2621 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 2622 2623 /* Check if device is still up and running, if so we are ready */ 2624 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) { 2625 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 2626 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 2627 goto cleanup; 2628 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 2629 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2630 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2631 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2632 brcmf_pcie_intr_enable(devinfo); 2633 brcmf_pcie_hostready(devinfo); 2634 brcmf_pcie_fwcon_timer(devinfo, true); 2635 return 0; 2636 } 2637 2638 cleanup: 2639 brcmf_chip_detach(devinfo->ci); 2640 devinfo->ci = NULL; 2641 pdev = devinfo->pdev; 2642 brcmf_pcie_remove(pdev); 2643 2644 err = brcmf_pcie_probe(pdev, NULL); 2645 if (err) 2646 __brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err); 2647 2648 return err; 2649 } 2650 2651 2652 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 2653 .suspend = brcmf_pcie_pm_enter_D3, 2654 .resume = brcmf_pcie_pm_leave_D3, 2655 .freeze = brcmf_pcie_pm_enter_D3, 2656 .restore = brcmf_pcie_pm_leave_D3, 2657 }; 2658 2659 2660 #endif /* CONFIG_PM */ 2661 2662 2663 #define BRCMF_PCIE_DEVICE(dev_id, fw_vend) \ 2664 { \ 2665 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \ 2666 PCI_ANY_ID, PCI_ANY_ID, \ 2667 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \ 2668 BRCMF_FWVENDOR_ ## fw_vend \ 2669 } 2670 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev, fw_vend) \ 2671 { \ 2672 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \ 2673 (subvend), (subdev), \ 2674 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \ 2675 BRCMF_FWVENDOR_ ## fw_vend \ 2676 } 2677 2678 static const struct pci_device_id brcmf_pcie_devid_table[] = { 2679 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID, WCC), 2680 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355, WCC), 2681 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID, WCC), 2682 BRCMF_PCIE_DEVICE(BRCM_PCIE_4355_DEVICE_ID, WCC), 2683 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID, WCC), 2684 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID, WCC), 2685 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID, WCC), 2686 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID, WCC), 2687 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID, WCC), 2688 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID, WCC), 2689 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID, WCC), 2690 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID, WCC), 2691 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID, WCC), 2692 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID, WCC), 2693 BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID, WCC), 2694 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID, BCA), 2695 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID, BCA), 2696 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID, BCA), 2697 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365, BCA), 2698 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID, BCA), 2699 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID, BCA), 2700 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA), 2701 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC), 2702 BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW), 2703 BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC), 2704 BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC), 2705 BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC), 2706 2707 { /* end: all zeroes */ } 2708 }; 2709 2710 2711 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 2712 2713 2714 static struct pci_driver brcmf_pciedrvr = { 2715 .name = KBUILD_MODNAME, 2716 .id_table = brcmf_pcie_devid_table, 2717 .probe = brcmf_pcie_probe, 2718 .remove = brcmf_pcie_remove, 2719 #ifdef CONFIG_PM 2720 .driver.pm = &brcmf_pciedrvr_pm, 2721 #endif 2722 .driver.coredump = brcmf_dev_coredump, 2723 }; 2724 2725 2726 int brcmf_pcie_register(void) 2727 { 2728 brcmf_dbg(PCIE, "Enter\n"); 2729 return pci_register_driver(&brcmf_pciedrvr); 2730 } 2731 2732 2733 void brcmf_pcie_exit(void) 2734 { 2735 brcmf_dbg(PCIE, "Enter\n"); 2736 pci_unregister_driver(&brcmf_pciedrvr); 2737 } 2738