1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2014 Broadcom Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/firmware.h> 9 #include <linux/pci.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/bcma/bcma.h> 14 #include <linux/sched.h> 15 #include <linux/sched/signal.h> 16 #include <linux/kthread.h> 17 #include <linux/io.h> 18 #include <asm/unaligned.h> 19 20 #include <soc.h> 21 #include <chipcommon.h> 22 #include <brcmu_utils.h> 23 #include <brcmu_wifi.h> 24 #include <brcm_hw_ids.h> 25 26 /* Custom brcmf_err() that takes bus arg and passes it further */ 27 #define brcmf_err(bus, fmt, ...) \ 28 do { \ 29 if (IS_ENABLED(CONFIG_BRCMDBG) || \ 30 IS_ENABLED(CONFIG_BRCM_TRACING) || \ 31 net_ratelimit()) \ 32 __brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \ 33 } while (0) 34 35 #include "debug.h" 36 #include "bus.h" 37 #include "commonring.h" 38 #include "msgbuf.h" 39 #include "pcie.h" 40 #include "firmware.h" 41 #include "chip.h" 42 #include "core.h" 43 #include "common.h" 44 45 46 enum brcmf_pcie_state { 47 BRCMFMAC_PCIE_STATE_DOWN, 48 BRCMFMAC_PCIE_STATE_UP 49 }; 50 51 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie"); 52 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie"); 53 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie"); 54 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie"); 55 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie"); 56 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie"); 57 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie"); 58 BRCMF_FW_DEF(4364, "brcmfmac4364-pcie"); 59 BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie"); 60 BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie"); 61 BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie"); 62 BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie"); 63 BRCMF_FW_DEF(4371, "brcmfmac4371-pcie"); 64 BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie"); 65 BRCMF_FW_DEF(4355, "brcmfmac89459-pcie"); 66 67 /* firmware config files */ 68 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt"); 69 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt"); 70 71 /* per-board firmware binaries */ 72 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin"); 73 MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob"); 74 75 static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { 76 BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602), 77 BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C), 78 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C), 79 BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350), 80 BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C), 81 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 82 BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570), 83 BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570), 84 BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570), 85 BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358), 86 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 87 BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFFF, 4364), 88 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B), 89 BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C), 90 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B), 91 BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C), 92 BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), 93 BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C), 94 BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), 95 BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFFF, 4378B1), /* revision ID 3 */ 96 BRCMF_FW_ENTRY(CY_CC_89459_CHIP_ID, 0xFFFFFFFF, 4355), 97 }; 98 99 #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */ 100 101 #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) 102 103 /* backplane addres space accessed by BAR0 */ 104 #define BRCMF_PCIE_BAR0_WINDOW 0x80 105 #define BRCMF_PCIE_BAR0_REG_SIZE 0x1000 106 #define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70 107 108 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000 109 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000 110 111 #define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40 112 #define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C 113 114 #define BRCMF_PCIE_REG_INTSTATUS 0x90 115 #define BRCMF_PCIE_REG_INTMASK 0x94 116 #define BRCMF_PCIE_REG_SBMBX 0x98 117 118 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC 119 120 #define BRCMF_PCIE_PCIE2REG_INTMASK 0x24 121 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48 122 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C 123 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120 124 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124 125 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140 126 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144 127 128 #define BRCMF_PCIE_64_PCIE2REG_INTMASK 0xC14 129 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT 0xC30 130 #define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK 0xC34 131 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0 0xA20 132 #define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1 0xA24 133 134 #define BRCMF_PCIE2_INTA 0x01 135 #define BRCMF_PCIE2_INTB 0x02 136 137 #define BRCMF_PCIE_INT_0 0x01 138 #define BRCMF_PCIE_INT_1 0x02 139 #define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \ 140 BRCMF_PCIE_INT_1) 141 142 #define BRCMF_PCIE_MB_INT_FN0_0 0x0100 143 #define BRCMF_PCIE_MB_INT_FN0_1 0x0200 144 #define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000 145 #define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000 146 #define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000 147 #define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000 148 #define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000 149 #define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000 150 #define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000 151 #define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000 152 153 #define BRCMF_PCIE_MB_INT_FN0 (BRCMF_PCIE_MB_INT_FN0_0 | \ 154 BRCMF_PCIE_MB_INT_FN0_1) 155 #define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \ 156 BRCMF_PCIE_MB_INT_D2H0_DB1 | \ 157 BRCMF_PCIE_MB_INT_D2H1_DB0 | \ 158 BRCMF_PCIE_MB_INT_D2H1_DB1 | \ 159 BRCMF_PCIE_MB_INT_D2H2_DB0 | \ 160 BRCMF_PCIE_MB_INT_D2H2_DB1 | \ 161 BRCMF_PCIE_MB_INT_D2H3_DB0 | \ 162 BRCMF_PCIE_MB_INT_D2H3_DB1) 163 164 #define BRCMF_PCIE_64_MB_INT_D2H0_DB0 0x1 165 #define BRCMF_PCIE_64_MB_INT_D2H0_DB1 0x2 166 #define BRCMF_PCIE_64_MB_INT_D2H1_DB0 0x4 167 #define BRCMF_PCIE_64_MB_INT_D2H1_DB1 0x8 168 #define BRCMF_PCIE_64_MB_INT_D2H2_DB0 0x10 169 #define BRCMF_PCIE_64_MB_INT_D2H2_DB1 0x20 170 #define BRCMF_PCIE_64_MB_INT_D2H3_DB0 0x40 171 #define BRCMF_PCIE_64_MB_INT_D2H3_DB1 0x80 172 #define BRCMF_PCIE_64_MB_INT_D2H4_DB0 0x100 173 #define BRCMF_PCIE_64_MB_INT_D2H4_DB1 0x200 174 #define BRCMF_PCIE_64_MB_INT_D2H5_DB0 0x400 175 #define BRCMF_PCIE_64_MB_INT_D2H5_DB1 0x800 176 #define BRCMF_PCIE_64_MB_INT_D2H6_DB0 0x1000 177 #define BRCMF_PCIE_64_MB_INT_D2H6_DB1 0x2000 178 #define BRCMF_PCIE_64_MB_INT_D2H7_DB0 0x4000 179 #define BRCMF_PCIE_64_MB_INT_D2H7_DB1 0x8000 180 181 #define BRCMF_PCIE_64_MB_INT_D2H_DB (BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \ 182 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \ 183 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \ 184 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \ 185 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \ 186 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \ 187 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \ 188 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \ 189 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \ 190 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \ 191 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \ 192 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \ 193 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \ 194 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \ 195 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \ 196 BRCMF_PCIE_64_MB_INT_D2H7_DB1) 197 198 #define BRCMF_PCIE_SHARED_VERSION_7 7 199 #define BRCMF_PCIE_MIN_SHARED_VERSION 5 200 #define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7 201 #define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF 202 #define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000 203 #define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000 204 #define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000 205 206 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000 207 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000 208 209 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34 210 #define BRCMF_SHARED_RING_BASE_OFFSET 52 211 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36 212 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20 213 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40 214 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44 215 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48 216 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52 217 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56 218 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64 219 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68 220 221 #define BRCMF_RING_H2D_RING_COUNT_OFFSET 0 222 #define BRCMF_RING_D2H_RING_COUNT_OFFSET 1 223 #define BRCMF_RING_H2D_RING_MEM_OFFSET 4 224 #define BRCMF_RING_H2D_RING_STATE_OFFSET 8 225 226 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8 227 #define BRCMF_RING_MAX_ITEM_OFFSET 4 228 #define BRCMF_RING_LEN_ITEMS_OFFSET 6 229 #define BRCMF_RING_MEM_SZ 16 230 #define BRCMF_RING_STATE_SZ 8 231 232 #define BRCMF_DEF_MAX_RXBUFPOST 255 233 234 #define BRCMF_CONSOLE_BUFADDR_OFFSET 8 235 #define BRCMF_CONSOLE_BUFSIZE_OFFSET 12 236 #define BRCMF_CONSOLE_WRITEIDX_OFFSET 16 237 238 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8 239 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024 240 241 #define BRCMF_D2H_DEV_D3_ACK 0x00000001 242 #define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002 243 #define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004 244 #define BRCMF_D2H_DEV_FWHALT 0x10000000 245 246 #define BRCMF_H2D_HOST_D3_INFORM 0x00000001 247 #define BRCMF_H2D_HOST_DS_ACK 0x00000002 248 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008 249 #define BRCMF_H2D_HOST_D0_INFORM 0x00000010 250 251 #define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000) 252 253 #define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4 254 #define BRCMF_PCIE_CFGREG_PM_CSR 0x4C 255 #define BRCMF_PCIE_CFGREG_MSI_CAP 0x58 256 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C 257 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60 258 #define BRCMF_PCIE_CFGREG_MSI_DATA 0x64 259 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC 260 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC 261 #define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228 262 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248 263 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0 264 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4 265 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3 266 267 /* Magic number at a magic location to find RAM size */ 268 #define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */ 269 #define BRCMF_RAMSIZE_OFFSET 0x6c 270 271 272 struct brcmf_pcie_console { 273 u32 base_addr; 274 u32 buf_addr; 275 u32 bufsize; 276 u32 read_idx; 277 u8 log_str[256]; 278 u8 log_idx; 279 }; 280 281 struct brcmf_pcie_shared_info { 282 u32 tcm_base_address; 283 u32 flags; 284 struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS]; 285 struct brcmf_pcie_ringbuf *flowrings; 286 u16 max_rxbufpost; 287 u16 max_flowrings; 288 u16 max_submissionrings; 289 u16 max_completionrings; 290 u32 rx_dataoffset; 291 u32 htod_mb_data_addr; 292 u32 dtoh_mb_data_addr; 293 u32 ring_info_addr; 294 struct brcmf_pcie_console console; 295 void *scratch; 296 dma_addr_t scratch_dmahandle; 297 void *ringupd; 298 dma_addr_t ringupd_dmahandle; 299 u8 version; 300 }; 301 302 struct brcmf_pcie_core_info { 303 u32 base; 304 u32 wrapbase; 305 }; 306 307 #define BRCMF_OTP_MAX_PARAM_LEN 16 308 309 struct brcmf_otp_params { 310 char module[BRCMF_OTP_MAX_PARAM_LEN]; 311 char vendor[BRCMF_OTP_MAX_PARAM_LEN]; 312 char version[BRCMF_OTP_MAX_PARAM_LEN]; 313 bool valid; 314 }; 315 316 struct brcmf_pciedev_info { 317 enum brcmf_pcie_state state; 318 bool in_irq; 319 struct pci_dev *pdev; 320 char fw_name[BRCMF_FW_NAME_LEN]; 321 char nvram_name[BRCMF_FW_NAME_LEN]; 322 char clm_name[BRCMF_FW_NAME_LEN]; 323 const struct firmware *clm_fw; 324 const struct brcmf_pcie_reginfo *reginfo; 325 void __iomem *regs; 326 void __iomem *tcm; 327 u32 ram_base; 328 u32 ram_size; 329 struct brcmf_chip *ci; 330 u32 coreid; 331 struct brcmf_pcie_shared_info shared; 332 wait_queue_head_t mbdata_resp_wait; 333 bool mbdata_completed; 334 bool irq_allocated; 335 bool wowl_enabled; 336 u8 dma_idx_sz; 337 void *idxbuf; 338 u32 idxbuf_sz; 339 dma_addr_t idxbuf_dmahandle; 340 u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset); 341 void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 342 u16 value); 343 struct brcmf_mp_device *settings; 344 struct brcmf_otp_params otp; 345 #ifdef DEBUG 346 u32 console_interval; 347 bool console_active; 348 struct timer_list timer; 349 #endif 350 }; 351 352 struct brcmf_pcie_ringbuf { 353 struct brcmf_commonring commonring; 354 dma_addr_t dma_handle; 355 u32 w_idx_addr; 356 u32 r_idx_addr; 357 struct brcmf_pciedev_info *devinfo; 358 u8 id; 359 }; 360 361 /** 362 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info 363 * 364 * @ringmem: dongle memory pointer to ring memory location 365 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers 366 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers 367 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers 368 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers 369 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers 370 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers 371 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers 372 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers 373 * @max_flowrings: maximum number of tx flow rings supported. 374 * @max_submissionrings: maximum number of submission rings(h2d) supported. 375 * @max_completionrings: maximum number of completion rings(d2h) supported. 376 */ 377 struct brcmf_pcie_dhi_ringinfo { 378 __le32 ringmem; 379 __le32 h2d_w_idx_ptr; 380 __le32 h2d_r_idx_ptr; 381 __le32 d2h_w_idx_ptr; 382 __le32 d2h_r_idx_ptr; 383 struct msgbuf_buf_addr h2d_w_idx_hostaddr; 384 struct msgbuf_buf_addr h2d_r_idx_hostaddr; 385 struct msgbuf_buf_addr d2h_w_idx_hostaddr; 386 struct msgbuf_buf_addr d2h_r_idx_hostaddr; 387 __le16 max_flowrings; 388 __le16 max_submissionrings; 389 __le16 max_completionrings; 390 }; 391 392 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = { 393 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM, 394 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM, 395 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM, 396 BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM, 397 BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 398 }; 399 400 static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = { 401 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 402 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 403 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 404 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7, 405 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7 406 }; 407 408 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = { 409 BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE, 410 BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE, 411 BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE, 412 BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE, 413 BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 414 }; 415 416 struct brcmf_pcie_reginfo { 417 u32 intmask; 418 u32 mailboxint; 419 u32 mailboxmask; 420 u32 h2d_mailbox_0; 421 u32 h2d_mailbox_1; 422 u32 int_d2h_db; 423 u32 int_fn0; 424 }; 425 426 static const struct brcmf_pcie_reginfo brcmf_reginfo_default = { 427 .intmask = BRCMF_PCIE_PCIE2REG_INTMASK, 428 .mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT, 429 .mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 430 .h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0, 431 .h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1, 432 .int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB, 433 .int_fn0 = BRCMF_PCIE_MB_INT_FN0, 434 }; 435 436 static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = { 437 .intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK, 438 .mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT, 439 .mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK, 440 .h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0, 441 .h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1, 442 .int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB, 443 .int_fn0 = 0, 444 }; 445 446 static void brcmf_pcie_setup(struct device *dev, int ret, 447 struct brcmf_fw_request *fwreq); 448 static struct brcmf_fw_request * 449 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo); 450 static void 451 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active); 452 static void brcmf_pcie_debugfs_create(struct device *dev); 453 454 static u16 455 brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 456 { 457 void __iomem *address = devinfo->regs + reg_offset; 458 459 return ioread16(address); 460 } 461 462 static u32 463 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) 464 { 465 void __iomem *address = devinfo->regs + reg_offset; 466 467 return (ioread32(address)); 468 } 469 470 471 static void 472 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, 473 u32 value) 474 { 475 void __iomem *address = devinfo->regs + reg_offset; 476 477 iowrite32(value, address); 478 } 479 480 481 static u8 482 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 483 { 484 void __iomem *address = devinfo->tcm + mem_offset; 485 486 return (ioread8(address)); 487 } 488 489 490 static u16 491 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 492 { 493 void __iomem *address = devinfo->tcm + mem_offset; 494 495 return (ioread16(address)); 496 } 497 498 499 static void 500 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 501 u16 value) 502 { 503 void __iomem *address = devinfo->tcm + mem_offset; 504 505 iowrite16(value, address); 506 } 507 508 509 static u16 510 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 511 { 512 u16 *address = devinfo->idxbuf + mem_offset; 513 514 return (*(address)); 515 } 516 517 518 static void 519 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 520 u16 value) 521 { 522 u16 *address = devinfo->idxbuf + mem_offset; 523 524 *(address) = value; 525 } 526 527 528 static u32 529 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 530 { 531 void __iomem *address = devinfo->tcm + mem_offset; 532 533 return (ioread32(address)); 534 } 535 536 537 static void 538 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 539 u32 value) 540 { 541 void __iomem *address = devinfo->tcm + mem_offset; 542 543 iowrite32(value, address); 544 } 545 546 547 static u32 548 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset) 549 { 550 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 551 552 return (ioread32(addr)); 553 } 554 555 556 static void 557 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 558 u32 value) 559 { 560 void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset; 561 562 iowrite32(value, addr); 563 } 564 565 566 static void 567 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset, 568 void *dstaddr, u32 len) 569 { 570 void __iomem *address = devinfo->tcm + mem_offset; 571 __le32 *dst32; 572 __le16 *dst16; 573 u8 *dst8; 574 575 if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) { 576 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) { 577 dst8 = (u8 *)dstaddr; 578 while (len) { 579 *dst8 = ioread8(address); 580 address++; 581 dst8++; 582 len--; 583 } 584 } else { 585 len = len / 2; 586 dst16 = (__le16 *)dstaddr; 587 while (len) { 588 *dst16 = cpu_to_le16(ioread16(address)); 589 address += 2; 590 dst16++; 591 len--; 592 } 593 } 594 } else { 595 len = len / 4; 596 dst32 = (__le32 *)dstaddr; 597 while (len) { 598 *dst32 = cpu_to_le32(ioread32(address)); 599 address += 4; 600 dst32++; 601 len--; 602 } 603 } 604 } 605 606 607 #define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \ 608 CHIPCREGOFFS(reg)) 609 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ 610 CHIPCREGOFFS(reg), value) 611 612 613 static void 614 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid) 615 { 616 const struct pci_dev *pdev = devinfo->pdev; 617 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 618 struct brcmf_core *core; 619 u32 bar0_win; 620 621 core = brcmf_chip_get_core(devinfo->ci, coreid); 622 if (core) { 623 bar0_win = core->base; 624 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win); 625 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, 626 &bar0_win) == 0) { 627 if (bar0_win != core->base) { 628 bar0_win = core->base; 629 pci_write_config_dword(pdev, 630 BRCMF_PCIE_BAR0_WINDOW, 631 bar0_win); 632 } 633 } 634 } else { 635 brcmf_err(bus, "Unsupported core selected %x\n", coreid); 636 } 637 } 638 639 640 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo) 641 { 642 struct brcmf_core *core; 643 u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD, 644 BRCMF_PCIE_CFGREG_PM_CSR, 645 BRCMF_PCIE_CFGREG_MSI_CAP, 646 BRCMF_PCIE_CFGREG_MSI_ADDR_L, 647 BRCMF_PCIE_CFGREG_MSI_ADDR_H, 648 BRCMF_PCIE_CFGREG_MSI_DATA, 649 BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2, 650 BRCMF_PCIE_CFGREG_RBAR_CTRL, 651 BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1, 652 BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG, 653 BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG }; 654 u32 i; 655 u32 val; 656 u32 lsc; 657 658 if (!devinfo->ci) 659 return; 660 661 /* Disable ASPM */ 662 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 663 pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 664 &lsc); 665 val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB); 666 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 667 val); 668 669 /* Watchdog reset */ 670 brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON); 671 WRITECC32(devinfo, watchdog, 4); 672 msleep(100); 673 674 /* Restore ASPM */ 675 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 676 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL, 677 lsc); 678 679 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 680 if (core->rev <= 13) { 681 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) { 682 brcmf_pcie_write_reg32(devinfo, 683 BRCMF_PCIE_PCIE2REG_CONFIGADDR, 684 cfg_offset[i]); 685 val = brcmf_pcie_read_reg32(devinfo, 686 BRCMF_PCIE_PCIE2REG_CONFIGDATA); 687 brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n", 688 cfg_offset[i], val); 689 brcmf_pcie_write_reg32(devinfo, 690 BRCMF_PCIE_PCIE2REG_CONFIGDATA, 691 val); 692 } 693 } 694 } 695 696 697 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo) 698 { 699 u32 config; 700 701 /* BAR1 window may not be sized properly */ 702 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 703 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0); 704 config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA); 705 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config); 706 707 device_wakeup_enable(&devinfo->pdev->dev); 708 } 709 710 711 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo) 712 { 713 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 714 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4); 715 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 716 5); 717 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 718 0); 719 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX, 720 7); 721 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA, 722 0); 723 } 724 return 0; 725 } 726 727 728 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo, 729 u32 resetintr) 730 { 731 struct brcmf_core *core; 732 733 if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) { 734 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM); 735 brcmf_chip_resetcore(core, 0, 0, 0); 736 } 737 738 if (!brcmf_chip_set_active(devinfo->ci, resetintr)) 739 return -EIO; 740 return 0; 741 } 742 743 744 static int 745 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data) 746 { 747 struct brcmf_pcie_shared_info *shared; 748 struct brcmf_core *core; 749 u32 addr; 750 u32 cur_htod_mb_data; 751 u32 i; 752 753 shared = &devinfo->shared; 754 addr = shared->htod_mb_data_addr; 755 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 756 757 if (cur_htod_mb_data != 0) 758 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n", 759 cur_htod_mb_data); 760 761 i = 0; 762 while (cur_htod_mb_data != 0) { 763 msleep(10); 764 i++; 765 if (i > 100) 766 return -EIO; 767 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 768 } 769 770 brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data); 771 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 772 773 /* Send mailbox interrupt twice as a hardware workaround */ 774 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 775 if (core->rev <= 13) 776 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1); 777 778 return 0; 779 } 780 781 782 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo) 783 { 784 struct brcmf_pcie_shared_info *shared; 785 u32 addr; 786 u32 dtoh_mb_data; 787 788 shared = &devinfo->shared; 789 addr = shared->dtoh_mb_data_addr; 790 dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr); 791 792 if (!dtoh_mb_data) 793 return; 794 795 brcmf_pcie_write_tcm32(devinfo, addr, 0); 796 797 brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data); 798 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) { 799 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n"); 800 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK); 801 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n"); 802 } 803 if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE) 804 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n"); 805 if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) { 806 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n"); 807 devinfo->mbdata_completed = true; 808 wake_up(&devinfo->mbdata_resp_wait); 809 } 810 if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) { 811 brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n"); 812 brcmf_fw_crashed(&devinfo->pdev->dev); 813 } 814 } 815 816 817 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo) 818 { 819 struct brcmf_pcie_shared_info *shared; 820 struct brcmf_pcie_console *console; 821 u32 addr; 822 823 shared = &devinfo->shared; 824 console = &shared->console; 825 addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET; 826 console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr); 827 828 addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET; 829 console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr); 830 addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET; 831 console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr); 832 833 brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n", 834 console->base_addr, console->buf_addr, console->bufsize); 835 } 836 837 /** 838 * brcmf_pcie_bus_console_read - reads firmware messages 839 * 840 * @devinfo: pointer to the device data structure 841 * @error: specifies if error has occurred (prints messages unconditionally) 842 */ 843 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo, 844 bool error) 845 { 846 struct pci_dev *pdev = devinfo->pdev; 847 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 848 struct brcmf_pcie_console *console; 849 u32 addr; 850 u8 ch; 851 u32 newidx; 852 853 if (!error && !BRCMF_FWCON_ON()) 854 return; 855 856 console = &devinfo->shared.console; 857 if (!console->base_addr) 858 return; 859 addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET; 860 newidx = brcmf_pcie_read_tcm32(devinfo, addr); 861 while (newidx != console->read_idx) { 862 addr = console->buf_addr + console->read_idx; 863 ch = brcmf_pcie_read_tcm8(devinfo, addr); 864 console->read_idx++; 865 if (console->read_idx == console->bufsize) 866 console->read_idx = 0; 867 if (ch == '\r') 868 continue; 869 console->log_str[console->log_idx] = ch; 870 console->log_idx++; 871 if ((ch != '\n') && 872 (console->log_idx == (sizeof(console->log_str) - 2))) { 873 ch = '\n'; 874 console->log_str[console->log_idx] = ch; 875 console->log_idx++; 876 } 877 if (ch == '\n') { 878 console->log_str[console->log_idx] = 0; 879 if (error) 880 __brcmf_err(bus, __func__, "CONSOLE: %s", 881 console->log_str); 882 else 883 pr_debug("CONSOLE: %s", console->log_str); 884 console->log_idx = 0; 885 } 886 } 887 } 888 889 890 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo) 891 { 892 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0); 893 } 894 895 896 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo) 897 { 898 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 899 devinfo->reginfo->int_d2h_db | 900 devinfo->reginfo->int_fn0); 901 } 902 903 static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo) 904 { 905 if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1) 906 brcmf_pcie_write_reg32(devinfo, 907 devinfo->reginfo->h2d_mailbox_1, 1); 908 } 909 910 static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg) 911 { 912 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 913 914 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) { 915 brcmf_pcie_intr_disable(devinfo); 916 brcmf_dbg(PCIE, "Enter\n"); 917 return IRQ_WAKE_THREAD; 918 } 919 return IRQ_NONE; 920 } 921 922 923 static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg) 924 { 925 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg; 926 u32 status; 927 928 devinfo->in_irq = true; 929 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint); 930 brcmf_dbg(PCIE, "Enter %x\n", status); 931 if (status) { 932 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, 933 status); 934 if (status & devinfo->reginfo->int_fn0) 935 brcmf_pcie_handle_mb_data(devinfo); 936 if (status & devinfo->reginfo->int_d2h_db) { 937 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 938 brcmf_proto_msgbuf_rx_trigger( 939 &devinfo->pdev->dev); 940 } 941 } 942 brcmf_pcie_bus_console_read(devinfo, false); 943 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP) 944 brcmf_pcie_intr_enable(devinfo); 945 devinfo->in_irq = false; 946 return IRQ_HANDLED; 947 } 948 949 950 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo) 951 { 952 struct pci_dev *pdev = devinfo->pdev; 953 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 954 955 brcmf_pcie_intr_disable(devinfo); 956 957 brcmf_dbg(PCIE, "Enter\n"); 958 959 pci_enable_msi(pdev); 960 if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr, 961 brcmf_pcie_isr_thread, IRQF_SHARED, 962 "brcmf_pcie_intr", devinfo)) { 963 pci_disable_msi(pdev); 964 brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq); 965 return -EIO; 966 } 967 devinfo->irq_allocated = true; 968 return 0; 969 } 970 971 972 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo) 973 { 974 struct pci_dev *pdev = devinfo->pdev; 975 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 976 u32 status; 977 u32 count; 978 979 if (!devinfo->irq_allocated) 980 return; 981 982 brcmf_pcie_intr_disable(devinfo); 983 free_irq(pdev->irq, devinfo); 984 pci_disable_msi(pdev); 985 986 msleep(50); 987 count = 0; 988 while ((devinfo->in_irq) && (count < 20)) { 989 msleep(50); 990 count++; 991 } 992 if (devinfo->in_irq) 993 brcmf_err(bus, "Still in IRQ (processing) !!!\n"); 994 995 status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint); 996 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status); 997 998 devinfo->irq_allocated = false; 999 } 1000 1001 1002 static int brcmf_pcie_ring_mb_write_rptr(void *ctx) 1003 { 1004 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1005 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1006 struct brcmf_commonring *commonring = &ring->commonring; 1007 1008 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1009 return -EIO; 1010 1011 brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr, 1012 commonring->w_ptr, ring->id); 1013 1014 devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr); 1015 1016 return 0; 1017 } 1018 1019 1020 static int brcmf_pcie_ring_mb_write_wptr(void *ctx) 1021 { 1022 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1023 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1024 struct brcmf_commonring *commonring = &ring->commonring; 1025 1026 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1027 return -EIO; 1028 1029 brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr, 1030 commonring->r_ptr, ring->id); 1031 1032 devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr); 1033 1034 return 0; 1035 } 1036 1037 1038 static int brcmf_pcie_ring_mb_ring_bell(void *ctx) 1039 { 1040 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1041 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1042 1043 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1044 return -EIO; 1045 1046 brcmf_dbg(PCIE, "RING !\n"); 1047 /* Any arbitrary value will do, lets use 1 */ 1048 brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1); 1049 1050 return 0; 1051 } 1052 1053 1054 static int brcmf_pcie_ring_mb_update_rptr(void *ctx) 1055 { 1056 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1057 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1058 struct brcmf_commonring *commonring = &ring->commonring; 1059 1060 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1061 return -EIO; 1062 1063 commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr); 1064 1065 brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr, 1066 commonring->w_ptr, ring->id); 1067 1068 return 0; 1069 } 1070 1071 1072 static int brcmf_pcie_ring_mb_update_wptr(void *ctx) 1073 { 1074 struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx; 1075 struct brcmf_pciedev_info *devinfo = ring->devinfo; 1076 struct brcmf_commonring *commonring = &ring->commonring; 1077 1078 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP) 1079 return -EIO; 1080 1081 commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr); 1082 1083 brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr, 1084 commonring->r_ptr, ring->id); 1085 1086 return 0; 1087 } 1088 1089 1090 static void * 1091 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo, 1092 u32 size, u32 tcm_dma_phys_addr, 1093 dma_addr_t *dma_handle) 1094 { 1095 void *ring; 1096 u64 address; 1097 1098 ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle, 1099 GFP_KERNEL); 1100 if (!ring) 1101 return NULL; 1102 1103 address = (u64)*dma_handle; 1104 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr, 1105 address & 0xffffffff); 1106 brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32); 1107 1108 return (ring); 1109 } 1110 1111 1112 static struct brcmf_pcie_ringbuf * 1113 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id, 1114 u32 tcm_ring_phys_addr) 1115 { 1116 void *dma_buf; 1117 dma_addr_t dma_handle; 1118 struct brcmf_pcie_ringbuf *ring; 1119 u32 size; 1120 u32 addr; 1121 const u32 *ring_itemsize_array; 1122 1123 if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7) 1124 ring_itemsize_array = brcmf_ring_itemsize_pre_v7; 1125 else 1126 ring_itemsize_array = brcmf_ring_itemsize; 1127 1128 size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id]; 1129 dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size, 1130 tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET, 1131 &dma_handle); 1132 if (!dma_buf) 1133 return NULL; 1134 1135 addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET; 1136 brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]); 1137 addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET; 1138 brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]); 1139 1140 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 1141 if (!ring) { 1142 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf, 1143 dma_handle); 1144 return NULL; 1145 } 1146 brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id], 1147 ring_itemsize_array[ring_id], dma_buf); 1148 ring->dma_handle = dma_handle; 1149 ring->devinfo = devinfo; 1150 brcmf_commonring_register_cb(&ring->commonring, 1151 brcmf_pcie_ring_mb_ring_bell, 1152 brcmf_pcie_ring_mb_update_rptr, 1153 brcmf_pcie_ring_mb_update_wptr, 1154 brcmf_pcie_ring_mb_write_rptr, 1155 brcmf_pcie_ring_mb_write_wptr, ring); 1156 1157 return (ring); 1158 } 1159 1160 1161 static void brcmf_pcie_release_ringbuffer(struct device *dev, 1162 struct brcmf_pcie_ringbuf *ring) 1163 { 1164 void *dma_buf; 1165 u32 size; 1166 1167 if (!ring) 1168 return; 1169 1170 dma_buf = ring->commonring.buf_addr; 1171 if (dma_buf) { 1172 size = ring->commonring.depth * ring->commonring.item_len; 1173 dma_free_coherent(dev, size, dma_buf, ring->dma_handle); 1174 } 1175 kfree(ring); 1176 } 1177 1178 1179 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo) 1180 { 1181 u32 i; 1182 1183 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1184 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev, 1185 devinfo->shared.commonrings[i]); 1186 devinfo->shared.commonrings[i] = NULL; 1187 } 1188 kfree(devinfo->shared.flowrings); 1189 devinfo->shared.flowrings = NULL; 1190 if (devinfo->idxbuf) { 1191 dma_free_coherent(&devinfo->pdev->dev, 1192 devinfo->idxbuf_sz, 1193 devinfo->idxbuf, 1194 devinfo->idxbuf_dmahandle); 1195 devinfo->idxbuf = NULL; 1196 } 1197 } 1198 1199 1200 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo) 1201 { 1202 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1203 struct brcmf_pcie_ringbuf *ring; 1204 struct brcmf_pcie_ringbuf *rings; 1205 u32 d2h_w_idx_ptr; 1206 u32 d2h_r_idx_ptr; 1207 u32 h2d_w_idx_ptr; 1208 u32 h2d_r_idx_ptr; 1209 u32 ring_mem_ptr; 1210 u32 i; 1211 u64 address; 1212 u32 bufsz; 1213 u8 idx_offset; 1214 struct brcmf_pcie_dhi_ringinfo ringinfo; 1215 u16 max_flowrings; 1216 u16 max_submissionrings; 1217 u16 max_completionrings; 1218 1219 memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr, 1220 sizeof(ringinfo)); 1221 if (devinfo->shared.version >= 6) { 1222 max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings); 1223 max_flowrings = le16_to_cpu(ringinfo.max_flowrings); 1224 max_completionrings = le16_to_cpu(ringinfo.max_completionrings); 1225 } else { 1226 max_submissionrings = le16_to_cpu(ringinfo.max_flowrings); 1227 max_flowrings = max_submissionrings - 1228 BRCMF_NROF_H2D_COMMON_MSGRINGS; 1229 max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS; 1230 } 1231 if (max_flowrings > 512) { 1232 brcmf_err(bus, "invalid max_flowrings(%d)\n", max_flowrings); 1233 return -EIO; 1234 } 1235 1236 if (devinfo->dma_idx_sz != 0) { 1237 bufsz = (max_submissionrings + max_completionrings) * 1238 devinfo->dma_idx_sz * 2; 1239 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz, 1240 &devinfo->idxbuf_dmahandle, 1241 GFP_KERNEL); 1242 if (!devinfo->idxbuf) 1243 devinfo->dma_idx_sz = 0; 1244 } 1245 1246 if (devinfo->dma_idx_sz == 0) { 1247 d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr); 1248 d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr); 1249 h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr); 1250 h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr); 1251 idx_offset = sizeof(u32); 1252 devinfo->write_ptr = brcmf_pcie_write_tcm16; 1253 devinfo->read_ptr = brcmf_pcie_read_tcm16; 1254 brcmf_dbg(PCIE, "Using TCM indices\n"); 1255 } else { 1256 memset(devinfo->idxbuf, 0, bufsz); 1257 devinfo->idxbuf_sz = bufsz; 1258 idx_offset = devinfo->dma_idx_sz; 1259 devinfo->write_ptr = brcmf_pcie_write_idx; 1260 devinfo->read_ptr = brcmf_pcie_read_idx; 1261 1262 h2d_w_idx_ptr = 0; 1263 address = (u64)devinfo->idxbuf_dmahandle; 1264 ringinfo.h2d_w_idx_hostaddr.low_addr = 1265 cpu_to_le32(address & 0xffffffff); 1266 ringinfo.h2d_w_idx_hostaddr.high_addr = 1267 cpu_to_le32(address >> 32); 1268 1269 h2d_r_idx_ptr = h2d_w_idx_ptr + 1270 max_submissionrings * idx_offset; 1271 address += max_submissionrings * idx_offset; 1272 ringinfo.h2d_r_idx_hostaddr.low_addr = 1273 cpu_to_le32(address & 0xffffffff); 1274 ringinfo.h2d_r_idx_hostaddr.high_addr = 1275 cpu_to_le32(address >> 32); 1276 1277 d2h_w_idx_ptr = h2d_r_idx_ptr + 1278 max_submissionrings * idx_offset; 1279 address += max_submissionrings * idx_offset; 1280 ringinfo.d2h_w_idx_hostaddr.low_addr = 1281 cpu_to_le32(address & 0xffffffff); 1282 ringinfo.d2h_w_idx_hostaddr.high_addr = 1283 cpu_to_le32(address >> 32); 1284 1285 d2h_r_idx_ptr = d2h_w_idx_ptr + 1286 max_completionrings * idx_offset; 1287 address += max_completionrings * idx_offset; 1288 ringinfo.d2h_r_idx_hostaddr.low_addr = 1289 cpu_to_le32(address & 0xffffffff); 1290 ringinfo.d2h_r_idx_hostaddr.high_addr = 1291 cpu_to_le32(address >> 32); 1292 1293 memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr, 1294 &ringinfo, sizeof(ringinfo)); 1295 brcmf_dbg(PCIE, "Using host memory indices\n"); 1296 } 1297 1298 ring_mem_ptr = le32_to_cpu(ringinfo.ringmem); 1299 1300 for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) { 1301 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1302 if (!ring) 1303 goto fail; 1304 ring->w_idx_addr = h2d_w_idx_ptr; 1305 ring->r_idx_addr = h2d_r_idx_ptr; 1306 ring->id = i; 1307 devinfo->shared.commonrings[i] = ring; 1308 1309 h2d_w_idx_ptr += idx_offset; 1310 h2d_r_idx_ptr += idx_offset; 1311 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1312 } 1313 1314 for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS; 1315 i < BRCMF_NROF_COMMON_MSGRINGS; i++) { 1316 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr); 1317 if (!ring) 1318 goto fail; 1319 ring->w_idx_addr = d2h_w_idx_ptr; 1320 ring->r_idx_addr = d2h_r_idx_ptr; 1321 ring->id = i; 1322 devinfo->shared.commonrings[i] = ring; 1323 1324 d2h_w_idx_ptr += idx_offset; 1325 d2h_r_idx_ptr += idx_offset; 1326 ring_mem_ptr += BRCMF_RING_MEM_SZ; 1327 } 1328 1329 devinfo->shared.max_flowrings = max_flowrings; 1330 devinfo->shared.max_submissionrings = max_submissionrings; 1331 devinfo->shared.max_completionrings = max_completionrings; 1332 rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL); 1333 if (!rings) 1334 goto fail; 1335 1336 brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings); 1337 1338 for (i = 0; i < max_flowrings; i++) { 1339 ring = &rings[i]; 1340 ring->devinfo = devinfo; 1341 ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART; 1342 brcmf_commonring_register_cb(&ring->commonring, 1343 brcmf_pcie_ring_mb_ring_bell, 1344 brcmf_pcie_ring_mb_update_rptr, 1345 brcmf_pcie_ring_mb_update_wptr, 1346 brcmf_pcie_ring_mb_write_rptr, 1347 brcmf_pcie_ring_mb_write_wptr, 1348 ring); 1349 ring->w_idx_addr = h2d_w_idx_ptr; 1350 ring->r_idx_addr = h2d_r_idx_ptr; 1351 h2d_w_idx_ptr += idx_offset; 1352 h2d_r_idx_ptr += idx_offset; 1353 } 1354 devinfo->shared.flowrings = rings; 1355 1356 return 0; 1357 1358 fail: 1359 brcmf_err(bus, "Allocating ring buffers failed\n"); 1360 brcmf_pcie_release_ringbuffers(devinfo); 1361 return -ENOMEM; 1362 } 1363 1364 1365 static void 1366 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1367 { 1368 if (devinfo->shared.scratch) 1369 dma_free_coherent(&devinfo->pdev->dev, 1370 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1371 devinfo->shared.scratch, 1372 devinfo->shared.scratch_dmahandle); 1373 if (devinfo->shared.ringupd) 1374 dma_free_coherent(&devinfo->pdev->dev, 1375 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1376 devinfo->shared.ringupd, 1377 devinfo->shared.ringupd_dmahandle); 1378 } 1379 1380 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo) 1381 { 1382 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1383 u64 address; 1384 u32 addr; 1385 1386 devinfo->shared.scratch = 1387 dma_alloc_coherent(&devinfo->pdev->dev, 1388 BRCMF_DMA_D2H_SCRATCH_BUF_LEN, 1389 &devinfo->shared.scratch_dmahandle, 1390 GFP_KERNEL); 1391 if (!devinfo->shared.scratch) 1392 goto fail; 1393 1394 addr = devinfo->shared.tcm_base_address + 1395 BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET; 1396 address = (u64)devinfo->shared.scratch_dmahandle; 1397 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1398 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1399 addr = devinfo->shared.tcm_base_address + 1400 BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET; 1401 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN); 1402 1403 devinfo->shared.ringupd = 1404 dma_alloc_coherent(&devinfo->pdev->dev, 1405 BRCMF_DMA_D2H_RINGUPD_BUF_LEN, 1406 &devinfo->shared.ringupd_dmahandle, 1407 GFP_KERNEL); 1408 if (!devinfo->shared.ringupd) 1409 goto fail; 1410 1411 addr = devinfo->shared.tcm_base_address + 1412 BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET; 1413 address = (u64)devinfo->shared.ringupd_dmahandle; 1414 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff); 1415 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32); 1416 addr = devinfo->shared.tcm_base_address + 1417 BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET; 1418 brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN); 1419 return 0; 1420 1421 fail: 1422 brcmf_err(bus, "Allocating scratch buffers failed\n"); 1423 brcmf_pcie_release_scratchbuffers(devinfo); 1424 return -ENOMEM; 1425 } 1426 1427 1428 static void brcmf_pcie_down(struct device *dev) 1429 { 1430 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1431 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie; 1432 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 1433 1434 brcmf_pcie_fwcon_timer(devinfo, false); 1435 } 1436 1437 static int brcmf_pcie_preinit(struct device *dev) 1438 { 1439 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1440 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1441 1442 brcmf_dbg(PCIE, "Enter\n"); 1443 1444 brcmf_pcie_intr_enable(buspub->devinfo); 1445 brcmf_pcie_hostready(buspub->devinfo); 1446 1447 return 0; 1448 } 1449 1450 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb) 1451 { 1452 return 0; 1453 } 1454 1455 1456 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg, 1457 uint len) 1458 { 1459 return 0; 1460 } 1461 1462 1463 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg, 1464 uint len) 1465 { 1466 return 0; 1467 } 1468 1469 1470 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled) 1471 { 1472 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1473 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1474 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1475 1476 brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled); 1477 devinfo->wowl_enabled = enabled; 1478 } 1479 1480 1481 static size_t brcmf_pcie_get_ramsize(struct device *dev) 1482 { 1483 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1484 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1485 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1486 1487 return devinfo->ci->ramsize - devinfo->ci->srsize; 1488 } 1489 1490 1491 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len) 1492 { 1493 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1494 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1495 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1496 1497 brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len); 1498 brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len); 1499 return 0; 1500 } 1501 1502 static int brcmf_pcie_get_blob(struct device *dev, const struct firmware **fw, 1503 enum brcmf_blob_type type) 1504 { 1505 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1506 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1507 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1508 1509 switch (type) { 1510 case BRCMF_BLOB_CLM: 1511 *fw = devinfo->clm_fw; 1512 devinfo->clm_fw = NULL; 1513 break; 1514 default: 1515 return -ENOENT; 1516 } 1517 1518 if (!*fw) 1519 return -ENOENT; 1520 1521 return 0; 1522 } 1523 1524 static int brcmf_pcie_reset(struct device *dev) 1525 { 1526 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 1527 struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie; 1528 struct brcmf_pciedev_info *devinfo = buspub->devinfo; 1529 struct brcmf_fw_request *fwreq; 1530 int err; 1531 1532 brcmf_pcie_intr_disable(devinfo); 1533 1534 brcmf_pcie_bus_console_read(devinfo, true); 1535 1536 brcmf_detach(dev); 1537 1538 brcmf_pcie_release_irq(devinfo); 1539 brcmf_pcie_release_scratchbuffers(devinfo); 1540 brcmf_pcie_release_ringbuffers(devinfo); 1541 brcmf_pcie_reset_device(devinfo); 1542 1543 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 1544 if (!fwreq) { 1545 dev_err(dev, "Failed to prepare FW request\n"); 1546 return -ENOMEM; 1547 } 1548 1549 err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup); 1550 if (err) { 1551 dev_err(dev, "Failed to prepare FW request\n"); 1552 kfree(fwreq); 1553 } 1554 1555 return err; 1556 } 1557 1558 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = { 1559 .preinit = brcmf_pcie_preinit, 1560 .txdata = brcmf_pcie_tx, 1561 .stop = brcmf_pcie_down, 1562 .txctl = brcmf_pcie_tx_ctlpkt, 1563 .rxctl = brcmf_pcie_rx_ctlpkt, 1564 .wowl_config = brcmf_pcie_wowl_config, 1565 .get_ramsize = brcmf_pcie_get_ramsize, 1566 .get_memdump = brcmf_pcie_get_memdump, 1567 .get_blob = brcmf_pcie_get_blob, 1568 .reset = brcmf_pcie_reset, 1569 .debugfs_create = brcmf_pcie_debugfs_create, 1570 }; 1571 1572 1573 static void 1574 brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data, 1575 u32 data_len) 1576 { 1577 __le32 *field; 1578 u32 newsize; 1579 1580 if (data_len < BRCMF_RAMSIZE_OFFSET + 8) 1581 return; 1582 1583 field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET]; 1584 if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC) 1585 return; 1586 field++; 1587 newsize = le32_to_cpup(field); 1588 1589 brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n", 1590 newsize); 1591 devinfo->ci->ramsize = newsize; 1592 } 1593 1594 1595 static int 1596 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo, 1597 u32 sharedram_addr) 1598 { 1599 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1600 struct brcmf_pcie_shared_info *shared; 1601 u32 addr; 1602 1603 shared = &devinfo->shared; 1604 shared->tcm_base_address = sharedram_addr; 1605 1606 shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr); 1607 shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK); 1608 brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version); 1609 if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) || 1610 (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) { 1611 brcmf_err(bus, "Unsupported PCIE version %d\n", 1612 shared->version); 1613 return -EINVAL; 1614 } 1615 1616 /* check firmware support dma indicies */ 1617 if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) { 1618 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX) 1619 devinfo->dma_idx_sz = sizeof(u16); 1620 else 1621 devinfo->dma_idx_sz = sizeof(u32); 1622 } 1623 1624 addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET; 1625 shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr); 1626 if (shared->max_rxbufpost == 0) 1627 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST; 1628 1629 addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET; 1630 shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr); 1631 1632 addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET; 1633 shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1634 1635 addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET; 1636 shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1637 1638 addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET; 1639 shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr); 1640 1641 brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n", 1642 shared->max_rxbufpost, shared->rx_dataoffset); 1643 1644 brcmf_pcie_bus_console_init(devinfo); 1645 brcmf_pcie_bus_console_read(devinfo, false); 1646 1647 return 0; 1648 } 1649 1650 1651 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo, 1652 const struct firmware *fw, void *nvram, 1653 u32 nvram_len) 1654 { 1655 struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev); 1656 u32 sharedram_addr; 1657 u32 sharedram_addr_written; 1658 u32 loop_counter; 1659 int err; 1660 u32 address; 1661 u32 resetintr; 1662 1663 brcmf_dbg(PCIE, "Halt ARM.\n"); 1664 err = brcmf_pcie_enter_download_state(devinfo); 1665 if (err) 1666 return err; 1667 1668 brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name); 1669 memcpy_toio(devinfo->tcm + devinfo->ci->rambase, 1670 (void *)fw->data, fw->size); 1671 1672 resetintr = get_unaligned_le32(fw->data); 1673 release_firmware(fw); 1674 1675 /* reset last 4 bytes of RAM address. to be used for shared 1676 * area. This identifies when FW is running 1677 */ 1678 brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0); 1679 1680 if (nvram) { 1681 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name); 1682 address = devinfo->ci->rambase + devinfo->ci->ramsize - 1683 nvram_len; 1684 memcpy_toio(devinfo->tcm + address, nvram, nvram_len); 1685 brcmf_fw_nvram_free(nvram); 1686 } else { 1687 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n", 1688 devinfo->nvram_name); 1689 } 1690 1691 sharedram_addr_written = brcmf_pcie_read_ram32(devinfo, 1692 devinfo->ci->ramsize - 1693 4); 1694 brcmf_dbg(PCIE, "Bring ARM in running state\n"); 1695 err = brcmf_pcie_exit_download_state(devinfo, resetintr); 1696 if (err) 1697 return err; 1698 1699 brcmf_dbg(PCIE, "Wait for FW init\n"); 1700 sharedram_addr = sharedram_addr_written; 1701 loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50; 1702 while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) { 1703 msleep(50); 1704 sharedram_addr = brcmf_pcie_read_ram32(devinfo, 1705 devinfo->ci->ramsize - 1706 4); 1707 loop_counter--; 1708 } 1709 if (sharedram_addr == sharedram_addr_written) { 1710 brcmf_err(bus, "FW failed to initialize\n"); 1711 return -ENODEV; 1712 } 1713 if (sharedram_addr < devinfo->ci->rambase || 1714 sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) { 1715 brcmf_err(bus, "Invalid shared RAM address 0x%08x\n", 1716 sharedram_addr); 1717 return -ENODEV; 1718 } 1719 brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr); 1720 1721 return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr)); 1722 } 1723 1724 1725 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo) 1726 { 1727 struct pci_dev *pdev = devinfo->pdev; 1728 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1729 int err; 1730 phys_addr_t bar0_addr, bar1_addr; 1731 ulong bar1_size; 1732 1733 err = pci_enable_device(pdev); 1734 if (err) { 1735 brcmf_err(bus, "pci_enable_device failed err=%d\n", err); 1736 return err; 1737 } 1738 1739 pci_set_master(pdev); 1740 1741 /* Bar-0 mapped address */ 1742 bar0_addr = pci_resource_start(pdev, 0); 1743 /* Bar-1 mapped address */ 1744 bar1_addr = pci_resource_start(pdev, 2); 1745 /* read Bar-1 mapped memory range */ 1746 bar1_size = pci_resource_len(pdev, 2); 1747 if ((bar1_size == 0) || (bar1_addr == 0)) { 1748 brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n", 1749 bar1_size, (unsigned long long)bar1_addr); 1750 return -EINVAL; 1751 } 1752 1753 devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE); 1754 devinfo->tcm = ioremap(bar1_addr, bar1_size); 1755 1756 if (!devinfo->regs || !devinfo->tcm) { 1757 brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs, 1758 devinfo->tcm); 1759 return -EINVAL; 1760 } 1761 brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n", 1762 devinfo->regs, (unsigned long long)bar0_addr); 1763 brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n", 1764 devinfo->tcm, (unsigned long long)bar1_addr, 1765 (unsigned int)bar1_size); 1766 1767 return 0; 1768 } 1769 1770 1771 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo) 1772 { 1773 if (devinfo->tcm) 1774 iounmap(devinfo->tcm); 1775 if (devinfo->regs) 1776 iounmap(devinfo->regs); 1777 1778 pci_disable_device(devinfo->pdev); 1779 } 1780 1781 1782 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr) 1783 { 1784 u32 ret_addr; 1785 1786 ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1); 1787 addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1); 1788 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr); 1789 1790 return ret_addr; 1791 } 1792 1793 1794 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr) 1795 { 1796 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1797 1798 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1799 return brcmf_pcie_read_reg32(devinfo, addr); 1800 } 1801 1802 1803 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value) 1804 { 1805 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1806 1807 addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr); 1808 brcmf_pcie_write_reg32(devinfo, addr, value); 1809 } 1810 1811 1812 static int brcmf_pcie_buscoreprep(void *ctx) 1813 { 1814 return brcmf_pcie_get_resource(ctx); 1815 } 1816 1817 1818 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip) 1819 { 1820 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1821 struct brcmf_core *core; 1822 u32 val, reg; 1823 1824 devinfo->ci = chip; 1825 brcmf_pcie_reset_device(devinfo); 1826 1827 /* reginfo is not ready yet */ 1828 core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2); 1829 if (core->rev >= 64) 1830 reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT; 1831 else 1832 reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT; 1833 1834 val = brcmf_pcie_read_reg32(devinfo, reg); 1835 if (val != 0xffffffff) 1836 brcmf_pcie_write_reg32(devinfo, reg, val); 1837 1838 return 0; 1839 } 1840 1841 1842 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip, 1843 u32 rstvec) 1844 { 1845 struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx; 1846 1847 brcmf_pcie_write_tcm32(devinfo, 0, rstvec); 1848 } 1849 1850 1851 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = { 1852 .prepare = brcmf_pcie_buscoreprep, 1853 .reset = brcmf_pcie_buscore_reset, 1854 .activate = brcmf_pcie_buscore_activate, 1855 .read32 = brcmf_pcie_buscore_read32, 1856 .write32 = brcmf_pcie_buscore_write32, 1857 }; 1858 1859 #define BRCMF_OTP_SYS_VENDOR 0x15 1860 #define BRCMF_OTP_BRCM_CIS 0x80 1861 1862 #define BRCMF_OTP_VENDOR_HDR 0x00000008 1863 1864 static int 1865 brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info *devinfo, 1866 u8 *data, size_t size) 1867 { 1868 int idx = 4; 1869 const char *chip_params; 1870 const char *board_params; 1871 const char *p; 1872 1873 /* 4-byte header and two empty strings */ 1874 if (size < 6) 1875 return -EINVAL; 1876 1877 if (get_unaligned_le32(data) != BRCMF_OTP_VENDOR_HDR) 1878 return -EINVAL; 1879 1880 chip_params = &data[idx]; 1881 1882 /* Skip first string, including terminator */ 1883 idx += strnlen(chip_params, size - idx) + 1; 1884 if (idx >= size) 1885 return -EINVAL; 1886 1887 board_params = &data[idx]; 1888 1889 /* Skip to terminator of second string */ 1890 idx += strnlen(board_params, size - idx); 1891 if (idx >= size) 1892 return -EINVAL; 1893 1894 /* At this point both strings are guaranteed NUL-terminated */ 1895 brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n", 1896 chip_params, board_params); 1897 1898 p = skip_spaces(board_params); 1899 while (*p) { 1900 char tag = *p++; 1901 const char *end; 1902 size_t len; 1903 1904 if (*p++ != '=') /* implicit NUL check */ 1905 return -EINVAL; 1906 1907 /* *p might be NUL here, if so end == p and len == 0 */ 1908 end = strchrnul(p, ' '); 1909 len = end - p; 1910 1911 /* leave 1 byte for NUL in destination string */ 1912 if (len > (BRCMF_OTP_MAX_PARAM_LEN - 1)) 1913 return -EINVAL; 1914 1915 /* Copy len characters plus a NUL terminator */ 1916 switch (tag) { 1917 case 'M': 1918 strscpy(devinfo->otp.module, p, len + 1); 1919 break; 1920 case 'V': 1921 strscpy(devinfo->otp.vendor, p, len + 1); 1922 break; 1923 case 'm': 1924 strscpy(devinfo->otp.version, p, len + 1); 1925 break; 1926 } 1927 1928 /* Skip to next arg, if any */ 1929 p = skip_spaces(end); 1930 } 1931 1932 brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n", 1933 devinfo->otp.module, devinfo->otp.vendor, 1934 devinfo->otp.version); 1935 1936 if (!devinfo->otp.module[0] || 1937 !devinfo->otp.vendor[0] || 1938 !devinfo->otp.version[0]) 1939 return -EINVAL; 1940 1941 devinfo->otp.valid = true; 1942 return 0; 1943 } 1944 1945 static int 1946 brcmf_pcie_parse_otp(struct brcmf_pciedev_info *devinfo, u8 *otp, size_t size) 1947 { 1948 int p = 0; 1949 int ret = -EINVAL; 1950 1951 brcmf_dbg(PCIE, "parse_otp size=%zd\n", size); 1952 1953 while (p < (size - 1)) { 1954 u8 type = otp[p]; 1955 u8 length = otp[p + 1]; 1956 1957 if (type == 0) 1958 break; 1959 1960 if ((p + 2 + length) > size) 1961 break; 1962 1963 switch (type) { 1964 case BRCMF_OTP_SYS_VENDOR: 1965 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n", 1966 p, length); 1967 ret = brcmf_pcie_parse_otp_sys_vendor(devinfo, 1968 &otp[p + 2], 1969 length); 1970 break; 1971 case BRCMF_OTP_BRCM_CIS: 1972 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n", 1973 p, length); 1974 break; 1975 default: 1976 brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n", 1977 p, length, type); 1978 break; 1979 } 1980 1981 p += 2 + length; 1982 } 1983 1984 return ret; 1985 } 1986 1987 static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo) 1988 { 1989 const struct pci_dev *pdev = devinfo->pdev; 1990 struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); 1991 u32 coreid, base, words, idx, sromctl; 1992 u16 *otp; 1993 struct brcmf_core *core; 1994 int ret; 1995 1996 switch (devinfo->ci->chip) { 1997 case BRCM_CC_4378_CHIP_ID: 1998 coreid = BCMA_CORE_GCI; 1999 base = 0x1120; 2000 words = 0x170; 2001 break; 2002 default: 2003 /* OTP not supported on this chip */ 2004 return 0; 2005 } 2006 2007 core = brcmf_chip_get_core(devinfo->ci, coreid); 2008 if (!core) { 2009 brcmf_err(bus, "No OTP core\n"); 2010 return -ENODEV; 2011 } 2012 2013 if (coreid == BCMA_CORE_CHIPCOMMON) { 2014 /* Chips with OTP accessed via ChipCommon need additional 2015 * handling to access the OTP 2016 */ 2017 brcmf_pcie_select_core(devinfo, coreid); 2018 sromctl = READCC32(devinfo, sromcontrol); 2019 2020 if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) { 2021 /* Chip lacks OTP, try without it... */ 2022 brcmf_err(bus, 2023 "OTP unavailable, using default firmware\n"); 2024 return 0; 2025 } 2026 2027 /* Map OTP to shadow area */ 2028 WRITECC32(devinfo, sromcontrol, 2029 sromctl | BCMA_CC_SROM_CONTROL_OTPSEL); 2030 } 2031 2032 otp = kcalloc(words, sizeof(u16), GFP_KERNEL); 2033 if (!otp) 2034 return -ENOMEM; 2035 2036 /* Map bus window to SROM/OTP shadow area in core */ 2037 base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base); 2038 2039 brcmf_dbg(PCIE, "OTP data:\n"); 2040 for (idx = 0; idx < words; idx++) { 2041 otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx); 2042 brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]); 2043 } 2044 2045 if (coreid == BCMA_CORE_CHIPCOMMON) { 2046 brcmf_pcie_select_core(devinfo, coreid); 2047 WRITECC32(devinfo, sromcontrol, sromctl); 2048 } 2049 2050 ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words); 2051 kfree(otp); 2052 2053 return ret; 2054 } 2055 2056 #define BRCMF_PCIE_FW_CODE 0 2057 #define BRCMF_PCIE_FW_NVRAM 1 2058 #define BRCMF_PCIE_FW_CLM 2 2059 2060 static void brcmf_pcie_setup(struct device *dev, int ret, 2061 struct brcmf_fw_request *fwreq) 2062 { 2063 const struct firmware *fw; 2064 void *nvram; 2065 struct brcmf_bus *bus; 2066 struct brcmf_pciedev *pcie_bus_dev; 2067 struct brcmf_pciedev_info *devinfo; 2068 struct brcmf_commonring **flowrings; 2069 u32 i, nvram_len; 2070 2071 bus = dev_get_drvdata(dev); 2072 pcie_bus_dev = bus->bus_priv.pcie; 2073 devinfo = pcie_bus_dev->devinfo; 2074 2075 /* check firmware loading result */ 2076 if (ret) 2077 goto fail; 2078 2079 brcmf_pcie_attach(devinfo); 2080 2081 fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary; 2082 nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data; 2083 nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len; 2084 devinfo->clm_fw = fwreq->items[BRCMF_PCIE_FW_CLM].binary; 2085 kfree(fwreq); 2086 2087 ret = brcmf_chip_get_raminfo(devinfo->ci); 2088 if (ret) { 2089 brcmf_err(bus, "Failed to get RAM info\n"); 2090 release_firmware(fw); 2091 brcmf_fw_nvram_free(nvram); 2092 goto fail; 2093 } 2094 2095 /* Some of the firmwares have the size of the memory of the device 2096 * defined inside the firmware. This is because part of the memory in 2097 * the device is shared and the devision is determined by FW. Parse 2098 * the firmware and adjust the chip memory size now. 2099 */ 2100 brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size); 2101 2102 ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len); 2103 if (ret) 2104 goto fail; 2105 2106 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2107 2108 ret = brcmf_pcie_init_ringbuffers(devinfo); 2109 if (ret) 2110 goto fail; 2111 2112 ret = brcmf_pcie_init_scratchbuffers(devinfo); 2113 if (ret) 2114 goto fail; 2115 2116 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2117 ret = brcmf_pcie_request_irq(devinfo); 2118 if (ret) 2119 goto fail; 2120 2121 /* hook the commonrings in the bus structure. */ 2122 for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) 2123 bus->msgbuf->commonrings[i] = 2124 &devinfo->shared.commonrings[i]->commonring; 2125 2126 flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings), 2127 GFP_KERNEL); 2128 if (!flowrings) 2129 goto fail; 2130 2131 for (i = 0; i < devinfo->shared.max_flowrings; i++) 2132 flowrings[i] = &devinfo->shared.flowrings[i].commonring; 2133 bus->msgbuf->flowrings = flowrings; 2134 2135 bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset; 2136 bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost; 2137 bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings; 2138 2139 init_waitqueue_head(&devinfo->mbdata_resp_wait); 2140 2141 ret = brcmf_attach(&devinfo->pdev->dev); 2142 if (ret) 2143 goto fail; 2144 2145 brcmf_pcie_bus_console_read(devinfo, false); 2146 2147 brcmf_pcie_fwcon_timer(devinfo, true); 2148 2149 return; 2150 2151 fail: 2152 brcmf_err(bus, "Dongle setup failed\n"); 2153 brcmf_pcie_bus_console_read(devinfo, true); 2154 brcmf_fw_crashed(dev); 2155 device_release_driver(dev); 2156 } 2157 2158 static struct brcmf_fw_request * 2159 brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo) 2160 { 2161 struct brcmf_fw_request *fwreq; 2162 struct brcmf_fw_name fwnames[] = { 2163 { ".bin", devinfo->fw_name }, 2164 { ".txt", devinfo->nvram_name }, 2165 { ".clm_blob", devinfo->clm_name }, 2166 }; 2167 2168 fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, 2169 brcmf_pcie_fwnames, 2170 ARRAY_SIZE(brcmf_pcie_fwnames), 2171 fwnames, ARRAY_SIZE(fwnames)); 2172 if (!fwreq) 2173 return NULL; 2174 2175 fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 2176 fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 2177 fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL; 2178 fwreq->items[BRCMF_PCIE_FW_CLM].type = BRCMF_FW_TYPE_BINARY; 2179 fwreq->items[BRCMF_PCIE_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL; 2180 /* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */ 2181 fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1; 2182 fwreq->bus_nr = devinfo->pdev->bus->number; 2183 2184 /* Apple platforms with fancy firmware/NVRAM selection */ 2185 if (devinfo->settings->board_type && 2186 devinfo->settings->antenna_sku && 2187 devinfo->otp.valid) { 2188 const struct brcmf_otp_params *otp = &devinfo->otp; 2189 struct device *dev = &devinfo->pdev->dev; 2190 const char **bt = fwreq->board_types; 2191 2192 brcmf_dbg(PCIE, "Apple board: %s\n", 2193 devinfo->settings->board_type); 2194 2195 /* Example: apple,shikoku-RASP-m-6.11-X3 */ 2196 bt[0] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s-%s", 2197 devinfo->settings->board_type, 2198 otp->module, otp->vendor, otp->version, 2199 devinfo->settings->antenna_sku); 2200 bt[1] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s", 2201 devinfo->settings->board_type, 2202 otp->module, otp->vendor, otp->version); 2203 bt[2] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s", 2204 devinfo->settings->board_type, 2205 otp->module, otp->vendor); 2206 bt[3] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", 2207 devinfo->settings->board_type, 2208 otp->module); 2209 bt[4] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", 2210 devinfo->settings->board_type, 2211 devinfo->settings->antenna_sku); 2212 bt[5] = devinfo->settings->board_type; 2213 2214 if (!bt[0] || !bt[1] || !bt[2] || !bt[3] || !bt[4]) { 2215 kfree(fwreq); 2216 return NULL; 2217 } 2218 } else { 2219 brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type); 2220 fwreq->board_types[0] = devinfo->settings->board_type; 2221 } 2222 2223 return fwreq; 2224 } 2225 2226 #ifdef DEBUG 2227 static void 2228 brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active) 2229 { 2230 if (!active) { 2231 if (devinfo->console_active) { 2232 del_timer_sync(&devinfo->timer); 2233 devinfo->console_active = false; 2234 } 2235 return; 2236 } 2237 2238 /* don't start the timer */ 2239 if (devinfo->state != BRCMFMAC_PCIE_STATE_UP || 2240 !devinfo->console_interval || !BRCMF_FWCON_ON()) 2241 return; 2242 2243 if (!devinfo->console_active) { 2244 devinfo->timer.expires = jiffies + devinfo->console_interval; 2245 add_timer(&devinfo->timer); 2246 devinfo->console_active = true; 2247 } else { 2248 /* Reschedule the timer */ 2249 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval); 2250 } 2251 } 2252 2253 static void 2254 brcmf_pcie_fwcon(struct timer_list *t) 2255 { 2256 struct brcmf_pciedev_info *devinfo = from_timer(devinfo, t, timer); 2257 2258 if (!devinfo->console_active) 2259 return; 2260 2261 brcmf_pcie_bus_console_read(devinfo, false); 2262 2263 /* Reschedule the timer if console interval is not zero */ 2264 mod_timer(&devinfo->timer, jiffies + devinfo->console_interval); 2265 } 2266 2267 static int brcmf_pcie_console_interval_get(void *data, u64 *val) 2268 { 2269 struct brcmf_pciedev_info *devinfo = data; 2270 2271 *val = devinfo->console_interval; 2272 2273 return 0; 2274 } 2275 2276 static int brcmf_pcie_console_interval_set(void *data, u64 val) 2277 { 2278 struct brcmf_pciedev_info *devinfo = data; 2279 2280 if (val > MAX_CONSOLE_INTERVAL) 2281 return -EINVAL; 2282 2283 devinfo->console_interval = val; 2284 2285 if (!val && devinfo->console_active) 2286 brcmf_pcie_fwcon_timer(devinfo, false); 2287 else if (val) 2288 brcmf_pcie_fwcon_timer(devinfo, true); 2289 2290 return 0; 2291 } 2292 2293 DEFINE_SIMPLE_ATTRIBUTE(brcmf_pcie_console_interval_fops, 2294 brcmf_pcie_console_interval_get, 2295 brcmf_pcie_console_interval_set, 2296 "%llu\n"); 2297 2298 static void brcmf_pcie_debugfs_create(struct device *dev) 2299 { 2300 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2301 struct brcmf_pub *drvr = bus_if->drvr; 2302 struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie; 2303 struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo; 2304 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 2305 2306 if (IS_ERR_OR_NULL(dentry)) 2307 return; 2308 2309 devinfo->console_interval = BRCMF_CONSOLE; 2310 2311 debugfs_create_file("console_interval", 0644, dentry, devinfo, 2312 &brcmf_pcie_console_interval_fops); 2313 } 2314 2315 #else 2316 void brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active) 2317 { 2318 } 2319 2320 static void brcmf_pcie_debugfs_create(struct device *dev) 2321 { 2322 } 2323 #endif 2324 2325 static int 2326 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2327 { 2328 int ret; 2329 struct brcmf_fw_request *fwreq; 2330 struct brcmf_pciedev_info *devinfo; 2331 struct brcmf_pciedev *pcie_bus_dev; 2332 struct brcmf_core *core; 2333 struct brcmf_bus *bus; 2334 2335 brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device); 2336 2337 ret = -ENOMEM; 2338 devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL); 2339 if (devinfo == NULL) 2340 return ret; 2341 2342 devinfo->pdev = pdev; 2343 pcie_bus_dev = NULL; 2344 devinfo->ci = brcmf_chip_attach(devinfo, pdev->device, 2345 &brcmf_pcie_buscore_ops); 2346 if (IS_ERR(devinfo->ci)) { 2347 ret = PTR_ERR(devinfo->ci); 2348 devinfo->ci = NULL; 2349 goto fail; 2350 } 2351 2352 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2); 2353 if (core->rev >= 64) 2354 devinfo->reginfo = &brcmf_reginfo_64; 2355 else 2356 devinfo->reginfo = &brcmf_reginfo_default; 2357 2358 pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL); 2359 if (pcie_bus_dev == NULL) { 2360 ret = -ENOMEM; 2361 goto fail; 2362 } 2363 2364 devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev, 2365 BRCMF_BUSTYPE_PCIE, 2366 devinfo->ci->chip, 2367 devinfo->ci->chiprev); 2368 if (!devinfo->settings) { 2369 ret = -ENOMEM; 2370 goto fail; 2371 } 2372 2373 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 2374 if (!bus) { 2375 ret = -ENOMEM; 2376 goto fail; 2377 } 2378 bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL); 2379 if (!bus->msgbuf) { 2380 ret = -ENOMEM; 2381 kfree(bus); 2382 goto fail; 2383 } 2384 2385 /* hook it all together. */ 2386 pcie_bus_dev->devinfo = devinfo; 2387 pcie_bus_dev->bus = bus; 2388 bus->dev = &pdev->dev; 2389 bus->bus_priv.pcie = pcie_bus_dev; 2390 bus->ops = &brcmf_pcie_bus_ops; 2391 bus->proto_type = BRCMF_PROTO_MSGBUF; 2392 bus->fwvid = id->driver_data; 2393 bus->chip = devinfo->coreid; 2394 bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot); 2395 dev_set_drvdata(&pdev->dev, bus); 2396 2397 ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings); 2398 if (ret) 2399 goto fail_bus; 2400 2401 ret = brcmf_pcie_read_otp(devinfo); 2402 if (ret) { 2403 brcmf_err(bus, "failed to parse OTP\n"); 2404 goto fail_brcmf; 2405 } 2406 2407 #ifdef DEBUG 2408 /* Set up the fwcon timer */ 2409 timer_setup(&devinfo->timer, brcmf_pcie_fwcon, 0); 2410 #endif 2411 2412 fwreq = brcmf_pcie_prepare_fw_request(devinfo); 2413 if (!fwreq) { 2414 ret = -ENOMEM; 2415 goto fail_brcmf; 2416 } 2417 2418 ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup); 2419 if (ret < 0) { 2420 kfree(fwreq); 2421 goto fail_brcmf; 2422 } 2423 return 0; 2424 2425 fail_brcmf: 2426 brcmf_free(&devinfo->pdev->dev); 2427 fail_bus: 2428 kfree(bus->msgbuf); 2429 kfree(bus); 2430 fail: 2431 brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device); 2432 brcmf_pcie_release_resource(devinfo); 2433 if (devinfo->ci) 2434 brcmf_chip_detach(devinfo->ci); 2435 if (devinfo->settings) 2436 brcmf_release_module_param(devinfo->settings); 2437 kfree(pcie_bus_dev); 2438 kfree(devinfo); 2439 return ret; 2440 } 2441 2442 2443 static void 2444 brcmf_pcie_remove(struct pci_dev *pdev) 2445 { 2446 struct brcmf_pciedev_info *devinfo; 2447 struct brcmf_bus *bus; 2448 2449 brcmf_dbg(PCIE, "Enter\n"); 2450 2451 bus = dev_get_drvdata(&pdev->dev); 2452 if (bus == NULL) 2453 return; 2454 2455 devinfo = bus->bus_priv.pcie->devinfo; 2456 brcmf_pcie_bus_console_read(devinfo, false); 2457 brcmf_pcie_fwcon_timer(devinfo, false); 2458 2459 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2460 if (devinfo->ci) 2461 brcmf_pcie_intr_disable(devinfo); 2462 2463 brcmf_detach(&pdev->dev); 2464 brcmf_free(&pdev->dev); 2465 2466 kfree(bus->bus_priv.pcie); 2467 kfree(bus->msgbuf->flowrings); 2468 kfree(bus->msgbuf); 2469 kfree(bus); 2470 2471 brcmf_pcie_release_irq(devinfo); 2472 brcmf_pcie_release_scratchbuffers(devinfo); 2473 brcmf_pcie_release_ringbuffers(devinfo); 2474 brcmf_pcie_reset_device(devinfo); 2475 brcmf_pcie_release_resource(devinfo); 2476 release_firmware(devinfo->clm_fw); 2477 2478 if (devinfo->ci) 2479 brcmf_chip_detach(devinfo->ci); 2480 if (devinfo->settings) 2481 brcmf_release_module_param(devinfo->settings); 2482 2483 kfree(devinfo); 2484 dev_set_drvdata(&pdev->dev, NULL); 2485 } 2486 2487 2488 #ifdef CONFIG_PM 2489 2490 2491 static int brcmf_pcie_pm_enter_D3(struct device *dev) 2492 { 2493 struct brcmf_pciedev_info *devinfo; 2494 struct brcmf_bus *bus; 2495 2496 brcmf_dbg(PCIE, "Enter\n"); 2497 2498 bus = dev_get_drvdata(dev); 2499 devinfo = bus->bus_priv.pcie->devinfo; 2500 2501 brcmf_pcie_fwcon_timer(devinfo, false); 2502 brcmf_bus_change_state(bus, BRCMF_BUS_DOWN); 2503 2504 devinfo->mbdata_completed = false; 2505 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM); 2506 2507 wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed, 2508 BRCMF_PCIE_MBDATA_TIMEOUT); 2509 if (!devinfo->mbdata_completed) { 2510 brcmf_err(bus, "Timeout on response for entering D3 substate\n"); 2511 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2512 return -EIO; 2513 } 2514 2515 devinfo->state = BRCMFMAC_PCIE_STATE_DOWN; 2516 2517 return 0; 2518 } 2519 2520 2521 static int brcmf_pcie_pm_leave_D3(struct device *dev) 2522 { 2523 struct brcmf_pciedev_info *devinfo; 2524 struct brcmf_bus *bus; 2525 struct pci_dev *pdev; 2526 int err; 2527 2528 brcmf_dbg(PCIE, "Enter\n"); 2529 2530 bus = dev_get_drvdata(dev); 2531 devinfo = bus->bus_priv.pcie->devinfo; 2532 brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus); 2533 2534 /* Check if device is still up and running, if so we are ready */ 2535 if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) { 2536 brcmf_dbg(PCIE, "Try to wakeup device....\n"); 2537 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM)) 2538 goto cleanup; 2539 brcmf_dbg(PCIE, "Hot resume, continue....\n"); 2540 devinfo->state = BRCMFMAC_PCIE_STATE_UP; 2541 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2); 2542 brcmf_bus_change_state(bus, BRCMF_BUS_UP); 2543 brcmf_pcie_intr_enable(devinfo); 2544 brcmf_pcie_hostready(devinfo); 2545 brcmf_pcie_fwcon_timer(devinfo, true); 2546 return 0; 2547 } 2548 2549 cleanup: 2550 brcmf_chip_detach(devinfo->ci); 2551 devinfo->ci = NULL; 2552 pdev = devinfo->pdev; 2553 brcmf_pcie_remove(pdev); 2554 2555 err = brcmf_pcie_probe(pdev, NULL); 2556 if (err) 2557 __brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err); 2558 2559 return err; 2560 } 2561 2562 2563 static const struct dev_pm_ops brcmf_pciedrvr_pm = { 2564 .suspend = brcmf_pcie_pm_enter_D3, 2565 .resume = brcmf_pcie_pm_leave_D3, 2566 .freeze = brcmf_pcie_pm_enter_D3, 2567 .restore = brcmf_pcie_pm_leave_D3, 2568 }; 2569 2570 2571 #endif /* CONFIG_PM */ 2572 2573 2574 #define BRCMF_PCIE_DEVICE(dev_id, fw_vend) \ 2575 { \ 2576 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \ 2577 PCI_ANY_ID, PCI_ANY_ID, \ 2578 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \ 2579 BRCMF_FWVENDOR_ ## fw_vend \ 2580 } 2581 #define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev, fw_vend) \ 2582 { \ 2583 BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \ 2584 (subvend), (subdev), \ 2585 PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \ 2586 BRCMF_FWVENDOR_ ## fw_vend \ 2587 } 2588 2589 static const struct pci_device_id brcmf_pcie_devid_table[] = { 2590 BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID, WCC), 2591 BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355, WCC), 2592 BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID, WCC), 2593 BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID, WCC), 2594 BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID, WCC), 2595 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID, WCC), 2596 BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID, WCC), 2597 BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID, WCC), 2598 BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID, WCC), 2599 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID, WCC), 2600 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID, WCC), 2601 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID, WCC), 2602 BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID, WCC), 2603 BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID, BCA), 2604 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID, BCA), 2605 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID, BCA), 2606 BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID, BCA), 2607 BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365, BCA), 2608 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID, BCA), 2609 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID, BCA), 2610 BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA), 2611 BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC), 2612 BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC), 2613 BRCMF_PCIE_DEVICE(CY_PCIE_89459_DEVICE_ID, CYW), 2614 BRCMF_PCIE_DEVICE(CY_PCIE_89459_RAW_DEVICE_ID, CYW), 2615 { /* end: all zeroes */ } 2616 }; 2617 2618 2619 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table); 2620 2621 2622 static struct pci_driver brcmf_pciedrvr = { 2623 .node = {}, 2624 .name = KBUILD_MODNAME, 2625 .id_table = brcmf_pcie_devid_table, 2626 .probe = brcmf_pcie_probe, 2627 .remove = brcmf_pcie_remove, 2628 #ifdef CONFIG_PM 2629 .driver.pm = &brcmf_pciedrvr_pm, 2630 #endif 2631 .driver.coredump = brcmf_dev_coredump, 2632 }; 2633 2634 2635 int brcmf_pcie_register(void) 2636 { 2637 brcmf_dbg(PCIE, "Enter\n"); 2638 return pci_register_driver(&brcmf_pciedrvr); 2639 } 2640 2641 2642 void brcmf_pcie_exit(void) 2643 { 2644 brcmf_dbg(PCIE, "Enter\n"); 2645 pci_unregister_driver(&brcmf_pciedrvr); 2646 } 2647