1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 4 Broadcom B43 wireless driver 5 6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> 7 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> 8 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch> 9 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> 10 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 11 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com> 12 13 SDIO support 14 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> 15 16 Some parts of the code in this file are derived from the ipw2200 17 driver Copyright(c) 2003 - 2004 Intel Corporation. 18 19 20 */ 21 22 #include <linux/delay.h> 23 #include <linux/init.h> 24 #include <linux/module.h> 25 #include <linux/if_arp.h> 26 #include <linux/etherdevice.h> 27 #include <linux/firmware.h> 28 #include <linux/workqueue.h> 29 #include <linux/skbuff.h> 30 #include <linux/io.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/slab.h> 33 #include <linux/unaligned.h> 34 35 #include "b43.h" 36 #include "main.h" 37 #include "debugfs.h" 38 #include "phy_common.h" 39 #include "phy_g.h" 40 #include "phy_n.h" 41 #include "dma.h" 42 #include "pio.h" 43 #include "sysfs.h" 44 #include "xmit.h" 45 #include "lo.h" 46 #include "sdio.h" 47 #include <linux/mmc/sdio_func.h> 48 49 MODULE_DESCRIPTION("Broadcom B43 wireless driver"); 50 MODULE_AUTHOR("Martin Langer"); 51 MODULE_AUTHOR("Stefano Brivio"); 52 MODULE_AUTHOR("Michael Buesch"); 53 MODULE_AUTHOR("Gábor Stefanik"); 54 MODULE_AUTHOR("Rafał Miłecki"); 55 MODULE_LICENSE("GPL"); 56 57 MODULE_FIRMWARE("b43/ucode11.fw"); 58 MODULE_FIRMWARE("b43/ucode13.fw"); 59 MODULE_FIRMWARE("b43/ucode14.fw"); 60 MODULE_FIRMWARE("b43/ucode15.fw"); 61 MODULE_FIRMWARE("b43/ucode16_lp.fw"); 62 MODULE_FIRMWARE("b43/ucode16_mimo.fw"); 63 MODULE_FIRMWARE("b43/ucode24_lcn.fw"); 64 MODULE_FIRMWARE("b43/ucode25_lcn.fw"); 65 MODULE_FIRMWARE("b43/ucode25_mimo.fw"); 66 MODULE_FIRMWARE("b43/ucode26_mimo.fw"); 67 MODULE_FIRMWARE("b43/ucode29_mimo.fw"); 68 MODULE_FIRMWARE("b43/ucode33_lcn40.fw"); 69 MODULE_FIRMWARE("b43/ucode30_mimo.fw"); 70 MODULE_FIRMWARE("b43/ucode5.fw"); 71 MODULE_FIRMWARE("b43/ucode40.fw"); 72 MODULE_FIRMWARE("b43/ucode42.fw"); 73 MODULE_FIRMWARE("b43/ucode9.fw"); 74 75 static int modparam_bad_frames_preempt; 76 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); 77 MODULE_PARM_DESC(bad_frames_preempt, 78 "enable(1) / disable(0) Bad Frames Preemption"); 79 80 static char modparam_fwpostfix[16]; 81 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); 82 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); 83 84 static int modparam_hwpctl; 85 module_param_named(hwpctl, modparam_hwpctl, int, 0444); 86 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); 87 88 static int modparam_nohwcrypt; 89 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 90 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 91 92 static int modparam_hwtkip; 93 module_param_named(hwtkip, modparam_hwtkip, int, 0444); 94 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip."); 95 96 static int modparam_qos = 1; 97 module_param_named(qos, modparam_qos, int, 0444); 98 MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); 99 100 static int modparam_btcoex = 1; 101 module_param_named(btcoex, modparam_btcoex, int, 0444); 102 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)"); 103 104 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT; 105 module_param_named(verbose, b43_modparam_verbose, int, 0644); 106 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug"); 107 108 static int b43_modparam_pio; 109 module_param_named(pio, b43_modparam_pio, int, 0644); 110 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO"); 111 112 static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC); 113 module_param_named(allhwsupport, modparam_allhwsupport, int, 0444); 114 MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)"); 115 116 #ifdef CONFIG_B43_BCMA 117 static const struct bcma_device_id b43_bcma_tbl[] = { 118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS), 119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x15, BCMA_ANY_CLASS), 120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x16, BCMA_ANY_CLASS), 121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS), 122 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS), 123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS), 124 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS), 125 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS), 126 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS), 127 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS), 128 {}, 129 }; 130 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl); 131 #endif 132 133 #ifdef CONFIG_B43_SSB 134 static const struct ssb_device_id b43_ssb_tbl[] = { 135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), 138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), 139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), 140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), 141 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12), 142 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), 143 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15), 144 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), 145 {}, 146 }; 147 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 148 #endif 149 150 /* Channel and ratetables are shared for all devices. 151 * They can't be const, because ieee80211 puts some precalculated 152 * data in there. This data is the same for all devices, so we don't 153 * get concurrency issues */ 154 #define RATETAB_ENT(_rateid, _flags) \ 155 { \ 156 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ 157 .hw_value = (_rateid), \ 158 .flags = (_flags), \ 159 } 160 161 /* 162 * NOTE: When changing this, sync with xmit.c's 163 * b43_plcp_get_bitrate_idx_* functions! 164 */ 165 static struct ieee80211_rate __b43_ratetable[] = { 166 RATETAB_ENT(B43_CCK_RATE_1MB, 0), 167 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), 168 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), 169 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), 170 RATETAB_ENT(B43_OFDM_RATE_6MB, 0), 171 RATETAB_ENT(B43_OFDM_RATE_9MB, 0), 172 RATETAB_ENT(B43_OFDM_RATE_12MB, 0), 173 RATETAB_ENT(B43_OFDM_RATE_18MB, 0), 174 RATETAB_ENT(B43_OFDM_RATE_24MB, 0), 175 RATETAB_ENT(B43_OFDM_RATE_36MB, 0), 176 RATETAB_ENT(B43_OFDM_RATE_48MB, 0), 177 RATETAB_ENT(B43_OFDM_RATE_54MB, 0), 178 }; 179 180 #define b43_a_ratetable (__b43_ratetable + 4) 181 #define b43_a_ratetable_size 8 182 #define b43_b_ratetable (__b43_ratetable + 0) 183 #define b43_b_ratetable_size 4 184 #define b43_g_ratetable (__b43_ratetable + 0) 185 #define b43_g_ratetable_size 12 186 187 #define CHAN2G(_channel, _freq, _flags) { \ 188 .band = NL80211_BAND_2GHZ, \ 189 .center_freq = (_freq), \ 190 .hw_value = (_channel), \ 191 .flags = (_flags), \ 192 .max_antenna_gain = 0, \ 193 .max_power = 30, \ 194 } 195 static struct ieee80211_channel b43_2ghz_chantable[] = { 196 CHAN2G(1, 2412, 0), 197 CHAN2G(2, 2417, 0), 198 CHAN2G(3, 2422, 0), 199 CHAN2G(4, 2427, 0), 200 CHAN2G(5, 2432, 0), 201 CHAN2G(6, 2437, 0), 202 CHAN2G(7, 2442, 0), 203 CHAN2G(8, 2447, 0), 204 CHAN2G(9, 2452, 0), 205 CHAN2G(10, 2457, 0), 206 CHAN2G(11, 2462, 0), 207 CHAN2G(12, 2467, 0), 208 CHAN2G(13, 2472, 0), 209 CHAN2G(14, 2484, 0), 210 }; 211 212 /* No support for the last 3 channels (12, 13, 14) */ 213 #define b43_2ghz_chantable_limited_size 11 214 #undef CHAN2G 215 216 #define CHAN4G(_channel, _flags) { \ 217 .band = NL80211_BAND_5GHZ, \ 218 .center_freq = 4000 + (5 * (_channel)), \ 219 .hw_value = (_channel), \ 220 .flags = (_flags), \ 221 .max_antenna_gain = 0, \ 222 .max_power = 30, \ 223 } 224 #define CHAN5G(_channel, _flags) { \ 225 .band = NL80211_BAND_5GHZ, \ 226 .center_freq = 5000 + (5 * (_channel)), \ 227 .hw_value = (_channel), \ 228 .flags = (_flags), \ 229 .max_antenna_gain = 0, \ 230 .max_power = 30, \ 231 } 232 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { 233 CHAN4G(184, 0), CHAN4G(186, 0), 234 CHAN4G(188, 0), CHAN4G(190, 0), 235 CHAN4G(192, 0), CHAN4G(194, 0), 236 CHAN4G(196, 0), CHAN4G(198, 0), 237 CHAN4G(200, 0), CHAN4G(202, 0), 238 CHAN4G(204, 0), CHAN4G(206, 0), 239 CHAN4G(208, 0), CHAN4G(210, 0), 240 CHAN4G(212, 0), CHAN4G(214, 0), 241 CHAN4G(216, 0), CHAN4G(218, 0), 242 CHAN4G(220, 0), CHAN4G(222, 0), 243 CHAN4G(224, 0), CHAN4G(226, 0), 244 CHAN4G(228, 0), 245 CHAN5G(32, 0), CHAN5G(34, 0), 246 CHAN5G(36, 0), CHAN5G(38, 0), 247 CHAN5G(40, 0), CHAN5G(42, 0), 248 CHAN5G(44, 0), CHAN5G(46, 0), 249 CHAN5G(48, 0), CHAN5G(50, 0), 250 CHAN5G(52, 0), CHAN5G(54, 0), 251 CHAN5G(56, 0), CHAN5G(58, 0), 252 CHAN5G(60, 0), CHAN5G(62, 0), 253 CHAN5G(64, 0), CHAN5G(66, 0), 254 CHAN5G(68, 0), CHAN5G(70, 0), 255 CHAN5G(72, 0), CHAN5G(74, 0), 256 CHAN5G(76, 0), CHAN5G(78, 0), 257 CHAN5G(80, 0), CHAN5G(82, 0), 258 CHAN5G(84, 0), CHAN5G(86, 0), 259 CHAN5G(88, 0), CHAN5G(90, 0), 260 CHAN5G(92, 0), CHAN5G(94, 0), 261 CHAN5G(96, 0), CHAN5G(98, 0), 262 CHAN5G(100, 0), CHAN5G(102, 0), 263 CHAN5G(104, 0), CHAN5G(106, 0), 264 CHAN5G(108, 0), CHAN5G(110, 0), 265 CHAN5G(112, 0), CHAN5G(114, 0), 266 CHAN5G(116, 0), CHAN5G(118, 0), 267 CHAN5G(120, 0), CHAN5G(122, 0), 268 CHAN5G(124, 0), CHAN5G(126, 0), 269 CHAN5G(128, 0), CHAN5G(130, 0), 270 CHAN5G(132, 0), CHAN5G(134, 0), 271 CHAN5G(136, 0), CHAN5G(138, 0), 272 CHAN5G(140, 0), CHAN5G(142, 0), 273 CHAN5G(144, 0), CHAN5G(145, 0), 274 CHAN5G(146, 0), CHAN5G(147, 0), 275 CHAN5G(148, 0), CHAN5G(149, 0), 276 CHAN5G(150, 0), CHAN5G(151, 0), 277 CHAN5G(152, 0), CHAN5G(153, 0), 278 CHAN5G(154, 0), CHAN5G(155, 0), 279 CHAN5G(156, 0), CHAN5G(157, 0), 280 CHAN5G(158, 0), CHAN5G(159, 0), 281 CHAN5G(160, 0), CHAN5G(161, 0), 282 CHAN5G(162, 0), CHAN5G(163, 0), 283 CHAN5G(164, 0), CHAN5G(165, 0), 284 CHAN5G(166, 0), CHAN5G(168, 0), 285 CHAN5G(170, 0), CHAN5G(172, 0), 286 CHAN5G(174, 0), CHAN5G(176, 0), 287 CHAN5G(178, 0), CHAN5G(180, 0), 288 CHAN5G(182, 0), 289 }; 290 291 static struct ieee80211_channel b43_5ghz_nphy_chantable_limited[] = { 292 CHAN5G(36, 0), CHAN5G(40, 0), 293 CHAN5G(44, 0), CHAN5G(48, 0), 294 CHAN5G(149, 0), CHAN5G(153, 0), 295 CHAN5G(157, 0), CHAN5G(161, 0), 296 CHAN5G(165, 0), 297 }; 298 299 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { 300 CHAN5G(34, 0), CHAN5G(36, 0), 301 CHAN5G(38, 0), CHAN5G(40, 0), 302 CHAN5G(42, 0), CHAN5G(44, 0), 303 CHAN5G(46, 0), CHAN5G(48, 0), 304 CHAN5G(52, 0), CHAN5G(56, 0), 305 CHAN5G(60, 0), CHAN5G(64, 0), 306 CHAN5G(100, 0), CHAN5G(104, 0), 307 CHAN5G(108, 0), CHAN5G(112, 0), 308 CHAN5G(116, 0), CHAN5G(120, 0), 309 CHAN5G(124, 0), CHAN5G(128, 0), 310 CHAN5G(132, 0), CHAN5G(136, 0), 311 CHAN5G(140, 0), CHAN5G(149, 0), 312 CHAN5G(153, 0), CHAN5G(157, 0), 313 CHAN5G(161, 0), CHAN5G(165, 0), 314 CHAN5G(184, 0), CHAN5G(188, 0), 315 CHAN5G(192, 0), CHAN5G(196, 0), 316 CHAN5G(200, 0), CHAN5G(204, 0), 317 CHAN5G(208, 0), CHAN5G(212, 0), 318 CHAN5G(216, 0), 319 }; 320 #undef CHAN4G 321 #undef CHAN5G 322 323 static struct ieee80211_supported_band b43_band_5GHz_nphy = { 324 .band = NL80211_BAND_5GHZ, 325 .channels = b43_5ghz_nphy_chantable, 326 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), 327 .bitrates = b43_a_ratetable, 328 .n_bitrates = b43_a_ratetable_size, 329 }; 330 331 static struct ieee80211_supported_band b43_band_5GHz_nphy_limited = { 332 .band = NL80211_BAND_5GHZ, 333 .channels = b43_5ghz_nphy_chantable_limited, 334 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable_limited), 335 .bitrates = b43_a_ratetable, 336 .n_bitrates = b43_a_ratetable_size, 337 }; 338 339 static struct ieee80211_supported_band b43_band_5GHz_aphy = { 340 .band = NL80211_BAND_5GHZ, 341 .channels = b43_5ghz_aphy_chantable, 342 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), 343 .bitrates = b43_a_ratetable, 344 .n_bitrates = b43_a_ratetable_size, 345 }; 346 347 static struct ieee80211_supported_band b43_band_2GHz = { 348 .band = NL80211_BAND_2GHZ, 349 .channels = b43_2ghz_chantable, 350 .n_channels = ARRAY_SIZE(b43_2ghz_chantable), 351 .bitrates = b43_g_ratetable, 352 .n_bitrates = b43_g_ratetable_size, 353 }; 354 355 static struct ieee80211_supported_band b43_band_2ghz_limited = { 356 .band = NL80211_BAND_2GHZ, 357 .channels = b43_2ghz_chantable, 358 .n_channels = b43_2ghz_chantable_limited_size, 359 .bitrates = b43_g_ratetable, 360 .n_bitrates = b43_g_ratetable_size, 361 }; 362 363 static void b43_wireless_core_exit(struct b43_wldev *dev); 364 static int b43_wireless_core_init(struct b43_wldev *dev); 365 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev); 366 static int b43_wireless_core_start(struct b43_wldev *dev); 367 static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 368 struct ieee80211_vif *vif, 369 struct ieee80211_bss_conf *conf, 370 u64 changed); 371 372 static int b43_ratelimit(struct b43_wl *wl) 373 { 374 if (!wl || !wl->current_dev) 375 return 1; 376 if (b43_status(wl->current_dev) < B43_STAT_STARTED) 377 return 1; 378 /* We are up and running. 379 * Ratelimit the messages to avoid DoS over the net. */ 380 return net_ratelimit(); 381 } 382 383 void b43info(struct b43_wl *wl, const char *fmt, ...) 384 { 385 struct va_format vaf; 386 va_list args; 387 388 if (b43_modparam_verbose < B43_VERBOSITY_INFO) 389 return; 390 if (!b43_ratelimit(wl)) 391 return; 392 393 va_start(args, fmt); 394 395 vaf.fmt = fmt; 396 vaf.va = &args; 397 398 printk(KERN_INFO "b43-%s: %pV", 399 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 400 401 va_end(args); 402 } 403 404 void b43err(struct b43_wl *wl, const char *fmt, ...) 405 { 406 struct va_format vaf; 407 va_list args; 408 409 if (b43_modparam_verbose < B43_VERBOSITY_ERROR) 410 return; 411 if (!b43_ratelimit(wl)) 412 return; 413 414 va_start(args, fmt); 415 416 vaf.fmt = fmt; 417 vaf.va = &args; 418 419 printk(KERN_ERR "b43-%s ERROR: %pV", 420 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 421 422 va_end(args); 423 } 424 425 void b43warn(struct b43_wl *wl, const char *fmt, ...) 426 { 427 struct va_format vaf; 428 va_list args; 429 430 if (b43_modparam_verbose < B43_VERBOSITY_WARN) 431 return; 432 if (!b43_ratelimit(wl)) 433 return; 434 435 va_start(args, fmt); 436 437 vaf.fmt = fmt; 438 vaf.va = &args; 439 440 printk(KERN_WARNING "b43-%s warning: %pV", 441 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 442 443 va_end(args); 444 } 445 446 void b43dbg(struct b43_wl *wl, const char *fmt, ...) 447 { 448 struct va_format vaf; 449 va_list args; 450 451 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 452 return; 453 454 va_start(args, fmt); 455 456 vaf.fmt = fmt; 457 vaf.va = &args; 458 459 printk(KERN_DEBUG "b43-%s debug: %pV", 460 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); 461 462 va_end(args); 463 } 464 465 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) 466 { 467 u32 macctl; 468 469 B43_WARN_ON(offset % 4 != 0); 470 471 macctl = b43_read32(dev, B43_MMIO_MACCTL); 472 if (macctl & B43_MACCTL_BE) 473 val = swab32(val); 474 475 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); 476 b43_write32(dev, B43_MMIO_RAM_DATA, val); 477 } 478 479 static inline void b43_shm_control_word(struct b43_wldev *dev, 480 u16 routing, u16 offset) 481 { 482 u32 control; 483 484 /* "offset" is the WORD offset. */ 485 control = routing; 486 control <<= 16; 487 control |= offset; 488 b43_write32(dev, B43_MMIO_SHM_CONTROL, control); 489 } 490 491 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) 492 { 493 u32 ret; 494 495 if (routing == B43_SHM_SHARED) { 496 B43_WARN_ON(offset & 0x0001); 497 if (offset & 0x0003) { 498 /* Unaligned access */ 499 b43_shm_control_word(dev, routing, offset >> 2); 500 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 501 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 502 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16; 503 504 goto out; 505 } 506 offset >>= 2; 507 } 508 b43_shm_control_word(dev, routing, offset); 509 ret = b43_read32(dev, B43_MMIO_SHM_DATA); 510 out: 511 return ret; 512 } 513 514 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset) 515 { 516 u16 ret; 517 518 if (routing == B43_SHM_SHARED) { 519 B43_WARN_ON(offset & 0x0001); 520 if (offset & 0x0003) { 521 /* Unaligned access */ 522 b43_shm_control_word(dev, routing, offset >> 2); 523 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); 524 525 goto out; 526 } 527 offset >>= 2; 528 } 529 b43_shm_control_word(dev, routing, offset); 530 ret = b43_read16(dev, B43_MMIO_SHM_DATA); 531 out: 532 return ret; 533 } 534 535 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) 536 { 537 if (routing == B43_SHM_SHARED) { 538 B43_WARN_ON(offset & 0x0001); 539 if (offset & 0x0003) { 540 /* Unaligned access */ 541 b43_shm_control_word(dev, routing, offset >> 2); 542 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, 543 value & 0xFFFF); 544 b43_shm_control_word(dev, routing, (offset >> 2) + 1); 545 b43_write16(dev, B43_MMIO_SHM_DATA, 546 (value >> 16) & 0xFFFF); 547 return; 548 } 549 offset >>= 2; 550 } 551 b43_shm_control_word(dev, routing, offset); 552 b43_write32(dev, B43_MMIO_SHM_DATA, value); 553 } 554 555 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) 556 { 557 if (routing == B43_SHM_SHARED) { 558 B43_WARN_ON(offset & 0x0001); 559 if (offset & 0x0003) { 560 /* Unaligned access */ 561 b43_shm_control_word(dev, routing, offset >> 2); 562 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); 563 return; 564 } 565 offset >>= 2; 566 } 567 b43_shm_control_word(dev, routing, offset); 568 b43_write16(dev, B43_MMIO_SHM_DATA, value); 569 } 570 571 /* Read HostFlags */ 572 u64 b43_hf_read(struct b43_wldev *dev) 573 { 574 u64 ret; 575 576 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3); 577 ret <<= 16; 578 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2); 579 ret <<= 16; 580 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1); 581 582 return ret; 583 } 584 585 /* Write HostFlags */ 586 void b43_hf_write(struct b43_wldev *dev, u64 value) 587 { 588 u16 lo, mi, hi; 589 590 lo = (value & 0x00000000FFFFULL); 591 mi = (value & 0x0000FFFF0000ULL) >> 16; 592 hi = (value & 0xFFFF00000000ULL) >> 32; 593 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo); 594 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi); 595 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi); 596 } 597 598 /* Read the firmware capabilities bitmask (Opensource firmware only) */ 599 static u16 b43_fwcapa_read(struct b43_wldev *dev) 600 { 601 B43_WARN_ON(!dev->fw.opensource); 602 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA); 603 } 604 605 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf) 606 { 607 u32 low, high; 608 609 B43_WARN_ON(dev->dev->core_rev < 3); 610 611 /* The hardware guarantees us an atomic read, if we 612 * read the low register first. */ 613 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); 614 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); 615 616 *tsf = high; 617 *tsf <<= 32; 618 *tsf |= low; 619 } 620 621 static void b43_time_lock(struct b43_wldev *dev) 622 { 623 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD); 624 /* Commit the write */ 625 b43_read32(dev, B43_MMIO_MACCTL); 626 } 627 628 static void b43_time_unlock(struct b43_wldev *dev) 629 { 630 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0); 631 /* Commit the write */ 632 b43_read32(dev, B43_MMIO_MACCTL); 633 } 634 635 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) 636 { 637 u32 low, high; 638 639 B43_WARN_ON(dev->dev->core_rev < 3); 640 641 low = tsf; 642 high = (tsf >> 32); 643 /* The hardware guarantees us an atomic write, if we 644 * write the low register first. */ 645 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low); 646 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high); 647 } 648 649 void b43_tsf_write(struct b43_wldev *dev, u64 tsf) 650 { 651 b43_time_lock(dev); 652 b43_tsf_write_locked(dev, tsf); 653 b43_time_unlock(dev); 654 } 655 656 static 657 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac) 658 { 659 static const u8 zero_addr[ETH_ALEN] = { 0 }; 660 u16 data; 661 662 if (!mac) 663 mac = zero_addr; 664 665 offset |= 0x0020; 666 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); 667 668 data = mac[0]; 669 data |= mac[1] << 8; 670 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 671 data = mac[2]; 672 data |= mac[3] << 8; 673 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 674 data = mac[4]; 675 data |= mac[5] << 8; 676 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); 677 } 678 679 static void b43_write_mac_bssid_templates(struct b43_wldev *dev) 680 { 681 const u8 *mac; 682 const u8 *bssid; 683 u8 mac_bssid[ETH_ALEN * 2]; 684 int i; 685 u32 tmp; 686 687 bssid = dev->wl->bssid; 688 mac = dev->wl->mac_addr; 689 690 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); 691 692 memcpy(mac_bssid, mac, ETH_ALEN); 693 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); 694 695 /* Write our MAC address and BSSID to template ram */ 696 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { 697 tmp = (u32) (mac_bssid[i + 0]); 698 tmp |= (u32) (mac_bssid[i + 1]) << 8; 699 tmp |= (u32) (mac_bssid[i + 2]) << 16; 700 tmp |= (u32) (mac_bssid[i + 3]) << 24; 701 b43_ram_write(dev, 0x20 + i, tmp); 702 } 703 } 704 705 static void b43_upload_card_macaddress(struct b43_wldev *dev) 706 { 707 b43_write_mac_bssid_templates(dev); 708 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); 709 } 710 711 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) 712 { 713 /* slot_time is in usec. */ 714 /* This test used to exit for all but a G PHY. */ 715 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) 716 return; 717 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time); 718 /* Shared memory location 0x0010 is the slot time and should be 719 * set to slot_time; however, this register is initially 0 and changing 720 * the value adversely affects the transmit rate for BCM4311 721 * devices. Until this behavior is unterstood, delete this step 722 * 723 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); 724 */ 725 } 726 727 static void b43_short_slot_timing_enable(struct b43_wldev *dev) 728 { 729 b43_set_slot_time(dev, 9); 730 } 731 732 static void b43_short_slot_timing_disable(struct b43_wldev *dev) 733 { 734 b43_set_slot_time(dev, 20); 735 } 736 737 /* DummyTransmission function, as documented on 738 * https://bcm-v4.sipsolutions.net/802.11/DummyTransmission 739 */ 740 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) 741 { 742 struct b43_phy *phy = &dev->phy; 743 unsigned int i, max_loop; 744 u16 value; 745 u32 buffer[5] = { 746 0x00000000, 747 0x00D40000, 748 0x00000000, 749 0x01000000, 750 0x00000000, 751 }; 752 753 if (ofdm) { 754 max_loop = 0x1E; 755 buffer[0] = 0x000201CC; 756 } else { 757 max_loop = 0xFA; 758 buffer[0] = 0x000B846E; 759 } 760 761 for (i = 0; i < 5; i++) 762 b43_ram_write(dev, i * 4, buffer[i]); 763 764 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000); 765 766 if (dev->dev->core_rev < 11) 767 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000); 768 else 769 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100); 770 771 value = (ofdm ? 0x41 : 0x40); 772 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value); 773 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP || 774 phy->type == B43_PHYTYPE_LCN) 775 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02); 776 777 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000); 778 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000); 779 780 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000); 781 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014); 782 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826); 783 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000); 784 785 if (!pa_on && phy->type == B43_PHYTYPE_N) { 786 ; /*b43_nphy_pa_override(dev, false) */ 787 } 788 789 switch (phy->type) { 790 case B43_PHYTYPE_N: 791 case B43_PHYTYPE_LCN: 792 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0); 793 break; 794 case B43_PHYTYPE_LP: 795 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050); 796 break; 797 default: 798 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030); 799 } 800 b43_read16(dev, B43_MMIO_TXE0_AUX); 801 802 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 803 b43_radio_write16(dev, 0x0051, 0x0017); 804 for (i = 0x00; i < max_loop; i++) { 805 value = b43_read16(dev, B43_MMIO_TXE0_STATUS); 806 if (value & 0x0080) 807 break; 808 udelay(10); 809 } 810 for (i = 0x00; i < 0x0A; i++) { 811 value = b43_read16(dev, B43_MMIO_TXE0_STATUS); 812 if (value & 0x0400) 813 break; 814 udelay(10); 815 } 816 for (i = 0x00; i < 0x19; i++) { 817 value = b43_read16(dev, B43_MMIO_IFSSTAT); 818 if (!(value & 0x0100)) 819 break; 820 udelay(10); 821 } 822 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) 823 b43_radio_write16(dev, 0x0051, 0x0037); 824 } 825 826 static void key_write(struct b43_wldev *dev, 827 u8 index, u8 algorithm, const u8 *key) 828 { 829 unsigned int i; 830 u32 offset; 831 u16 value; 832 u16 kidx; 833 834 /* Key index/algo block */ 835 kidx = b43_kidx_to_fw(dev, index); 836 value = ((kidx << 4) | algorithm); 837 b43_shm_write16(dev, B43_SHM_SHARED, 838 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); 839 840 /* Write the key to the Key Table Pointer offset */ 841 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 842 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 843 value = key[i]; 844 value |= (u16) (key[i + 1]) << 8; 845 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); 846 } 847 } 848 849 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr) 850 { 851 u32 addrtmp[2] = { 0, 0, }; 852 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 853 854 if (b43_new_kidx_api(dev)) 855 pairwise_keys_start = B43_NR_GROUP_KEYS; 856 857 B43_WARN_ON(index < pairwise_keys_start); 858 /* We have four default TX keys and possibly four default RX keys. 859 * Physical mac 0 is mapped to physical key 4 or 8, depending 860 * on the firmware version. 861 * So we must adjust the index here. 862 */ 863 index -= pairwise_keys_start; 864 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 865 866 if (addr) { 867 addrtmp[0] = addr[0]; 868 addrtmp[0] |= ((u32) (addr[1]) << 8); 869 addrtmp[0] |= ((u32) (addr[2]) << 16); 870 addrtmp[0] |= ((u32) (addr[3]) << 24); 871 addrtmp[1] = addr[4]; 872 addrtmp[1] |= ((u32) (addr[5]) << 8); 873 } 874 875 /* Receive match transmitter address (RCMTA) mechanism */ 876 b43_shm_write32(dev, B43_SHM_RCMTA, 877 (index * 2) + 0, addrtmp[0]); 878 b43_shm_write16(dev, B43_SHM_RCMTA, 879 (index * 2) + 1, addrtmp[1]); 880 } 881 882 /* The ucode will use phase1 key with TEK key to decrypt rx packets. 883 * When a packet is received, the iv32 is checked. 884 * - if it doesn't the packet is returned without modification (and software 885 * decryption can be done). That's what happen when iv16 wrap. 886 * - if it does, the rc4 key is computed, and decryption is tried. 887 * Either it will success and B43_RX_MAC_DEC is returned, 888 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned 889 * and the packet is not usable (it got modified by the ucode). 890 * So in order to never have B43_RX_MAC_DECERR, we should provide 891 * a iv32 and phase1key that match. Because we drop packets in case of 892 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all 893 * packets will be lost without higher layer knowing (ie no resync possible 894 * until next wrap). 895 * 896 * NOTE : this should support 50 key like RCMTA because 897 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50 898 */ 899 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32, 900 u16 *phase1key) 901 { 902 unsigned int i; 903 u32 offset; 904 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 905 906 if (!modparam_hwtkip) 907 return; 908 909 if (b43_new_kidx_api(dev)) 910 pairwise_keys_start = B43_NR_GROUP_KEYS; 911 912 B43_WARN_ON(index < pairwise_keys_start); 913 /* We have four default TX keys and possibly four default RX keys. 914 * Physical mac 0 is mapped to physical key 4 or 8, depending 915 * on the firmware version. 916 * So we must adjust the index here. 917 */ 918 index -= pairwise_keys_start; 919 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); 920 921 if (b43_debug(dev, B43_DBG_KEYS)) { 922 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", 923 index, iv32); 924 } 925 /* Write the key to the RX tkip shared mem */ 926 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4); 927 for (i = 0; i < 10; i += 2) { 928 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, 929 phase1key ? phase1key[i / 2] : 0); 930 } 931 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32); 932 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16); 933 } 934 935 static void b43_op_update_tkip_key(struct ieee80211_hw *hw, 936 struct ieee80211_vif *vif, 937 struct ieee80211_key_conf *keyconf, 938 struct ieee80211_sta *sta, 939 u32 iv32, u16 *phase1key) 940 { 941 struct b43_wl *wl = hw_to_b43_wl(hw); 942 struct b43_wldev *dev; 943 int index = keyconf->hw_key_idx; 944 945 if (B43_WARN_ON(!modparam_hwtkip)) 946 return; 947 948 /* This is only called from the RX path through mac80211, where 949 * our mutex is already locked. */ 950 B43_WARN_ON(!mutex_is_locked(&wl->mutex)); 951 dev = wl->current_dev; 952 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED); 953 954 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */ 955 956 rx_tkip_phase1_write(dev, index, iv32, phase1key); 957 /* only pairwise TKIP keys are supported right now */ 958 if (WARN_ON(!sta)) 959 return; 960 keymac_write(dev, index, sta->addr); 961 } 962 963 static void do_key_write(struct b43_wldev *dev, 964 u8 index, u8 algorithm, 965 const u8 *key, size_t key_len, const u8 *mac_addr) 966 { 967 u8 buf[B43_SEC_KEYSIZE] = { 0, }; 968 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 969 970 if (b43_new_kidx_api(dev)) 971 pairwise_keys_start = B43_NR_GROUP_KEYS; 972 973 B43_WARN_ON(index >= ARRAY_SIZE(dev->key)); 974 B43_WARN_ON(key_len > B43_SEC_KEYSIZE); 975 976 if (index >= pairwise_keys_start) 977 keymac_write(dev, index, NULL); /* First zero out mac. */ 978 if (algorithm == B43_SEC_ALGO_TKIP) { 979 /* 980 * We should provide an initial iv32, phase1key pair. 981 * We could start with iv32=0 and compute the corresponding 982 * phase1key, but this means calling ieee80211_get_tkip_key 983 * with a fake skb (or export other tkip function). 984 * Because we are lazy we hope iv32 won't start with 985 * 0xffffffff and let's b43_op_update_tkip_key provide a 986 * correct pair. 987 */ 988 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); 989 } else if (index >= pairwise_keys_start) /* clear it */ 990 rx_tkip_phase1_write(dev, index, 0, NULL); 991 if (key) 992 memcpy(buf, key, key_len); 993 key_write(dev, index, algorithm, buf); 994 if (index >= pairwise_keys_start) 995 keymac_write(dev, index, mac_addr); 996 997 dev->key[index].algorithm = algorithm; 998 } 999 1000 static int b43_key_write(struct b43_wldev *dev, 1001 int index, u8 algorithm, 1002 const u8 *key, size_t key_len, 1003 const u8 *mac_addr, 1004 struct ieee80211_key_conf *keyconf) 1005 { 1006 int i; 1007 int pairwise_keys_start; 1008 1009 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block: 1010 * - Temporal Encryption Key (128 bits) 1011 * - Temporal Authenticator Tx MIC Key (64 bits) 1012 * - Temporal Authenticator Rx MIC Key (64 bits) 1013 * 1014 * Hardware only store TEK 1015 */ 1016 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32) 1017 key_len = 16; 1018 if (key_len > B43_SEC_KEYSIZE) 1019 return -EINVAL; 1020 for (i = 0; i < ARRAY_SIZE(dev->key); i++) { 1021 /* Check that we don't already have this key. */ 1022 B43_WARN_ON(dev->key[i].keyconf == keyconf); 1023 } 1024 if (index < 0) { 1025 /* Pairwise key. Get an empty slot for the key. */ 1026 if (b43_new_kidx_api(dev)) 1027 pairwise_keys_start = B43_NR_GROUP_KEYS; 1028 else 1029 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 1030 for (i = pairwise_keys_start; 1031 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS; 1032 i++) { 1033 B43_WARN_ON(i >= ARRAY_SIZE(dev->key)); 1034 if (!dev->key[i].keyconf) { 1035 /* found empty */ 1036 index = i; 1037 break; 1038 } 1039 } 1040 if (index < 0) { 1041 b43warn(dev->wl, "Out of hardware key memory\n"); 1042 return -ENOSPC; 1043 } 1044 } else 1045 B43_WARN_ON(index > 3); 1046 1047 do_key_write(dev, index, algorithm, key, key_len, mac_addr); 1048 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1049 /* Default RX key */ 1050 B43_WARN_ON(mac_addr); 1051 do_key_write(dev, index + 4, algorithm, key, key_len, NULL); 1052 } 1053 keyconf->hw_key_idx = index; 1054 dev->key[index].keyconf = keyconf; 1055 1056 return 0; 1057 } 1058 1059 static int b43_key_clear(struct b43_wldev *dev, int index) 1060 { 1061 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) 1062 return -EINVAL; 1063 do_key_write(dev, index, B43_SEC_ALGO_NONE, 1064 NULL, B43_SEC_KEYSIZE, NULL); 1065 if ((index <= 3) && !b43_new_kidx_api(dev)) { 1066 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, 1067 NULL, B43_SEC_KEYSIZE, NULL); 1068 } 1069 dev->key[index].keyconf = NULL; 1070 1071 return 0; 1072 } 1073 1074 static void b43_clear_keys(struct b43_wldev *dev) 1075 { 1076 int i, count; 1077 1078 if (b43_new_kidx_api(dev)) 1079 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1080 else 1081 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1082 for (i = 0; i < count; i++) 1083 b43_key_clear(dev, i); 1084 } 1085 1086 static void b43_dump_keymemory(struct b43_wldev *dev) 1087 { 1088 unsigned int i, index, count, offset, pairwise_keys_start; 1089 u8 mac[ETH_ALEN]; 1090 u16 algo; 1091 u32 rcmta0; 1092 u16 rcmta1; 1093 u64 hf; 1094 struct b43_key *key; 1095 1096 if (!b43_debug(dev, B43_DBG_KEYS)) 1097 return; 1098 1099 hf = b43_hf_read(dev); 1100 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n", 1101 !!(hf & B43_HF_USEDEFKEYS)); 1102 if (b43_new_kidx_api(dev)) { 1103 pairwise_keys_start = B43_NR_GROUP_KEYS; 1104 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; 1105 } else { 1106 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; 1107 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; 1108 } 1109 for (index = 0; index < count; index++) { 1110 key = &(dev->key[index]); 1111 printk(KERN_DEBUG "Key slot %02u: %s", 1112 index, (key->keyconf == NULL) ? " " : "*"); 1113 offset = dev->ktp + (index * B43_SEC_KEYSIZE); 1114 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { 1115 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1116 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1117 } 1118 1119 algo = b43_shm_read16(dev, B43_SHM_SHARED, 1120 B43_SHM_SH_KEYIDXBLOCK + (index * 2)); 1121 printk(" Algo: %04X/%02X", algo, key->algorithm); 1122 1123 if (index >= pairwise_keys_start) { 1124 if (key->algorithm == B43_SEC_ALGO_TKIP) { 1125 printk(" TKIP: "); 1126 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4); 1127 for (i = 0; i < 14; i += 2) { 1128 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); 1129 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); 1130 } 1131 } 1132 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA, 1133 ((index - pairwise_keys_start) * 2) + 0); 1134 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA, 1135 ((index - pairwise_keys_start) * 2) + 1); 1136 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); 1137 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1); 1138 printk(" MAC: %pM", mac); 1139 } else 1140 printk(" DEFAULT KEY"); 1141 printk("\n"); 1142 } 1143 } 1144 1145 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) 1146 { 1147 u32 macctl; 1148 u16 ucstat; 1149 bool hwps; 1150 bool awake; 1151 int i; 1152 1153 B43_WARN_ON((ps_flags & B43_PS_ENABLED) && 1154 (ps_flags & B43_PS_DISABLED)); 1155 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); 1156 1157 if (ps_flags & B43_PS_ENABLED) { 1158 hwps = true; 1159 } else if (ps_flags & B43_PS_DISABLED) { 1160 hwps = false; 1161 } else { 1162 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc 1163 // and thus is not an AP and we are associated, set bit 25 1164 } 1165 if (ps_flags & B43_PS_AWAKE) { 1166 awake = true; 1167 } else if (ps_flags & B43_PS_ASLEEP) { 1168 awake = false; 1169 } else { 1170 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, 1171 // or we are associated, or FIXME, or the latest PS-Poll packet sent was 1172 // successful, set bit26 1173 } 1174 1175 /* FIXME: For now we force awake-on and hwps-off */ 1176 hwps = false; 1177 awake = true; 1178 1179 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1180 if (hwps) 1181 macctl |= B43_MACCTL_HWPS; 1182 else 1183 macctl &= ~B43_MACCTL_HWPS; 1184 if (awake) 1185 macctl |= B43_MACCTL_AWAKE; 1186 else 1187 macctl &= ~B43_MACCTL_AWAKE; 1188 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1189 /* Commit write */ 1190 b43_read32(dev, B43_MMIO_MACCTL); 1191 if (awake && dev->dev->core_rev >= 5) { 1192 /* Wait for the microcode to wake up. */ 1193 for (i = 0; i < 100; i++) { 1194 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 1195 B43_SHM_SH_UCODESTAT); 1196 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) 1197 break; 1198 udelay(10); 1199 } 1200 } 1201 } 1202 1203 /* https://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */ 1204 void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev) 1205 { 1206 struct bcma_drv_cc *bcma_cc __maybe_unused; 1207 struct ssb_chipcommon *ssb_cc __maybe_unused; 1208 1209 switch (dev->dev->bus_type) { 1210 #ifdef CONFIG_B43_BCMA 1211 case B43_BUS_BCMA: 1212 bcma_cc = &dev->dev->bdev->bus->drv_cc; 1213 1214 bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0); 1215 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4); 1216 bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4); 1217 bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4); 1218 break; 1219 #endif 1220 #ifdef CONFIG_B43_SSB 1221 case B43_BUS_SSB: 1222 ssb_cc = &dev->dev->sdev->bus->chipco; 1223 1224 chipco_write32(ssb_cc, SSB_CHIPCO_CHIPCTL_ADDR, 0); 1225 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4); 1226 chipco_set32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, 0x4); 1227 chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4); 1228 break; 1229 #endif 1230 } 1231 } 1232 1233 #ifdef CONFIG_B43_BCMA 1234 static void b43_bcma_phy_reset(struct b43_wldev *dev) 1235 { 1236 u32 flags; 1237 1238 /* Put PHY into reset */ 1239 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1240 flags |= B43_BCMA_IOCTL_PHY_RESET; 1241 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */ 1242 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); 1243 udelay(2); 1244 1245 b43_phy_take_out_of_reset(dev); 1246 } 1247 1248 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1249 { 1250 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ | 1251 B43_BCMA_CLKCTLST_PHY_PLL_REQ; 1252 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST | 1253 B43_BCMA_CLKCTLST_PHY_PLL_ST; 1254 u32 flags; 1255 1256 flags = B43_BCMA_IOCTL_PHY_CLKEN; 1257 if (gmode) 1258 flags |= B43_BCMA_IOCTL_GMODE; 1259 b43_device_enable(dev, flags); 1260 1261 if (dev->phy.type == B43_PHYTYPE_AC) { 1262 u16 tmp; 1263 1264 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1265 tmp &= ~B43_BCMA_IOCTL_DAC; 1266 tmp |= 0x100; 1267 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); 1268 1269 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1270 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN; 1271 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); 1272 1273 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 1274 tmp |= B43_BCMA_IOCTL_PHY_CLKEN; 1275 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); 1276 } 1277 1278 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST); 1279 b43_bcma_phy_reset(dev); 1280 bcma_core_pll_ctl(dev->dev->bdev, req, status, true); 1281 } 1282 #endif 1283 1284 #ifdef CONFIG_B43_SSB 1285 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1286 { 1287 u32 flags = 0; 1288 1289 if (gmode) 1290 flags |= B43_TMSLOW_GMODE; 1291 flags |= B43_TMSLOW_PHYCLKEN; 1292 flags |= B43_TMSLOW_PHYRESET; 1293 if (dev->phy.type == B43_PHYTYPE_N) 1294 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */ 1295 b43_device_enable(dev, flags); 1296 msleep(2); /* Wait for the PLL to turn on. */ 1297 1298 b43_phy_take_out_of_reset(dev); 1299 } 1300 #endif 1301 1302 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1303 { 1304 u32 macctl; 1305 1306 switch (dev->dev->bus_type) { 1307 #ifdef CONFIG_B43_BCMA 1308 case B43_BUS_BCMA: 1309 b43_bcma_wireless_core_reset(dev, gmode); 1310 break; 1311 #endif 1312 #ifdef CONFIG_B43_SSB 1313 case B43_BUS_SSB: 1314 b43_ssb_wireless_core_reset(dev, gmode); 1315 break; 1316 #endif 1317 } 1318 1319 /* Turn Analog ON, but only if we already know the PHY-type. 1320 * This protects against very early setup where we don't know the 1321 * PHY-type, yet. wireless_core_reset will be called once again later, 1322 * when we know the PHY-type. */ 1323 if (dev->phy.ops) 1324 dev->phy.ops->switch_analog(dev, 1); 1325 1326 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1327 macctl &= ~B43_MACCTL_GMODE; 1328 if (gmode) 1329 macctl |= B43_MACCTL_GMODE; 1330 macctl |= B43_MACCTL_IHR_ENABLED; 1331 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1332 } 1333 1334 static void handle_irq_transmit_status(struct b43_wldev *dev) 1335 { 1336 u32 v0, v1; 1337 u16 tmp; 1338 struct b43_txstatus stat; 1339 1340 while (1) { 1341 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1342 if (!(v0 & 0x00000001)) 1343 break; 1344 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1345 1346 stat.cookie = (v0 >> 16); 1347 stat.seq = (v1 & 0x0000FFFF); 1348 stat.phy_stat = ((v1 & 0x00FF0000) >> 16); 1349 tmp = (v0 & 0x0000FFFF); 1350 stat.frame_count = ((tmp & 0xF000) >> 12); 1351 stat.rts_count = ((tmp & 0x0F00) >> 8); 1352 stat.supp_reason = ((tmp & 0x001C) >> 2); 1353 stat.pm_indicated = !!(tmp & 0x0080); 1354 stat.intermediate = !!(tmp & 0x0040); 1355 stat.for_ampdu = !!(tmp & 0x0020); 1356 stat.acked = !!(tmp & 0x0002); 1357 1358 b43_handle_txstatus(dev, &stat); 1359 } 1360 } 1361 1362 static void drain_txstatus_queue(struct b43_wldev *dev) 1363 { 1364 u32 dummy; 1365 1366 if (dev->dev->core_rev < 5) 1367 return; 1368 /* Read all entries from the microcode TXstatus FIFO 1369 * and throw them away. 1370 */ 1371 while (1) { 1372 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); 1373 if (!(dummy & 0x00000001)) 1374 break; 1375 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); 1376 } 1377 } 1378 1379 static u32 b43_jssi_read(struct b43_wldev *dev) 1380 { 1381 u32 val = 0; 1382 1383 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1); 1384 val <<= 16; 1385 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0); 1386 1387 return val; 1388 } 1389 1390 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1391 { 1392 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0, 1393 (jssi & 0x0000FFFF)); 1394 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1, 1395 (jssi & 0xFFFF0000) >> 16); 1396 } 1397 1398 static void b43_generate_noise_sample(struct b43_wldev *dev) 1399 { 1400 b43_jssi_write(dev, 0x7F7F7F7F); 1401 b43_write32(dev, B43_MMIO_MACCMD, 1402 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); 1403 } 1404 1405 static void b43_calculate_link_quality(struct b43_wldev *dev) 1406 { 1407 /* Top half of Link Quality calculation. */ 1408 1409 if (dev->phy.type != B43_PHYTYPE_G) 1410 return; 1411 if (dev->noisecalc.calculation_running) 1412 return; 1413 dev->noisecalc.calculation_running = true; 1414 dev->noisecalc.nr_samples = 0; 1415 1416 b43_generate_noise_sample(dev); 1417 } 1418 1419 static void handle_irq_noise(struct b43_wldev *dev) 1420 { 1421 struct b43_phy_g *phy = dev->phy.g; 1422 u16 tmp; 1423 u8 noise[4]; 1424 u8 i, j; 1425 s32 average; 1426 1427 /* Bottom half of Link Quality calculation. */ 1428 1429 if (dev->phy.type != B43_PHYTYPE_G) 1430 return; 1431 1432 /* Possible race condition: It might be possible that the user 1433 * changed to a different channel in the meantime since we 1434 * started the calculation. We ignore that fact, since it's 1435 * not really that much of a problem. The background noise is 1436 * an estimation only anyway. Slightly wrong results will get damped 1437 * by the averaging of the 8 sample rounds. Additionally the 1438 * value is shortlived. So it will be replaced by the next noise 1439 * calculation round soon. */ 1440 1441 B43_WARN_ON(!dev->noisecalc.calculation_running); 1442 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); 1443 if (noise[0] == 0x7F || noise[1] == 0x7F || 1444 noise[2] == 0x7F || noise[3] == 0x7F) 1445 goto generate_new; 1446 1447 /* Get the noise samples. */ 1448 B43_WARN_ON(dev->noisecalc.nr_samples >= 8); 1449 i = dev->noisecalc.nr_samples; 1450 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1451 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1452 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1453 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); 1454 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; 1455 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; 1456 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; 1457 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; 1458 dev->noisecalc.nr_samples++; 1459 if (dev->noisecalc.nr_samples == 8) { 1460 /* Calculate the Link Quality by the noise samples. */ 1461 average = 0; 1462 for (i = 0; i < 8; i++) { 1463 for (j = 0; j < 4; j++) 1464 average += dev->noisecalc.samples[i][j]; 1465 } 1466 average /= (8 * 4); 1467 average *= 125; 1468 average += 64; 1469 average /= 128; 1470 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); 1471 tmp = (tmp / 128) & 0x1F; 1472 if (tmp >= 8) 1473 average += 2; 1474 else 1475 average -= 25; 1476 if (tmp == 8) 1477 average -= 72; 1478 else 1479 average -= 48; 1480 1481 dev->stats.link_noise = average; 1482 dev->noisecalc.calculation_running = false; 1483 return; 1484 } 1485 generate_new: 1486 b43_generate_noise_sample(dev); 1487 } 1488 1489 static void handle_irq_tbtt_indication(struct b43_wldev *dev) 1490 { 1491 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) { 1492 ///TODO: PS TBTT 1493 } else { 1494 if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) 1495 b43_power_saving_ctl_bits(dev, 0); 1496 } 1497 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 1498 dev->dfq_valid = true; 1499 } 1500 1501 static void handle_irq_atim_end(struct b43_wldev *dev) 1502 { 1503 if (dev->dfq_valid) { 1504 b43_write32(dev, B43_MMIO_MACCMD, 1505 b43_read32(dev, B43_MMIO_MACCMD) 1506 | B43_MACCMD_DFQ_VALID); 1507 dev->dfq_valid = false; 1508 } 1509 } 1510 1511 static void handle_irq_pmq(struct b43_wldev *dev) 1512 { 1513 u32 tmp; 1514 1515 //TODO: AP mode. 1516 1517 while (1) { 1518 tmp = b43_read32(dev, B43_MMIO_PS_STATUS); 1519 if (!(tmp & 0x00000008)) 1520 break; 1521 } 1522 /* 16bit write is odd, but correct. */ 1523 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); 1524 } 1525 1526 static void b43_write_template_common(struct b43_wldev *dev, 1527 const u8 *data, u16 size, 1528 u16 ram_offset, 1529 u16 shm_size_offset, u8 rate) 1530 { 1531 u32 i, tmp; 1532 struct b43_plcp_hdr4 plcp; 1533 1534 plcp.data = 0; 1535 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); 1536 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); 1537 ram_offset += sizeof(u32); 1538 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. 1539 * So leave the first two bytes of the next write blank. 1540 */ 1541 tmp = (u32) (data[0]) << 16; 1542 tmp |= (u32) (data[1]) << 24; 1543 b43_ram_write(dev, ram_offset, tmp); 1544 ram_offset += sizeof(u32); 1545 for (i = 2; i < size; i += sizeof(u32)) { 1546 tmp = (u32) (data[i + 0]); 1547 if (i + 1 < size) 1548 tmp |= (u32) (data[i + 1]) << 8; 1549 if (i + 2 < size) 1550 tmp |= (u32) (data[i + 2]) << 16; 1551 if (i + 3 < size) 1552 tmp |= (u32) (data[i + 3]) << 24; 1553 b43_ram_write(dev, ram_offset + i - 2, tmp); 1554 } 1555 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, 1556 size + sizeof(struct b43_plcp_hdr6)); 1557 } 1558 1559 /* Check if the use of the antenna that ieee80211 told us to 1560 * use is possible. This will fall back to DEFAULT. 1561 * "antenna_nr" is the antenna identifier we got from ieee80211. */ 1562 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, 1563 u8 antenna_nr) 1564 { 1565 u8 antenna_mask; 1566 1567 if (antenna_nr == 0) { 1568 /* Zero means "use default antenna". That's always OK. */ 1569 return 0; 1570 } 1571 1572 /* Get the mask of available antennas. */ 1573 if (dev->phy.gmode) 1574 antenna_mask = dev->dev->bus_sprom->ant_available_bg; 1575 else 1576 antenna_mask = dev->dev->bus_sprom->ant_available_a; 1577 1578 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 1579 /* This antenna is not available. Fall back to default. */ 1580 return 0; 1581 } 1582 1583 return antenna_nr; 1584 } 1585 1586 /* Convert a b43 antenna number value to the PHY TX control value. */ 1587 static u16 b43_antenna_to_phyctl(int antenna) 1588 { 1589 switch (antenna) { 1590 case B43_ANTENNA0: 1591 return B43_TXH_PHY_ANT0; 1592 case B43_ANTENNA1: 1593 return B43_TXH_PHY_ANT1; 1594 case B43_ANTENNA2: 1595 return B43_TXH_PHY_ANT2; 1596 case B43_ANTENNA3: 1597 return B43_TXH_PHY_ANT3; 1598 case B43_ANTENNA_AUTO0: 1599 case B43_ANTENNA_AUTO1: 1600 return B43_TXH_PHY_ANT01AUTO; 1601 } 1602 B43_WARN_ON(1); 1603 return 0; 1604 } 1605 1606 static void b43_write_beacon_template(struct b43_wldev *dev, 1607 u16 ram_offset, 1608 u16 shm_size_offset) 1609 { 1610 unsigned int i, len, variable_len; 1611 const struct ieee80211_mgmt *bcn; 1612 const u8 *ie; 1613 bool tim_found = false; 1614 unsigned int rate; 1615 u16 ctl; 1616 int antenna; 1617 struct ieee80211_tx_info *info; 1618 unsigned long flags; 1619 struct sk_buff *beacon_skb; 1620 1621 spin_lock_irqsave(&dev->wl->beacon_lock, flags); 1622 info = IEEE80211_SKB_CB(dev->wl->current_beacon); 1623 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; 1624 /* Clone the beacon, so it cannot go away, while we write it to hw. */ 1625 beacon_skb = skb_clone(dev->wl->current_beacon, GFP_ATOMIC); 1626 spin_unlock_irqrestore(&dev->wl->beacon_lock, flags); 1627 1628 if (!beacon_skb) { 1629 b43dbg(dev->wl, "Could not upload beacon. " 1630 "Failed to clone beacon skb."); 1631 return; 1632 } 1633 1634 bcn = (const struct ieee80211_mgmt *)(beacon_skb->data); 1635 len = min_t(size_t, beacon_skb->len, 1636 0x200 - sizeof(struct b43_plcp_hdr6)); 1637 1638 b43_write_template_common(dev, (const u8 *)bcn, 1639 len, ram_offset, shm_size_offset, rate); 1640 1641 /* Write the PHY TX control parameters. */ 1642 antenna = B43_ANTENNA_DEFAULT; 1643 antenna = b43_antenna_to_phyctl(antenna); 1644 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); 1645 /* We can't send beacons with short preamble. Would get PHY errors. */ 1646 ctl &= ~B43_TXH_PHY_SHORTPRMBL; 1647 ctl &= ~B43_TXH_PHY_ANT; 1648 ctl &= ~B43_TXH_PHY_ENC; 1649 ctl |= antenna; 1650 if (b43_is_cck_rate(rate)) 1651 ctl |= B43_TXH_PHY_ENC_CCK; 1652 else 1653 ctl |= B43_TXH_PHY_ENC_OFDM; 1654 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 1655 1656 /* Find the position of the TIM and the DTIM_period value 1657 * and write them to SHM. */ 1658 ie = bcn->u.beacon.variable; 1659 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); 1660 for (i = 0; i < variable_len - 2; ) { 1661 uint8_t ie_id, ie_len; 1662 1663 ie_id = ie[i]; 1664 ie_len = ie[i + 1]; 1665 if (ie_id == 5) { 1666 u16 tim_position; 1667 u16 dtim_period; 1668 /* This is the TIM Information Element */ 1669 1670 /* Check whether the ie_len is in the beacon data range. */ 1671 if (variable_len < ie_len + 2 + i) 1672 break; 1673 /* A valid TIM is at least 4 bytes long. */ 1674 if (ie_len < 4) 1675 break; 1676 tim_found = true; 1677 1678 tim_position = sizeof(struct b43_plcp_hdr6); 1679 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); 1680 tim_position += i; 1681 1682 dtim_period = ie[i + 3]; 1683 1684 b43_shm_write16(dev, B43_SHM_SHARED, 1685 B43_SHM_SH_TIMBPOS, tim_position); 1686 b43_shm_write16(dev, B43_SHM_SHARED, 1687 B43_SHM_SH_DTIMPER, dtim_period); 1688 break; 1689 } 1690 i += ie_len + 2; 1691 } 1692 if (!tim_found) { 1693 /* 1694 * If ucode wants to modify TIM do it behind the beacon, this 1695 * will happen, for example, when doing mesh networking. 1696 */ 1697 b43_shm_write16(dev, B43_SHM_SHARED, 1698 B43_SHM_SH_TIMBPOS, 1699 len + sizeof(struct b43_plcp_hdr6)); 1700 b43_shm_write16(dev, B43_SHM_SHARED, 1701 B43_SHM_SH_DTIMPER, 0); 1702 } 1703 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); 1704 1705 dev_kfree_skb_any(beacon_skb); 1706 } 1707 1708 static void b43_upload_beacon0(struct b43_wldev *dev) 1709 { 1710 struct b43_wl *wl = dev->wl; 1711 1712 if (wl->beacon0_uploaded) 1713 return; 1714 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0); 1715 wl->beacon0_uploaded = true; 1716 } 1717 1718 static void b43_upload_beacon1(struct b43_wldev *dev) 1719 { 1720 struct b43_wl *wl = dev->wl; 1721 1722 if (wl->beacon1_uploaded) 1723 return; 1724 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1); 1725 wl->beacon1_uploaded = true; 1726 } 1727 1728 static void handle_irq_beacon(struct b43_wldev *dev) 1729 { 1730 struct b43_wl *wl = dev->wl; 1731 u32 cmd, beacon0_valid, beacon1_valid; 1732 1733 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && 1734 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) && 1735 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 1736 return; 1737 1738 /* This is the bottom half of the asynchronous beacon update. */ 1739 1740 /* Ignore interrupt in the future. */ 1741 dev->irq_mask &= ~B43_IRQ_BEACON; 1742 1743 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1744 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); 1745 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); 1746 1747 /* Schedule interrupt manually, if busy. */ 1748 if (beacon0_valid && beacon1_valid) { 1749 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); 1750 dev->irq_mask |= B43_IRQ_BEACON; 1751 return; 1752 } 1753 1754 if (unlikely(wl->beacon_templates_virgin)) { 1755 /* We never uploaded a beacon before. 1756 * Upload both templates now, but only mark one valid. */ 1757 wl->beacon_templates_virgin = false; 1758 b43_upload_beacon0(dev); 1759 b43_upload_beacon1(dev); 1760 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1761 cmd |= B43_MACCMD_BEACON0_VALID; 1762 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1763 } else { 1764 if (!beacon0_valid) { 1765 b43_upload_beacon0(dev); 1766 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1767 cmd |= B43_MACCMD_BEACON0_VALID; 1768 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1769 } else if (!beacon1_valid) { 1770 b43_upload_beacon1(dev); 1771 cmd = b43_read32(dev, B43_MMIO_MACCMD); 1772 cmd |= B43_MACCMD_BEACON1_VALID; 1773 b43_write32(dev, B43_MMIO_MACCMD, cmd); 1774 } 1775 } 1776 } 1777 1778 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev) 1779 { 1780 u32 old_irq_mask = dev->irq_mask; 1781 1782 /* update beacon right away or defer to irq */ 1783 handle_irq_beacon(dev); 1784 if (old_irq_mask != dev->irq_mask) { 1785 /* The handler updated the IRQ mask. */ 1786 B43_WARN_ON(!dev->irq_mask); 1787 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) { 1788 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 1789 } else { 1790 /* Device interrupts are currently disabled. That means 1791 * we just ran the hardirq handler and scheduled the 1792 * IRQ thread. The thread will write the IRQ mask when 1793 * it finished, so there's nothing to do here. Writing 1794 * the mask _here_ would incorrectly re-enable IRQs. */ 1795 } 1796 } 1797 } 1798 1799 static void b43_beacon_update_trigger_work(struct work_struct *work) 1800 { 1801 struct b43_wl *wl = container_of(work, struct b43_wl, 1802 beacon_update_trigger); 1803 struct b43_wldev *dev; 1804 1805 mutex_lock(&wl->mutex); 1806 dev = wl->current_dev; 1807 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { 1808 if (b43_bus_host_is_sdio(dev->dev)) { 1809 /* wl->mutex is enough. */ 1810 b43_do_beacon_update_trigger_work(dev); 1811 } else { 1812 spin_lock_irq(&wl->hardirq_lock); 1813 b43_do_beacon_update_trigger_work(dev); 1814 spin_unlock_irq(&wl->hardirq_lock); 1815 } 1816 } 1817 mutex_unlock(&wl->mutex); 1818 } 1819 1820 /* Asynchronously update the packet templates in template RAM. */ 1821 static void b43_update_templates(struct b43_wl *wl) 1822 { 1823 struct sk_buff *beacon, *old_beacon; 1824 unsigned long flags; 1825 1826 /* This is the top half of the asynchronous beacon update. 1827 * The bottom half is the beacon IRQ. 1828 * Beacon update must be asynchronous to avoid sending an 1829 * invalid beacon. This can happen for example, if the firmware 1830 * transmits a beacon while we are updating it. */ 1831 1832 /* We could modify the existing beacon and set the aid bit in 1833 * the TIM field, but that would probably require resizing and 1834 * moving of data within the beacon template. 1835 * Simply request a new beacon and let mac80211 do the hard work. */ 1836 beacon = ieee80211_beacon_get(wl->hw, wl->vif, 0); 1837 if (unlikely(!beacon)) 1838 return; 1839 1840 spin_lock_irqsave(&wl->beacon_lock, flags); 1841 old_beacon = wl->current_beacon; 1842 wl->current_beacon = beacon; 1843 wl->beacon0_uploaded = false; 1844 wl->beacon1_uploaded = false; 1845 spin_unlock_irqrestore(&wl->beacon_lock, flags); 1846 1847 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); 1848 1849 if (old_beacon) 1850 dev_kfree_skb_any(old_beacon); 1851 } 1852 1853 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1854 { 1855 b43_time_lock(dev); 1856 if (dev->dev->core_rev >= 3) { 1857 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); 1858 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); 1859 } else { 1860 b43_write16(dev, 0x606, (beacon_int >> 6)); 1861 b43_write16(dev, 0x610, beacon_int); 1862 } 1863 b43_time_unlock(dev); 1864 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); 1865 } 1866 1867 static void b43_handle_firmware_panic(struct b43_wldev *dev) 1868 { 1869 u16 reason; 1870 1871 /* Read the register that contains the reason code for the panic. */ 1872 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG); 1873 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason); 1874 1875 switch (reason) { 1876 default: 1877 b43dbg(dev->wl, "The panic reason is unknown.\n"); 1878 fallthrough; 1879 case B43_FWPANIC_DIE: 1880 /* Do not restart the controller or firmware. 1881 * The device is nonfunctional from now on. 1882 * Restarting would result in this panic to trigger again, 1883 * so we avoid that recursion. */ 1884 break; 1885 case B43_FWPANIC_RESTART: 1886 b43_controller_restart(dev, "Microcode panic"); 1887 break; 1888 } 1889 } 1890 1891 static void handle_irq_ucode_debug(struct b43_wldev *dev) 1892 { 1893 unsigned int i, cnt; 1894 u16 reason, marker_id, marker_line; 1895 __le16 *buf; 1896 1897 /* The proprietary firmware doesn't have this IRQ. */ 1898 if (!dev->fw.opensource) 1899 return; 1900 1901 /* Read the register that contains the reason code for this IRQ. */ 1902 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG); 1903 1904 switch (reason) { 1905 case B43_DEBUGIRQ_PANIC: 1906 b43_handle_firmware_panic(dev); 1907 break; 1908 case B43_DEBUGIRQ_DUMP_SHM: 1909 if (!B43_DEBUG) 1910 break; /* Only with driver debugging enabled. */ 1911 buf = kmalloc(4096, GFP_ATOMIC); 1912 if (!buf) { 1913 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n"); 1914 goto out; 1915 } 1916 for (i = 0; i < 4096; i += 2) { 1917 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i); 1918 buf[i / 2] = cpu_to_le16(tmp); 1919 } 1920 b43info(dev->wl, "Shared memory dump:\n"); 1921 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 1922 16, 2, buf, 4096, 1); 1923 kfree(buf); 1924 break; 1925 case B43_DEBUGIRQ_DUMP_REGS: 1926 if (!B43_DEBUG) 1927 break; /* Only with driver debugging enabled. */ 1928 b43info(dev->wl, "Microcode register dump:\n"); 1929 for (i = 0, cnt = 0; i < 64; i++) { 1930 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i); 1931 if (cnt == 0) 1932 printk(KERN_INFO); 1933 printk("r%02u: 0x%04X ", i, tmp); 1934 cnt++; 1935 if (cnt == 6) { 1936 printk("\n"); 1937 cnt = 0; 1938 } 1939 } 1940 printk("\n"); 1941 break; 1942 case B43_DEBUGIRQ_MARKER: 1943 if (!B43_DEBUG) 1944 break; /* Only with driver debugging enabled. */ 1945 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH, 1946 B43_MARKER_ID_REG); 1947 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH, 1948 B43_MARKER_LINE_REG); 1949 b43info(dev->wl, "The firmware just executed the MARKER(%u) " 1950 "at line number %u\n", 1951 marker_id, marker_line); 1952 break; 1953 default: 1954 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n", 1955 reason); 1956 } 1957 out: 1958 /* Acknowledge the debug-IRQ, so the firmware can continue. */ 1959 b43_shm_write16(dev, B43_SHM_SCRATCH, 1960 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK); 1961 } 1962 1963 static void b43_do_interrupt_thread(struct b43_wldev *dev) 1964 { 1965 u32 reason; 1966 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; 1967 u32 merged_dma_reason = 0; 1968 int i; 1969 1970 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 1971 return; 1972 1973 reason = dev->irq_reason; 1974 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { 1975 dma_reason[i] = dev->dma_reason[i]; 1976 merged_dma_reason |= dma_reason[i]; 1977 } 1978 1979 if (unlikely(reason & B43_IRQ_MAC_TXERR)) 1980 b43err(dev->wl, "MAC transmission error\n"); 1981 1982 if (unlikely(reason & B43_IRQ_PHY_TXERR)) { 1983 b43err(dev->wl, "PHY transmission error\n"); 1984 rmb(); 1985 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { 1986 atomic_set(&dev->phy.txerr_cnt, 1987 B43_PHY_TX_BADNESS_LIMIT); 1988 b43err(dev->wl, "Too many PHY TX errors, " 1989 "restarting the controller\n"); 1990 b43_controller_restart(dev, "PHY TX errors"); 1991 } 1992 } 1993 1994 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) { 1995 b43err(dev->wl, 1996 "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n", 1997 dma_reason[0], dma_reason[1], 1998 dma_reason[2], dma_reason[3], 1999 dma_reason[4], dma_reason[5]); 2000 b43err(dev->wl, "This device does not support DMA " 2001 "on your system. It will now be switched to PIO.\n"); 2002 /* Fall back to PIO transfers if we get fatal DMA errors! */ 2003 dev->use_pio = true; 2004 b43_controller_restart(dev, "DMA error"); 2005 return; 2006 } 2007 2008 if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) 2009 handle_irq_ucode_debug(dev); 2010 if (reason & B43_IRQ_TBTT_INDI) 2011 handle_irq_tbtt_indication(dev); 2012 if (reason & B43_IRQ_ATIM_END) 2013 handle_irq_atim_end(dev); 2014 if (reason & B43_IRQ_BEACON) 2015 handle_irq_beacon(dev); 2016 if (reason & B43_IRQ_PMQ) 2017 handle_irq_pmq(dev); 2018 if (reason & B43_IRQ_TXFIFO_FLUSH_OK) { 2019 ;/* TODO */ 2020 } 2021 if (reason & B43_IRQ_NOISESAMPLE_OK) 2022 handle_irq_noise(dev); 2023 2024 /* Check the DMA reason registers for received data. */ 2025 if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) { 2026 if (B43_DEBUG) 2027 b43warn(dev->wl, "RX descriptor underrun\n"); 2028 b43_dma_handle_rx_overflow(dev->dma.rx_ring); 2029 } 2030 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { 2031 if (b43_using_pio_transfers(dev)) 2032 b43_pio_rx(dev->pio.rx_queue); 2033 else 2034 b43_dma_rx(dev->dma.rx_ring); 2035 } 2036 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); 2037 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); 2038 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); 2039 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); 2040 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); 2041 2042 if (reason & B43_IRQ_TX_OK) 2043 handle_irq_transmit_status(dev); 2044 2045 /* Re-enable interrupts on the device by restoring the current interrupt mask. */ 2046 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 2047 2048 #if B43_DEBUG 2049 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 2050 dev->irq_count++; 2051 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 2052 if (reason & (1 << i)) 2053 dev->irq_bit_count[i]++; 2054 } 2055 } 2056 #endif 2057 } 2058 2059 /* Interrupt thread handler. Handles device interrupts in thread context. */ 2060 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id) 2061 { 2062 struct b43_wldev *dev = dev_id; 2063 2064 mutex_lock(&dev->wl->mutex); 2065 b43_do_interrupt_thread(dev); 2066 mutex_unlock(&dev->wl->mutex); 2067 2068 return IRQ_HANDLED; 2069 } 2070 2071 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev) 2072 { 2073 u32 reason; 2074 2075 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses. 2076 * On SDIO, this runs under wl->mutex. */ 2077 2078 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2079 if (reason == 0xffffffff) /* shared IRQ */ 2080 return IRQ_NONE; 2081 reason &= dev->irq_mask; 2082 if (!reason) 2083 return IRQ_NONE; 2084 2085 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 2086 & 0x0001FC00; 2087 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) 2088 & 0x0000DC00; 2089 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) 2090 & 0x0000DC00; 2091 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) 2092 & 0x0001DC00; 2093 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) 2094 & 0x0000DC00; 2095 /* Unused ring 2096 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) 2097 & 0x0000DC00; 2098 */ 2099 2100 /* ACK the interrupt. */ 2101 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); 2102 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); 2103 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); 2104 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); 2105 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); 2106 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); 2107 /* Unused ring 2108 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); 2109 */ 2110 2111 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */ 2112 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 2113 /* Save the reason bitmasks for the IRQ thread handler. */ 2114 dev->irq_reason = reason; 2115 2116 return IRQ_WAKE_THREAD; 2117 } 2118 2119 /* Interrupt handler top-half. This runs with interrupts disabled. */ 2120 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) 2121 { 2122 struct b43_wldev *dev = dev_id; 2123 irqreturn_t ret; 2124 2125 if (unlikely(b43_status(dev) < B43_STAT_STARTED)) 2126 return IRQ_NONE; 2127 2128 spin_lock(&dev->wl->hardirq_lock); 2129 ret = b43_do_interrupt(dev); 2130 spin_unlock(&dev->wl->hardirq_lock); 2131 2132 return ret; 2133 } 2134 2135 /* SDIO interrupt handler. This runs in process context. */ 2136 static void b43_sdio_interrupt_handler(struct b43_wldev *dev) 2137 { 2138 struct b43_wl *wl = dev->wl; 2139 irqreturn_t ret; 2140 2141 mutex_lock(&wl->mutex); 2142 2143 ret = b43_do_interrupt(dev); 2144 if (ret == IRQ_WAKE_THREAD) 2145 b43_do_interrupt_thread(dev); 2146 2147 mutex_unlock(&wl->mutex); 2148 } 2149 2150 void b43_do_release_fw(struct b43_firmware_file *fw) 2151 { 2152 release_firmware(fw->data); 2153 fw->data = NULL; 2154 fw->filename = NULL; 2155 } 2156 2157 static void b43_release_firmware(struct b43_wldev *dev) 2158 { 2159 complete(&dev->fw_load_complete); 2160 b43_do_release_fw(&dev->fw.ucode); 2161 b43_do_release_fw(&dev->fw.pcm); 2162 b43_do_release_fw(&dev->fw.initvals); 2163 b43_do_release_fw(&dev->fw.initvals_band); 2164 } 2165 2166 static void b43_print_fw_helptext(struct b43_wl *wl, bool error) 2167 { 2168 const char text[] = 2169 "You must go to " \ 2170 "https://wireless.docs.kernel.org/en/latest/en/users/drivers/b43/developers.html#list-of-firmware " \ 2171 "and download the correct firmware for this driver version. " \ 2172 "Please carefully read all instructions on this website.\n"; 2173 2174 if (error) 2175 b43err(wl, text); 2176 else 2177 b43warn(wl, text); 2178 } 2179 2180 static void b43_fw_cb(const struct firmware *firmware, void *context) 2181 { 2182 struct b43_request_fw_context *ctx = context; 2183 2184 ctx->blob = firmware; 2185 complete(&ctx->dev->fw_load_complete); 2186 } 2187 2188 int b43_do_request_fw(struct b43_request_fw_context *ctx, 2189 const char *name, 2190 struct b43_firmware_file *fw, bool async) 2191 { 2192 struct b43_fw_header *hdr; 2193 u32 size; 2194 int err; 2195 2196 if (!name) { 2197 /* Don't fetch anything. Free possibly cached firmware. */ 2198 /* FIXME: We should probably keep it anyway, to save some headache 2199 * on suspend/resume with multiband devices. */ 2200 b43_do_release_fw(fw); 2201 return 0; 2202 } 2203 if (fw->filename) { 2204 if ((fw->type == ctx->req_type) && 2205 (strcmp(fw->filename, name) == 0)) 2206 return 0; /* Already have this fw. */ 2207 /* Free the cached firmware first. */ 2208 /* FIXME: We should probably do this later after we successfully 2209 * got the new fw. This could reduce headache with multiband devices. 2210 * We could also redesign this to cache the firmware for all possible 2211 * bands all the time. */ 2212 b43_do_release_fw(fw); 2213 } 2214 2215 switch (ctx->req_type) { 2216 case B43_FWTYPE_PROPRIETARY: 2217 snprintf(ctx->fwname, sizeof(ctx->fwname), 2218 "b43%s/%s.fw", 2219 modparam_fwpostfix, name); 2220 break; 2221 case B43_FWTYPE_OPENSOURCE: 2222 snprintf(ctx->fwname, sizeof(ctx->fwname), 2223 "b43-open%s/%s.fw", 2224 modparam_fwpostfix, name); 2225 break; 2226 default: 2227 B43_WARN_ON(1); 2228 return -ENOSYS; 2229 } 2230 if (async) { 2231 /* do this part asynchronously */ 2232 init_completion(&ctx->dev->fw_load_complete); 2233 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname, 2234 ctx->dev->dev->dev, GFP_KERNEL, 2235 ctx, b43_fw_cb); 2236 if (err < 0) { 2237 pr_err("Unable to load firmware\n"); 2238 return err; 2239 } 2240 wait_for_completion(&ctx->dev->fw_load_complete); 2241 if (ctx->blob) 2242 goto fw_ready; 2243 /* On some ARM systems, the async request will fail, but the next sync 2244 * request works. For this reason, we fall through here 2245 */ 2246 } 2247 err = request_firmware(&ctx->blob, ctx->fwname, 2248 ctx->dev->dev->dev); 2249 if (err == -ENOENT) { 2250 snprintf(ctx->errors[ctx->req_type], 2251 sizeof(ctx->errors[ctx->req_type]), 2252 "Firmware file \"%s\" not found\n", 2253 ctx->fwname); 2254 return err; 2255 } else if (err) { 2256 snprintf(ctx->errors[ctx->req_type], 2257 sizeof(ctx->errors[ctx->req_type]), 2258 "Firmware file \"%s\" request failed (err=%d)\n", 2259 ctx->fwname, err); 2260 return err; 2261 } 2262 fw_ready: 2263 if (ctx->blob->size < sizeof(struct b43_fw_header)) 2264 goto err_format; 2265 hdr = (struct b43_fw_header *)(ctx->blob->data); 2266 switch (hdr->type) { 2267 case B43_FW_TYPE_UCODE: 2268 case B43_FW_TYPE_PCM: 2269 size = be32_to_cpu(hdr->size); 2270 if (size != ctx->blob->size - sizeof(struct b43_fw_header)) 2271 goto err_format; 2272 fallthrough; 2273 case B43_FW_TYPE_IV: 2274 if (hdr->ver != 1) 2275 goto err_format; 2276 break; 2277 default: 2278 goto err_format; 2279 } 2280 2281 fw->data = ctx->blob; 2282 fw->filename = name; 2283 fw->type = ctx->req_type; 2284 2285 return 0; 2286 2287 err_format: 2288 snprintf(ctx->errors[ctx->req_type], 2289 sizeof(ctx->errors[ctx->req_type]), 2290 "Firmware file \"%s\" format error.\n", ctx->fwname); 2291 release_firmware(ctx->blob); 2292 2293 return -EPROTO; 2294 } 2295 2296 /* https://bcm-v4.sipsolutions.net/802.11/Init/Firmware */ 2297 static int b43_try_request_fw(struct b43_request_fw_context *ctx) 2298 { 2299 struct b43_wldev *dev = ctx->dev; 2300 struct b43_firmware *fw = &ctx->dev->fw; 2301 struct b43_phy *phy = &dev->phy; 2302 const u8 rev = ctx->dev->dev->core_rev; 2303 const char *filename; 2304 int err; 2305 2306 /* Get microcode */ 2307 filename = NULL; 2308 switch (rev) { 2309 case 42: 2310 if (phy->type == B43_PHYTYPE_AC) 2311 filename = "ucode42"; 2312 break; 2313 case 40: 2314 if (phy->type == B43_PHYTYPE_AC) 2315 filename = "ucode40"; 2316 break; 2317 case 33: 2318 if (phy->type == B43_PHYTYPE_LCN40) 2319 filename = "ucode33_lcn40"; 2320 break; 2321 case 30: 2322 if (phy->type == B43_PHYTYPE_N) 2323 filename = "ucode30_mimo"; 2324 break; 2325 case 29: 2326 if (phy->type == B43_PHYTYPE_HT) 2327 filename = "ucode29_mimo"; 2328 break; 2329 case 26: 2330 if (phy->type == B43_PHYTYPE_HT) 2331 filename = "ucode26_mimo"; 2332 break; 2333 case 28: 2334 case 25: 2335 if (phy->type == B43_PHYTYPE_N) 2336 filename = "ucode25_mimo"; 2337 else if (phy->type == B43_PHYTYPE_LCN) 2338 filename = "ucode25_lcn"; 2339 break; 2340 case 24: 2341 if (phy->type == B43_PHYTYPE_LCN) 2342 filename = "ucode24_lcn"; 2343 break; 2344 case 23: 2345 if (phy->type == B43_PHYTYPE_N) 2346 filename = "ucode16_mimo"; 2347 break; 2348 case 22: 2349 if (phy->type == B43_PHYTYPE_N) 2350 filename = "ucode22_mimo"; 2351 break; 2352 case 16 ... 19: 2353 if (phy->type == B43_PHYTYPE_N) 2354 filename = "ucode16_mimo"; 2355 else if (phy->type == B43_PHYTYPE_LP) 2356 filename = "ucode16_lp"; 2357 break; 2358 case 15: 2359 filename = "ucode15"; 2360 break; 2361 case 14: 2362 filename = "ucode14"; 2363 break; 2364 case 13: 2365 filename = "ucode13"; 2366 break; 2367 case 11 ... 12: 2368 filename = "ucode11"; 2369 break; 2370 case 5 ... 10: 2371 filename = "ucode5"; 2372 break; 2373 } 2374 if (!filename) 2375 goto err_no_ucode; 2376 err = b43_do_request_fw(ctx, filename, &fw->ucode, true); 2377 if (err) 2378 goto err_load; 2379 2380 /* Get PCM code */ 2381 if ((rev >= 5) && (rev <= 10)) 2382 filename = "pcm5"; 2383 else if (rev >= 11) 2384 filename = NULL; 2385 else 2386 goto err_no_pcm; 2387 fw->pcm_request_failed = false; 2388 err = b43_do_request_fw(ctx, filename, &fw->pcm, false); 2389 if (err == -ENOENT) { 2390 /* We did not find a PCM file? Not fatal, but 2391 * core rev <= 10 must do without hwcrypto then. */ 2392 fw->pcm_request_failed = true; 2393 } else if (err) 2394 goto err_load; 2395 2396 /* Get initvals */ 2397 filename = NULL; 2398 switch (dev->phy.type) { 2399 case B43_PHYTYPE_G: 2400 if (rev == 13) 2401 filename = "b0g0initvals13"; 2402 else if (rev >= 5 && rev <= 10) 2403 filename = "b0g0initvals5"; 2404 break; 2405 case B43_PHYTYPE_N: 2406 if (rev == 30) 2407 filename = "n16initvals30"; 2408 else if (rev == 28 || rev == 25) 2409 filename = "n0initvals25"; 2410 else if (rev == 24) 2411 filename = "n0initvals24"; 2412 else if (rev == 23) 2413 filename = "n0initvals16"; 2414 else if (rev == 22) 2415 filename = "n0initvals22"; 2416 else if (rev >= 16 && rev <= 18) 2417 filename = "n0initvals16"; 2418 else if (rev >= 11 && rev <= 12) 2419 filename = "n0initvals11"; 2420 break; 2421 case B43_PHYTYPE_LP: 2422 if (rev >= 16 && rev <= 18) 2423 filename = "lp0initvals16"; 2424 else if (rev == 15) 2425 filename = "lp0initvals15"; 2426 else if (rev == 14) 2427 filename = "lp0initvals14"; 2428 else if (rev == 13) 2429 filename = "lp0initvals13"; 2430 break; 2431 case B43_PHYTYPE_HT: 2432 if (rev == 29) 2433 filename = "ht0initvals29"; 2434 else if (rev == 26) 2435 filename = "ht0initvals26"; 2436 break; 2437 case B43_PHYTYPE_LCN: 2438 if (rev == 24) 2439 filename = "lcn0initvals24"; 2440 break; 2441 case B43_PHYTYPE_LCN40: 2442 if (rev == 33) 2443 filename = "lcn400initvals33"; 2444 break; 2445 case B43_PHYTYPE_AC: 2446 if (rev == 42) 2447 filename = "ac1initvals42"; 2448 else if (rev == 40) 2449 filename = "ac0initvals40"; 2450 break; 2451 } 2452 if (!filename) 2453 goto err_no_initvals; 2454 err = b43_do_request_fw(ctx, filename, &fw->initvals, false); 2455 if (err) 2456 goto err_load; 2457 2458 /* Get bandswitch initvals */ 2459 filename = NULL; 2460 switch (dev->phy.type) { 2461 case B43_PHYTYPE_G: 2462 if (rev == 13) 2463 filename = "b0g0bsinitvals13"; 2464 else if (rev >= 5 && rev <= 10) 2465 filename = "b0g0bsinitvals5"; 2466 break; 2467 case B43_PHYTYPE_N: 2468 if (rev == 30) 2469 filename = "n16bsinitvals30"; 2470 else if (rev == 28 || rev == 25) 2471 filename = "n0bsinitvals25"; 2472 else if (rev == 24) 2473 filename = "n0bsinitvals24"; 2474 else if (rev == 23) 2475 filename = "n0bsinitvals16"; 2476 else if (rev == 22) 2477 filename = "n0bsinitvals22"; 2478 else if (rev >= 16 && rev <= 18) 2479 filename = "n0bsinitvals16"; 2480 else if (rev >= 11 && rev <= 12) 2481 filename = "n0bsinitvals11"; 2482 break; 2483 case B43_PHYTYPE_LP: 2484 if (rev >= 16 && rev <= 18) 2485 filename = "lp0bsinitvals16"; 2486 else if (rev == 15) 2487 filename = "lp0bsinitvals15"; 2488 else if (rev == 14) 2489 filename = "lp0bsinitvals14"; 2490 else if (rev == 13) 2491 filename = "lp0bsinitvals13"; 2492 break; 2493 case B43_PHYTYPE_HT: 2494 if (rev == 29) 2495 filename = "ht0bsinitvals29"; 2496 else if (rev == 26) 2497 filename = "ht0bsinitvals26"; 2498 break; 2499 case B43_PHYTYPE_LCN: 2500 if (rev == 24) 2501 filename = "lcn0bsinitvals24"; 2502 break; 2503 case B43_PHYTYPE_LCN40: 2504 if (rev == 33) 2505 filename = "lcn400bsinitvals33"; 2506 break; 2507 case B43_PHYTYPE_AC: 2508 if (rev == 42) 2509 filename = "ac1bsinitvals42"; 2510 else if (rev == 40) 2511 filename = "ac0bsinitvals40"; 2512 break; 2513 } 2514 if (!filename) 2515 goto err_no_initvals; 2516 err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false); 2517 if (err) 2518 goto err_load; 2519 2520 fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE); 2521 2522 return 0; 2523 2524 err_no_ucode: 2525 err = ctx->fatal_failure = -EOPNOTSUPP; 2526 b43err(dev->wl, "The driver does not know which firmware (ucode) " 2527 "is required for your device (wl-core rev %u)\n", rev); 2528 goto error; 2529 2530 err_no_pcm: 2531 err = ctx->fatal_failure = -EOPNOTSUPP; 2532 b43err(dev->wl, "The driver does not know which firmware (PCM) " 2533 "is required for your device (wl-core rev %u)\n", rev); 2534 goto error; 2535 2536 err_no_initvals: 2537 err = ctx->fatal_failure = -EOPNOTSUPP; 2538 b43err(dev->wl, "The driver does not know which firmware (initvals) " 2539 "is required for your device (wl-core rev %u)\n", rev); 2540 goto error; 2541 2542 err_load: 2543 /* We failed to load this firmware image. The error message 2544 * already is in ctx->errors. Return and let our caller decide 2545 * what to do. */ 2546 goto error; 2547 2548 error: 2549 b43_release_firmware(dev); 2550 return err; 2551 } 2552 2553 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl); 2554 static void b43_one_core_detach(struct b43_bus_dev *dev); 2555 static int b43_rng_init(struct b43_wl *wl); 2556 2557 static void b43_request_firmware(struct work_struct *work) 2558 { 2559 struct b43_wl *wl = container_of(work, 2560 struct b43_wl, firmware_load); 2561 struct b43_wldev *dev = wl->current_dev; 2562 struct b43_request_fw_context *ctx; 2563 unsigned int i; 2564 int err; 2565 const char *errmsg; 2566 2567 ctx = kzalloc_obj(*ctx); 2568 if (!ctx) 2569 return; 2570 ctx->dev = dev; 2571 2572 ctx->req_type = B43_FWTYPE_PROPRIETARY; 2573 err = b43_try_request_fw(ctx); 2574 if (!err) 2575 goto start_ieee80211; /* Successfully loaded it. */ 2576 /* Was fw version known? */ 2577 if (ctx->fatal_failure) 2578 goto out; 2579 2580 /* proprietary fw not found, try open source */ 2581 ctx->req_type = B43_FWTYPE_OPENSOURCE; 2582 err = b43_try_request_fw(ctx); 2583 if (!err) 2584 goto start_ieee80211; /* Successfully loaded it. */ 2585 if(ctx->fatal_failure) 2586 goto out; 2587 2588 /* Could not find a usable firmware. Print the errors. */ 2589 for (i = 0; i < B43_NR_FWTYPES; i++) { 2590 errmsg = ctx->errors[i]; 2591 if (strlen(errmsg)) 2592 b43err(dev->wl, "%s", errmsg); 2593 } 2594 b43_print_fw_helptext(dev->wl, 1); 2595 goto out; 2596 2597 start_ieee80211: 2598 wl->hw->queues = B43_QOS_QUEUE_NUM; 2599 if (!modparam_qos || dev->fw.opensource || 2600 dev->dev->chip_id == BCMA_CHIP_ID_BCM4331) 2601 wl->hw->queues = 1; 2602 2603 err = ieee80211_register_hw(wl->hw); 2604 if (err) 2605 goto out; 2606 wl->hw_registered = true; 2607 b43_leds_register(wl->current_dev); 2608 2609 /* Register HW RNG driver */ 2610 b43_rng_init(wl); 2611 2612 out: 2613 kfree(ctx); 2614 } 2615 2616 static int b43_upload_microcode(struct b43_wldev *dev) 2617 { 2618 struct wiphy *wiphy = dev->wl->hw->wiphy; 2619 const size_t hdr_len = sizeof(struct b43_fw_header); 2620 const __be32 *data; 2621 unsigned int i, len; 2622 u16 fwrev, fwpatch, fwdate, fwtime; 2623 u32 tmp, macctl; 2624 int err = 0; 2625 2626 /* Jump the microcode PSM to offset 0 */ 2627 macctl = b43_read32(dev, B43_MMIO_MACCTL); 2628 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); 2629 macctl |= B43_MACCTL_PSM_JMP0; 2630 b43_write32(dev, B43_MMIO_MACCTL, macctl); 2631 /* Zero out all microcode PSM registers and shared memory. */ 2632 for (i = 0; i < 64; i++) 2633 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); 2634 for (i = 0; i < 4096; i += 2) 2635 b43_shm_write16(dev, B43_SHM_SHARED, i, 0); 2636 2637 /* Upload Microcode. */ 2638 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); 2639 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); 2640 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); 2641 for (i = 0; i < len; i++) { 2642 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2643 udelay(10); 2644 } 2645 2646 if (dev->fw.pcm.data) { 2647 /* Upload PCM data. */ 2648 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); 2649 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); 2650 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); 2651 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); 2652 /* No need for autoinc bit in SHM_HW */ 2653 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); 2654 for (i = 0; i < len; i++) { 2655 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); 2656 udelay(10); 2657 } 2658 } 2659 2660 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); 2661 2662 /* Start the microcode PSM */ 2663 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0, 2664 B43_MACCTL_PSM_RUN); 2665 2666 /* Wait for the microcode to load and respond */ 2667 i = 0; 2668 while (1) { 2669 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2670 if (tmp == B43_IRQ_MAC_SUSPENDED) 2671 break; 2672 i++; 2673 if (i >= 20) { 2674 b43err(dev->wl, "Microcode not responding\n"); 2675 b43_print_fw_helptext(dev->wl, 1); 2676 err = -ENODEV; 2677 goto error; 2678 } 2679 msleep(50); 2680 } 2681 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ 2682 2683 /* Get and check the revisions. */ 2684 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); 2685 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); 2686 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); 2687 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); 2688 2689 if (fwrev <= 0x128) { 2690 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " 2691 "binary drivers older than version 4.x is unsupported. " 2692 "You must upgrade your firmware files.\n"); 2693 b43_print_fw_helptext(dev->wl, 1); 2694 err = -EOPNOTSUPP; 2695 goto error; 2696 } 2697 dev->fw.rev = fwrev; 2698 dev->fw.patch = fwpatch; 2699 if (dev->fw.rev >= 598) 2700 dev->fw.hdr_format = B43_FW_HDR_598; 2701 else if (dev->fw.rev >= 410) 2702 dev->fw.hdr_format = B43_FW_HDR_410; 2703 else 2704 dev->fw.hdr_format = B43_FW_HDR_351; 2705 WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF)); 2706 2707 dev->qos_enabled = dev->wl->hw->queues > 1; 2708 /* Default to firmware/hardware crypto acceleration. */ 2709 dev->hwcrypto_enabled = true; 2710 2711 if (dev->fw.opensource) { 2712 u16 fwcapa; 2713 2714 /* Patchlevel info is encoded in the "time" field. */ 2715 dev->fw.patch = fwtime; 2716 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n", 2717 dev->fw.rev, dev->fw.patch); 2718 2719 fwcapa = b43_fwcapa_read(dev); 2720 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) { 2721 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n"); 2722 /* Disable hardware crypto and fall back to software crypto. */ 2723 dev->hwcrypto_enabled = false; 2724 } 2725 /* adding QoS support should use an offline discovery mechanism */ 2726 WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n"); 2727 } else { 2728 b43info(dev->wl, "Loading firmware version %u.%u " 2729 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", 2730 fwrev, fwpatch, 2731 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, 2732 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); 2733 if (dev->fw.pcm_request_failed) { 2734 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. " 2735 "Hardware accelerated cryptography is disabled.\n"); 2736 b43_print_fw_helptext(dev->wl, 0); 2737 } 2738 } 2739 2740 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", 2741 dev->fw.rev, dev->fw.patch); 2742 wiphy->hw_version = dev->dev->core_id; 2743 2744 if (dev->fw.hdr_format == B43_FW_HDR_351) { 2745 /* We're over the deadline, but we keep support for old fw 2746 * until it turns out to be in major conflict with something new. */ 2747 b43warn(dev->wl, "You are using an old firmware image. " 2748 "Support for old firmware will be removed soon " 2749 "(official deadline was July 2008).\n"); 2750 b43_print_fw_helptext(dev->wl, 0); 2751 } 2752 2753 return 0; 2754 2755 error: 2756 /* Stop the microcode PSM. */ 2757 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN, 2758 B43_MACCTL_PSM_JMP0); 2759 2760 return err; 2761 } 2762 2763 static int b43_write_initvals(struct b43_wldev *dev, 2764 const struct b43_iv *ivals, 2765 size_t count, 2766 size_t array_size) 2767 { 2768 const struct b43_iv *iv; 2769 u16 offset; 2770 size_t i; 2771 bool bit32; 2772 2773 BUILD_BUG_ON(sizeof(struct b43_iv) != 6); 2774 iv = ivals; 2775 for (i = 0; i < count; i++) { 2776 if (array_size < sizeof(iv->offset_size)) 2777 goto err_format; 2778 array_size -= sizeof(iv->offset_size); 2779 offset = be16_to_cpu(iv->offset_size); 2780 bit32 = !!(offset & B43_IV_32BIT); 2781 offset &= B43_IV_OFFSET_MASK; 2782 if (offset >= 0x1000) 2783 goto err_format; 2784 if (bit32) { 2785 u32 value; 2786 2787 if (array_size < sizeof(iv->data.d32)) 2788 goto err_format; 2789 array_size -= sizeof(iv->data.d32); 2790 2791 value = get_unaligned_be32(&iv->data.d32); 2792 b43_write32(dev, offset, value); 2793 2794 iv = (const struct b43_iv *)((const uint8_t *)iv + 2795 sizeof(__be16) + 2796 sizeof(__be32)); 2797 } else { 2798 u16 value; 2799 2800 if (array_size < sizeof(iv->data.d16)) 2801 goto err_format; 2802 array_size -= sizeof(iv->data.d16); 2803 2804 value = be16_to_cpu(iv->data.d16); 2805 b43_write16(dev, offset, value); 2806 2807 iv = (const struct b43_iv *)((const uint8_t *)iv + 2808 sizeof(__be16) + 2809 sizeof(__be16)); 2810 } 2811 } 2812 if (array_size) 2813 goto err_format; 2814 2815 return 0; 2816 2817 err_format: 2818 b43err(dev->wl, "Initial Values Firmware file-format error.\n"); 2819 b43_print_fw_helptext(dev->wl, 1); 2820 2821 return -EPROTO; 2822 } 2823 2824 static int b43_upload_initvals(struct b43_wldev *dev) 2825 { 2826 const size_t hdr_len = sizeof(struct b43_fw_header); 2827 const struct b43_fw_header *hdr; 2828 struct b43_firmware *fw = &dev->fw; 2829 const struct b43_iv *ivals; 2830 size_t count; 2831 2832 hdr = (const struct b43_fw_header *)(fw->initvals.data->data); 2833 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); 2834 count = be32_to_cpu(hdr->size); 2835 return b43_write_initvals(dev, ivals, count, 2836 fw->initvals.data->size - hdr_len); 2837 } 2838 2839 static int b43_upload_initvals_band(struct b43_wldev *dev) 2840 { 2841 const size_t hdr_len = sizeof(struct b43_fw_header); 2842 const struct b43_fw_header *hdr; 2843 struct b43_firmware *fw = &dev->fw; 2844 const struct b43_iv *ivals; 2845 size_t count; 2846 2847 if (!fw->initvals_band.data) 2848 return 0; 2849 2850 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); 2851 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); 2852 count = be32_to_cpu(hdr->size); 2853 return b43_write_initvals(dev, ivals, count, 2854 fw->initvals_band.data->size - hdr_len); 2855 } 2856 2857 /* Initialize the GPIOs 2858 * https://bcm-specs.sipsolutions.net/GPIO 2859 */ 2860 2861 #ifdef CONFIG_B43_SSB 2862 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev) 2863 { 2864 struct ssb_bus *bus = dev->dev->sdev->bus; 2865 2866 #ifdef CONFIG_SSB_DRIVER_PCICORE 2867 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev); 2868 #else 2869 return bus->chipco.dev; 2870 #endif 2871 } 2872 #endif 2873 2874 static int b43_gpio_init(struct b43_wldev *dev) 2875 { 2876 #ifdef CONFIG_B43_SSB 2877 struct ssb_device *gpiodev; 2878 #endif 2879 u32 mask, set; 2880 2881 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); 2882 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF); 2883 2884 mask = 0x0000001F; 2885 set = 0x0000000F; 2886 if (dev->dev->chip_id == 0x4301) { 2887 mask |= 0x0060; 2888 set |= 0x0060; 2889 } else if (dev->dev->chip_id == 0x5354) { 2890 /* Don't allow overtaking buttons GPIOs */ 2891 set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */ 2892 } 2893 2894 if (0 /* FIXME: conditional unknown */ ) { 2895 b43_write16(dev, B43_MMIO_GPIO_MASK, 2896 b43_read16(dev, B43_MMIO_GPIO_MASK) 2897 | 0x0100); 2898 /* BT Coexistance Input */ 2899 mask |= 0x0080; 2900 set |= 0x0080; 2901 /* BT Coexistance Out */ 2902 mask |= 0x0100; 2903 set |= 0x0100; 2904 } 2905 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) { 2906 /* PA is controlled by gpio 9, let ucode handle it */ 2907 b43_write16(dev, B43_MMIO_GPIO_MASK, 2908 b43_read16(dev, B43_MMIO_GPIO_MASK) 2909 | 0x0200); 2910 mask |= 0x0200; 2911 set |= 0x0200; 2912 } 2913 2914 switch (dev->dev->bus_type) { 2915 #ifdef CONFIG_B43_BCMA 2916 case B43_BUS_BCMA: 2917 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set); 2918 break; 2919 #endif 2920 #ifdef CONFIG_B43_SSB 2921 case B43_BUS_SSB: 2922 gpiodev = b43_ssb_gpio_dev(dev); 2923 if (gpiodev) 2924 ssb_write32(gpiodev, B43_GPIO_CONTROL, 2925 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2926 & ~mask) | set); 2927 break; 2928 #endif 2929 } 2930 2931 return 0; 2932 } 2933 2934 /* Turn off all GPIO stuff. Call this on module unload, for example. */ 2935 static void b43_gpio_cleanup(struct b43_wldev *dev) 2936 { 2937 #ifdef CONFIG_B43_SSB 2938 struct ssb_device *gpiodev; 2939 #endif 2940 2941 switch (dev->dev->bus_type) { 2942 #ifdef CONFIG_B43_BCMA 2943 case B43_BUS_BCMA: 2944 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0); 2945 break; 2946 #endif 2947 #ifdef CONFIG_B43_SSB 2948 case B43_BUS_SSB: 2949 gpiodev = b43_ssb_gpio_dev(dev); 2950 if (gpiodev) 2951 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2952 break; 2953 #endif 2954 } 2955 } 2956 2957 /* http://bcm-specs.sipsolutions.net/EnableMac */ 2958 void b43_mac_enable(struct b43_wldev *dev) 2959 { 2960 if (b43_debug(dev, B43_DBG_FIRMWARE)) { 2961 u16 fwstate; 2962 2963 fwstate = b43_shm_read16(dev, B43_SHM_SHARED, 2964 B43_SHM_SH_UCODESTAT); 2965 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) && 2966 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) { 2967 b43err(dev->wl, "b43_mac_enable(): The firmware " 2968 "should be suspended, but current state is %u\n", 2969 fwstate); 2970 } 2971 } 2972 2973 dev->mac_suspended--; 2974 B43_WARN_ON(dev->mac_suspended < 0); 2975 if (dev->mac_suspended == 0) { 2976 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED); 2977 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 2978 B43_IRQ_MAC_SUSPENDED); 2979 /* Commit writes */ 2980 b43_read32(dev, B43_MMIO_MACCTL); 2981 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 2982 b43_power_saving_ctl_bits(dev, 0); 2983 } 2984 } 2985 2986 /* https://bcm-specs.sipsolutions.net/SuspendMAC */ 2987 void b43_mac_suspend(struct b43_wldev *dev) 2988 { 2989 int i; 2990 u32 tmp; 2991 2992 might_sleep(); 2993 B43_WARN_ON(dev->mac_suspended < 0); 2994 2995 if (dev->mac_suspended == 0) { 2996 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 2997 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0); 2998 /* force pci to flush the write */ 2999 b43_read32(dev, B43_MMIO_MACCTL); 3000 for (i = 35; i; i--) { 3001 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 3002 if (tmp & B43_IRQ_MAC_SUSPENDED) 3003 goto out; 3004 udelay(10); 3005 } 3006 /* Hm, it seems this will take some time. Use msleep(). */ 3007 for (i = 40; i; i--) { 3008 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); 3009 if (tmp & B43_IRQ_MAC_SUSPENDED) 3010 goto out; 3011 msleep(1); 3012 } 3013 b43err(dev->wl, "MAC suspend failed\n"); 3014 } 3015 out: 3016 dev->mac_suspended++; 3017 } 3018 3019 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 3020 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on) 3021 { 3022 u32 tmp; 3023 3024 switch (dev->dev->bus_type) { 3025 #ifdef CONFIG_B43_BCMA 3026 case B43_BUS_BCMA: 3027 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 3028 if (on) 3029 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN; 3030 else 3031 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN; 3032 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); 3033 break; 3034 #endif 3035 #ifdef CONFIG_B43_SSB 3036 case B43_BUS_SSB: 3037 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 3038 if (on) 3039 tmp |= B43_TMSLOW_MACPHYCLKEN; 3040 else 3041 tmp &= ~B43_TMSLOW_MACPHYCLKEN; 3042 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 3043 break; 3044 #endif 3045 } 3046 } 3047 3048 /* brcms_b_switch_macfreq */ 3049 void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode) 3050 { 3051 u16 chip_id = dev->dev->chip_id; 3052 3053 if (chip_id == BCMA_CHIP_ID_BCM4331) { 3054 switch (spurmode) { 3055 case 2: /* 168 Mhz: 2^26/168 = 0x61862 */ 3056 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862); 3057 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); 3058 break; 3059 case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */ 3060 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70); 3061 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); 3062 break; 3063 default: /* 160 Mhz: 2^26/160 = 0x66666 */ 3064 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666); 3065 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); 3066 break; 3067 } 3068 } else if (chip_id == BCMA_CHIP_ID_BCM43131 || 3069 chip_id == BCMA_CHIP_ID_BCM43217 || 3070 chip_id == BCMA_CHIP_ID_BCM43222 || 3071 chip_id == BCMA_CHIP_ID_BCM43224 || 3072 chip_id == BCMA_CHIP_ID_BCM43225 || 3073 chip_id == BCMA_CHIP_ID_BCM43227 || 3074 chip_id == BCMA_CHIP_ID_BCM43228) { 3075 switch (spurmode) { 3076 case 2: /* 126 Mhz */ 3077 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082); 3078 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); 3079 break; 3080 case 1: /* 123 Mhz */ 3081 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341); 3082 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); 3083 break; 3084 default: /* 120 Mhz */ 3085 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889); 3086 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); 3087 break; 3088 } 3089 } else if (dev->phy.type == B43_PHYTYPE_LCN) { 3090 switch (spurmode) { 3091 case 1: /* 82 Mhz */ 3092 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0); 3093 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC); 3094 break; 3095 default: /* 80 Mhz */ 3096 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD); 3097 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC); 3098 break; 3099 } 3100 } 3101 } 3102 3103 static void b43_adjust_opmode(struct b43_wldev *dev) 3104 { 3105 struct b43_wl *wl = dev->wl; 3106 u32 ctl; 3107 u16 cfp_pretbtt; 3108 3109 ctl = b43_read32(dev, B43_MMIO_MACCTL); 3110 /* Reset status to STA infrastructure mode. */ 3111 ctl &= ~B43_MACCTL_AP; 3112 ctl &= ~B43_MACCTL_KEEP_CTL; 3113 ctl &= ~B43_MACCTL_KEEP_BADPLCP; 3114 ctl &= ~B43_MACCTL_KEEP_BAD; 3115 ctl &= ~B43_MACCTL_PROMISC; 3116 ctl &= ~B43_MACCTL_BEACPROMISC; 3117 ctl |= B43_MACCTL_INFRA; 3118 3119 if (b43_is_mode(wl, NL80211_IFTYPE_AP) || 3120 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) 3121 ctl |= B43_MACCTL_AP; 3122 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) 3123 ctl &= ~B43_MACCTL_INFRA; 3124 3125 if (wl->filter_flags & FIF_CONTROL) 3126 ctl |= B43_MACCTL_KEEP_CTL; 3127 if (wl->filter_flags & FIF_FCSFAIL) 3128 ctl |= B43_MACCTL_KEEP_BAD; 3129 if (wl->filter_flags & FIF_PLCPFAIL) 3130 ctl |= B43_MACCTL_KEEP_BADPLCP; 3131 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) 3132 ctl |= B43_MACCTL_BEACPROMISC; 3133 3134 /* Workaround: On old hardware the HW-MAC-address-filter 3135 * doesn't work properly, so always run promisc in filter 3136 * it in software. */ 3137 if (dev->dev->core_rev <= 4) 3138 ctl |= B43_MACCTL_PROMISC; 3139 3140 b43_write32(dev, B43_MMIO_MACCTL, ctl); 3141 3142 cfp_pretbtt = 2; 3143 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 3144 if (dev->dev->chip_id == 0x4306 && 3145 dev->dev->chip_rev == 3) 3146 cfp_pretbtt = 100; 3147 else 3148 cfp_pretbtt = 50; 3149 } 3150 b43_write16(dev, 0x612, cfp_pretbtt); 3151 3152 /* FIXME: We don't currently implement the PMQ mechanism, 3153 * so always disable it. If we want to implement PMQ, 3154 * we need to enable it here (clear DISCPMQ) in AP mode. 3155 */ 3156 if (0 /* ctl & B43_MACCTL_AP */) 3157 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0); 3158 else 3159 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ); 3160 } 3161 3162 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) 3163 { 3164 u16 offset; 3165 3166 if (is_ofdm) { 3167 offset = 0x480; 3168 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; 3169 } else { 3170 offset = 0x4C0; 3171 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; 3172 } 3173 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, 3174 b43_shm_read16(dev, B43_SHM_SHARED, offset)); 3175 } 3176 3177 static void b43_rate_memory_init(struct b43_wldev *dev) 3178 { 3179 switch (dev->phy.type) { 3180 case B43_PHYTYPE_G: 3181 case B43_PHYTYPE_N: 3182 case B43_PHYTYPE_LP: 3183 case B43_PHYTYPE_HT: 3184 case B43_PHYTYPE_LCN: 3185 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); 3186 b43_rate_memory_write(dev, B43_OFDM_RATE_9MB, 1); 3187 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); 3188 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); 3189 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); 3190 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); 3191 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); 3192 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); 3193 fallthrough; 3194 case B43_PHYTYPE_B: 3195 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); 3196 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); 3197 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); 3198 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); 3199 break; 3200 default: 3201 B43_WARN_ON(1); 3202 } 3203 } 3204 3205 /* Set the default values for the PHY TX Control Words. */ 3206 static void b43_set_phytxctl_defaults(struct b43_wldev *dev) 3207 { 3208 u16 ctl = 0; 3209 3210 ctl |= B43_TXH_PHY_ENC_CCK; 3211 ctl |= B43_TXH_PHY_ANT01AUTO; 3212 ctl |= B43_TXH_PHY_TXPWR; 3213 3214 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); 3215 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); 3216 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); 3217 } 3218 3219 /* Set the TX-Antenna for management frames sent by firmware. */ 3220 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) 3221 { 3222 u16 ant; 3223 u16 tmp; 3224 3225 ant = b43_antenna_to_phyctl(antenna); 3226 3227 /* For ACK/CTS */ 3228 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); 3229 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 3230 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); 3231 /* For Probe Resposes */ 3232 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); 3233 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; 3234 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); 3235 } 3236 3237 /* This is the opposite of b43_chip_init() */ 3238 static void b43_chip_exit(struct b43_wldev *dev) 3239 { 3240 b43_phy_exit(dev); 3241 b43_gpio_cleanup(dev); 3242 /* firmware is released later */ 3243 } 3244 3245 /* Initialize the chip 3246 * https://bcm-specs.sipsolutions.net/ChipInit 3247 */ 3248 static int b43_chip_init(struct b43_wldev *dev) 3249 { 3250 struct b43_phy *phy = &dev->phy; 3251 int err; 3252 u32 macctl; 3253 u16 value16; 3254 3255 /* Initialize the MAC control */ 3256 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; 3257 if (dev->phy.gmode) 3258 macctl |= B43_MACCTL_GMODE; 3259 macctl |= B43_MACCTL_INFRA; 3260 b43_write32(dev, B43_MMIO_MACCTL, macctl); 3261 3262 err = b43_upload_microcode(dev); 3263 if (err) 3264 goto out; /* firmware is released later */ 3265 3266 err = b43_gpio_init(dev); 3267 if (err) 3268 goto out; /* firmware is released later */ 3269 3270 err = b43_upload_initvals(dev); 3271 if (err) 3272 goto err_gpio_clean; 3273 3274 err = b43_upload_initvals_band(dev); 3275 if (err) 3276 goto err_gpio_clean; 3277 3278 /* Turn the Analog on and initialize the PHY. */ 3279 phy->ops->switch_analog(dev, 1); 3280 err = b43_phy_init(dev); 3281 if (err) 3282 goto err_gpio_clean; 3283 3284 /* Disable Interference Mitigation. */ 3285 if (phy->ops->interf_mitigation) 3286 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); 3287 3288 /* Select the antennae */ 3289 if (phy->ops->set_rx_antenna) 3290 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 3291 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 3292 3293 if (phy->type == B43_PHYTYPE_B) { 3294 value16 = b43_read16(dev, 0x005E); 3295 value16 |= 0x0004; 3296 b43_write16(dev, 0x005E, value16); 3297 } 3298 b43_write32(dev, 0x0100, 0x01000000); 3299 if (dev->dev->core_rev < 5) 3300 b43_write32(dev, 0x010C, 0x01000000); 3301 3302 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0); 3303 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA); 3304 3305 /* Probe Response Timeout value */ 3306 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 3307 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0); 3308 3309 /* Initially set the wireless operation mode. */ 3310 b43_adjust_opmode(dev); 3311 3312 if (dev->dev->core_rev < 3) { 3313 b43_write16(dev, 0x060E, 0x0000); 3314 b43_write16(dev, 0x0610, 0x8000); 3315 b43_write16(dev, 0x0604, 0x0000); 3316 b43_write16(dev, 0x0606, 0x0200); 3317 } else { 3318 b43_write32(dev, 0x0188, 0x80000000); 3319 b43_write32(dev, 0x018C, 0x02000000); 3320 } 3321 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); 3322 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00); 3323 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); 3324 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); 3325 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); 3326 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); 3327 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); 3328 3329 b43_mac_phy_clock_set(dev, true); 3330 3331 switch (dev->dev->bus_type) { 3332 #ifdef CONFIG_B43_BCMA 3333 case B43_BUS_BCMA: 3334 /* FIXME: 0xE74 is quite common, but should be read from CC */ 3335 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74); 3336 break; 3337 #endif 3338 #ifdef CONFIG_B43_SSB 3339 case B43_BUS_SSB: 3340 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 3341 dev->dev->sdev->bus->chipco.fast_pwrup_delay); 3342 break; 3343 #endif 3344 } 3345 3346 err = 0; 3347 b43dbg(dev->wl, "Chip initialized\n"); 3348 out: 3349 return err; 3350 3351 err_gpio_clean: 3352 b43_gpio_cleanup(dev); 3353 return err; 3354 } 3355 3356 static void b43_periodic_every60sec(struct b43_wldev *dev) 3357 { 3358 const struct b43_phy_operations *ops = dev->phy.ops; 3359 3360 if (ops->pwork_60sec) 3361 ops->pwork_60sec(dev); 3362 3363 /* Force check the TX power emission now. */ 3364 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME); 3365 } 3366 3367 static void b43_periodic_every30sec(struct b43_wldev *dev) 3368 { 3369 /* Update device statistics. */ 3370 b43_calculate_link_quality(dev); 3371 } 3372 3373 static void b43_periodic_every15sec(struct b43_wldev *dev) 3374 { 3375 struct b43_phy *phy = &dev->phy; 3376 u16 wdr; 3377 3378 if (dev->fw.opensource) { 3379 /* Check if the firmware is still alive. 3380 * It will reset the watchdog counter to 0 in its idle loop. */ 3381 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG); 3382 if (unlikely(wdr)) { 3383 b43err(dev->wl, "Firmware watchdog: The firmware died!\n"); 3384 b43_controller_restart(dev, "Firmware watchdog"); 3385 return; 3386 } else { 3387 b43_shm_write16(dev, B43_SHM_SCRATCH, 3388 B43_WATCHDOG_REG, 1); 3389 } 3390 } 3391 3392 if (phy->ops->pwork_15sec) 3393 phy->ops->pwork_15sec(dev); 3394 3395 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3396 wmb(); 3397 3398 #if B43_DEBUG 3399 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { 3400 unsigned int i; 3401 3402 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n", 3403 dev->irq_count / 15, 3404 dev->tx_count / 15, 3405 dev->rx_count / 15); 3406 dev->irq_count = 0; 3407 dev->tx_count = 0; 3408 dev->rx_count = 0; 3409 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { 3410 if (dev->irq_bit_count[i]) { 3411 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", 3412 dev->irq_bit_count[i] / 15, i, (1 << i)); 3413 dev->irq_bit_count[i] = 0; 3414 } 3415 } 3416 } 3417 #endif 3418 } 3419 3420 static void do_periodic_work(struct b43_wldev *dev) 3421 { 3422 unsigned int state; 3423 3424 state = dev->periodic_state; 3425 if (state % 4 == 0) 3426 b43_periodic_every60sec(dev); 3427 if (state % 2 == 0) 3428 b43_periodic_every30sec(dev); 3429 b43_periodic_every15sec(dev); 3430 } 3431 3432 /* Periodic work locking policy: 3433 * The whole periodic work handler is protected by 3434 * wl->mutex. If another lock is needed somewhere in the 3435 * pwork callchain, it's acquired in-place, where it's needed. 3436 */ 3437 static void b43_periodic_work_handler(struct work_struct *work) 3438 { 3439 struct b43_wldev *dev = container_of(work, struct b43_wldev, 3440 periodic_work.work); 3441 struct b43_wl *wl = dev->wl; 3442 unsigned long delay; 3443 3444 mutex_lock(&wl->mutex); 3445 3446 if (unlikely(b43_status(dev) != B43_STAT_STARTED)) 3447 goto out; 3448 if (b43_debug(dev, B43_DBG_PWORK_STOP)) 3449 goto out_requeue; 3450 3451 do_periodic_work(dev); 3452 3453 dev->periodic_state++; 3454 out_requeue: 3455 if (b43_debug(dev, B43_DBG_PWORK_FAST)) 3456 delay = msecs_to_jiffies(50); 3457 else 3458 delay = round_jiffies_relative(HZ * 15); 3459 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); 3460 out: 3461 mutex_unlock(&wl->mutex); 3462 } 3463 3464 static void b43_periodic_tasks_setup(struct b43_wldev *dev) 3465 { 3466 struct delayed_work *work = &dev->periodic_work; 3467 3468 dev->periodic_state = 0; 3469 INIT_DELAYED_WORK(work, b43_periodic_work_handler); 3470 ieee80211_queue_delayed_work(dev->wl->hw, work, 0); 3471 } 3472 3473 /* Check if communication with the device works correctly. */ 3474 static int b43_validate_chipaccess(struct b43_wldev *dev) 3475 { 3476 u32 v, backup0, backup4; 3477 3478 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); 3479 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4); 3480 3481 /* Check for read/write and endianness problems. */ 3482 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); 3483 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) 3484 goto error; 3485 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); 3486 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) 3487 goto error; 3488 3489 /* Check if unaligned 32bit SHM_SHARED access works properly. 3490 * However, don't bail out on failure, because it's noncritical. */ 3491 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); 3492 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); 3493 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); 3494 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); 3495 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) 3496 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n"); 3497 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); 3498 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || 3499 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || 3500 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || 3501 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) 3502 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n"); 3503 3504 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); 3505 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); 3506 3507 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) { 3508 /* The 32bit register shadows the two 16bit registers 3509 * with update sideeffects. Validate this. */ 3510 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 3511 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); 3512 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) 3513 goto error; 3514 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) 3515 goto error; 3516 } 3517 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); 3518 3519 v = b43_read32(dev, B43_MMIO_MACCTL); 3520 v |= B43_MACCTL_GMODE; 3521 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) 3522 goto error; 3523 3524 return 0; 3525 error: 3526 b43err(dev->wl, "Failed to validate the chipaccess\n"); 3527 return -ENODEV; 3528 } 3529 3530 static void b43_security_init(struct b43_wldev *dev) 3531 { 3532 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); 3533 /* KTP is a word address, but we address SHM bytewise. 3534 * So multiply by two. 3535 */ 3536 dev->ktp *= 2; 3537 /* Number of RCMTA address slots */ 3538 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS); 3539 /* Clear the key memory. */ 3540 b43_clear_keys(dev); 3541 } 3542 3543 #ifdef CONFIG_B43_HWRNG 3544 static int b43_rng_read(struct hwrng *rng, u32 *data) 3545 { 3546 struct b43_wl *wl = (struct b43_wl *)rng->priv; 3547 struct b43_wldev *dev; 3548 int count = -ENODEV; 3549 3550 mutex_lock(&wl->mutex); 3551 dev = wl->current_dev; 3552 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) { 3553 *data = b43_read16(dev, B43_MMIO_RNG); 3554 count = sizeof(u16); 3555 } 3556 mutex_unlock(&wl->mutex); 3557 3558 return count; 3559 } 3560 #endif /* CONFIG_B43_HWRNG */ 3561 3562 static void b43_rng_exit(struct b43_wl *wl) 3563 { 3564 #ifdef CONFIG_B43_HWRNG 3565 if (wl->rng_initialized) 3566 hwrng_unregister(&wl->rng); 3567 #endif /* CONFIG_B43_HWRNG */ 3568 } 3569 3570 static int b43_rng_init(struct b43_wl *wl) 3571 { 3572 int err = 0; 3573 3574 #ifdef CONFIG_B43_HWRNG 3575 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), 3576 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); 3577 wl->rng.name = wl->rng_name; 3578 wl->rng.data_read = b43_rng_read; 3579 wl->rng.priv = (unsigned long)wl; 3580 wl->rng_initialized = true; 3581 err = hwrng_register(&wl->rng); 3582 if (err) { 3583 wl->rng_initialized = false; 3584 b43err(wl, "Failed to register the random " 3585 "number generator (%d)\n", err); 3586 } 3587 #endif /* CONFIG_B43_HWRNG */ 3588 3589 return err; 3590 } 3591 3592 static void b43_tx_work(struct work_struct *work) 3593 { 3594 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work); 3595 struct b43_wldev *dev; 3596 struct sk_buff *skb; 3597 int queue_num; 3598 int err = 0; 3599 3600 mutex_lock(&wl->mutex); 3601 dev = wl->current_dev; 3602 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) { 3603 mutex_unlock(&wl->mutex); 3604 return; 3605 } 3606 3607 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { 3608 while (skb_queue_len(&wl->tx_queue[queue_num])) { 3609 skb = skb_dequeue(&wl->tx_queue[queue_num]); 3610 if (b43_using_pio_transfers(dev)) 3611 err = b43_pio_tx(dev, skb); 3612 else 3613 err = b43_dma_tx(dev, skb); 3614 if (err == -ENOSPC) { 3615 wl->tx_queue_stopped[queue_num] = true; 3616 b43_stop_queue(dev, queue_num); 3617 skb_queue_head(&wl->tx_queue[queue_num], skb); 3618 break; 3619 } 3620 if (unlikely(err)) 3621 ieee80211_free_txskb(wl->hw, skb); 3622 err = 0; 3623 } 3624 3625 if (!err) 3626 wl->tx_queue_stopped[queue_num] = false; 3627 } 3628 3629 #if B43_DEBUG 3630 dev->tx_count++; 3631 #endif 3632 mutex_unlock(&wl->mutex); 3633 } 3634 3635 static void b43_op_tx(struct ieee80211_hw *hw, 3636 struct ieee80211_tx_control *control, 3637 struct sk_buff *skb) 3638 { 3639 struct b43_wl *wl = hw_to_b43_wl(hw); 3640 u16 skb_queue_mapping; 3641 3642 if (unlikely(skb->len < 2 + 2 + 6)) { 3643 /* Too short, this can't be a valid frame. */ 3644 ieee80211_free_txskb(hw, skb); 3645 return; 3646 } 3647 B43_WARN_ON(skb_shinfo(skb)->nr_frags); 3648 3649 skb_queue_mapping = skb_get_queue_mapping(skb); 3650 skb_queue_tail(&wl->tx_queue[skb_queue_mapping], skb); 3651 if (!wl->tx_queue_stopped[skb_queue_mapping]) 3652 ieee80211_queue_work(wl->hw, &wl->tx_work); 3653 else 3654 b43_stop_queue(wl->current_dev, skb_queue_mapping); 3655 } 3656 3657 static void b43_qos_params_upload(struct b43_wldev *dev, 3658 const struct ieee80211_tx_queue_params *p, 3659 u16 shm_offset) 3660 { 3661 u16 params[B43_NR_QOSPARAMS]; 3662 int bslots, tmp; 3663 unsigned int i; 3664 3665 if (!dev->qos_enabled) 3666 return; 3667 3668 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min; 3669 3670 memset(¶ms, 0, sizeof(params)); 3671 3672 params[B43_QOSPARAM_TXOP] = p->txop * 32; 3673 params[B43_QOSPARAM_CWMIN] = p->cw_min; 3674 params[B43_QOSPARAM_CWMAX] = p->cw_max; 3675 params[B43_QOSPARAM_CWCUR] = p->cw_min; 3676 params[B43_QOSPARAM_AIFS] = p->aifs; 3677 params[B43_QOSPARAM_BSLOTS] = bslots; 3678 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs; 3679 3680 for (i = 0; i < ARRAY_SIZE(params); i++) { 3681 if (i == B43_QOSPARAM_STATUS) { 3682 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 3683 shm_offset + (i * 2)); 3684 /* Mark the parameters as updated. */ 3685 tmp |= 0x100; 3686 b43_shm_write16(dev, B43_SHM_SHARED, 3687 shm_offset + (i * 2), 3688 tmp); 3689 } else { 3690 b43_shm_write16(dev, B43_SHM_SHARED, 3691 shm_offset + (i * 2), 3692 params[i]); 3693 } 3694 } 3695 } 3696 3697 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */ 3698 static const u16 b43_qos_shm_offsets[] = { 3699 /* [mac80211-queue-nr] = SHM_OFFSET, */ 3700 [0] = B43_QOS_VOICE, 3701 [1] = B43_QOS_VIDEO, 3702 [2] = B43_QOS_BESTEFFORT, 3703 [3] = B43_QOS_BACKGROUND, 3704 }; 3705 3706 /* Update all QOS parameters in hardware. */ 3707 static void b43_qos_upload_all(struct b43_wldev *dev) 3708 { 3709 struct b43_wl *wl = dev->wl; 3710 struct b43_qos_params *params; 3711 unsigned int i; 3712 3713 if (!dev->qos_enabled) 3714 return; 3715 3716 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3717 ARRAY_SIZE(wl->qos_params)); 3718 3719 b43_mac_suspend(dev); 3720 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3721 params = &(wl->qos_params[i]); 3722 b43_qos_params_upload(dev, &(params->p), 3723 b43_qos_shm_offsets[i]); 3724 } 3725 b43_mac_enable(dev); 3726 } 3727 3728 static void b43_qos_clear(struct b43_wl *wl) 3729 { 3730 struct b43_qos_params *params; 3731 unsigned int i; 3732 3733 /* Initialize QoS parameters to sane defaults. */ 3734 3735 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3736 ARRAY_SIZE(wl->qos_params)); 3737 3738 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { 3739 params = &(wl->qos_params[i]); 3740 3741 switch (b43_qos_shm_offsets[i]) { 3742 case B43_QOS_VOICE: 3743 params->p.txop = 0; 3744 params->p.aifs = 2; 3745 params->p.cw_min = 0x0001; 3746 params->p.cw_max = 0x0001; 3747 break; 3748 case B43_QOS_VIDEO: 3749 params->p.txop = 0; 3750 params->p.aifs = 2; 3751 params->p.cw_min = 0x0001; 3752 params->p.cw_max = 0x0001; 3753 break; 3754 case B43_QOS_BESTEFFORT: 3755 params->p.txop = 0; 3756 params->p.aifs = 3; 3757 params->p.cw_min = 0x0001; 3758 params->p.cw_max = 0x03FF; 3759 break; 3760 case B43_QOS_BACKGROUND: 3761 params->p.txop = 0; 3762 params->p.aifs = 7; 3763 params->p.cw_min = 0x0001; 3764 params->p.cw_max = 0x03FF; 3765 break; 3766 default: 3767 B43_WARN_ON(1); 3768 } 3769 } 3770 } 3771 3772 /* Initialize the core's QOS capabilities */ 3773 static void b43_qos_init(struct b43_wldev *dev) 3774 { 3775 if (!dev->qos_enabled) { 3776 /* Disable QOS support. */ 3777 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF); 3778 b43_write16(dev, B43_MMIO_IFSCTL, 3779 b43_read16(dev, B43_MMIO_IFSCTL) 3780 & ~B43_MMIO_IFSCTL_USE_EDCF); 3781 b43dbg(dev->wl, "QoS disabled\n"); 3782 return; 3783 } 3784 3785 /* Upload the current QOS parameters. */ 3786 b43_qos_upload_all(dev); 3787 3788 /* Enable QOS support. */ 3789 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); 3790 b43_write16(dev, B43_MMIO_IFSCTL, 3791 b43_read16(dev, B43_MMIO_IFSCTL) 3792 | B43_MMIO_IFSCTL_USE_EDCF); 3793 b43dbg(dev->wl, "QoS enabled\n"); 3794 } 3795 3796 static int b43_op_conf_tx(struct ieee80211_hw *hw, 3797 struct ieee80211_vif *vif, 3798 unsigned int link_id, u16 _queue, 3799 const struct ieee80211_tx_queue_params *params) 3800 { 3801 struct b43_wl *wl = hw_to_b43_wl(hw); 3802 struct b43_wldev *dev; 3803 unsigned int queue = (unsigned int)_queue; 3804 int err = -ENODEV; 3805 3806 if (queue >= ARRAY_SIZE(wl->qos_params)) { 3807 /* Queue not available or don't support setting 3808 * params on this queue. Return success to not 3809 * confuse mac80211. */ 3810 return 0; 3811 } 3812 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != 3813 ARRAY_SIZE(wl->qos_params)); 3814 3815 mutex_lock(&wl->mutex); 3816 dev = wl->current_dev; 3817 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) 3818 goto out_unlock; 3819 3820 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params)); 3821 b43_mac_suspend(dev); 3822 b43_qos_params_upload(dev, &(wl->qos_params[queue].p), 3823 b43_qos_shm_offsets[queue]); 3824 b43_mac_enable(dev); 3825 err = 0; 3826 3827 out_unlock: 3828 mutex_unlock(&wl->mutex); 3829 3830 return err; 3831 } 3832 3833 static int b43_op_get_stats(struct ieee80211_hw *hw, 3834 struct ieee80211_low_level_stats *stats) 3835 { 3836 struct b43_wl *wl = hw_to_b43_wl(hw); 3837 3838 mutex_lock(&wl->mutex); 3839 memcpy(stats, &wl->ieee_stats, sizeof(*stats)); 3840 mutex_unlock(&wl->mutex); 3841 3842 return 0; 3843 } 3844 3845 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 3846 { 3847 struct b43_wl *wl = hw_to_b43_wl(hw); 3848 struct b43_wldev *dev; 3849 u64 tsf; 3850 3851 mutex_lock(&wl->mutex); 3852 dev = wl->current_dev; 3853 3854 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3855 b43_tsf_read(dev, &tsf); 3856 else 3857 tsf = 0; 3858 3859 mutex_unlock(&wl->mutex); 3860 3861 return tsf; 3862 } 3863 3864 static void b43_op_set_tsf(struct ieee80211_hw *hw, 3865 struct ieee80211_vif *vif, u64 tsf) 3866 { 3867 struct b43_wl *wl = hw_to_b43_wl(hw); 3868 struct b43_wldev *dev; 3869 3870 mutex_lock(&wl->mutex); 3871 dev = wl->current_dev; 3872 3873 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) 3874 b43_tsf_write(dev, tsf); 3875 3876 mutex_unlock(&wl->mutex); 3877 } 3878 3879 static const char *band_to_string(enum nl80211_band band) 3880 { 3881 switch (band) { 3882 case NL80211_BAND_5GHZ: 3883 return "5"; 3884 case NL80211_BAND_2GHZ: 3885 return "2.4"; 3886 default: 3887 break; 3888 } 3889 B43_WARN_ON(1); 3890 return ""; 3891 } 3892 3893 /* Expects wl->mutex locked */ 3894 static int b43_switch_band(struct b43_wldev *dev, 3895 struct ieee80211_channel *chan) 3896 { 3897 struct b43_phy *phy = &dev->phy; 3898 bool gmode; 3899 u32 tmp; 3900 3901 switch (chan->band) { 3902 case NL80211_BAND_5GHZ: 3903 gmode = false; 3904 break; 3905 case NL80211_BAND_2GHZ: 3906 gmode = true; 3907 break; 3908 default: 3909 B43_WARN_ON(1); 3910 return -EINVAL; 3911 } 3912 3913 if (!((gmode && phy->supports_2ghz) || 3914 (!gmode && phy->supports_5ghz))) { 3915 b43err(dev->wl, "This device doesn't support %s-GHz band\n", 3916 band_to_string(chan->band)); 3917 return -ENODEV; 3918 } 3919 3920 if (!!phy->gmode == !!gmode) { 3921 /* This device is already running. */ 3922 return 0; 3923 } 3924 3925 b43dbg(dev->wl, "Switching to %s GHz band\n", 3926 band_to_string(chan->band)); 3927 3928 /* Some new devices don't need disabling radio for band switching */ 3929 if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3)) 3930 b43_software_rfkill(dev, true); 3931 3932 phy->gmode = gmode; 3933 b43_phy_put_into_reset(dev); 3934 switch (dev->dev->bus_type) { 3935 #ifdef CONFIG_B43_BCMA 3936 case B43_BUS_BCMA: 3937 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); 3938 if (gmode) 3939 tmp |= B43_BCMA_IOCTL_GMODE; 3940 else 3941 tmp &= ~B43_BCMA_IOCTL_GMODE; 3942 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); 3943 break; 3944 #endif 3945 #ifdef CONFIG_B43_SSB 3946 case B43_BUS_SSB: 3947 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); 3948 if (gmode) 3949 tmp |= B43_TMSLOW_GMODE; 3950 else 3951 tmp &= ~B43_TMSLOW_GMODE; 3952 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); 3953 break; 3954 #endif 3955 } 3956 b43_phy_take_out_of_reset(dev); 3957 3958 b43_upload_initvals_band(dev); 3959 3960 b43_phy_init(dev); 3961 3962 return 0; 3963 } 3964 3965 static void b43_set_beacon_listen_interval(struct b43_wldev *dev, u16 interval) 3966 { 3967 interval = min_t(u16, interval, (u16)0xFF); 3968 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BCN_LI, interval); 3969 } 3970 3971 /* Write the short and long frame retry limit values. */ 3972 static void b43_set_retry_limits(struct b43_wldev *dev, 3973 unsigned int short_retry, 3974 unsigned int long_retry) 3975 { 3976 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing 3977 * the chip-internal counter. */ 3978 short_retry = min(short_retry, (unsigned int)0xF); 3979 long_retry = min(long_retry, (unsigned int)0xF); 3980 3981 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, 3982 short_retry); 3983 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, 3984 long_retry); 3985 } 3986 3987 static int b43_op_config(struct ieee80211_hw *hw, int radio_idx, u32 changed) 3988 { 3989 struct b43_wl *wl = hw_to_b43_wl(hw); 3990 struct b43_wldev *dev = wl->current_dev; 3991 struct b43_phy *phy = &dev->phy; 3992 struct ieee80211_conf *conf = &hw->conf; 3993 int antenna; 3994 int err = 0; 3995 3996 mutex_lock(&wl->mutex); 3997 b43_mac_suspend(dev); 3998 3999 if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) 4000 b43_set_beacon_listen_interval(dev, conf->listen_interval); 4001 4002 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 4003 phy->chandef = &conf->chandef; 4004 phy->channel = conf->chandef.chan->hw_value; 4005 4006 /* Switch the band (if necessary). */ 4007 err = b43_switch_band(dev, conf->chandef.chan); 4008 if (err) 4009 goto out_mac_enable; 4010 4011 /* Switch to the requested channel. 4012 * The firmware takes care of races with the TX handler. 4013 */ 4014 b43_switch_channel(dev, phy->channel); 4015 } 4016 4017 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 4018 b43_set_retry_limits(dev, conf->short_frame_max_tx_count, 4019 conf->long_frame_max_tx_count); 4020 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; 4021 if (!changed) 4022 goto out_mac_enable; 4023 4024 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 4025 4026 /* Adjust the desired TX power level. */ 4027 if (conf->power_level != 0) { 4028 if (conf->power_level != phy->desired_txpower) { 4029 phy->desired_txpower = conf->power_level; 4030 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME | 4031 B43_TXPWR_IGNORE_TSSI); 4032 } 4033 } 4034 4035 /* Antennas for RX and management frame TX. */ 4036 antenna = B43_ANTENNA_DEFAULT; 4037 b43_mgmtframe_txantenna(dev, antenna); 4038 antenna = B43_ANTENNA_DEFAULT; 4039 if (phy->ops->set_rx_antenna) 4040 phy->ops->set_rx_antenna(dev, antenna); 4041 4042 if (wl->radio_enabled != phy->radio_on) { 4043 if (wl->radio_enabled) { 4044 b43_software_rfkill(dev, false); 4045 b43info(dev->wl, "Radio turned on by software\n"); 4046 if (!dev->radio_hw_enable) { 4047 b43info(dev->wl, "The hardware RF-kill button " 4048 "still turns the radio physically off. " 4049 "Press the button to turn it on.\n"); 4050 } 4051 } else { 4052 b43_software_rfkill(dev, true); 4053 b43info(dev->wl, "Radio turned off by software\n"); 4054 } 4055 } 4056 4057 out_mac_enable: 4058 b43_mac_enable(dev); 4059 mutex_unlock(&wl->mutex); 4060 4061 return err; 4062 } 4063 4064 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates) 4065 { 4066 struct ieee80211_supported_band *sband = 4067 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)]; 4068 const struct ieee80211_rate *rate; 4069 int i; 4070 u16 basic, direct, offset, basic_offset, rateptr; 4071 4072 for (i = 0; i < sband->n_bitrates; i++) { 4073 rate = &sband->bitrates[i]; 4074 4075 if (b43_is_cck_rate(rate->hw_value)) { 4076 direct = B43_SHM_SH_CCKDIRECT; 4077 basic = B43_SHM_SH_CCKBASIC; 4078 offset = b43_plcp_get_ratecode_cck(rate->hw_value); 4079 offset &= 0xF; 4080 } else { 4081 direct = B43_SHM_SH_OFDMDIRECT; 4082 basic = B43_SHM_SH_OFDMBASIC; 4083 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 4084 offset &= 0xF; 4085 } 4086 4087 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); 4088 4089 if (b43_is_cck_rate(rate->hw_value)) { 4090 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value); 4091 basic_offset &= 0xF; 4092 } else { 4093 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); 4094 basic_offset &= 0xF; 4095 } 4096 4097 /* 4098 * Get the pointer that we need to point to 4099 * from the direct map 4100 */ 4101 rateptr = b43_shm_read16(dev, B43_SHM_SHARED, 4102 direct + 2 * basic_offset); 4103 /* and write it to the basic map */ 4104 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset, 4105 rateptr); 4106 } 4107 } 4108 4109 static void b43_op_bss_info_changed(struct ieee80211_hw *hw, 4110 struct ieee80211_vif *vif, 4111 struct ieee80211_bss_conf *conf, 4112 u64 changed) 4113 { 4114 struct b43_wl *wl = hw_to_b43_wl(hw); 4115 struct b43_wldev *dev; 4116 4117 mutex_lock(&wl->mutex); 4118 4119 dev = wl->current_dev; 4120 if (!dev || b43_status(dev) < B43_STAT_STARTED) 4121 goto out_unlock_mutex; 4122 4123 B43_WARN_ON(wl->vif != vif); 4124 4125 if (changed & BSS_CHANGED_BSSID) { 4126 if (conf->bssid) 4127 memcpy(wl->bssid, conf->bssid, ETH_ALEN); 4128 else 4129 eth_zero_addr(wl->bssid); 4130 } 4131 4132 if (b43_status(dev) >= B43_STAT_INITIALIZED) { 4133 if (changed & BSS_CHANGED_BEACON && 4134 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 4135 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 4136 b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) 4137 b43_update_templates(wl); 4138 4139 if (changed & BSS_CHANGED_BSSID) 4140 b43_write_mac_bssid_templates(dev); 4141 } 4142 4143 b43_mac_suspend(dev); 4144 4145 /* Update templates for AP/mesh mode. */ 4146 if (changed & BSS_CHANGED_BEACON_INT && 4147 (b43_is_mode(wl, NL80211_IFTYPE_AP) || 4148 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || 4149 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) && 4150 conf->beacon_int) 4151 b43_set_beacon_int(dev, conf->beacon_int); 4152 4153 if (changed & BSS_CHANGED_BASIC_RATES) 4154 b43_update_basic_rates(dev, conf->basic_rates); 4155 4156 if (changed & BSS_CHANGED_ERP_SLOT) { 4157 if (conf->use_short_slot) 4158 b43_short_slot_timing_enable(dev); 4159 else 4160 b43_short_slot_timing_disable(dev); 4161 } 4162 4163 b43_mac_enable(dev); 4164 out_unlock_mutex: 4165 mutex_unlock(&wl->mutex); 4166 } 4167 4168 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 4169 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 4170 struct ieee80211_key_conf *key) 4171 { 4172 struct b43_wl *wl = hw_to_b43_wl(hw); 4173 struct b43_wldev *dev; 4174 u8 algorithm; 4175 u8 index; 4176 int err; 4177 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 4178 4179 if (modparam_nohwcrypt) 4180 return -ENOSPC; /* User disabled HW-crypto */ 4181 4182 if ((vif->type == NL80211_IFTYPE_ADHOC || 4183 vif->type == NL80211_IFTYPE_MESH_POINT) && 4184 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 4185 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 4186 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 4187 /* 4188 * For now, disable hw crypto for the RSN IBSS group keys. This 4189 * could be optimized in the future, but until that gets 4190 * implemented, use of software crypto for group addressed 4191 * frames is a acceptable to allow RSN IBSS to be used. 4192 */ 4193 return -EOPNOTSUPP; 4194 } 4195 4196 mutex_lock(&wl->mutex); 4197 4198 dev = wl->current_dev; 4199 err = -ENODEV; 4200 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) 4201 goto out_unlock; 4202 4203 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) { 4204 /* We don't have firmware for the crypto engine. 4205 * Must use software-crypto. */ 4206 err = -EOPNOTSUPP; 4207 goto out_unlock; 4208 } 4209 4210 err = -EINVAL; 4211 switch (key->cipher) { 4212 case WLAN_CIPHER_SUITE_WEP40: 4213 algorithm = B43_SEC_ALGO_WEP40; 4214 break; 4215 case WLAN_CIPHER_SUITE_WEP104: 4216 algorithm = B43_SEC_ALGO_WEP104; 4217 break; 4218 case WLAN_CIPHER_SUITE_TKIP: 4219 algorithm = B43_SEC_ALGO_TKIP; 4220 break; 4221 case WLAN_CIPHER_SUITE_CCMP: 4222 algorithm = B43_SEC_ALGO_AES; 4223 break; 4224 default: 4225 B43_WARN_ON(1); 4226 goto out_unlock; 4227 } 4228 index = (u8) (key->keyidx); 4229 if (index > 3) 4230 goto out_unlock; 4231 4232 switch (cmd) { 4233 case SET_KEY: 4234 if (algorithm == B43_SEC_ALGO_TKIP && 4235 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) || 4236 !modparam_hwtkip)) { 4237 /* We support only pairwise key */ 4238 err = -EOPNOTSUPP; 4239 goto out_unlock; 4240 } 4241 4242 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { 4243 if (WARN_ON(!sta)) { 4244 err = -EOPNOTSUPP; 4245 goto out_unlock; 4246 } 4247 /* Pairwise key with an assigned MAC address. */ 4248 err = b43_key_write(dev, -1, algorithm, 4249 key->key, key->keylen, 4250 sta->addr, key); 4251 } else { 4252 /* Group key */ 4253 err = b43_key_write(dev, index, algorithm, 4254 key->key, key->keylen, NULL, key); 4255 } 4256 if (err) 4257 goto out_unlock; 4258 4259 if (algorithm == B43_SEC_ALGO_WEP40 || 4260 algorithm == B43_SEC_ALGO_WEP104) { 4261 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); 4262 } else { 4263 b43_hf_write(dev, 4264 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); 4265 } 4266 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 4267 if (algorithm == B43_SEC_ALGO_TKIP) 4268 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 4269 break; 4270 case DISABLE_KEY: { 4271 err = b43_key_clear(dev, key->hw_key_idx); 4272 if (err) 4273 goto out_unlock; 4274 break; 4275 } 4276 default: 4277 B43_WARN_ON(1); 4278 } 4279 4280 out_unlock: 4281 if (!err) { 4282 b43dbg(wl, "%s hardware based encryption for keyidx: %d, " 4283 "mac: %pM\n", 4284 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, 4285 sta ? sta->addr : bcast_addr); 4286 b43_dump_keymemory(dev); 4287 } 4288 mutex_unlock(&wl->mutex); 4289 4290 return err; 4291 } 4292 4293 static void b43_op_configure_filter(struct ieee80211_hw *hw, 4294 unsigned int changed, unsigned int *fflags, 4295 u64 multicast) 4296 { 4297 struct b43_wl *wl = hw_to_b43_wl(hw); 4298 struct b43_wldev *dev; 4299 4300 mutex_lock(&wl->mutex); 4301 dev = wl->current_dev; 4302 if (!dev) { 4303 *fflags = 0; 4304 goto out_unlock; 4305 } 4306 4307 *fflags &= FIF_ALLMULTI | 4308 FIF_FCSFAIL | 4309 FIF_PLCPFAIL | 4310 FIF_CONTROL | 4311 FIF_OTHER_BSS | 4312 FIF_BCN_PRBRESP_PROMISC; 4313 4314 changed &= FIF_ALLMULTI | 4315 FIF_FCSFAIL | 4316 FIF_PLCPFAIL | 4317 FIF_CONTROL | 4318 FIF_OTHER_BSS | 4319 FIF_BCN_PRBRESP_PROMISC; 4320 4321 wl->filter_flags = *fflags; 4322 4323 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) 4324 b43_adjust_opmode(dev); 4325 4326 out_unlock: 4327 mutex_unlock(&wl->mutex); 4328 } 4329 4330 /* Locking: wl->mutex 4331 * Returns the current dev. This might be different from the passed in dev, 4332 * because the core might be gone away while we unlocked the mutex. */ 4333 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev) 4334 { 4335 struct b43_wl *wl; 4336 struct b43_wldev *orig_dev; 4337 u32 mask; 4338 int queue_num; 4339 4340 if (!dev) 4341 return NULL; 4342 wl = dev->wl; 4343 redo: 4344 if (!dev || b43_status(dev) < B43_STAT_STARTED) 4345 return dev; 4346 4347 /* Cancel work. Unlock to avoid deadlocks. */ 4348 mutex_unlock(&wl->mutex); 4349 cancel_delayed_work_sync(&dev->periodic_work); 4350 cancel_work_sync(&wl->tx_work); 4351 b43_leds_stop(dev); 4352 mutex_lock(&wl->mutex); 4353 dev = wl->current_dev; 4354 if (!dev || b43_status(dev) < B43_STAT_STARTED) { 4355 /* Whoops, aliens ate up the device while we were unlocked. */ 4356 return dev; 4357 } 4358 4359 /* Disable interrupts on the device. */ 4360 b43_set_status(dev, B43_STAT_INITIALIZED); 4361 if (b43_bus_host_is_sdio(dev->dev)) { 4362 /* wl->mutex is locked. That is enough. */ 4363 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4364 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4365 } else { 4366 spin_lock_irq(&wl->hardirq_lock); 4367 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4368 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4369 spin_unlock_irq(&wl->hardirq_lock); 4370 } 4371 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ 4372 orig_dev = dev; 4373 mutex_unlock(&wl->mutex); 4374 if (b43_bus_host_is_sdio(dev->dev)) 4375 b43_sdio_free_irq(dev); 4376 else 4377 free_irq(dev->dev->irq, dev); 4378 mutex_lock(&wl->mutex); 4379 dev = wl->current_dev; 4380 if (!dev) 4381 return dev; 4382 if (dev != orig_dev) { 4383 if (b43_status(dev) >= B43_STAT_STARTED) 4384 goto redo; 4385 return dev; 4386 } 4387 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); 4388 B43_WARN_ON(mask != 0xFFFFFFFF && mask); 4389 4390 /* Drain all TX queues. */ 4391 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { 4392 while (skb_queue_len(&wl->tx_queue[queue_num])) { 4393 struct sk_buff *skb; 4394 4395 skb = skb_dequeue(&wl->tx_queue[queue_num]); 4396 ieee80211_free_txskb(wl->hw, skb); 4397 } 4398 } 4399 4400 b43_mac_suspend(dev); 4401 b43_leds_exit(dev); 4402 b43dbg(wl, "Wireless interface stopped\n"); 4403 4404 return dev; 4405 } 4406 4407 /* Locking: wl->mutex */ 4408 static int b43_wireless_core_start(struct b43_wldev *dev) 4409 { 4410 int err; 4411 4412 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 4413 4414 drain_txstatus_queue(dev); 4415 if (b43_bus_host_is_sdio(dev->dev)) { 4416 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); 4417 if (err) { 4418 b43err(dev->wl, "Cannot request SDIO IRQ\n"); 4419 goto out; 4420 } 4421 } else { 4422 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler, 4423 b43_interrupt_thread_handler, 4424 IRQF_SHARED, KBUILD_MODNAME, dev); 4425 if (err) { 4426 b43err(dev->wl, "Cannot request IRQ-%d\n", 4427 dev->dev->irq); 4428 goto out; 4429 } 4430 } 4431 4432 /* We are ready to run. */ 4433 ieee80211_wake_queues(dev->wl->hw); 4434 b43_set_status(dev, B43_STAT_STARTED); 4435 4436 /* Start data flow (TX/RX). */ 4437 b43_mac_enable(dev); 4438 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); 4439 4440 /* Start maintenance work */ 4441 b43_periodic_tasks_setup(dev); 4442 4443 b43_leds_init(dev); 4444 4445 b43dbg(dev->wl, "Wireless interface started\n"); 4446 out: 4447 return err; 4448 } 4449 4450 static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type) 4451 { 4452 switch (phy_type) { 4453 case B43_PHYTYPE_A: 4454 return "A"; 4455 case B43_PHYTYPE_B: 4456 return "B"; 4457 case B43_PHYTYPE_G: 4458 return "G"; 4459 case B43_PHYTYPE_N: 4460 return "N"; 4461 case B43_PHYTYPE_LP: 4462 return "LP"; 4463 case B43_PHYTYPE_SSLPN: 4464 return "SSLPN"; 4465 case B43_PHYTYPE_HT: 4466 return "HT"; 4467 case B43_PHYTYPE_LCN: 4468 return "LCN"; 4469 case B43_PHYTYPE_LCNXN: 4470 return "LCNXN"; 4471 case B43_PHYTYPE_LCN40: 4472 return "LCN40"; 4473 case B43_PHYTYPE_AC: 4474 return "AC"; 4475 } 4476 return "UNKNOWN"; 4477 } 4478 4479 /* Get PHY and RADIO versioning numbers */ 4480 static int b43_phy_versioning(struct b43_wldev *dev) 4481 { 4482 struct b43_phy *phy = &dev->phy; 4483 const u8 core_rev = dev->dev->core_rev; 4484 u32 tmp; 4485 u8 analog_type; 4486 u8 phy_type; 4487 u8 phy_rev; 4488 u16 radio_manuf; 4489 u16 radio_id; 4490 u16 radio_rev; 4491 u8 radio_ver; 4492 int unsupported = 0; 4493 4494 /* Get PHY versioning */ 4495 tmp = b43_read16(dev, B43_MMIO_PHY_VER); 4496 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; 4497 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; 4498 phy_rev = (tmp & B43_PHYVER_VERSION); 4499 4500 /* LCNXN is continuation of N which run out of revisions */ 4501 if (phy_type == B43_PHYTYPE_LCNXN) { 4502 phy_type = B43_PHYTYPE_N; 4503 phy_rev += 16; 4504 } 4505 4506 switch (phy_type) { 4507 #ifdef CONFIG_B43_PHY_G 4508 case B43_PHYTYPE_G: 4509 if (phy_rev > 9) 4510 unsupported = 1; 4511 break; 4512 #endif 4513 #ifdef CONFIG_B43_PHY_N 4514 case B43_PHYTYPE_N: 4515 if (phy_rev >= 19) 4516 unsupported = 1; 4517 break; 4518 #endif 4519 #ifdef CONFIG_B43_PHY_LP 4520 case B43_PHYTYPE_LP: 4521 if (phy_rev > 2) 4522 unsupported = 1; 4523 break; 4524 #endif 4525 #ifdef CONFIG_B43_PHY_HT 4526 case B43_PHYTYPE_HT: 4527 if (phy_rev > 1) 4528 unsupported = 1; 4529 break; 4530 #endif 4531 #ifdef CONFIG_B43_PHY_LCN 4532 case B43_PHYTYPE_LCN: 4533 if (phy_rev > 1) 4534 unsupported = 1; 4535 break; 4536 #endif 4537 #ifdef CONFIG_B43_PHY_AC 4538 case B43_PHYTYPE_AC: 4539 if (phy_rev > 1) 4540 unsupported = 1; 4541 break; 4542 #endif 4543 default: 4544 unsupported = 1; 4545 } 4546 if (unsupported) { 4547 b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n", 4548 analog_type, phy_type, b43_phy_name(dev, phy_type), 4549 phy_rev); 4550 return -EOPNOTSUPP; 4551 } 4552 b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n", 4553 analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev); 4554 4555 /* Get RADIO versioning */ 4556 if (core_rev == 40 || core_rev == 42) { 4557 radio_manuf = 0x17F; 4558 4559 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0); 4560 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4561 4562 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1); 4563 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4564 4565 radio_ver = 0; /* Is there version somewhere? */ 4566 } else if (core_rev >= 24 || core_rev == 22) { 4567 /* 4568 * D11 corerev 22 pairs an older 802.11 core with a 2057 4569 * radio that requires the 24-bit indirect access path. 4570 */ 4571 u16 radio24[3]; 4572 4573 for (tmp = 0; tmp < 3; tmp++) { 4574 b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp); 4575 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4576 } 4577 4578 radio_manuf = 0x17F; 4579 radio_id = (radio24[2] << 8) | radio24[1]; 4580 radio_rev = (radio24[0] & 0xF); 4581 radio_ver = (radio24[0] & 0xF0) >> 4; 4582 } else { 4583 if (dev->dev->chip_id == 0x4317) { 4584 if (dev->dev->chip_rev == 0) 4585 tmp = 0x3205017F; 4586 else if (dev->dev->chip_rev == 1) 4587 tmp = 0x4205017F; 4588 else 4589 tmp = 0x5205017F; 4590 } else { 4591 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, 4592 B43_RADIOCTL_ID); 4593 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 4594 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, 4595 B43_RADIOCTL_ID); 4596 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; 4597 } 4598 radio_manuf = (tmp & 0x00000FFF); 4599 radio_id = (tmp & 0x0FFFF000) >> 12; 4600 radio_rev = (tmp & 0xF0000000) >> 28; 4601 radio_ver = 0; /* Probably not available on old hw */ 4602 } 4603 4604 if (radio_manuf != 0x17F /* Broadcom */) 4605 unsupported = 1; 4606 switch (phy_type) { 4607 case B43_PHYTYPE_B: 4608 if ((radio_id & 0xFFF0) != 0x2050) 4609 unsupported = 1; 4610 break; 4611 case B43_PHYTYPE_G: 4612 if (radio_id != 0x2050) 4613 unsupported = 1; 4614 break; 4615 case B43_PHYTYPE_N: 4616 if (radio_id != 0x2055 && radio_id != 0x2056 && 4617 radio_id != 0x2057) 4618 unsupported = 1; 4619 if (radio_id == 0x2057 && 4620 !(radio_rev == 8 || radio_rev == 9 || 4621 radio_rev == 14)) 4622 unsupported = 1; 4623 break; 4624 case B43_PHYTYPE_LP: 4625 if (radio_id != 0x2062 && radio_id != 0x2063) 4626 unsupported = 1; 4627 break; 4628 case B43_PHYTYPE_HT: 4629 if (radio_id != 0x2059) 4630 unsupported = 1; 4631 break; 4632 case B43_PHYTYPE_LCN: 4633 if (radio_id != 0x2064) 4634 unsupported = 1; 4635 break; 4636 case B43_PHYTYPE_AC: 4637 if (radio_id != 0x2069) 4638 unsupported = 1; 4639 break; 4640 default: 4641 B43_WARN_ON(1); 4642 } 4643 if (unsupported) { 4644 b43err(dev->wl, 4645 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n", 4646 radio_manuf, radio_id, radio_rev, radio_ver); 4647 return -EOPNOTSUPP; 4648 } 4649 b43info(dev->wl, 4650 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n", 4651 radio_manuf, radio_id, radio_rev, radio_ver); 4652 4653 /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */ 4654 phy->radio_manuf = radio_manuf; 4655 phy->radio_ver = radio_id; 4656 phy->radio_rev = radio_rev; 4657 4658 phy->analog = analog_type; 4659 phy->type = phy_type; 4660 phy->rev = phy_rev; 4661 4662 return 0; 4663 } 4664 4665 static void setup_struct_phy_for_init(struct b43_wldev *dev, 4666 struct b43_phy *phy) 4667 { 4668 phy->hardware_power_control = !!modparam_hwpctl; 4669 phy->next_txpwr_check_time = jiffies; 4670 /* PHY TX errors counter. */ 4671 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 4672 4673 #if B43_DEBUG 4674 phy->phy_locked = false; 4675 phy->radio_locked = false; 4676 #endif 4677 } 4678 4679 static void setup_struct_wldev_for_init(struct b43_wldev *dev) 4680 { 4681 dev->dfq_valid = false; 4682 4683 /* Assume the radio is enabled. If it's not enabled, the state will 4684 * immediately get fixed on the first periodic work run. */ 4685 dev->radio_hw_enable = true; 4686 4687 /* Stats */ 4688 memset(&dev->stats, 0, sizeof(dev->stats)); 4689 4690 setup_struct_phy_for_init(dev, &dev->phy); 4691 4692 /* IRQ related flags */ 4693 dev->irq_reason = 0; 4694 memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); 4695 dev->irq_mask = B43_IRQ_MASKTEMPLATE; 4696 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) 4697 dev->irq_mask &= ~B43_IRQ_PHY_TXERR; 4698 4699 dev->mac_suspended = 1; 4700 4701 /* Noise calculation context */ 4702 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); 4703 } 4704 4705 static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 4706 { 4707 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4708 u64 hf; 4709 4710 if (!modparam_btcoex) 4711 return; 4712 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) 4713 return; 4714 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) 4715 return; 4716 4717 hf = b43_hf_read(dev); 4718 if (sprom->boardflags_lo & B43_BFL_BTCMOD) 4719 hf |= B43_HF_BTCOEXALT; 4720 else 4721 hf |= B43_HF_BTCOEX; 4722 b43_hf_write(dev, hf); 4723 } 4724 4725 static void b43_bluetooth_coext_disable(struct b43_wldev *dev) 4726 { 4727 if (!modparam_btcoex) 4728 return; 4729 //TODO 4730 } 4731 4732 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 4733 { 4734 struct ssb_bus *bus; 4735 u32 tmp; 4736 4737 #ifdef CONFIG_B43_SSB 4738 if (dev->dev->bus_type != B43_BUS_SSB) 4739 return; 4740 #else 4741 return; 4742 #endif 4743 4744 bus = dev->dev->sdev->bus; 4745 4746 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || 4747 (bus->chip_id == 0x4312)) { 4748 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO); 4749 tmp &= ~SSB_IMCFGLO_REQTO; 4750 tmp &= ~SSB_IMCFGLO_SERTO; 4751 tmp |= 0x3; 4752 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp); 4753 ssb_commit_settings(bus); 4754 } 4755 } 4756 4757 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) 4758 { 4759 u16 pu_delay; 4760 4761 /* The time value is in microseconds. */ 4762 pu_delay = 1050; 4763 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) 4764 pu_delay = 500; 4765 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) 4766 pu_delay = max(pu_delay, (u16)2400); 4767 4768 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); 4769 } 4770 4771 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ 4772 static void b43_set_pretbtt(struct b43_wldev *dev) 4773 { 4774 u16 pretbtt; 4775 4776 /* The time value is in microseconds. */ 4777 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) 4778 pretbtt = 2; 4779 else 4780 pretbtt = 250; 4781 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); 4782 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); 4783 } 4784 4785 /* Shutdown a wireless core */ 4786 /* Locking: wl->mutex */ 4787 static void b43_wireless_core_exit(struct b43_wldev *dev) 4788 { 4789 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED); 4790 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED) 4791 return; 4792 4793 b43_set_status(dev, B43_STAT_UNINIT); 4794 4795 /* Stop the microcode PSM. */ 4796 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN, 4797 B43_MACCTL_PSM_JMP0); 4798 4799 switch (dev->dev->bus_type) { 4800 #ifdef CONFIG_B43_BCMA 4801 case B43_BUS_BCMA: 4802 bcma_host_pci_down(dev->dev->bdev->bus); 4803 break; 4804 #endif 4805 #ifdef CONFIG_B43_SSB 4806 case B43_BUS_SSB: 4807 /* TODO */ 4808 break; 4809 #endif 4810 } 4811 4812 b43_dma_free(dev); 4813 b43_pio_free(dev); 4814 b43_chip_exit(dev); 4815 dev->phy.ops->switch_analog(dev, 0); 4816 if (dev->wl->current_beacon) { 4817 dev_kfree_skb_any(dev->wl->current_beacon); 4818 dev->wl->current_beacon = NULL; 4819 } 4820 4821 b43_device_disable(dev, 0); 4822 b43_bus_may_powerdown(dev); 4823 } 4824 4825 /* Initialize a wireless core */ 4826 static int b43_wireless_core_init(struct b43_wldev *dev) 4827 { 4828 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4829 struct b43_phy *phy = &dev->phy; 4830 int err; 4831 u64 hf; 4832 4833 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4834 4835 err = b43_bus_powerup(dev, 0); 4836 if (err) 4837 goto out; 4838 if (!b43_device_is_enabled(dev)) 4839 b43_wireless_core_reset(dev, phy->gmode); 4840 4841 /* Reset all data structures. */ 4842 setup_struct_wldev_for_init(dev); 4843 phy->ops->prepare_structs(dev); 4844 4845 /* Enable IRQ routing to this device. */ 4846 switch (dev->dev->bus_type) { 4847 #ifdef CONFIG_B43_BCMA 4848 case B43_BUS_BCMA: 4849 bcma_host_pci_irq_ctl(dev->dev->bdev->bus, 4850 dev->dev->bdev, true); 4851 bcma_host_pci_up(dev->dev->bdev->bus); 4852 break; 4853 #endif 4854 #ifdef CONFIG_B43_SSB 4855 case B43_BUS_SSB: 4856 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore, 4857 dev->dev->sdev); 4858 break; 4859 #endif 4860 } 4861 4862 b43_imcfglo_timeouts_workaround(dev); 4863 b43_bluetooth_coext_disable(dev); 4864 if (phy->ops->prepare_hardware) { 4865 err = phy->ops->prepare_hardware(dev); 4866 if (err) 4867 goto err_busdown; 4868 } 4869 err = b43_chip_init(dev); 4870 if (err) 4871 goto err_busdown; 4872 b43_shm_write16(dev, B43_SHM_SHARED, 4873 B43_SHM_SH_WLCOREREV, dev->dev->core_rev); 4874 hf = b43_hf_read(dev); 4875 if (phy->type == B43_PHYTYPE_G) { 4876 hf |= B43_HF_SYMW; 4877 if (phy->rev == 1) 4878 hf |= B43_HF_GDCW; 4879 if (sprom->boardflags_lo & B43_BFL_PACTRL) 4880 hf |= B43_HF_OFDMPABOOST; 4881 } 4882 if (phy->radio_ver == 0x2050) { 4883 if (phy->radio_rev == 6) 4884 hf |= B43_HF_4318TSSI; 4885 if (phy->radio_rev < 6) 4886 hf |= B43_HF_VCORECALC; 4887 } 4888 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) 4889 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ 4890 #if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE) 4891 if (dev->dev->bus_type == B43_BUS_SSB && 4892 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI && 4893 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10) 4894 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ 4895 #endif 4896 hf &= ~B43_HF_SKCFPUP; 4897 b43_hf_write(dev, hf); 4898 4899 /* tell the ucode MAC capabilities */ 4900 if (dev->dev->core_rev >= 13) { 4901 u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP); 4902 4903 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_L, 4904 mac_hw_cap & 0xffff); 4905 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_H, 4906 (mac_hw_cap >> 16) & 0xffff); 4907 } 4908 4909 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, 4910 B43_DEFAULT_LONG_RETRY_LIMIT); 4911 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); 4912 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); 4913 4914 /* Disable sending probe responses from firmware. 4915 * Setting the MaxTime to one usec will always trigger 4916 * a timeout, so we never send any probe resp. 4917 * A timeout of zero is infinite. */ 4918 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); 4919 4920 b43_rate_memory_init(dev); 4921 b43_set_phytxctl_defaults(dev); 4922 4923 /* Minimum Contention Window */ 4924 if (phy->type == B43_PHYTYPE_B) 4925 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); 4926 else 4927 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); 4928 /* Maximum Contention Window */ 4929 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 4930 4931 /* write phytype and phyvers */ 4932 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYTYPE, phy->type); 4933 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYVER, phy->rev); 4934 4935 if (b43_bus_host_is_pcmcia(dev->dev) || 4936 b43_bus_host_is_sdio(dev->dev)) { 4937 dev->__using_pio_transfers = true; 4938 err = b43_pio_init(dev); 4939 } else if (dev->use_pio) { 4940 b43warn(dev->wl, "Forced PIO by use_pio module parameter. " 4941 "This should not be needed and will result in lower " 4942 "performance.\n"); 4943 dev->__using_pio_transfers = true; 4944 err = b43_pio_init(dev); 4945 } else { 4946 dev->__using_pio_transfers = false; 4947 err = b43_dma_init(dev); 4948 } 4949 if (err) 4950 goto err_chip_exit; 4951 b43_qos_init(dev); 4952 b43_set_synth_pu_delay(dev, 1); 4953 b43_bluetooth_coext_enable(dev); 4954 4955 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); 4956 b43_upload_card_macaddress(dev); 4957 b43_security_init(dev); 4958 4959 ieee80211_wake_queues(dev->wl->hw); 4960 4961 b43_set_status(dev, B43_STAT_INITIALIZED); 4962 4963 out: 4964 return err; 4965 4966 err_chip_exit: 4967 b43_chip_exit(dev); 4968 err_busdown: 4969 b43_bus_may_powerdown(dev); 4970 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4971 return err; 4972 } 4973 4974 static int b43_op_add_interface(struct ieee80211_hw *hw, 4975 struct ieee80211_vif *vif) 4976 { 4977 struct b43_wl *wl = hw_to_b43_wl(hw); 4978 struct b43_wldev *dev; 4979 int err = -EOPNOTSUPP; 4980 4981 /* TODO: allow AP devices to coexist */ 4982 4983 if (vif->type != NL80211_IFTYPE_AP && 4984 vif->type != NL80211_IFTYPE_MESH_POINT && 4985 vif->type != NL80211_IFTYPE_STATION && 4986 vif->type != NL80211_IFTYPE_ADHOC) 4987 return -EOPNOTSUPP; 4988 4989 mutex_lock(&wl->mutex); 4990 if (wl->operating) 4991 goto out_mutex_unlock; 4992 4993 b43dbg(wl, "Adding Interface type %d\n", vif->type); 4994 4995 dev = wl->current_dev; 4996 wl->operating = true; 4997 wl->vif = vif; 4998 wl->if_type = vif->type; 4999 memcpy(wl->mac_addr, vif->addr, ETH_ALEN); 5000 5001 b43_adjust_opmode(dev); 5002 b43_set_pretbtt(dev); 5003 b43_set_synth_pu_delay(dev, 0); 5004 b43_upload_card_macaddress(dev); 5005 5006 err = 0; 5007 out_mutex_unlock: 5008 mutex_unlock(&wl->mutex); 5009 5010 if (err == 0) 5011 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0); 5012 5013 return err; 5014 } 5015 5016 static void b43_op_remove_interface(struct ieee80211_hw *hw, 5017 struct ieee80211_vif *vif) 5018 { 5019 struct b43_wl *wl = hw_to_b43_wl(hw); 5020 struct b43_wldev *dev = wl->current_dev; 5021 5022 b43dbg(wl, "Removing Interface type %d\n", vif->type); 5023 5024 mutex_lock(&wl->mutex); 5025 5026 B43_WARN_ON(!wl->operating); 5027 B43_WARN_ON(wl->vif != vif); 5028 wl->vif = NULL; 5029 5030 wl->operating = false; 5031 5032 b43_adjust_opmode(dev); 5033 eth_zero_addr(wl->mac_addr); 5034 b43_upload_card_macaddress(dev); 5035 5036 mutex_unlock(&wl->mutex); 5037 } 5038 5039 static int b43_op_start(struct ieee80211_hw *hw) 5040 { 5041 struct b43_wl *wl = hw_to_b43_wl(hw); 5042 struct b43_wldev *dev = wl->current_dev; 5043 int did_init = 0; 5044 int err = 0; 5045 5046 /* Kill all old instance specific information to make sure 5047 * the card won't use it in the short timeframe between start 5048 * and mac80211 reconfiguring it. */ 5049 eth_zero_addr(wl->bssid); 5050 eth_zero_addr(wl->mac_addr); 5051 wl->filter_flags = 0; 5052 wl->radiotap_enabled = false; 5053 b43_qos_clear(wl); 5054 wl->beacon0_uploaded = false; 5055 wl->beacon1_uploaded = false; 5056 wl->beacon_templates_virgin = true; 5057 wl->radio_enabled = true; 5058 5059 mutex_lock(&wl->mutex); 5060 5061 if (b43_status(dev) < B43_STAT_INITIALIZED) { 5062 err = b43_wireless_core_init(dev); 5063 if (err) 5064 goto out_mutex_unlock; 5065 did_init = 1; 5066 } 5067 5068 if (b43_status(dev) < B43_STAT_STARTED) { 5069 err = b43_wireless_core_start(dev); 5070 if (err) { 5071 if (did_init) 5072 b43_wireless_core_exit(dev); 5073 goto out_mutex_unlock; 5074 } 5075 } 5076 5077 /* XXX: only do if device doesn't support rfkill irq */ 5078 wiphy_rfkill_start_polling(hw->wiphy); 5079 5080 out_mutex_unlock: 5081 mutex_unlock(&wl->mutex); 5082 5083 /* 5084 * Configuration may have been overwritten during initialization. 5085 * Reload the configuration, but only if initialization was 5086 * successful. Reloading the configuration after a failed init 5087 * may hang the system. 5088 */ 5089 if (!err) 5090 b43_op_config(hw, -1, ~0); 5091 5092 return err; 5093 } 5094 5095 static void b43_op_stop(struct ieee80211_hw *hw, bool suspend) 5096 { 5097 struct b43_wl *wl = hw_to_b43_wl(hw); 5098 struct b43_wldev *dev = wl->current_dev; 5099 5100 cancel_work_sync(&(wl->beacon_update_trigger)); 5101 5102 if (!dev) 5103 goto out; 5104 5105 mutex_lock(&wl->mutex); 5106 if (b43_status(dev) >= B43_STAT_STARTED) { 5107 dev = b43_wireless_core_stop(dev); 5108 if (!dev) 5109 goto out_unlock; 5110 } 5111 b43_wireless_core_exit(dev); 5112 wl->radio_enabled = false; 5113 5114 out_unlock: 5115 mutex_unlock(&wl->mutex); 5116 out: 5117 cancel_work_sync(&(wl->txpower_adjust_work)); 5118 } 5119 5120 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, 5121 struct ieee80211_sta *sta, bool set) 5122 { 5123 struct b43_wl *wl = hw_to_b43_wl(hw); 5124 5125 b43_update_templates(wl); 5126 5127 return 0; 5128 } 5129 5130 static void b43_op_sta_notify(struct ieee80211_hw *hw, 5131 struct ieee80211_vif *vif, 5132 enum sta_notify_cmd notify_cmd, 5133 struct ieee80211_sta *sta) 5134 { 5135 struct b43_wl *wl = hw_to_b43_wl(hw); 5136 5137 B43_WARN_ON(!vif || wl->vif != vif); 5138 } 5139 5140 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw, 5141 struct ieee80211_vif *vif, 5142 const u8 *mac_addr) 5143 { 5144 struct b43_wl *wl = hw_to_b43_wl(hw); 5145 struct b43_wldev *dev; 5146 5147 mutex_lock(&wl->mutex); 5148 dev = wl->current_dev; 5149 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 5150 /* Disable CFP update during scan on other channels. */ 5151 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP); 5152 } 5153 mutex_unlock(&wl->mutex); 5154 } 5155 5156 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw, 5157 struct ieee80211_vif *vif) 5158 { 5159 struct b43_wl *wl = hw_to_b43_wl(hw); 5160 struct b43_wldev *dev; 5161 5162 mutex_lock(&wl->mutex); 5163 dev = wl->current_dev; 5164 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { 5165 /* Re-enable CFP update. */ 5166 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP); 5167 } 5168 mutex_unlock(&wl->mutex); 5169 } 5170 5171 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx, 5172 struct survey_info *survey) 5173 { 5174 struct b43_wl *wl = hw_to_b43_wl(hw); 5175 struct b43_wldev *dev = wl->current_dev; 5176 struct ieee80211_conf *conf = &hw->conf; 5177 5178 if (idx != 0) 5179 return -ENOENT; 5180 5181 survey->channel = conf->chandef.chan; 5182 survey->filled = SURVEY_INFO_NOISE_DBM; 5183 survey->noise = dev->stats.link_noise; 5184 5185 return 0; 5186 } 5187 5188 static const struct ieee80211_ops b43_hw_ops = { 5189 .add_chanctx = ieee80211_emulate_add_chanctx, 5190 .remove_chanctx = ieee80211_emulate_remove_chanctx, 5191 .change_chanctx = ieee80211_emulate_change_chanctx, 5192 .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx, 5193 .tx = b43_op_tx, 5194 .wake_tx_queue = ieee80211_handle_wake_tx_queue, 5195 .conf_tx = b43_op_conf_tx, 5196 .add_interface = b43_op_add_interface, 5197 .remove_interface = b43_op_remove_interface, 5198 .config = b43_op_config, 5199 .bss_info_changed = b43_op_bss_info_changed, 5200 .configure_filter = b43_op_configure_filter, 5201 .set_key = b43_op_set_key, 5202 .update_tkip_key = b43_op_update_tkip_key, 5203 .get_stats = b43_op_get_stats, 5204 .get_tsf = b43_op_get_tsf, 5205 .set_tsf = b43_op_set_tsf, 5206 .start = b43_op_start, 5207 .stop = b43_op_stop, 5208 .set_tim = b43_op_beacon_set_tim, 5209 .sta_notify = b43_op_sta_notify, 5210 .sw_scan_start = b43_op_sw_scan_start_notifier, 5211 .sw_scan_complete = b43_op_sw_scan_complete_notifier, 5212 .get_survey = b43_op_get_survey, 5213 .rfkill_poll = b43_rfkill_poll, 5214 }; 5215 5216 /* Hard-reset the chip. Do not call this directly. 5217 * Use b43_controller_restart() 5218 */ 5219 static void b43_chip_reset(struct work_struct *work) 5220 { 5221 struct b43_wldev *dev = 5222 container_of(work, struct b43_wldev, restart_work); 5223 struct b43_wl *wl = dev->wl; 5224 int err = 0; 5225 int prev_status; 5226 5227 mutex_lock(&wl->mutex); 5228 5229 prev_status = b43_status(dev); 5230 /* Bring the device down... */ 5231 if (prev_status >= B43_STAT_STARTED) { 5232 dev = b43_wireless_core_stop(dev); 5233 if (!dev) { 5234 err = -ENODEV; 5235 goto out; 5236 } 5237 } 5238 if (prev_status >= B43_STAT_INITIALIZED) 5239 b43_wireless_core_exit(dev); 5240 5241 /* ...and up again. */ 5242 if (prev_status >= B43_STAT_INITIALIZED) { 5243 err = b43_wireless_core_init(dev); 5244 if (err) 5245 goto out; 5246 } 5247 if (prev_status >= B43_STAT_STARTED) { 5248 err = b43_wireless_core_start(dev); 5249 if (err) { 5250 b43_wireless_core_exit(dev); 5251 goto out; 5252 } 5253 } 5254 out: 5255 if (err) 5256 wl->current_dev = NULL; /* Failed to init the dev. */ 5257 mutex_unlock(&wl->mutex); 5258 5259 if (err) { 5260 b43err(wl, "Controller restart FAILED\n"); 5261 return; 5262 } 5263 5264 /* reload configuration */ 5265 b43_op_config(wl->hw, -1, ~0); 5266 if (wl->vif) 5267 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0); 5268 5269 b43info(wl, "Controller restarted\n"); 5270 } 5271 5272 static int b43_setup_bands(struct b43_wldev *dev, 5273 bool have_2ghz_phy, bool have_5ghz_phy) 5274 { 5275 struct ieee80211_hw *hw = dev->wl->hw; 5276 struct b43_phy *phy = &dev->phy; 5277 bool limited_2g; 5278 bool limited_5g; 5279 5280 /* We don't support all 2 GHz channels on some devices */ 5281 limited_2g = phy->radio_ver == 0x2057 && 5282 (phy->radio_rev == 9 || phy->radio_rev == 14); 5283 limited_5g = phy->radio_ver == 0x2057 && 5284 phy->radio_rev == 9; 5285 5286 if (have_2ghz_phy) 5287 hw->wiphy->bands[NL80211_BAND_2GHZ] = limited_2g ? 5288 &b43_band_2ghz_limited : &b43_band_2GHz; 5289 if (dev->phy.type == B43_PHYTYPE_N) { 5290 if (have_5ghz_phy) 5291 hw->wiphy->bands[NL80211_BAND_5GHZ] = limited_5g ? 5292 &b43_band_5GHz_nphy_limited : 5293 &b43_band_5GHz_nphy; 5294 } else { 5295 if (have_5ghz_phy) 5296 hw->wiphy->bands[NL80211_BAND_5GHZ] = &b43_band_5GHz_aphy; 5297 } 5298 5299 dev->phy.supports_2ghz = have_2ghz_phy; 5300 dev->phy.supports_5ghz = have_5ghz_phy; 5301 5302 return 0; 5303 } 5304 5305 static void b43_wireless_core_detach(struct b43_wldev *dev) 5306 { 5307 /* We release firmware that late to not be required to re-request 5308 * is all the time when we reinit the core. */ 5309 b43_release_firmware(dev); 5310 b43_phy_free(dev); 5311 } 5312 5313 static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy, 5314 bool *have_5ghz_phy) 5315 { 5316 u16 dev_id = 0; 5317 5318 #ifdef CONFIG_B43_BCMA 5319 if (dev->dev->bus_type == B43_BUS_BCMA && 5320 dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI) 5321 dev_id = dev->dev->bdev->bus->host_pci->device; 5322 #endif 5323 #ifdef CONFIG_B43_SSB 5324 if (dev->dev->bus_type == B43_BUS_SSB && 5325 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) 5326 dev_id = dev->dev->sdev->bus->host_pci->device; 5327 #endif 5328 /* Override with SPROM value if available */ 5329 if (dev->dev->bus_sprom->dev_id) 5330 dev_id = dev->dev->bus_sprom->dev_id; 5331 5332 /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */ 5333 switch (dev_id) { 5334 case 0x4324: /* BCM4306 */ 5335 case 0x4312: /* BCM4311 */ 5336 case 0x4319: /* BCM4318 */ 5337 case 0x4328: /* BCM4321 */ 5338 case 0x432b: /* BCM4322 */ 5339 case 0x4350: /* BCM43222 */ 5340 case 0x4353: /* BCM43224 */ 5341 case 0x0576: /* BCM43224 */ 5342 case 0x435f: /* BCM6362 */ 5343 case 0x4331: /* BCM4331 */ 5344 case 0x4359: /* BCM43228 */ 5345 case 0x43a0: /* BCM4360 */ 5346 case 0x43b1: /* BCM4352 */ 5347 /* Dual band devices */ 5348 *have_2ghz_phy = true; 5349 *have_5ghz_phy = true; 5350 return; 5351 case 0x4321: /* BCM4306 */ 5352 /* There are 14e4:4321 PCI devs with 2.4 GHz BCM4321 (N-PHY) */ 5353 if (dev->phy.type != B43_PHYTYPE_G) 5354 break; 5355 fallthrough; 5356 case 0x4313: /* BCM4311 */ 5357 case 0x431a: /* BCM4318 */ 5358 case 0x432a: /* BCM4321 */ 5359 case 0x432d: /* BCM4322 */ 5360 case 0x4352: /* BCM43222 */ 5361 case 0x435a: /* BCM43228 */ 5362 case 0x4333: /* BCM4331 */ 5363 case 0x43a2: /* BCM4360 */ 5364 case 0x43b3: /* BCM4352 */ 5365 /* 5 GHz only devices */ 5366 *have_2ghz_phy = false; 5367 *have_5ghz_phy = true; 5368 return; 5369 } 5370 5371 /* As a fallback, try to guess using PHY type */ 5372 switch (dev->phy.type) { 5373 case B43_PHYTYPE_G: 5374 case B43_PHYTYPE_N: 5375 case B43_PHYTYPE_LP: 5376 case B43_PHYTYPE_HT: 5377 case B43_PHYTYPE_LCN: 5378 *have_2ghz_phy = true; 5379 *have_5ghz_phy = false; 5380 return; 5381 } 5382 5383 B43_WARN_ON(1); 5384 } 5385 5386 static int b43_wireless_core_attach(struct b43_wldev *dev) 5387 { 5388 struct b43_wl *wl = dev->wl; 5389 struct b43_phy *phy = &dev->phy; 5390 int err; 5391 u32 tmp; 5392 bool have_2ghz_phy = false, have_5ghz_phy = false; 5393 5394 /* Do NOT do any device initialization here. 5395 * Do it in wireless_core_init() instead. 5396 * This function is for gathering basic information about the HW, only. 5397 * Also some structs may be set up here. But most likely you want to have 5398 * that in core_init(), too. 5399 */ 5400 5401 err = b43_bus_powerup(dev, 0); 5402 if (err) { 5403 b43err(wl, "Bus powerup failed\n"); 5404 goto out; 5405 } 5406 5407 phy->do_full_init = true; 5408 5409 /* Try to guess supported bands for the first init needs */ 5410 switch (dev->dev->bus_type) { 5411 #ifdef CONFIG_B43_BCMA 5412 case B43_BUS_BCMA: 5413 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST); 5414 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY); 5415 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY); 5416 break; 5417 #endif 5418 #ifdef CONFIG_B43_SSB 5419 case B43_BUS_SSB: 5420 if (dev->dev->core_rev >= 5) { 5421 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); 5422 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY); 5423 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY); 5424 } else 5425 B43_WARN_ON(1); 5426 break; 5427 #endif 5428 } 5429 5430 dev->phy.gmode = have_2ghz_phy; 5431 b43_wireless_core_reset(dev, dev->phy.gmode); 5432 5433 /* Get the PHY type. */ 5434 err = b43_phy_versioning(dev); 5435 if (err) 5436 goto err_powerdown; 5437 5438 /* Get real info about supported bands */ 5439 b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy); 5440 5441 /* We don't support 5 GHz on some PHYs yet */ 5442 if (have_5ghz_phy) { 5443 switch (dev->phy.type) { 5444 case B43_PHYTYPE_G: 5445 case B43_PHYTYPE_LP: 5446 case B43_PHYTYPE_HT: 5447 b43warn(wl, "5 GHz band is unsupported on this PHY\n"); 5448 have_5ghz_phy = false; 5449 } 5450 } 5451 5452 if (!have_2ghz_phy && !have_5ghz_phy) { 5453 b43err(wl, "b43 can't support any band on this device\n"); 5454 err = -EOPNOTSUPP; 5455 goto err_powerdown; 5456 } 5457 5458 err = b43_phy_allocate(dev); 5459 if (err) 5460 goto err_powerdown; 5461 5462 dev->phy.gmode = have_2ghz_phy; 5463 b43_wireless_core_reset(dev, dev->phy.gmode); 5464 5465 err = b43_validate_chipaccess(dev); 5466 if (err) 5467 goto err_phy_free; 5468 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); 5469 if (err) 5470 goto err_phy_free; 5471 5472 /* Now set some default "current_dev" */ 5473 if (!wl->current_dev) 5474 wl->current_dev = dev; 5475 INIT_WORK(&dev->restart_work, b43_chip_reset); 5476 5477 dev->phy.ops->switch_analog(dev, 0); 5478 b43_device_disable(dev, 0); 5479 b43_bus_may_powerdown(dev); 5480 5481 out: 5482 return err; 5483 5484 err_phy_free: 5485 b43_phy_free(dev); 5486 err_powerdown: 5487 b43_bus_may_powerdown(dev); 5488 return err; 5489 } 5490 5491 static void b43_one_core_detach(struct b43_bus_dev *dev) 5492 { 5493 struct b43_wldev *wldev; 5494 5495 /* Do not cancel ieee80211-workqueue based work here. 5496 * See comment in b43_remove(). */ 5497 5498 wldev = b43_bus_get_wldev(dev); 5499 b43_debugfs_remove_device(wldev); 5500 b43_wireless_core_detach(wldev); 5501 list_del(&wldev->list); 5502 b43_bus_set_wldev(dev, NULL); 5503 kfree(wldev); 5504 } 5505 5506 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl) 5507 { 5508 struct b43_wldev *wldev; 5509 int err = -ENOMEM; 5510 5511 wldev = kzalloc_obj(*wldev); 5512 if (!wldev) 5513 goto out; 5514 5515 wldev->use_pio = b43_modparam_pio; 5516 wldev->dev = dev; 5517 wldev->wl = wl; 5518 b43_set_status(wldev, B43_STAT_UNINIT); 5519 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 5520 INIT_LIST_HEAD(&wldev->list); 5521 5522 err = b43_wireless_core_attach(wldev); 5523 if (err) 5524 goto err_kfree_wldev; 5525 5526 b43_bus_set_wldev(dev, wldev); 5527 b43_debugfs_add_device(wldev); 5528 5529 out: 5530 return err; 5531 5532 err_kfree_wldev: 5533 kfree(wldev); 5534 return err; 5535 } 5536 5537 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ 5538 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ 5539 (pdev->device == _device) && \ 5540 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ 5541 (pdev->subsystem_device == _subdevice) ) 5542 5543 #ifdef CONFIG_B43_SSB 5544 static void b43_sprom_fixup(struct ssb_bus *bus) 5545 { 5546 struct pci_dev *pdev; 5547 5548 /* boardflags workarounds */ 5549 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && 5550 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74) 5551 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; 5552 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 5553 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40) 5554 bus->sprom.boardflags_lo |= B43_BFL_PACTRL; 5555 if (bus->bustype == SSB_BUSTYPE_PCI) { 5556 pdev = bus->host_pci; 5557 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || 5558 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || 5559 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || 5560 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || 5561 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || 5562 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || 5563 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) 5564 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; 5565 } 5566 } 5567 5568 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl) 5569 { 5570 struct ieee80211_hw *hw = wl->hw; 5571 5572 ssb_set_devtypedata(dev->sdev, NULL); 5573 ieee80211_free_hw(hw); 5574 } 5575 #endif 5576 5577 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev) 5578 { 5579 struct ssb_sprom *sprom = dev->bus_sprom; 5580 struct ieee80211_hw *hw; 5581 struct b43_wl *wl; 5582 char chip_name[6]; 5583 int queue_num; 5584 5585 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 5586 if (!hw) { 5587 b43err(NULL, "Could not allocate ieee80211 device\n"); 5588 return ERR_PTR(-ENOMEM); 5589 } 5590 wl = hw_to_b43_wl(hw); 5591 5592 /* fill hw info */ 5593 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 5594 ieee80211_hw_set(hw, SIGNAL_DBM); 5595 ieee80211_hw_set(hw, MFP_CAPABLE); 5596 hw->wiphy->interface_modes = 5597 BIT(NL80211_IFTYPE_AP) | 5598 BIT(NL80211_IFTYPE_MESH_POINT) | 5599 BIT(NL80211_IFTYPE_STATION) | 5600 BIT(NL80211_IFTYPE_ADHOC); 5601 5602 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 5603 5604 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 5605 5606 wl->hw_registered = false; 5607 hw->max_rates = 2; 5608 SET_IEEE80211_DEV(hw, dev->dev); 5609 if (is_valid_ether_addr(sprom->et1mac)) 5610 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); 5611 else 5612 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); 5613 5614 /* Initialize struct b43_wl */ 5615 wl->hw = hw; 5616 mutex_init(&wl->mutex); 5617 spin_lock_init(&wl->hardirq_lock); 5618 spin_lock_init(&wl->beacon_lock); 5619 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); 5620 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work); 5621 INIT_WORK(&wl->tx_work, b43_tx_work); 5622 5623 /* Initialize queues and flags. */ 5624 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { 5625 skb_queue_head_init(&wl->tx_queue[queue_num]); 5626 wl->tx_queue_stopped[queue_num] = false; 5627 } 5628 5629 snprintf(chip_name, ARRAY_SIZE(chip_name), 5630 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id); 5631 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name, 5632 dev->core_rev); 5633 return wl; 5634 } 5635 5636 #ifdef CONFIG_B43_BCMA 5637 static int b43_bcma_probe(struct bcma_device *core) 5638 { 5639 struct b43_bus_dev *dev; 5640 struct b43_wl *wl; 5641 int err; 5642 5643 if (!modparam_allhwsupport && 5644 (core->id.rev == 0x17 || core->id.rev == 0x18)) { 5645 pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n"); 5646 return -ENOTSUPP; 5647 } 5648 5649 dev = b43_bus_dev_bcma_init(core); 5650 if (!dev) 5651 return -ENODEV; 5652 5653 wl = b43_wireless_init(dev); 5654 if (IS_ERR(wl)) { 5655 err = PTR_ERR(wl); 5656 goto bcma_out; 5657 } 5658 5659 err = b43_one_core_attach(dev, wl); 5660 if (err) 5661 goto bcma_err_wireless_exit; 5662 5663 /* setup and start work to load firmware */ 5664 INIT_WORK(&wl->firmware_load, b43_request_firmware); 5665 schedule_work(&wl->firmware_load); 5666 5667 return err; 5668 5669 bcma_err_wireless_exit: 5670 ieee80211_free_hw(wl->hw); 5671 bcma_out: 5672 kfree(dev); 5673 return err; 5674 } 5675 5676 static void b43_bcma_remove(struct bcma_device *core) 5677 { 5678 struct b43_wldev *wldev = bcma_get_drvdata(core); 5679 struct b43_wl *wl = wldev->wl; 5680 5681 /* We must cancel any work here before unregistering from ieee80211, 5682 * as the ieee80211 unreg will destroy the workqueue. */ 5683 cancel_work_sync(&wldev->restart_work); 5684 cancel_work_sync(&wl->firmware_load); 5685 5686 B43_WARN_ON(!wl); 5687 if (!wldev->fw.ucode.data) 5688 return; /* NULL if firmware never loaded */ 5689 if (wl->current_dev == wldev && wl->hw_registered) { 5690 b43_leds_stop(wldev); 5691 ieee80211_unregister_hw(wl->hw); 5692 } 5693 5694 b43_one_core_detach(wldev->dev); 5695 5696 /* Unregister HW RNG driver */ 5697 b43_rng_exit(wl); 5698 5699 b43_leds_unregister(wl); 5700 ieee80211_free_hw(wl->hw); 5701 kfree(wldev->dev); 5702 } 5703 5704 static struct bcma_driver b43_bcma_driver = { 5705 .name = KBUILD_MODNAME, 5706 .id_table = b43_bcma_tbl, 5707 .probe = b43_bcma_probe, 5708 .remove = b43_bcma_remove, 5709 }; 5710 #endif 5711 5712 #ifdef CONFIG_B43_SSB 5713 static 5714 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id) 5715 { 5716 struct b43_bus_dev *dev; 5717 struct b43_wl *wl; 5718 int err; 5719 5720 dev = b43_bus_dev_ssb_init(sdev); 5721 if (!dev) 5722 return -ENOMEM; 5723 5724 wl = ssb_get_devtypedata(sdev); 5725 if (wl) { 5726 b43err(NULL, "Dual-core devices are not supported\n"); 5727 err = -ENOTSUPP; 5728 goto err_ssb_kfree_dev; 5729 } 5730 5731 b43_sprom_fixup(sdev->bus); 5732 5733 wl = b43_wireless_init(dev); 5734 if (IS_ERR(wl)) { 5735 err = PTR_ERR(wl); 5736 goto err_ssb_kfree_dev; 5737 } 5738 ssb_set_devtypedata(sdev, wl); 5739 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl); 5740 5741 err = b43_one_core_attach(dev, wl); 5742 if (err) 5743 goto err_ssb_wireless_exit; 5744 5745 /* setup and start work to load firmware */ 5746 INIT_WORK(&wl->firmware_load, b43_request_firmware); 5747 schedule_work(&wl->firmware_load); 5748 5749 return err; 5750 5751 err_ssb_wireless_exit: 5752 b43_wireless_exit(dev, wl); 5753 err_ssb_kfree_dev: 5754 kfree(dev); 5755 return err; 5756 } 5757 5758 static void b43_ssb_remove(struct ssb_device *sdev) 5759 { 5760 struct b43_wl *wl = ssb_get_devtypedata(sdev); 5761 struct b43_wldev *wldev = ssb_get_drvdata(sdev); 5762 struct b43_bus_dev *dev = wldev->dev; 5763 5764 /* We must cancel any work here before unregistering from ieee80211, 5765 * as the ieee80211 unreg will destroy the workqueue. */ 5766 cancel_work_sync(&wldev->restart_work); 5767 cancel_work_sync(&wl->firmware_load); 5768 5769 B43_WARN_ON(!wl); 5770 if (!wldev->fw.ucode.data) 5771 return; /* NULL if firmware never loaded */ 5772 if (wl->current_dev == wldev && wl->hw_registered) { 5773 b43_leds_stop(wldev); 5774 ieee80211_unregister_hw(wl->hw); 5775 } 5776 5777 b43_one_core_detach(dev); 5778 5779 /* Unregister HW RNG driver */ 5780 b43_rng_exit(wl); 5781 5782 b43_leds_unregister(wl); 5783 b43_wireless_exit(dev, wl); 5784 kfree(dev); 5785 } 5786 5787 static struct ssb_driver b43_ssb_driver = { 5788 .name = KBUILD_MODNAME, 5789 .id_table = b43_ssb_tbl, 5790 .probe = b43_ssb_probe, 5791 .remove = b43_ssb_remove, 5792 }; 5793 #endif /* CONFIG_B43_SSB */ 5794 5795 /* Perform a hardware reset. This can be called from any context. */ 5796 void b43_controller_restart(struct b43_wldev *dev, const char *reason) 5797 { 5798 /* Must avoid requeueing, if we are in shutdown. */ 5799 if (b43_status(dev) < B43_STAT_INITIALIZED) 5800 return; 5801 b43info(dev->wl, "Controller RESET (%s) ...\n", reason); 5802 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 5803 } 5804 5805 static void b43_print_driverinfo(void) 5806 { 5807 const char *feat_pci = "", *feat_nphy = "", 5808 *feat_leds = "", *feat_sdio = ""; 5809 5810 #ifdef CONFIG_B43_PCI_AUTOSELECT 5811 feat_pci = "P"; 5812 #endif 5813 #ifdef CONFIG_B43_PHY_N 5814 feat_nphy = "N"; 5815 #endif 5816 #ifdef CONFIG_B43_LEDS 5817 feat_leds = "L"; 5818 #endif 5819 #ifdef CONFIG_B43_SDIO 5820 feat_sdio = "S"; 5821 #endif 5822 printk(KERN_INFO "Broadcom 43xx driver loaded " 5823 "[ Features: %s%s%s%s ]\n", 5824 feat_pci, feat_nphy, feat_leds, feat_sdio); 5825 } 5826 5827 static int __init b43_init(void) 5828 { 5829 int err; 5830 5831 b43_debugfs_init(); 5832 err = b43_sdio_init(); 5833 if (err) 5834 goto err_dfs_exit; 5835 #ifdef CONFIG_B43_BCMA 5836 err = bcma_driver_register(&b43_bcma_driver); 5837 if (err) 5838 goto err_sdio_exit; 5839 #endif 5840 #ifdef CONFIG_B43_SSB 5841 err = ssb_driver_register(&b43_ssb_driver); 5842 if (err) 5843 goto err_bcma_driver_exit; 5844 #endif 5845 b43_print_driverinfo(); 5846 5847 return err; 5848 5849 #ifdef CONFIG_B43_SSB 5850 err_bcma_driver_exit: 5851 #endif 5852 #ifdef CONFIG_B43_BCMA 5853 bcma_driver_unregister(&b43_bcma_driver); 5854 err_sdio_exit: 5855 #endif 5856 b43_sdio_exit(); 5857 err_dfs_exit: 5858 b43_debugfs_exit(); 5859 return err; 5860 } 5861 5862 static void __exit b43_exit(void) 5863 { 5864 #ifdef CONFIG_B43_SSB 5865 ssb_driver_unregister(&b43_ssb_driver); 5866 #endif 5867 #ifdef CONFIG_B43_BCMA 5868 bcma_driver_unregister(&b43_bcma_driver); 5869 #endif 5870 b43_sdio_exit(); 5871 b43_debugfs_exit(); 5872 } 5873 5874 module_init(b43_init) 5875 module_exit(b43_exit) 5876