1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __WIL6210_H__ 19 #define __WIL6210_H__ 20 21 #include <linux/etherdevice.h> 22 #include <linux/netdevice.h> 23 #include <linux/wireless.h> 24 #include <net/cfg80211.h> 25 #include <linux/timex.h> 26 #include <linux/types.h> 27 #include <linux/irqreturn.h> 28 #include "wmi.h" 29 #include "wil_platform.h" 30 #include "fw.h" 31 32 extern bool no_fw_recovery; 33 extern unsigned int mtu_max; 34 extern unsigned short rx_ring_overflow_thrsh; 35 extern int agg_wsize; 36 extern bool rx_align_2; 37 extern bool rx_large_buf; 38 extern bool debug_fw; 39 extern bool disable_ap_sme; 40 extern bool ftm_mode; 41 42 struct wil6210_priv; 43 struct wil6210_vif; 44 union wil_tx_desc; 45 46 #define WIL_NAME "wil6210" 47 48 #define WIL_FW_NAME_DEFAULT "wil6210.fw" 49 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw" 50 51 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" 52 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw" 53 54 #define WIL_FW_NAME_TALYN "wil6436.fw" 55 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw" 56 #define WIL_BRD_NAME_TALYN "wil6436.brd" 57 58 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */ 59 60 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */ 61 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 62 63 #define WIL_NUM_LATENCY_BINS 200 64 65 /* maximum number of virtual interfaces the driver supports 66 * (including the main interface) 67 */ 68 #define WIL_MAX_VIFS 4 69 70 /** 71 * extract bits [@b0:@b1] (inclusive) from the value @x 72 * it should be @b0 <= @b1, or result is incorrect 73 */ 74 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 75 { 76 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 77 } 78 79 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL) 80 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL) 81 82 #define WIL_TX_Q_LEN_DEFAULT (4000) 83 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 84 #define WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT (11) 85 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 86 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 87 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 88 /* limit ring size in range [32..32k] */ 89 #define WIL_RING_SIZE_ORDER_MIN (5) 90 #define WIL_RING_SIZE_ORDER_MAX (15) 91 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 92 #define WIL6210_MAX_CID (8) /* HW limit */ 93 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 94 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 95 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 96 #define WIL_MAX_AMPDU_SIZE_128 (128 * 1024) /* FW/HW limit */ 97 #define WIL_MAX_AGG_WSIZE_64 (64) /* FW/HW limit */ 98 #define WIL6210_MAX_STATUS_RINGS (8) 99 100 /* Hardware offload block adds the following: 101 * 26 bytes - 3-address QoS data header 102 * 8 bytes - IV + EIV (for GCMP) 103 * 8 bytes - SNAP 104 * 16 bytes - MIC (for GCMP) 105 * 4 bytes - CRC 106 */ 107 #define WIL_MAX_MPDU_OVERHEAD (62) 108 109 struct wil_suspend_count_stats { 110 unsigned long successful_suspends; 111 unsigned long successful_resumes; 112 unsigned long failed_suspends; 113 unsigned long failed_resumes; 114 }; 115 116 struct wil_suspend_stats { 117 struct wil_suspend_count_stats r_off; 118 struct wil_suspend_count_stats r_on; 119 unsigned long rejected_by_device; /* only radio on */ 120 unsigned long rejected_by_host; 121 }; 122 123 /* Calculate MAC buffer size for the firmware. It includes all overhead, 124 * as it will go over the air, and need to be 8 byte aligned 125 */ 126 static inline u32 wil_mtu2macbuf(u32 mtu) 127 { 128 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 129 } 130 131 /* MTU for Ethernet need to take into account 8-byte SNAP header 132 * to be added when encapsulating Ethernet frame into 802.11 133 */ 134 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 135 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 136 #define WIL6210_ITR_TRSH_MAX (5000000) 137 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 138 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 139 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 140 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 141 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 142 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 143 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 144 #define WIL6210_DISCONNECT_TO_MS (2000) 145 #define WIL6210_RX_HIGH_TRSH_INIT (0) 146 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 147 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 148 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see 149 * 802.11REVmc/D5.0, section 9.4.1.8) 150 */ 151 /* Hardware definitions begin */ 152 153 /* 154 * Mapping 155 * RGF File | Host addr | FW addr 156 * | | 157 * user_rgf | 0x000000 | 0x880000 158 * dma_rgf | 0x001000 | 0x881000 159 * pcie_rgf | 0x002000 | 0x882000 160 * | | 161 */ 162 163 /* Where various structures placed in host address space */ 164 #define WIL6210_FW_HOST_OFF (0x880000UL) 165 166 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 167 168 /* 169 * Interrupt control registers block 170 * 171 * each interrupt controlled by the same bit in all registers 172 */ 173 struct RGF_ICR { 174 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 175 u32 ICR; /* Cause, W1C/COR depending on ICC */ 176 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 177 u32 ICS; /* Cause Set, WO */ 178 u32 IMV; /* Mask, RW+S/C */ 179 u32 IMS; /* Mask Set, write 1 to set */ 180 u32 IMC; /* Mask Clear, write 1 to clear */ 181 } __packed; 182 183 /* registers - FW addresses */ 184 #define RGF_USER_USAGE_1 (0x880004) 185 #define RGF_USER_USAGE_6 (0x880018) 186 #define BIT_USER_OOB_MODE BIT(31) 187 #define BIT_USER_OOB_R2_MODE BIT(30) 188 #define RGF_USER_USAGE_8 (0x880020) 189 #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) 190 #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) 191 #define BIT_USER_EXT_CLK BIT(2) 192 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 193 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 194 #define RGF_USER_USER_CPU_0 (0x8801e0) 195 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 196 #define RGF_USER_CPU_PC (0x8801e8) 197 #define RGF_USER_MAC_CPU_0 (0x8801fc) 198 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 199 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 200 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 201 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 202 #define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result 203 * b8-15:signature 204 */ 205 #define CALIB_RESULT_SIGNATURE (0x11) 206 #define RGF_USER_CLKS_CTL_0 (0x880abc) 207 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 208 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 209 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 210 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 211 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 212 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 213 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 214 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 215 #define BIT_CAR_PERST_RST BIT(7) 216 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 217 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 218 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 219 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 220 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 221 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 222 #define RGF_USER_OTP_HW_RD_MACHINE_1 (0x880ce0) 223 #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) 224 #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) 225 #define BIT_NO_FLASH_INDICATION BIT(8) 226 #define RGF_USER_XPM_IFC_RD_TIME1 (0x880cec) 227 #define RGF_USER_XPM_IFC_RD_TIME2 (0x880cf0) 228 #define RGF_USER_XPM_IFC_RD_TIME3 (0x880cf4) 229 #define RGF_USER_XPM_IFC_RD_TIME4 (0x880cf8) 230 #define RGF_USER_XPM_IFC_RD_TIME5 (0x880cfc) 231 #define RGF_USER_XPM_IFC_RD_TIME6 (0x880d00) 232 #define RGF_USER_XPM_IFC_RD_TIME7 (0x880d04) 233 #define RGF_USER_XPM_IFC_RD_TIME8 (0x880d08) 234 #define RGF_USER_XPM_IFC_RD_TIME9 (0x880d0c) 235 #define RGF_USER_XPM_IFC_RD_TIME10 (0x880d10) 236 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64) 237 238 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 239 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 240 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 241 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 242 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 243 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 244 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 245 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 246 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 247 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 248 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 249 250 /* Legacy interrupt moderation control (before Sparrow v2)*/ 251 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 252 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 253 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 254 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 255 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 256 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 257 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 258 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 259 260 /* Offload control (Sparrow B0+) */ 261 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 262 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 263 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 264 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 265 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 266 267 /* New (sparrow v2+) interrupt moderation control */ 268 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 269 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 270 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 271 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 272 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 273 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 274 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 275 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 276 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 277 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 278 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 279 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 280 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 281 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 282 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 283 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 284 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 285 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 286 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 287 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 288 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 289 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 290 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 291 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 292 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 293 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 294 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 295 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 296 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 297 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 298 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 299 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 300 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 301 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 302 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 303 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 304 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 305 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 306 #define RGF_DMA_MISC_CTL (0x881d6c) 307 #define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7) 308 309 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 310 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 311 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 312 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 313 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 314 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 315 316 #define RGF_HP_CTRL (0x88265c) 317 #define RGF_PAL_UNIT_ICR (0x88266c) /* struct RGF_ICR */ 318 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 319 320 /* MAC timer, usec, for packet lifetime */ 321 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 322 323 #define RGF_CAF_ICR_TALYN_MB (0x8893d4) /* struct RGF_ICR */ 324 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 325 #define RGF_CAF_OSC_CONTROL (0x88afa4) 326 #define BIT_CAF_OSC_XTAL_EN BIT(0) 327 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 328 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 329 330 #define RGF_OTP_QC_SECURED (0x8a0038) 331 #define BIT_BOOT_FROM_ROM BIT(31) 332 333 /* eDMA */ 334 #define RGF_INT_COUNT_ON_SPECIAL_EVT (0x8b62d8) 335 336 #define RGF_INT_CTRL_INT_GEN_CFG_0 (0x8bc000) 337 #define RGF_INT_CTRL_INT_GEN_CFG_1 (0x8bc004) 338 #define RGF_INT_GEN_TIME_UNIT_LIMIT (0x8bc0c8) 339 340 #define RGF_INT_GEN_CTRL (0x8bc0ec) 341 #define BIT_CONTROL_0 BIT(0) 342 343 /* eDMA status interrupts */ 344 #define RGF_INT_GEN_RX_ICR (0x8bc0f4) 345 #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) 346 #define RGF_INT_GEN_TX_ICR (0x8bc110) 347 #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) 348 #define RGF_INT_CTRL_RX_INT_MASK (0x8bc12c) 349 #define RGF_INT_CTRL_TX_INT_MASK (0x8bc130) 350 351 #define RGF_INT_GEN_IDLE_TIME_LIMIT (0x8bc134) 352 353 #define USER_EXT_USER_PMU_3 (0x88d00c) 354 #define BIT_PMU_DEVICE_RDY BIT(0) 355 356 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 357 #define JTAG_DEV_ID_SPARROW (0x2632072f) 358 #define JTAG_DEV_ID_TALYN (0x7e0e1) 359 #define JTAG_DEV_ID_TALYN_MB (0x1007e0e1) 360 361 #define RGF_USER_REVISION_ID (0x88afe4) 362 #define RGF_USER_REVISION_ID_MASK (3) 363 #define REVISION_ID_SPARROW_B0 (0x0) 364 #define REVISION_ID_SPARROW_D0 (0x3) 365 366 #define RGF_OTP_MAC_TALYN_MB (0x8a0304) 367 #define RGF_OTP_MAC (0x8a0620) 368 369 /* Talyn-MB */ 370 #define RGF_USER_USER_CPU_0_TALYN_MB (0x8c0138) 371 #define RGF_USER_MAC_CPU_0_TALYN_MB (0x8c0154) 372 373 /* crash codes for FW/Ucode stored here */ 374 375 /* ASSERT RGFs */ 376 #define SPARROW_RGF_FW_ASSERT_CODE (0x91f020) 377 #define SPARROW_RGF_UCODE_ASSERT_CODE (0x91f028) 378 #define TALYN_RGF_FW_ASSERT_CODE (0xa37020) 379 #define TALYN_RGF_UCODE_ASSERT_CODE (0xa37028) 380 381 enum { 382 HW_VER_UNKNOWN, 383 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */ 384 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */ 385 HW_VER_TALYN, /* JTAG_DEV_ID_TALYN */ 386 HW_VER_TALYN_MB /* JTAG_DEV_ID_TALYN_MB */ 387 }; 388 389 /* popular locations */ 390 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 391 #define HOST_MBOX HOSTADDR(RGF_MBOX) 392 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 393 394 /* ISR register bits */ 395 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 396 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 397 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 398 399 #define WIL_DATA_COMPLETION_TO_MS 200 400 401 /* Hardware definitions end */ 402 #define SPARROW_FW_MAPPING_TABLE_SIZE 10 403 #define TALYN_FW_MAPPING_TABLE_SIZE 13 404 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19 405 #define MAX_FW_MAPPING_TABLE_SIZE 19 406 407 /* Common representation of physical address in wil ring */ 408 struct wil_ring_dma_addr { 409 __le32 addr_low; 410 __le16 addr_high; 411 } __packed; 412 413 struct fw_map { 414 u32 from; /* linker address - from, inclusive */ 415 u32 to; /* linker address - to, exclusive */ 416 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 417 const char *name; /* for debugfs */ 418 bool fw; /* true if FW mapping, false if UCODE mapping */ 419 bool crash_dump; /* true if should be dumped during crash dump */ 420 }; 421 422 /* array size should be in sync with actual definition in the wmi.c */ 423 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE]; 424 extern const struct fw_map sparrow_d0_mac_rgf_ext; 425 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE]; 426 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE]; 427 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE]; 428 429 /** 430 * mk_cidxtid - construct @cidxtid field 431 * @cid: CID value 432 * @tid: TID value 433 * 434 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 435 */ 436 static inline u8 mk_cidxtid(u8 cid, u8 tid) 437 { 438 return ((tid & 0xf) << 4) | (cid & 0xf); 439 } 440 441 /** 442 * parse_cidxtid - parse @cidxtid field 443 * @cid: store CID value here 444 * @tid: store TID value here 445 * 446 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 447 */ 448 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 449 { 450 *cid = cidxtid & 0xf; 451 *tid = (cidxtid >> 4) & 0xf; 452 } 453 454 /** 455 * wil_cid_valid - check cid is valid 456 * @cid: CID value 457 */ 458 static inline bool wil_cid_valid(u8 cid) 459 { 460 return cid < WIL6210_MAX_CID; 461 } 462 463 struct wil6210_mbox_ring { 464 u32 base; 465 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 466 u16 size; 467 u32 tail; 468 u32 head; 469 } __packed; 470 471 struct wil6210_mbox_ring_desc { 472 __le32 sync; 473 __le32 addr; 474 } __packed; 475 476 /* at HOST_OFF_WIL6210_MBOX_CTL */ 477 struct wil6210_mbox_ctl { 478 struct wil6210_mbox_ring tx; 479 struct wil6210_mbox_ring rx; 480 } __packed; 481 482 struct wil6210_mbox_hdr { 483 __le16 seq; 484 __le16 len; /* payload, bytes after this header */ 485 __le16 type; 486 u8 flags; 487 u8 reserved; 488 } __packed; 489 490 #define WIL_MBOX_HDR_TYPE_WMI (0) 491 492 /* max. value for wil6210_mbox_hdr.len */ 493 #define MAX_MBOXITEM_SIZE (240) 494 495 struct pending_wmi_event { 496 struct list_head list; 497 struct { 498 struct wil6210_mbox_hdr hdr; 499 struct wmi_cmd_hdr wmi; 500 u8 data[0]; 501 } __packed event; 502 }; 503 504 enum { /* for wil_ctx.mapped_as */ 505 wil_mapped_as_none = 0, 506 wil_mapped_as_single = 1, 507 wil_mapped_as_page = 2, 508 }; 509 510 /** 511 * struct wil_ctx - software context for ring descriptor 512 */ 513 struct wil_ctx { 514 struct sk_buff *skb; 515 u8 nr_frags; 516 u8 mapped_as; 517 }; 518 519 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */ 520 u32 *va; 521 dma_addr_t pa; 522 }; 523 524 /** 525 * A general ring structure, used for RX and TX. 526 * In legacy DMA it represents the vring, 527 * In enahnced DMA it represents the descriptor ring (vrings are handled by FW) 528 */ 529 struct wil_ring { 530 dma_addr_t pa; 531 volatile union wil_ring_desc *va; 532 u16 size; /* number of wil_ring_desc elements */ 533 u32 swtail; 534 u32 swhead; 535 u32 hwtail; /* write here to inform hw */ 536 struct wil_ctx *ctx; /* ctx[size] - software context */ 537 struct wil_desc_ring_rx_swtail edma_rx_swtail; 538 bool is_rx; 539 }; 540 541 /** 542 * Additional data for Rx ring. 543 * Used for enhanced DMA RX chaining. 544 */ 545 struct wil_ring_rx_data { 546 /* the skb being assembled */ 547 struct sk_buff *skb; 548 /* true if we are skipping a bad fragmented packet */ 549 bool skipping; 550 u16 buff_size; 551 }; 552 553 /** 554 * Status ring structure, used for enhanced DMA completions for RX and TX. 555 */ 556 struct wil_status_ring { 557 dma_addr_t pa; 558 void *va; /* pointer to ring_[tr]x_status elements */ 559 u16 size; /* number of status elements */ 560 size_t elem_size; /* status element size in bytes */ 561 u32 swhead; 562 u32 hwtail; /* write here to inform hw */ 563 bool is_rx; 564 u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ 565 struct wil_ring_rx_data rx_data; 566 }; 567 568 #define WIL_STA_TID_NUM (16) 569 #define WIL_MCS_MAX (12) /* Maximum MCS supported */ 570 571 struct wil_net_stats { 572 unsigned long rx_packets; 573 unsigned long tx_packets; 574 unsigned long rx_bytes; 575 unsigned long tx_bytes; 576 unsigned long tx_errors; 577 u32 tx_latency_min_us; 578 u32 tx_latency_max_us; 579 u64 tx_latency_total_us; 580 unsigned long rx_dropped; 581 unsigned long rx_non_data_frame; 582 unsigned long rx_short_frame; 583 unsigned long rx_large_frame; 584 unsigned long rx_replay; 585 unsigned long rx_mic_error; 586 unsigned long rx_key_error; /* eDMA specific */ 587 unsigned long rx_amsdu_error; /* eDMA specific */ 588 unsigned long rx_csum_err; 589 u16 last_mcs_rx; 590 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 591 u32 ft_roams; /* relevant in STA mode */ 592 }; 593 594 /** 595 * struct tx_rx_ops - different TX/RX ops for legacy and enhanced 596 * DMA flow 597 */ 598 struct wil_txrx_ops { 599 void (*configure_interrupt_moderation)(struct wil6210_priv *wil); 600 /* TX ops */ 601 int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id, 602 int size, int cid, int tid); 603 void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring); 604 int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size); 605 int (*tx_init)(struct wil6210_priv *wil); 606 void (*tx_fini)(struct wil6210_priv *wil); 607 int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa, 608 u32 len, int ring_index); 609 void (*tx_desc_unmap)(struct device *dev, 610 union wil_tx_desc *desc, 611 struct wil_ctx *ctx); 612 int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif, 613 struct wil_ring *ring, struct sk_buff *skb); 614 int (*tx_ring_modify)(struct wil6210_vif *vif, int ring_id, 615 int cid, int tid); 616 irqreturn_t (*irq_tx)(int irq, void *cookie); 617 /* RX ops */ 618 int (*rx_init)(struct wil6210_priv *wil, uint ring_order); 619 void (*rx_fini)(struct wil6210_priv *wil); 620 int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid, 621 u8 tid, u8 token, u16 status, bool amsdu, 622 u16 agg_wsize, u16 timeout); 623 void (*get_reorder_params)(struct wil6210_priv *wil, 624 struct sk_buff *skb, int *tid, int *cid, 625 int *mid, u16 *seq, int *mcast, int *retry); 626 void (*get_netif_rx_params)(struct sk_buff *skb, 627 int *cid, int *security); 628 int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb); 629 int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb, 630 struct wil_net_stats *stats); 631 bool (*is_rx_idle)(struct wil6210_priv *wil); 632 irqreturn_t (*irq_rx)(int irq, void *cookie); 633 }; 634 635 /** 636 * Additional data for Tx ring 637 */ 638 struct wil_ring_tx_data { 639 bool dot1x_open; 640 int enabled; 641 cycles_t idle, last_idle, begin; 642 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 643 u16 agg_timeout; 644 u8 agg_amsdu; 645 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 646 u8 mid; 647 spinlock_t lock; 648 }; 649 650 enum { /* for wil6210_priv.status */ 651 wil_status_fwready = 0, /* FW operational */ 652 wil_status_dontscan, 653 wil_status_mbox_ready, /* MBOX structures ready */ 654 wil_status_irqen, /* interrupts enabled - for debug */ 655 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 656 wil_status_resetting, /* reset in progress */ 657 wil_status_suspending, /* suspend in progress */ 658 wil_status_suspended, /* suspend completed, device is suspended */ 659 wil_status_resuming, /* resume in progress */ 660 wil_status_collecting_dumps, /* crashdump collection in progress */ 661 wil_status_last /* keep last */ 662 }; 663 664 struct pci_dev; 665 666 /** 667 * struct tid_ampdu_rx - TID aggregation information (Rx). 668 * 669 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 670 * @last_rx: jiffies of last rx activity 671 * @head_seq_num: head sequence number in reordering buffer. 672 * @stored_mpdu_num: number of MPDUs in reordering buffer 673 * @ssn: Starting Sequence Number expected to be aggregated. 674 * @buf_size: buffer size for incoming A-MPDUs 675 * @ssn_last_drop: SSN of the last dropped frame 676 * @total: total number of processed incoming frames 677 * @drop_dup: duplicate frames dropped for this reorder buffer 678 * @drop_old: old frames dropped for this reorder buffer 679 * @first_time: true when this buffer used 1-st time 680 * @mcast_last_seq: sequence number (SN) of last received multicast packet 681 * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer 682 */ 683 struct wil_tid_ampdu_rx { 684 struct sk_buff **reorder_buf; 685 unsigned long last_rx; 686 u16 head_seq_num; 687 u16 stored_mpdu_num; 688 u16 ssn; 689 u16 buf_size; 690 u16 ssn_last_drop; 691 unsigned long long total; /* frames processed */ 692 unsigned long long drop_dup; 693 unsigned long long drop_old; 694 bool first_time; /* is it 1-st time this buffer used? */ 695 u16 mcast_last_seq; /* multicast dup detection */ 696 unsigned long long drop_dup_mcast; 697 }; 698 699 /** 700 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 701 * 702 * @pn: GCMP PN for the session 703 * @key_set: valid key present 704 */ 705 struct wil_tid_crypto_rx_single { 706 u8 pn[IEEE80211_GCMP_PN_LEN]; 707 bool key_set; 708 }; 709 710 struct wil_tid_crypto_rx { 711 struct wil_tid_crypto_rx_single key_id[4]; 712 }; 713 714 struct wil_p2p_info { 715 struct ieee80211_channel listen_chan; 716 u8 discovery_started; 717 u64 cookie; 718 struct wireless_dev *pending_listen_wdev; 719 unsigned int listen_duration; 720 struct timer_list discovery_timer; /* listen/search duration */ 721 struct work_struct discovery_expired_work; /* listen/search expire */ 722 struct work_struct delayed_listen_work; /* listen after scan done */ 723 }; 724 725 enum wil_sta_status { 726 wil_sta_unused = 0, 727 wil_sta_conn_pending = 1, 728 wil_sta_connected = 2, 729 }; 730 731 /** 732 * struct wil_sta_info - data for peer 733 * 734 * Peer identified by its CID (connection ID) 735 * NIC performs beam forming for each peer; 736 * if no beam forming done, frame exchange is not 737 * possible. 738 */ 739 struct wil_sta_info { 740 u8 addr[ETH_ALEN]; 741 u8 mid; 742 enum wil_sta_status status; 743 struct wil_net_stats stats; 744 /** 745 * 20 latency bins. 1st bin counts packets with latency 746 * of 0..tx_latency_res, last bin counts packets with latency 747 * of 19*tx_latency_res and above. 748 * tx_latency_res is configured from "tx_latency" debug-fs. 749 */ 750 u64 *tx_latency_bins; 751 struct wmi_link_stats_basic fw_stats_basic; 752 /* Rx BACK */ 753 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 754 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 755 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 756 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 757 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 758 struct wil_tid_crypto_rx group_crypto_rx; 759 u8 aid; /* 1-254; 0 if unknown/not reported */ 760 }; 761 762 enum { 763 fw_recovery_idle = 0, 764 fw_recovery_pending = 1, 765 fw_recovery_running = 2, 766 }; 767 768 enum { 769 hw_capa_no_flash, 770 hw_capa_last 771 }; 772 773 struct wil_probe_client_req { 774 struct list_head list; 775 u64 cookie; 776 u8 cid; 777 }; 778 779 struct pmc_ctx { 780 /* alloc, free, and read operations must own the lock */ 781 struct mutex lock; 782 struct vring_tx_desc *pring_va; 783 dma_addr_t pring_pa; 784 struct desc_alloc_info *descriptors; 785 int last_cmd_status; 786 int num_descriptors; 787 int descriptor_size; 788 }; 789 790 struct wil_halp { 791 struct mutex lock; /* protect halp ref_cnt */ 792 unsigned int ref_cnt; 793 struct completion comp; 794 }; 795 796 struct wil_blob_wrapper { 797 struct wil6210_priv *wil; 798 struct debugfs_blob_wrapper blob; 799 }; 800 801 #define WIL_LED_MAX_ID (2) 802 #define WIL_LED_INVALID_ID (0xF) 803 #define WIL_LED_BLINK_ON_SLOW_MS (300) 804 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 805 #define WIL_LED_BLINK_ON_MED_MS (200) 806 #define WIL_LED_BLINK_OFF_MED_MS (200) 807 #define WIL_LED_BLINK_ON_FAST_MS (100) 808 #define WIL_LED_BLINK_OFF_FAST_MS (100) 809 enum { 810 WIL_LED_TIME_SLOW = 0, 811 WIL_LED_TIME_MED, 812 WIL_LED_TIME_FAST, 813 WIL_LED_TIME_LAST, 814 }; 815 816 struct blink_on_off_time { 817 u32 on_ms; 818 u32 off_ms; 819 }; 820 821 struct wil_debugfs_iomem_data { 822 void *offset; 823 struct wil6210_priv *wil; 824 }; 825 826 struct wil_debugfs_data { 827 struct wil_debugfs_iomem_data *data_arr; 828 int iomem_data_count; 829 }; 830 831 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 832 extern u8 led_id; 833 extern u8 led_polarity; 834 835 enum wil6210_vif_status { 836 wil_vif_fwconnecting, 837 wil_vif_fwconnected, 838 wil_vif_ft_roam, 839 wil_vif_status_last /* keep last */ 840 }; 841 842 struct wil6210_vif { 843 struct wireless_dev wdev; 844 struct net_device *ndev; 845 struct wil6210_priv *wil; 846 u8 mid; 847 DECLARE_BITMAP(status, wil_vif_status_last); 848 u32 privacy; /* secure connection? */ 849 u16 channel; /* relevant in AP mode */ 850 u8 hidden_ssid; /* relevant in AP mode */ 851 u32 ap_isolate; /* no intra-BSS communication */ 852 bool pbss; 853 int bi; 854 u8 *proberesp, *proberesp_ies, *assocresp_ies; 855 size_t proberesp_len, proberesp_ies_len, assocresp_ies_len; 856 u8 ssid[IEEE80211_MAX_SSID_LEN]; 857 size_t ssid_len; 858 u8 gtk_index; 859 u8 gtk[WMI_MAX_KEY_LEN]; 860 size_t gtk_len; 861 int bcast_ring; 862 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */ 863 int locally_generated_disc; /* relevant in STA mode */ 864 struct timer_list connect_timer; 865 struct work_struct disconnect_worker; 866 /* scan */ 867 struct cfg80211_scan_request *scan_request; 868 struct timer_list scan_timer; /* detect scan timeout */ 869 struct wil_p2p_info p2p; 870 /* keep alive */ 871 struct list_head probe_client_pending; 872 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 873 struct work_struct probe_client_worker; 874 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 875 bool fw_stats_ready; /* per-cid statistics are ready inside sta_info */ 876 u64 fw_stats_tsf; /* measurement timestamp */ 877 }; 878 879 /** 880 * RX buffer allocated for enhanced DMA RX descriptors 881 */ 882 struct wil_rx_buff { 883 struct sk_buff *skb; 884 struct list_head list; 885 int id; 886 }; 887 888 /** 889 * During Rx completion processing, the driver extracts a buffer ID which 890 * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB 891 * is given to the network stack and the buffer is moved from the 'active' 892 * list to the 'free' list. 893 * During Rx refill, SKBs are attached to free buffers and moved to the 894 * 'active' list. 895 */ 896 struct wil_rx_buff_mgmt { 897 struct wil_rx_buff *buff_arr; 898 size_t size; /* number of items in buff_arr */ 899 struct list_head active; 900 struct list_head free; 901 unsigned long free_list_empty_cnt; /* statistics */ 902 }; 903 904 struct wil_fw_stats_global { 905 bool ready; 906 u64 tsf; /* measurement timestamp */ 907 struct wmi_link_stats_global stats; 908 }; 909 910 struct wil6210_priv { 911 struct pci_dev *pdev; 912 u32 bar_size; 913 struct wiphy *wiphy; 914 struct net_device *main_ndev; 915 int n_msi; 916 void __iomem *csr; 917 DECLARE_BITMAP(status, wil_status_last); 918 u8 fw_version[ETHTOOL_FWVERS_LEN]; 919 u32 hw_version; 920 u8 chip_revision; 921 const char *hw_name; 922 const char *wil_fw_name; 923 char *board_file; 924 u32 brd_file_addr; 925 u32 brd_file_max_size; 926 DECLARE_BITMAP(hw_capa, hw_capa_last); 927 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 928 DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX); 929 u32 recovery_count; /* num of FW recovery attempts in a short time */ 930 u32 recovery_state; /* FW recovery state machine */ 931 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 932 wait_queue_head_t wq; /* for all wait_event() use */ 933 u8 max_vifs; /* maximum number of interfaces, including main */ 934 struct wil6210_vif *vifs[WIL_MAX_VIFS]; 935 struct mutex vif_mutex; /* protects access to VIF entries */ 936 atomic_t connected_vifs; 937 /* profile */ 938 struct cfg80211_chan_def monitor_chandef; 939 u32 monitor_flags; 940 int sinfo_gen; 941 /* interrupt moderation */ 942 u32 tx_max_burst_duration; 943 u32 tx_interframe_timeout; 944 u32 rx_max_burst_duration; 945 u32 rx_interframe_timeout; 946 /* cached ISR registers */ 947 u32 isr_misc; 948 /* mailbox related */ 949 struct mutex wmi_mutex; 950 struct wil6210_mbox_ctl mbox_ctl; 951 struct completion wmi_ready; 952 struct completion wmi_call; 953 u16 wmi_seq; 954 u16 reply_id; /**< wait for this WMI event */ 955 u8 reply_mid; 956 void *reply_buf; 957 u16 reply_size; 958 struct workqueue_struct *wmi_wq; /* for deferred calls */ 959 struct work_struct wmi_event_worker; 960 struct workqueue_struct *wq_service; 961 struct work_struct fw_error_worker; /* for FW error recovery */ 962 struct list_head pending_wmi_ev; 963 /* 964 * protect pending_wmi_ev 965 * - fill in IRQ from wil6210_irq_misc, 966 * - consumed in thread by wmi_event_worker 967 */ 968 spinlock_t wmi_ev_lock; 969 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 970 struct napi_struct napi_rx; 971 struct napi_struct napi_tx; 972 struct net_device napi_ndev; /* dummy net_device serving all VIFs */ 973 974 /* DMA related */ 975 struct wil_ring ring_rx; 976 unsigned int rx_buf_len; 977 struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS]; 978 struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS]; 979 struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS]; 980 u8 num_rx_status_rings; 981 int tx_sring_idx; 982 u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 983 struct wil_sta_info sta[WIL6210_MAX_CID]; 984 u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once */ 985 u32 dma_addr_size; /* indicates dma addr size */ 986 struct wil_rx_buff_mgmt rx_buff_mgmt; 987 bool use_enhanced_dma_hw; 988 struct wil_txrx_ops txrx_ops; 989 990 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 991 /* statistics */ 992 atomic_t isr_count_rx, isr_count_tx; 993 /* debugfs */ 994 struct dentry *debug; 995 struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE]; 996 u8 discovery_mode; 997 u8 abft_len; 998 u8 wakeup_trigger; 999 struct wil_suspend_stats suspend_stats; 1000 struct wil_debugfs_data dbg_data; 1001 bool tx_latency; /* collect TX latency measurements */ 1002 size_t tx_latency_res; /* bin resolution in usec */ 1003 1004 void *platform_handle; 1005 struct wil_platform_ops platform_ops; 1006 bool keep_radio_on_during_sleep; 1007 1008 struct pmc_ctx pmc; 1009 1010 u8 p2p_dev_started; 1011 1012 /* P2P_DEVICE vif */ 1013 struct wireless_dev *p2p_wdev; 1014 struct wireless_dev *radio_wdev; 1015 1016 /* High Access Latency Policy voting */ 1017 struct wil_halp halp; 1018 1019 enum wmi_ps_profile_type ps_profile; 1020 1021 int fw_calib_result; 1022 1023 struct notifier_block pm_notify; 1024 1025 bool suspend_resp_rcvd; 1026 bool suspend_resp_comp; 1027 u32 bus_request_kbps; 1028 u32 bus_request_kbps_pre_suspend; 1029 1030 u32 rgf_fw_assert_code_addr; 1031 u32 rgf_ucode_assert_code_addr; 1032 u32 iccm_base; 1033 1034 /* relevant only for eDMA */ 1035 bool use_compressed_rx_status; 1036 u32 rx_status_ring_order; 1037 u32 tx_status_ring_order; 1038 u32 rx_buff_id_count; 1039 bool amsdu_en; 1040 bool use_rx_hw_reordering; 1041 bool secured_boot; 1042 u8 boot_config; 1043 1044 struct wil_fw_stats_global fw_stats_global; 1045 1046 u32 max_agg_wsize; 1047 u32 max_ampdu_size; 1048 }; 1049 1050 #define wil_to_wiphy(i) (i->wiphy) 1051 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 1052 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 1053 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 1054 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 1055 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n)) 1056 #define vif_to_wil(v) (v->wil) 1057 #define vif_to_ndev(v) (v->ndev) 1058 #define vif_to_wdev(v) (&v->wdev) 1059 1060 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil, 1061 struct wireless_dev *wdev) 1062 { 1063 /* main interface is shared with P2P device */ 1064 if (wdev == wil->p2p_wdev) 1065 return ndev_to_vif(wil->main_ndev); 1066 else 1067 return container_of(wdev, struct wil6210_vif, wdev); 1068 } 1069 1070 static inline struct wireless_dev * 1071 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif) 1072 { 1073 /* main interface is shared with P2P device */ 1074 if (vif->mid) 1075 return vif_to_wdev(vif); 1076 else 1077 return wil->radio_wdev; 1078 } 1079 1080 __printf(2, 3) 1081 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 1082 __printf(2, 3) 1083 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 1084 __printf(2, 3) 1085 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 1086 __printf(2, 3) 1087 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 1088 __printf(2, 3) 1089 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 1090 #define wil_dbg(wil, fmt, arg...) do { \ 1091 netdev_dbg(wil->main_ndev, fmt, ##arg); \ 1092 wil_dbg_trace(wil, fmt, ##arg); \ 1093 } while (0) 1094 1095 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 1096 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 1097 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 1098 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 1099 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 1100 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 1101 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 1102 #define wil_err_ratelimited(wil, fmt, arg...) \ 1103 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 1104 1105 /* target operations */ 1106 /* register read */ 1107 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 1108 { 1109 return readl(wil->csr + HOSTADDR(reg)); 1110 } 1111 1112 /* register write. wmb() to make sure it is completed */ 1113 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 1114 { 1115 writel(val, wil->csr + HOSTADDR(reg)); 1116 wmb(); /* wait for write to propagate to the HW */ 1117 } 1118 1119 /* register set = read, OR, write */ 1120 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 1121 { 1122 wil_w(wil, reg, wil_r(wil, reg) | val); 1123 } 1124 1125 /* register clear = read, AND with inverted, write */ 1126 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 1127 { 1128 wil_w(wil, reg, wil_r(wil, reg) & ~val); 1129 } 1130 1131 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len); 1132 1133 #if defined(CONFIG_DYNAMIC_DEBUG) 1134 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 1135 groupsize, buf, len, ascii) \ 1136 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 1137 prefix_type, rowsize, \ 1138 groupsize, buf, len, ascii) 1139 1140 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 1141 groupsize, buf, len, ascii) \ 1142 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 1143 prefix_type, rowsize, \ 1144 groupsize, buf, len, ascii) 1145 1146 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \ 1147 groupsize, buf, len, ascii) \ 1148 print_hex_dump_debug("DBG[MISC]" prefix_str,\ 1149 prefix_type, rowsize, \ 1150 groupsize, buf, len, ascii) 1151 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 1152 static inline 1153 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 1154 int groupsize, const void *buf, size_t len, bool ascii) 1155 { 1156 } 1157 1158 static inline 1159 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 1160 int groupsize, const void *buf, size_t len, bool ascii) 1161 { 1162 } 1163 1164 static inline 1165 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize, 1166 int groupsize, const void *buf, size_t len, bool ascii) 1167 { 1168 } 1169 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 1170 1171 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 1172 size_t count); 1173 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 1174 size_t count); 1175 1176 struct wil6210_vif * 1177 wil_vif_alloc(struct wil6210_priv *wil, const char *name, 1178 unsigned char name_assign_type, enum nl80211_iftype iftype); 1179 void wil_vif_free(struct wil6210_vif *vif); 1180 void *wil_if_alloc(struct device *dev); 1181 bool wil_has_other_active_ifaces(struct wil6210_priv *wil, 1182 struct net_device *ndev, bool up, bool ok); 1183 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok); 1184 void wil_if_free(struct wil6210_priv *wil); 1185 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif); 1186 int wil_if_add(struct wil6210_priv *wil); 1187 void wil_vif_remove(struct wil6210_priv *wil, u8 mid); 1188 void wil_if_remove(struct wil6210_priv *wil); 1189 int wil_priv_init(struct wil6210_priv *wil); 1190 void wil_priv_deinit(struct wil6210_priv *wil); 1191 int wil_ps_update(struct wil6210_priv *wil, 1192 enum wmi_ps_profile_type ps_profile); 1193 int wil_reset(struct wil6210_priv *wil, bool no_fw); 1194 void wil_fw_error_recovery(struct wil6210_priv *wil); 1195 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 1196 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 1197 int wil_up(struct wil6210_priv *wil); 1198 int __wil_up(struct wil6210_priv *wil); 1199 int wil_down(struct wil6210_priv *wil); 1200 int __wil_down(struct wil6210_priv *wil); 1201 void wil_refresh_fw_capabilities(struct wil6210_priv *wil); 1202 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 1203 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac); 1204 void wil_set_ethtoolops(struct net_device *ndev); 1205 1206 struct fw_map *wil_find_fw_mapping(const char *section); 1207 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size); 1208 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 1209 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 1210 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 1211 struct wil6210_mbox_hdr *hdr); 1212 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len); 1213 void wmi_recv_cmd(struct wil6210_priv *wil); 1214 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len, 1215 u16 reply_id, void *reply, u16 reply_size, int to_msec); 1216 void wmi_event_worker(struct work_struct *work); 1217 void wmi_event_flush(struct wil6210_priv *wil); 1218 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid); 1219 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid); 1220 int wmi_set_channel(struct wil6210_priv *wil, int channel); 1221 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 1222 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index, 1223 const void *mac_addr, int key_usage); 1224 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index, 1225 const void *mac_addr, int key_len, const void *key, 1226 int key_usage); 1227 int wmi_echo(struct wil6210_priv *wil); 1228 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie); 1229 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring); 1230 int wmi_update_ft_ies(struct wil6210_vif *vif, u16 ie_len, const void *ie); 1231 int wmi_rxon(struct wil6210_priv *wil, bool on); 1232 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 1233 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, u16 reason, 1234 bool del_sta); 1235 int wmi_addba(struct wil6210_priv *wil, u8 mid, 1236 u8 ringid, u8 size, u16 timeout); 1237 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason); 1238 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cidxtid, u16 reason); 1239 int wmi_addba_rx_resp(struct wil6210_priv *wil, 1240 u8 mid, u8 cid, u8 tid, u8 token, 1241 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 1242 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 1243 enum wmi_ps_profile_type ps_profile); 1244 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 1245 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 1246 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid); 1247 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid, 1248 const u8 *mac, enum nl80211_iftype iftype); 1249 int wmi_port_delete(struct wil6210_priv *wil, u8 mid); 1250 int wmi_link_stats_cfg(struct wil6210_vif *vif, u32 type, u8 cid, u32 interval); 1251 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, 1252 u8 cidxtid, u8 dialog_token, __le16 ba_param_set, 1253 __le16 ba_timeout, __le16 ba_seq_ctrl); 1254 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 1255 1256 void wil6210_clear_irq(struct wil6210_priv *wil); 1257 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 1258 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 1259 void wil_mask_irq(struct wil6210_priv *wil); 1260 void wil_unmask_irq(struct wil6210_priv *wil); 1261 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 1262 void wil_disable_irq(struct wil6210_priv *wil); 1263 void wil_enable_irq(struct wil6210_priv *wil); 1264 void wil6210_mask_halp(struct wil6210_priv *wil); 1265 1266 /* P2P */ 1267 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 1268 int wil_p2p_search(struct wil6210_vif *vif, 1269 struct cfg80211_scan_request *request); 1270 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 1271 unsigned int duration, struct ieee80211_channel *chan, 1272 u64 *cookie); 1273 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif); 1274 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie); 1275 void wil_p2p_listen_expired(struct work_struct *work); 1276 void wil_p2p_search_expired(struct work_struct *work); 1277 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 1278 void wil_p2p_delayed_listen_work(struct work_struct *work); 1279 1280 /* WMI for P2P */ 1281 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi); 1282 int wmi_start_listen(struct wil6210_vif *vif); 1283 int wmi_start_search(struct wil6210_vif *vif); 1284 int wmi_stop_discovery(struct wil6210_vif *vif); 1285 1286 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 1287 struct cfg80211_mgmt_tx_params *params, 1288 u64 *cookie); 1289 void wil_cfg80211_ap_recovery(struct wil6210_priv *wil); 1290 int wil_cfg80211_iface_combinations_from_fw( 1291 struct wil6210_priv *wil, 1292 const struct wil_fw_record_concurrency *conc); 1293 int wil_vif_prepare_stop(struct wil6210_vif *vif); 1294 1295 #if defined(CONFIG_WIL6210_DEBUGFS) 1296 int wil6210_debugfs_init(struct wil6210_priv *wil); 1297 void wil6210_debugfs_remove(struct wil6210_priv *wil); 1298 #else 1299 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; } 1300 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {} 1301 #endif 1302 1303 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid, 1304 struct station_info *sinfo); 1305 1306 struct wil6210_priv *wil_cfg80211_init(struct device *dev); 1307 void wil_cfg80211_deinit(struct wil6210_priv *wil); 1308 void wil_p2p_wdev_free(struct wil6210_priv *wil); 1309 1310 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 1311 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan, 1312 u8 hidden_ssid, u8 is_go); 1313 int wmi_pcp_stop(struct wil6210_vif *vif); 1314 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 1315 int wmi_abort_scan(struct wil6210_vif *vif); 1316 void wil_abort_scan(struct wil6210_vif *vif, bool sync); 1317 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync); 1318 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps); 1319 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 1320 u16 reason_code); 1321 void wil6210_disconnect_complete(struct wil6210_vif *vif, const u8 *bssid, 1322 u16 reason_code); 1323 void wil_probe_client_flush(struct wil6210_vif *vif); 1324 void wil_probe_client_worker(struct work_struct *work); 1325 void wil_disconnect_worker(struct work_struct *work); 1326 1327 void wil_init_txrx_ops(struct wil6210_priv *wil); 1328 1329 /* TX API */ 1330 int wil_ring_init_tx(struct wil6210_vif *vif, int cid); 1331 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); 1332 int wil_bcast_init(struct wil6210_vif *vif); 1333 void wil_bcast_fini(struct wil6210_vif *vif); 1334 void wil_bcast_fini_all(struct wil6210_priv *wil); 1335 1336 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 1337 struct wil_ring *ring, bool should_stop); 1338 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 1339 struct wil_ring *ring, bool check_stop); 1340 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 1341 int wil_tx_complete(struct wil6210_vif *vif, int ringid); 1342 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 1343 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil); 1344 1345 /* RX API */ 1346 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 1347 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 1348 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil); 1349 void wil_set_crypto_rx(u8 key_index, enum wmi_key_usage key_usage, 1350 struct wil_sta_info *cs, 1351 struct key_params *params); 1352 1353 int wil_iftype_nl2wmi(enum nl80211_iftype type); 1354 1355 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 1356 bool load); 1357 int wil_request_board(struct wil6210_priv *wil, const char *name); 1358 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name); 1359 1360 void wil_pm_runtime_allow(struct wil6210_priv *wil); 1361 void wil_pm_runtime_forbid(struct wil6210_priv *wil); 1362 int wil_pm_runtime_get(struct wil6210_priv *wil); 1363 void wil_pm_runtime_put(struct wil6210_priv *wil); 1364 1365 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 1366 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1367 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1368 bool wil_is_wmi_idle(struct wil6210_priv *wil); 1369 int wmi_resume(struct wil6210_priv *wil); 1370 int wmi_suspend(struct wil6210_priv *wil); 1371 bool wil_is_tx_idle(struct wil6210_priv *wil); 1372 1373 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 1374 void wil_fw_core_dump(struct wil6210_priv *wil); 1375 1376 void wil_halp_vote(struct wil6210_priv *wil); 1377 void wil_halp_unvote(struct wil6210_priv *wil); 1378 void wil6210_set_halp(struct wil6210_priv *wil); 1379 void wil6210_clear_halp(struct wil6210_priv *wil); 1380 1381 int wmi_start_sched_scan(struct wil6210_priv *wil, 1382 struct cfg80211_sched_scan_request *request); 1383 int wmi_stop_sched_scan(struct wil6210_priv *wil); 1384 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len); 1385 int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len, 1386 u8 channel, u16 duration_ms); 1387 1388 int reverse_memcmp(const void *cs, const void *ct, size_t count); 1389 1390 /* WMI for enhanced DMA */ 1391 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id); 1392 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil, 1393 u16 max_rx_pl_per_desc); 1394 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id); 1395 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id); 1396 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid, 1397 int tid); 1398 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id); 1399 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid, 1400 u8 tid, u8 token, u16 status, bool amsdu, 1401 u16 agg_wsize, u16 timeout); 1402 1403 void update_supported_bands(struct wil6210_priv *wil); 1404 1405 #endif /* __WIL6210_H__ */ 1406