xref: /linux/drivers/net/wireless/ath/wil6210/wil6210.h (revision 2ba9268dd603d23e17643437b2246acb6844953b)
1 /*
2  * Copyright (c) 2012-2015 Qualcomm Atheros, Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef __WIL6210_H__
18 #define __WIL6210_H__
19 
20 #include <linux/netdevice.h>
21 #include <linux/wireless.h>
22 #include <net/cfg80211.h>
23 #include <linux/timex.h>
24 #include "wil_platform.h"
25 
26 extern bool no_fw_recovery;
27 extern unsigned int mtu_max;
28 extern unsigned short rx_ring_overflow_thrsh;
29 extern int agg_wsize;
30 
31 #define WIL_NAME "wil6210"
32 #define WIL_FW_NAME "wil6210.fw"
33 
34 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */
35 
36 /**
37  * extract bits [@b0:@b1] (inclusive) from the value @x
38  * it should be @b0 <= @b1, or result is incorrect
39  */
40 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
41 {
42 	return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
43 }
44 
45 #define WIL6210_MEM_SIZE (2*1024*1024UL)
46 
47 #define WIL_TX_Q_LEN_DEFAULT		(4000)
48 #define WIL_RX_RING_SIZE_ORDER_DEFAULT	(10)
49 #define WIL_TX_RING_SIZE_ORDER_DEFAULT	(10)
50 /* limit ring size in range [32..32k] */
51 #define WIL_RING_SIZE_ORDER_MIN	(5)
52 #define WIL_RING_SIZE_ORDER_MAX	(15)
53 #define WIL6210_MAX_TX_RINGS	(24) /* HW limit */
54 #define WIL6210_MAX_CID		(8) /* HW limit */
55 #define WIL6210_NAPI_BUDGET	(16) /* arbitrary */
56 #define WIL_MAX_AMPDU_SIZE	(64 * 1024) /* FW/HW limit */
57 #define WIL_MAX_AGG_WSIZE	(32) /* FW/HW limit */
58 /* Hardware offload block adds the following:
59  * 26 bytes - 3-address QoS data header
60  *  8 bytes - IV + EIV (for GCMP)
61  *  8 bytes - SNAP
62  * 16 bytes - MIC (for GCMP)
63  *  4 bytes - CRC
64  */
65 #define WIL_MAX_MPDU_OVERHEAD	(62)
66 
67 /* Calculate MAC buffer size for the firmware. It includes all overhead,
68  * as it will go over the air, and need to be 8 byte aligned
69  */
70 static inline u32 wil_mtu2macbuf(u32 mtu)
71 {
72 	return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8);
73 }
74 
75 /* MTU for Ethernet need to take into account 8-byte SNAP header
76  * to be added when encapsulating Ethernet frame into 802.11
77  */
78 #define WIL_MAX_ETH_MTU		(IEEE80211_MAX_DATA_LEN_DMG - 8)
79 /* Max supported by wil6210 value for interrupt threshold is 5sec. */
80 #define WIL6210_ITR_TRSH_MAX (5000000)
81 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
82 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
83 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
84 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
85 #define WIL6210_FW_RECOVERY_RETRIES	(5) /* try to recover this many times */
86 #define WIL6210_FW_RECOVERY_TO	msecs_to_jiffies(5000)
87 #define WIL6210_SCAN_TO		msecs_to_jiffies(10000)
88 #define WIL6210_RX_HIGH_TRSH_INIT		(0)
89 #define WIL6210_RX_HIGH_TRSH_DEFAULT \
90 				(1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3))
91 /* Hardware definitions begin */
92 
93 /*
94  * Mapping
95  * RGF File      | Host addr    |  FW addr
96  *               |              |
97  * user_rgf      | 0x000000     | 0x880000
98  *  dma_rgf      | 0x001000     | 0x881000
99  * pcie_rgf      | 0x002000     | 0x882000
100  *               |              |
101  */
102 
103 /* Where various structures placed in host address space */
104 #define WIL6210_FW_HOST_OFF      (0x880000UL)
105 
106 #define HOSTADDR(fwaddr)        (fwaddr - WIL6210_FW_HOST_OFF)
107 
108 /*
109  * Interrupt control registers block
110  *
111  * each interrupt controlled by the same bit in all registers
112  */
113 struct RGF_ICR {
114 	u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
115 	u32 ICR; /* Cause, W1C/COR depending on ICC */
116 	u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
117 	u32 ICS; /* Cause Set, WO */
118 	u32 IMV; /* Mask, RW+S/C */
119 	u32 IMS; /* Mask Set, write 1 to set */
120 	u32 IMC; /* Mask Clear, write 1 to clear */
121 } __packed;
122 
123 /* registers - FW addresses */
124 #define RGF_USER_USAGE_1		(0x880004)
125 #define RGF_USER_USAGE_6		(0x880018)
126 #define RGF_USER_HW_MACHINE_STATE	(0x8801dc)
127 	#define HW_MACHINE_BOOT_DONE	(0x3fffffd)
128 #define RGF_USER_USER_CPU_0		(0x8801e0)
129 	#define BIT_USER_USER_CPU_MAN_RST	BIT(1) /* user_cpu_man_rst */
130 #define RGF_USER_MAC_CPU_0		(0x8801fc)
131 	#define BIT_USER_MAC_CPU_MAN_RST	BIT(1) /* mac_cpu_man_rst */
132 #define RGF_USER_USER_SCRATCH_PAD	(0x8802bc)
133 #define RGF_USER_FW_REV_ID		(0x880a8c) /* chip revision */
134 #define RGF_USER_CLKS_CTL_0		(0x880abc)
135 	#define BIT_USER_CLKS_CAR_AHB_SW_SEL	BIT(1) /* ref clk/PLL */
136 	#define BIT_USER_CLKS_RST_PWGD	BIT(11) /* reset on "power good" */
137 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0	(0x880b04)
138 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1	(0x880b08)
139 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2	(0x880b0c)
140 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3	(0x880b10)
141 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0	(0x880b14)
142 	#define BIT_HPAL_PERST_FROM_PAD	BIT(6)
143 	#define BIT_CAR_PERST_RST	BIT(7)
144 #define RGF_USER_USER_ICR		(0x880b4c) /* struct RGF_ICR */
145 	#define BIT_USER_USER_ICR_SW_INT_2	BIT(18)
146 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0	(0x880c18)
147 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1	(0x880c2c)
148 #define RGF_USER_SPARROW_M_4			(0x880c50) /* Sparrow */
149 	#define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF	BIT(2)
150 
151 #define RGF_DMA_EP_TX_ICR		(0x881bb4) /* struct RGF_ICR */
152 	#define BIT_DMA_EP_TX_ICR_TX_DONE	BIT(0)
153 	#define BIT_DMA_EP_TX_ICR_TX_DONE_N(n)	BIT(n+1) /* n = [0..23] */
154 #define RGF_DMA_EP_RX_ICR		(0x881bd0) /* struct RGF_ICR */
155 	#define BIT_DMA_EP_RX_ICR_RX_DONE	BIT(0)
156 	#define BIT_DMA_EP_RX_ICR_RX_HTRSH	BIT(1)
157 #define RGF_DMA_EP_MISC_ICR		(0x881bec) /* struct RGF_ICR */
158 	#define BIT_DMA_EP_MISC_ICR_RX_HTRSH	BIT(0)
159 	#define BIT_DMA_EP_MISC_ICR_TX_NO_ACT	BIT(1)
160 	#define BIT_DMA_EP_MISC_ICR_FW_INT(n)	BIT(28+n) /* n = [0..3] */
161 
162 /* Legacy interrupt moderation control (before Sparrow v2)*/
163 #define RGF_DMA_ITR_CNT_TRSH		(0x881c5c)
164 #define RGF_DMA_ITR_CNT_DATA		(0x881c60)
165 #define RGF_DMA_ITR_CNT_CRL		(0x881c64)
166 	#define BIT_DMA_ITR_CNT_CRL_EN		BIT(0)
167 	#define BIT_DMA_ITR_CNT_CRL_EXT_TICK	BIT(1)
168 	#define BIT_DMA_ITR_CNT_CRL_FOREVER	BIT(2)
169 	#define BIT_DMA_ITR_CNT_CRL_CLR		BIT(3)
170 	#define BIT_DMA_ITR_CNT_CRL_REACH_TRSH	BIT(4)
171 
172 /* New (sparrow v2+) interrupt moderation control */
173 #define RGF_DMA_ITR_TX_DESQ_NO_MOD		(0x881d40)
174 #define RGF_DMA_ITR_TX_CNT_TRSH			(0x881d34)
175 #define RGF_DMA_ITR_TX_CNT_DATA			(0x881d38)
176 #define RGF_DMA_ITR_TX_CNT_CTL			(0x881d3c)
177 	#define BIT_DMA_ITR_TX_CNT_CTL_EN		BIT(0)
178 	#define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL	BIT(1)
179 	#define BIT_DMA_ITR_TX_CNT_CTL_FOREVER		BIT(2)
180 	#define BIT_DMA_ITR_TX_CNT_CTL_CLR		BIT(3)
181 	#define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH	BIT(4)
182 	#define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN		BIT(5)
183 	#define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG	BIT(6)
184 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH			(0x881d60)
185 #define RGF_DMA_ITR_TX_IDL_CNT_DATA			(0x881d64)
186 #define RGF_DMA_ITR_TX_IDL_CNT_CTL			(0x881d68)
187 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN			BIT(0)
188 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL		BIT(1)
189 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER		BIT(2)
190 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR			BIT(3)
191 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH	BIT(4)
192 #define RGF_DMA_ITR_RX_DESQ_NO_MOD		(0x881d50)
193 #define RGF_DMA_ITR_RX_CNT_TRSH			(0x881d44)
194 #define RGF_DMA_ITR_RX_CNT_DATA			(0x881d48)
195 #define RGF_DMA_ITR_RX_CNT_CTL			(0x881d4c)
196 	#define BIT_DMA_ITR_RX_CNT_CTL_EN		BIT(0)
197 	#define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL	BIT(1)
198 	#define BIT_DMA_ITR_RX_CNT_CTL_FOREVER		BIT(2)
199 	#define BIT_DMA_ITR_RX_CNT_CTL_CLR		BIT(3)
200 	#define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH	BIT(4)
201 	#define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN		BIT(5)
202 	#define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG	BIT(6)
203 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH			(0x881d54)
204 #define RGF_DMA_ITR_RX_IDL_CNT_DATA			(0x881d58)
205 #define RGF_DMA_ITR_RX_IDL_CNT_CTL			(0x881d5c)
206 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN			BIT(0)
207 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL		BIT(1)
208 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER		BIT(2)
209 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR			BIT(3)
210 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH	BIT(4)
211 
212 #define RGF_DMA_PSEUDO_CAUSE		(0x881c68)
213 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW	(0x881c6c)
214 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW	(0x881c70)
215 	#define BIT_DMA_PSEUDO_CAUSE_RX		BIT(0)
216 	#define BIT_DMA_PSEUDO_CAUSE_TX		BIT(1)
217 	#define BIT_DMA_PSEUDO_CAUSE_MISC	BIT(2)
218 
219 #define RGF_HP_CTRL			(0x88265c)
220 #define RGF_PCIE_LOS_COUNTER_CTL	(0x882dc4)
221 
222 /* MAC timer, usec, for packet lifetime */
223 #define RGF_MAC_MTRL_COUNTER_0		(0x886aa8)
224 
225 #define RGF_CAF_ICR			(0x88946c) /* struct RGF_ICR */
226 #define RGF_CAF_OSC_CONTROL		(0x88afa4)
227 	#define BIT_CAF_OSC_XTAL_EN		BIT(0)
228 #define RGF_CAF_PLL_LOCK_STATUS		(0x88afec)
229 	#define BIT_CAF_OSC_DIG_XTAL_STABLE	BIT(0)
230 
231 #define RGF_USER_JTAG_DEV_ID	(0x880b34) /* device ID */
232 	#define JTAG_DEV_ID_MARLON_B0	(0x0612072f)
233 	#define JTAG_DEV_ID_SPARROW_A0	(0x0632072f)
234 	#define JTAG_DEV_ID_SPARROW_A1	(0x1632072f)
235 	#define JTAG_DEV_ID_SPARROW_B0	(0x2632072f)
236 
237 enum {
238 	HW_VER_UNKNOWN,
239 	HW_VER_MARLON_B0,  /* JTAG_DEV_ID_MARLON_B0  */
240 	HW_VER_SPARROW_A0, /* JTAG_DEV_ID_SPARROW_A0 */
241 	HW_VER_SPARROW_A1, /* JTAG_DEV_ID_SPARROW_A1 */
242 	HW_VER_SPARROW_B0, /* JTAG_DEV_ID_SPARROW_B0 */
243 };
244 
245 /* popular locations */
246 #define HOST_MBOX   HOSTADDR(RGF_USER_USER_SCRATCH_PAD)
247 #define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \
248 	offsetof(struct RGF_ICR, ICS))
249 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
250 
251 /* ISR register bits */
252 #define ISR_MISC_FW_READY	BIT_DMA_EP_MISC_ICR_FW_INT(0)
253 #define ISR_MISC_MBOX_EVT	BIT_DMA_EP_MISC_ICR_FW_INT(1)
254 #define ISR_MISC_FW_ERROR	BIT_DMA_EP_MISC_ICR_FW_INT(3)
255 
256 /* Hardware definitions end */
257 struct fw_map {
258 	u32 from; /* linker address - from, inclusive */
259 	u32 to;   /* linker address - to, exclusive */
260 	u32 host; /* PCI/Host address - BAR0 + 0x880000 */
261 	const char *name; /* for debugfs */
262 };
263 
264 /* array size should be in sync with actual definition in the wmi.c */
265 extern const struct fw_map fw_mapping[7];
266 
267 /**
268  * mk_cidxtid - construct @cidxtid field
269  * @cid: CID value
270  * @tid: TID value
271  *
272  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
273  */
274 static inline u8 mk_cidxtid(u8 cid, u8 tid)
275 {
276 	return ((tid & 0xf) << 4) | (cid & 0xf);
277 }
278 
279 /**
280  * parse_cidxtid - parse @cidxtid field
281  * @cid: store CID value here
282  * @tid: store TID value here
283  *
284  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
285  */
286 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid)
287 {
288 	*cid = cidxtid & 0xf;
289 	*tid = (cidxtid >> 4) & 0xf;
290 }
291 
292 struct wil6210_mbox_ring {
293 	u32 base;
294 	u16 entry_size; /* max. size of mbox entry, incl. all headers */
295 	u16 size;
296 	u32 tail;
297 	u32 head;
298 } __packed;
299 
300 struct wil6210_mbox_ring_desc {
301 	__le32 sync;
302 	__le32 addr;
303 } __packed;
304 
305 /* at HOST_OFF_WIL6210_MBOX_CTL */
306 struct wil6210_mbox_ctl {
307 	struct wil6210_mbox_ring tx;
308 	struct wil6210_mbox_ring rx;
309 } __packed;
310 
311 struct wil6210_mbox_hdr {
312 	__le16 seq;
313 	__le16 len; /* payload, bytes after this header */
314 	__le16 type;
315 	u8 flags;
316 	u8 reserved;
317 } __packed;
318 
319 #define WIL_MBOX_HDR_TYPE_WMI (0)
320 
321 /* max. value for wil6210_mbox_hdr.len */
322 #define MAX_MBOXITEM_SIZE   (240)
323 
324 /**
325  * struct wil6210_mbox_hdr_wmi - WMI header
326  *
327  * @mid: MAC ID
328  *	00 - default, created by FW
329  *	01..0f - WiFi ports, driver to create
330  *	10..fe - debug
331  *	ff - broadcast
332  * @id: command/event ID
333  * @timestamp: FW fills for events, free-running msec timer
334  */
335 struct wil6210_mbox_hdr_wmi {
336 	u8 mid;
337 	u8 reserved;
338 	__le16 id;
339 	__le32 timestamp;
340 } __packed;
341 
342 struct pending_wmi_event {
343 	struct list_head list;
344 	struct {
345 		struct wil6210_mbox_hdr hdr;
346 		struct wil6210_mbox_hdr_wmi wmi;
347 		u8 data[0];
348 	} __packed event;
349 };
350 
351 enum { /* for wil_ctx.mapped_as */
352 	wil_mapped_as_none = 0,
353 	wil_mapped_as_single = 1,
354 	wil_mapped_as_page = 2,
355 };
356 
357 /**
358  * struct wil_ctx - software context for Vring descriptor
359  */
360 struct wil_ctx {
361 	struct sk_buff *skb;
362 	u8 nr_frags;
363 	u8 mapped_as;
364 };
365 
366 union vring_desc;
367 
368 struct vring {
369 	dma_addr_t pa;
370 	volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */
371 	u16 size; /* number of vring_desc elements */
372 	u32 swtail;
373 	u32 swhead;
374 	u32 hwtail; /* write here to inform hw */
375 	struct wil_ctx *ctx; /* ctx[size] - software context */
376 };
377 
378 /**
379  * Additional data for Tx Vring
380  */
381 struct vring_tx_data {
382 	int enabled;
383 	cycles_t idle, last_idle, begin;
384 	u8 agg_wsize; /* agreed aggregation window, 0 - no agg */
385 	u16 agg_timeout;
386 	u8 agg_amsdu;
387 	bool addba_in_progress; /* if set, agg_xxx is for request in progress */
388 	spinlock_t lock;
389 };
390 
391 enum { /* for wil6210_priv.status */
392 	wil_status_fwready = 0,
393 	wil_status_fwconnecting,
394 	wil_status_fwconnected,
395 	wil_status_dontscan,
396 	wil_status_reset_done,
397 	wil_status_irqen, /* FIXME: interrupts enabled - for debug */
398 	wil_status_napi_en, /* NAPI enabled protected by wil->mutex */
399 	wil_status_last /* keep last */
400 };
401 
402 struct pci_dev;
403 
404 /**
405  * struct tid_ampdu_rx - TID aggregation information (Rx).
406  *
407  * @reorder_buf: buffer to reorder incoming aggregated MPDUs
408  * @reorder_time: jiffies when skb was added
409  * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value)
410  * @reorder_timer: releases expired frames from the reorder buffer.
411  * @last_rx: jiffies of last rx activity
412  * @head_seq_num: head sequence number in reordering buffer.
413  * @stored_mpdu_num: number of MPDUs in reordering buffer
414  * @ssn: Starting Sequence Number expected to be aggregated.
415  * @buf_size: buffer size for incoming A-MPDUs
416  * @timeout: reset timer value (in TUs).
417  * @dialog_token: dialog token for aggregation session
418  * @rcu_head: RCU head used for freeing this struct
419  *
420  * This structure's lifetime is managed by RCU, assignments to
421  * the array holding it must hold the aggregation mutex.
422  *
423  */
424 struct wil_tid_ampdu_rx {
425 	struct sk_buff **reorder_buf;
426 	unsigned long *reorder_time;
427 	struct timer_list session_timer;
428 	struct timer_list reorder_timer;
429 	unsigned long last_rx;
430 	u16 head_seq_num;
431 	u16 stored_mpdu_num;
432 	u16 ssn;
433 	u16 buf_size;
434 	u16 timeout;
435 	u16 ssn_last_drop;
436 	u8 dialog_token;
437 	bool first_time; /* is it 1-st time this buffer used? */
438 };
439 
440 enum wil_sta_status {
441 	wil_sta_unused = 0,
442 	wil_sta_conn_pending = 1,
443 	wil_sta_connected = 2,
444 };
445 
446 #define WIL_STA_TID_NUM (16)
447 
448 struct wil_net_stats {
449 	unsigned long	rx_packets;
450 	unsigned long	tx_packets;
451 	unsigned long	rx_bytes;
452 	unsigned long	tx_bytes;
453 	unsigned long	tx_errors;
454 	unsigned long	rx_dropped;
455 	u16 last_mcs_rx;
456 };
457 
458 /**
459  * struct wil_sta_info - data for peer
460  *
461  * Peer identified by its CID (connection ID)
462  * NIC performs beam forming for each peer;
463  * if no beam forming done, frame exchange is not
464  * possible.
465  */
466 struct wil_sta_info {
467 	u8 addr[ETH_ALEN];
468 	enum wil_sta_status status;
469 	struct wil_net_stats stats;
470 	bool data_port_open; /* can send any data, not only EAPOL */
471 	/* Rx BACK */
472 	struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM];
473 	spinlock_t tid_rx_lock; /* guarding tid_rx array */
474 	unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)];
475 	unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)];
476 };
477 
478 enum {
479 	fw_recovery_idle = 0,
480 	fw_recovery_pending = 1,
481 	fw_recovery_running = 2,
482 };
483 
484 enum {
485 	hw_capability_reset_v2 = 0,
486 	hw_capability_advanced_itr_moderation = 1,
487 	hw_capability_last
488 };
489 
490 struct wil_back_rx {
491 	struct list_head list;
492 	/* request params, converted to CPU byte order - what we asked for */
493 	u8 cidxtid;
494 	u8 dialog_token;
495 	u16 ba_param_set;
496 	u16 ba_timeout;
497 	u16 ba_seq_ctrl;
498 };
499 
500 struct wil_back_tx {
501 	struct list_head list;
502 	/* request params, converted to CPU byte order - what we asked for */
503 	u8 ringid;
504 	u8 agg_wsize;
505 	u16 agg_timeout;
506 };
507 
508 struct wil_probe_client_req {
509 	struct list_head list;
510 	u64 cookie;
511 	u8 cid;
512 };
513 
514 struct wil6210_priv {
515 	struct pci_dev *pdev;
516 	int n_msi;
517 	struct wireless_dev *wdev;
518 	void __iomem *csr;
519 	DECLARE_BITMAP(status, wil_status_last);
520 	u32 fw_version;
521 	u32 hw_version;
522 	const char *hw_name;
523 	DECLARE_BITMAP(hw_capabilities, hw_capability_last);
524 	u8 n_mids; /* number of additional MIDs as reported by FW */
525 	u32 recovery_count; /* num of FW recovery attempts in a short time */
526 	u32 recovery_state; /* FW recovery state machine */
527 	unsigned long last_fw_recovery; /* jiffies of last fw recovery */
528 	wait_queue_head_t wq; /* for all wait_event() use */
529 	/* profile */
530 	u32 monitor_flags;
531 	u32 secure_pcp; /* create secure PCP? */
532 	int sinfo_gen;
533 	/* interrupt moderation */
534 	u32 tx_max_burst_duration;
535 	u32 tx_interframe_timeout;
536 	u32 rx_max_burst_duration;
537 	u32 rx_interframe_timeout;
538 	/* cached ISR registers */
539 	u32 isr_misc;
540 	/* mailbox related */
541 	struct mutex wmi_mutex;
542 	struct wil6210_mbox_ctl mbox_ctl;
543 	struct completion wmi_ready;
544 	struct completion wmi_call;
545 	u16 wmi_seq;
546 	u16 reply_id; /**< wait for this WMI event */
547 	void *reply_buf;
548 	u16 reply_size;
549 	struct workqueue_struct *wmi_wq; /* for deferred calls */
550 	struct work_struct wmi_event_worker;
551 	struct workqueue_struct *wq_service;
552 	struct work_struct connect_worker;
553 	struct work_struct disconnect_worker;
554 	struct work_struct fw_error_worker;	/* for FW error recovery */
555 	struct timer_list connect_timer;
556 	struct timer_list scan_timer; /* detect scan timeout */
557 	int pending_connect_cid;
558 	struct list_head pending_wmi_ev;
559 	/*
560 	 * protect pending_wmi_ev
561 	 * - fill in IRQ from wil6210_irq_misc,
562 	 * - consumed in thread by wmi_event_worker
563 	 */
564 	spinlock_t wmi_ev_lock;
565 	struct napi_struct napi_rx;
566 	struct napi_struct napi_tx;
567 	/* BACK */
568 	struct list_head back_rx_pending;
569 	struct mutex back_rx_mutex; /* protect @back_rx_pending */
570 	struct work_struct back_rx_worker;
571 	struct list_head back_tx_pending;
572 	struct mutex back_tx_mutex; /* protect @back_tx_pending */
573 	struct work_struct back_tx_worker;
574 	/* keep alive */
575 	struct list_head probe_client_pending;
576 	struct mutex probe_client_mutex; /* protect @probe_client_pending */
577 	struct work_struct probe_client_worker;
578 	/* DMA related */
579 	struct vring vring_rx;
580 	struct vring vring_tx[WIL6210_MAX_TX_RINGS];
581 	struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS];
582 	u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */
583 	struct wil_sta_info sta[WIL6210_MAX_CID];
584 	/* scan */
585 	struct cfg80211_scan_request *scan_request;
586 
587 	struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
588 	/* statistics */
589 	atomic_t isr_count_rx, isr_count_tx;
590 	/* debugfs */
591 	struct dentry *debug;
592 	struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)];
593 
594 	void *platform_handle;
595 	struct wil_platform_ops platform_ops;
596 };
597 
598 #define wil_to_wiphy(i) (i->wdev->wiphy)
599 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
600 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
601 #define wil_to_wdev(i) (i->wdev)
602 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
603 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
604 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
605 
606 __printf(2, 3)
607 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...);
608 __printf(2, 3)
609 void wil_err(struct wil6210_priv *wil, const char *fmt, ...);
610 __printf(2, 3)
611 void wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...);
612 __printf(2, 3)
613 void wil_info(struct wil6210_priv *wil, const char *fmt, ...);
614 #define wil_dbg(wil, fmt, arg...) do { \
615 	netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \
616 	wil_dbg_trace(wil, fmt, ##arg); \
617 } while (0)
618 
619 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
620 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
621 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
622 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
623 
624 #if defined(CONFIG_DYNAMIC_DEBUG)
625 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize,	\
626 			  groupsize, buf, len, ascii)		\
627 			  print_hex_dump_debug("DBG[TXRX]" prefix_str,\
628 					 prefix_type, rowsize,	\
629 					 groupsize, buf, len, ascii)
630 
631 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize,	\
632 			 groupsize, buf, len, ascii)		\
633 			 print_hex_dump_debug("DBG[ WMI]" prefix_str,\
634 					prefix_type, rowsize,	\
635 					groupsize, buf, len, ascii)
636 #else /* defined(CONFIG_DYNAMIC_DEBUG) */
637 static inline
638 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize,
639 		       int groupsize, const void *buf, size_t len, bool ascii)
640 {
641 }
642 
643 static inline
644 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize,
645 		      int groupsize, const void *buf, size_t len, bool ascii)
646 {
647 }
648 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */
649 
650 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
651 			  size_t count);
652 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
653 			size_t count);
654 
655 void *wil_if_alloc(struct device *dev, void __iomem *csr);
656 void wil_if_free(struct wil6210_priv *wil);
657 int wil_if_add(struct wil6210_priv *wil);
658 void wil_if_remove(struct wil6210_priv *wil);
659 int wil_priv_init(struct wil6210_priv *wil);
660 void wil_priv_deinit(struct wil6210_priv *wil);
661 int wil_reset(struct wil6210_priv *wil);
662 void wil_fw_error_recovery(struct wil6210_priv *wil);
663 void wil_set_recovery_state(struct wil6210_priv *wil, int state);
664 int wil_up(struct wil6210_priv *wil);
665 int __wil_up(struct wil6210_priv *wil);
666 int wil_down(struct wil6210_priv *wil);
667 int __wil_down(struct wil6210_priv *wil);
668 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
669 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac);
670 void wil_set_ethtoolops(struct net_device *ndev);
671 
672 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
673 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
674 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
675 		 struct wil6210_mbox_hdr *hdr);
676 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len);
677 void wmi_recv_cmd(struct wil6210_priv *wil);
678 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
679 	     u16 reply_id, void *reply, u8 reply_size, int to_msec);
680 void wmi_event_worker(struct work_struct *work);
681 void wmi_event_flush(struct wil6210_priv *wil);
682 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid);
683 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid);
684 int wmi_set_channel(struct wil6210_priv *wil, int channel);
685 int wmi_get_channel(struct wil6210_priv *wil, int *channel);
686 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index,
687 		       const void *mac_addr);
688 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index,
689 		       const void *mac_addr, int key_len, const void *key);
690 int wmi_echo(struct wil6210_priv *wil);
691 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie);
692 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring);
693 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel);
694 int wmi_rxon(struct wil6210_priv *wil, bool on);
695 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r);
696 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason);
697 int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout);
698 int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason);
699 int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason);
700 int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token,
701 		      u16 status, bool amsdu, u16 agg_wsize, u16 timeout);
702 int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid,
703 			 u8 dialog_token, __le16 ba_param_set,
704 			 __le16 ba_timeout, __le16 ba_seq_ctrl);
705 void wil_back_rx_worker(struct work_struct *work);
706 void wil_back_rx_flush(struct wil6210_priv *wil);
707 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize);
708 void wil_back_tx_worker(struct work_struct *work);
709 void wil_back_tx_flush(struct wil6210_priv *wil);
710 
711 void wil6210_clear_irq(struct wil6210_priv *wil);
712 int wil6210_init_irq(struct wil6210_priv *wil, int irq);
713 void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
714 void wil_mask_irq(struct wil6210_priv *wil);
715 void wil_unmask_irq(struct wil6210_priv *wil);
716 void wil_configure_interrupt_moderation(struct wil6210_priv *wil);
717 void wil_disable_irq(struct wil6210_priv *wil);
718 void wil_enable_irq(struct wil6210_priv *wil);
719 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
720 			 struct cfg80211_mgmt_tx_params *params,
721 			 u64 *cookie);
722 
723 int wil6210_debugfs_init(struct wil6210_priv *wil);
724 void wil6210_debugfs_remove(struct wil6210_priv *wil);
725 int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid,
726 		       struct station_info *sinfo);
727 
728 struct wireless_dev *wil_cfg80211_init(struct device *dev);
729 void wil_wdev_free(struct wil6210_priv *wil);
730 
731 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr);
732 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan);
733 int wmi_pcp_stop(struct wil6210_priv *wil);
734 void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid,
735 			u16 reason_code, bool from_event);
736 void wil_probe_client_flush(struct wil6210_priv *wil);
737 void wil_probe_client_worker(struct work_struct *work);
738 
739 int wil_rx_init(struct wil6210_priv *wil, u16 size);
740 void wil_rx_fini(struct wil6210_priv *wil);
741 
742 /* TX API */
743 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
744 		      int cid, int tid);
745 void wil_vring_fini_tx(struct wil6210_priv *wil, int id);
746 
747 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
748 int wil_tx_complete(struct wil6210_priv *wil, int ringid);
749 void wil6210_unmask_irq_tx(struct wil6210_priv *wil);
750 
751 /* RX API */
752 void wil_rx_handle(struct wil6210_priv *wil, int *quota);
753 void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
754 
755 int wil_iftype_nl2wmi(enum nl80211_iftype type);
756 
757 int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd);
758 int wil_request_firmware(struct wil6210_priv *wil, const char *name);
759 
760 #endif /* __WIL6210_H__ */
761