1 /* 2 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __WIL6210_H__ 18 #define __WIL6210_H__ 19 20 #include <linux/netdevice.h> 21 #include <linux/wireless.h> 22 #include <net/cfg80211.h> 23 #include <linux/timex.h> 24 #include <linux/types.h> 25 #include "wmi.h" 26 #include "wil_platform.h" 27 28 extern bool no_fw_recovery; 29 extern unsigned int mtu_max; 30 extern unsigned short rx_ring_overflow_thrsh; 31 extern int agg_wsize; 32 extern u32 vring_idle_trsh; 33 extern bool rx_align_2; 34 extern bool debug_fw; 35 36 #define WIL_NAME "wil6210" 37 #define WIL_FW_NAME "wil6210.fw" /* code */ 38 #define WIL_FW2_NAME "wil6210.brd" /* board & radio parameters */ 39 40 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 41 42 /** 43 * extract bits [@b0:@b1] (inclusive) from the value @x 44 * it should be @b0 <= @b1, or result is incorrect 45 */ 46 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 47 { 48 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 49 } 50 51 #define WIL6210_MEM_SIZE (2*1024*1024UL) 52 53 #define WIL_TX_Q_LEN_DEFAULT (4000) 54 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 55 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 56 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 57 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 58 /* limit ring size in range [32..32k] */ 59 #define WIL_RING_SIZE_ORDER_MIN (5) 60 #define WIL_RING_SIZE_ORDER_MAX (15) 61 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 62 #define WIL6210_MAX_CID (8) /* HW limit */ 63 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 64 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 65 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 66 /* Hardware offload block adds the following: 67 * 26 bytes - 3-address QoS data header 68 * 8 bytes - IV + EIV (for GCMP) 69 * 8 bytes - SNAP 70 * 16 bytes - MIC (for GCMP) 71 * 4 bytes - CRC 72 */ 73 #define WIL_MAX_MPDU_OVERHEAD (62) 74 75 /* Calculate MAC buffer size for the firmware. It includes all overhead, 76 * as it will go over the air, and need to be 8 byte aligned 77 */ 78 static inline u32 wil_mtu2macbuf(u32 mtu) 79 { 80 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 81 } 82 83 /* MTU for Ethernet need to take into account 8-byte SNAP header 84 * to be added when encapsulating Ethernet frame into 802.11 85 */ 86 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 87 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 88 #define WIL6210_ITR_TRSH_MAX (5000000) 89 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 90 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 91 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 92 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 93 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 94 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 95 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 96 #define WIL6210_DISCONNECT_TO_MS (2000) 97 #define WIL6210_RX_HIGH_TRSH_INIT (0) 98 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 99 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 100 /* Hardware definitions begin */ 101 102 /* 103 * Mapping 104 * RGF File | Host addr | FW addr 105 * | | 106 * user_rgf | 0x000000 | 0x880000 107 * dma_rgf | 0x001000 | 0x881000 108 * pcie_rgf | 0x002000 | 0x882000 109 * | | 110 */ 111 112 /* Where various structures placed in host address space */ 113 #define WIL6210_FW_HOST_OFF (0x880000UL) 114 115 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 116 117 /* 118 * Interrupt control registers block 119 * 120 * each interrupt controlled by the same bit in all registers 121 */ 122 struct RGF_ICR { 123 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 124 u32 ICR; /* Cause, W1C/COR depending on ICC */ 125 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 126 u32 ICS; /* Cause Set, WO */ 127 u32 IMV; /* Mask, RW+S/C */ 128 u32 IMS; /* Mask Set, write 1 to set */ 129 u32 IMC; /* Mask Clear, write 1 to clear */ 130 } __packed; 131 132 /* registers - FW addresses */ 133 #define RGF_USER_USAGE_1 (0x880004) 134 #define RGF_USER_USAGE_6 (0x880018) 135 #define BIT_USER_OOB_MODE BIT(31) 136 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 137 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 138 #define RGF_USER_USER_CPU_0 (0x8801e0) 139 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 140 #define RGF_USER_MAC_CPU_0 (0x8801fc) 141 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 142 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 143 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 144 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 145 #define RGF_USER_CLKS_CTL_0 (0x880abc) 146 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 147 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 148 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 149 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 150 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 151 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 152 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 153 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 154 #define BIT_CAR_PERST_RST BIT(7) 155 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 156 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 157 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 158 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 159 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 160 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 161 162 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 163 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 164 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 165 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 166 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 167 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 168 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 169 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 170 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 171 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 172 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 173 174 /* Legacy interrupt moderation control (before Sparrow v2)*/ 175 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 176 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 177 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 178 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 179 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 180 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 181 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 182 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 183 184 /* Offload control (Sparrow B0+) */ 185 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 186 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 187 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 188 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 189 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 190 191 /* New (sparrow v2+) interrupt moderation control */ 192 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 193 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 194 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 195 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 196 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 197 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 198 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 199 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 200 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 201 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 202 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 203 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 204 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 205 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 206 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 207 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 208 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 209 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 210 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 211 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 212 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 213 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 214 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 215 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 216 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 217 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 218 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 219 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 220 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 221 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 222 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 223 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 224 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 225 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 226 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 227 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 228 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 229 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 230 231 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 232 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 233 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 234 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 235 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 236 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 237 238 #define RGF_HP_CTRL (0x88265c) 239 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 240 241 /* MAC timer, usec, for packet lifetime */ 242 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 243 244 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 245 #define RGF_CAF_OSC_CONTROL (0x88afa4) 246 #define BIT_CAF_OSC_XTAL_EN BIT(0) 247 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 248 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 249 250 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 251 #define JTAG_DEV_ID_SPARROW_B0 (0x2632072f) 252 253 /* crash codes for FW/Ucode stored here */ 254 #define RGF_FW_ASSERT_CODE (0x91f020) 255 #define RGF_UCODE_ASSERT_CODE (0x91f028) 256 257 enum { 258 HW_VER_UNKNOWN, 259 HW_VER_SPARROW_B0, /* JTAG_DEV_ID_SPARROW_B0 */ 260 }; 261 262 /* popular locations */ 263 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 264 #define HOST_MBOX HOSTADDR(RGF_MBOX) 265 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 266 267 /* ISR register bits */ 268 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 269 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 270 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 271 272 /* Hardware definitions end */ 273 struct fw_map { 274 u32 from; /* linker address - from, inclusive */ 275 u32 to; /* linker address - to, exclusive */ 276 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 277 const char *name; /* for debugfs */ 278 }; 279 280 /* array size should be in sync with actual definition in the wmi.c */ 281 extern const struct fw_map fw_mapping[8]; 282 283 /** 284 * mk_cidxtid - construct @cidxtid field 285 * @cid: CID value 286 * @tid: TID value 287 * 288 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 289 */ 290 static inline u8 mk_cidxtid(u8 cid, u8 tid) 291 { 292 return ((tid & 0xf) << 4) | (cid & 0xf); 293 } 294 295 /** 296 * parse_cidxtid - parse @cidxtid field 297 * @cid: store CID value here 298 * @tid: store TID value here 299 * 300 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 301 */ 302 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 303 { 304 *cid = cidxtid & 0xf; 305 *tid = (cidxtid >> 4) & 0xf; 306 } 307 308 struct wil6210_mbox_ring { 309 u32 base; 310 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 311 u16 size; 312 u32 tail; 313 u32 head; 314 } __packed; 315 316 struct wil6210_mbox_ring_desc { 317 __le32 sync; 318 __le32 addr; 319 } __packed; 320 321 /* at HOST_OFF_WIL6210_MBOX_CTL */ 322 struct wil6210_mbox_ctl { 323 struct wil6210_mbox_ring tx; 324 struct wil6210_mbox_ring rx; 325 } __packed; 326 327 struct wil6210_mbox_hdr { 328 __le16 seq; 329 __le16 len; /* payload, bytes after this header */ 330 __le16 type; 331 u8 flags; 332 u8 reserved; 333 } __packed; 334 335 #define WIL_MBOX_HDR_TYPE_WMI (0) 336 337 /* max. value for wil6210_mbox_hdr.len */ 338 #define MAX_MBOXITEM_SIZE (240) 339 340 struct pending_wmi_event { 341 struct list_head list; 342 struct { 343 struct wil6210_mbox_hdr hdr; 344 struct wmi_cmd_hdr wmi; 345 u8 data[0]; 346 } __packed event; 347 }; 348 349 enum { /* for wil_ctx.mapped_as */ 350 wil_mapped_as_none = 0, 351 wil_mapped_as_single = 1, 352 wil_mapped_as_page = 2, 353 }; 354 355 /** 356 * struct wil_ctx - software context for Vring descriptor 357 */ 358 struct wil_ctx { 359 struct sk_buff *skb; 360 u8 nr_frags; 361 u8 mapped_as; 362 }; 363 364 union vring_desc; 365 366 struct vring { 367 dma_addr_t pa; 368 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */ 369 u16 size; /* number of vring_desc elements */ 370 u32 swtail; 371 u32 swhead; 372 u32 hwtail; /* write here to inform hw */ 373 struct wil_ctx *ctx; /* ctx[size] - software context */ 374 }; 375 376 /** 377 * Additional data for Tx Vring 378 */ 379 struct vring_tx_data { 380 bool dot1x_open; 381 int enabled; 382 cycles_t idle, last_idle, begin; 383 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 384 u16 agg_timeout; 385 u8 agg_amsdu; 386 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 387 spinlock_t lock; 388 }; 389 390 enum { /* for wil6210_priv.status */ 391 wil_status_fwready = 0, /* FW operational */ 392 wil_status_fwconnecting, 393 wil_status_fwconnected, 394 wil_status_dontscan, 395 wil_status_mbox_ready, /* MBOX structures ready */ 396 wil_status_irqen, /* FIXME: interrupts enabled - for debug */ 397 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 398 wil_status_resetting, /* reset in progress */ 399 wil_status_last /* keep last */ 400 }; 401 402 struct pci_dev; 403 404 /** 405 * struct tid_ampdu_rx - TID aggregation information (Rx). 406 * 407 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 408 * @reorder_time: jiffies when skb was added 409 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value) 410 * @reorder_timer: releases expired frames from the reorder buffer. 411 * @last_rx: jiffies of last rx activity 412 * @head_seq_num: head sequence number in reordering buffer. 413 * @stored_mpdu_num: number of MPDUs in reordering buffer 414 * @ssn: Starting Sequence Number expected to be aggregated. 415 * @buf_size: buffer size for incoming A-MPDUs 416 * @timeout: reset timer value (in TUs). 417 * @ssn_last_drop: SSN of the last dropped frame 418 * @total: total number of processed incoming frames 419 * @drop_dup: duplicate frames dropped for this reorder buffer 420 * @drop_old: old frames dropped for this reorder buffer 421 * @dialog_token: dialog token for aggregation session 422 * @first_time: true when this buffer used 1-st time 423 */ 424 struct wil_tid_ampdu_rx { 425 struct sk_buff **reorder_buf; 426 unsigned long *reorder_time; 427 struct timer_list session_timer; 428 struct timer_list reorder_timer; 429 unsigned long last_rx; 430 u16 head_seq_num; 431 u16 stored_mpdu_num; 432 u16 ssn; 433 u16 buf_size; 434 u16 timeout; 435 u16 ssn_last_drop; 436 unsigned long long total; /* frames processed */ 437 unsigned long long drop_dup; 438 unsigned long long drop_old; 439 u8 dialog_token; 440 bool first_time; /* is it 1-st time this buffer used? */ 441 }; 442 443 /** 444 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 445 * 446 * @pn: GCMP PN for the session 447 * @key_set: valid key present 448 */ 449 struct wil_tid_crypto_rx_single { 450 u8 pn[IEEE80211_GCMP_PN_LEN]; 451 bool key_set; 452 }; 453 454 struct wil_tid_crypto_rx { 455 struct wil_tid_crypto_rx_single key_id[4]; 456 }; 457 458 struct wil_p2p_info { 459 struct ieee80211_channel listen_chan; 460 u8 discovery_started; 461 u64 cookie; 462 struct timer_list discovery_timer; /* listen/search duration */ 463 struct work_struct discovery_expired_work; /* listen/search expire */ 464 }; 465 466 enum wil_sta_status { 467 wil_sta_unused = 0, 468 wil_sta_conn_pending = 1, 469 wil_sta_connected = 2, 470 }; 471 472 #define WIL_STA_TID_NUM (16) 473 #define WIL_MCS_MAX (12) /* Maximum MCS supported */ 474 475 struct wil_net_stats { 476 unsigned long rx_packets; 477 unsigned long tx_packets; 478 unsigned long rx_bytes; 479 unsigned long tx_bytes; 480 unsigned long tx_errors; 481 unsigned long rx_dropped; 482 unsigned long rx_non_data_frame; 483 unsigned long rx_short_frame; 484 unsigned long rx_large_frame; 485 unsigned long rx_replay; 486 u16 last_mcs_rx; 487 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 488 }; 489 490 /** 491 * struct wil_sta_info - data for peer 492 * 493 * Peer identified by its CID (connection ID) 494 * NIC performs beam forming for each peer; 495 * if no beam forming done, frame exchange is not 496 * possible. 497 */ 498 struct wil_sta_info { 499 u8 addr[ETH_ALEN]; 500 enum wil_sta_status status; 501 struct wil_net_stats stats; 502 /* Rx BACK */ 503 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 504 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 505 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 506 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 507 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 508 struct wil_tid_crypto_rx group_crypto_rx; 509 }; 510 511 enum { 512 fw_recovery_idle = 0, 513 fw_recovery_pending = 1, 514 fw_recovery_running = 2, 515 }; 516 517 enum { 518 hw_capability_last 519 }; 520 521 struct wil_probe_client_req { 522 struct list_head list; 523 u64 cookie; 524 u8 cid; 525 }; 526 527 struct pmc_ctx { 528 /* alloc, free, and read operations must own the lock */ 529 struct mutex lock; 530 struct vring_tx_desc *pring_va; 531 dma_addr_t pring_pa; 532 struct desc_alloc_info *descriptors; 533 int last_cmd_status; 534 int num_descriptors; 535 int descriptor_size; 536 }; 537 538 struct wil_halp { 539 struct mutex lock; /* protect halp ref_cnt */ 540 unsigned int ref_cnt; 541 struct completion comp; 542 }; 543 544 struct wil_blob_wrapper { 545 struct wil6210_priv *wil; 546 struct debugfs_blob_wrapper blob; 547 }; 548 549 #define WIL_LED_MAX_ID (2) 550 #define WIL_LED_INVALID_ID (0xF) 551 #define WIL_LED_BLINK_ON_SLOW_MS (300) 552 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 553 #define WIL_LED_BLINK_ON_MED_MS (200) 554 #define WIL_LED_BLINK_OFF_MED_MS (200) 555 #define WIL_LED_BLINK_ON_FAST_MS (100) 556 #define WIL_LED_BLINK_OFF_FAST_MS (100) 557 enum { 558 WIL_LED_TIME_SLOW = 0, 559 WIL_LED_TIME_MED, 560 WIL_LED_TIME_FAST, 561 WIL_LED_TIME_LAST, 562 }; 563 564 struct blink_on_off_time { 565 u32 on_ms; 566 u32 off_ms; 567 }; 568 569 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 570 extern u8 led_id; 571 extern u8 led_polarity; 572 573 struct wil6210_priv { 574 struct pci_dev *pdev; 575 struct wireless_dev *wdev; 576 void __iomem *csr; 577 DECLARE_BITMAP(status, wil_status_last); 578 u32 fw_version; 579 u32 hw_version; 580 const char *hw_name; 581 DECLARE_BITMAP(hw_capabilities, hw_capability_last); 582 u8 n_mids; /* number of additional MIDs as reported by FW */ 583 u32 recovery_count; /* num of FW recovery attempts in a short time */ 584 u32 recovery_state; /* FW recovery state machine */ 585 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 586 wait_queue_head_t wq; /* for all wait_event() use */ 587 /* profile */ 588 u32 monitor_flags; 589 u32 privacy; /* secure connection? */ 590 u8 hidden_ssid; /* relevant in AP mode */ 591 u16 channel; /* relevant in AP mode */ 592 int sinfo_gen; 593 u32 ap_isolate; /* no intra-BSS communication */ 594 /* interrupt moderation */ 595 u32 tx_max_burst_duration; 596 u32 tx_interframe_timeout; 597 u32 rx_max_burst_duration; 598 u32 rx_interframe_timeout; 599 /* cached ISR registers */ 600 u32 isr_misc; 601 /* mailbox related */ 602 struct mutex wmi_mutex; 603 struct wil6210_mbox_ctl mbox_ctl; 604 struct completion wmi_ready; 605 struct completion wmi_call; 606 u16 wmi_seq; 607 u16 reply_id; /**< wait for this WMI event */ 608 void *reply_buf; 609 u16 reply_size; 610 struct workqueue_struct *wmi_wq; /* for deferred calls */ 611 struct work_struct wmi_event_worker; 612 struct workqueue_struct *wq_service; 613 struct work_struct disconnect_worker; 614 struct work_struct fw_error_worker; /* for FW error recovery */ 615 struct timer_list connect_timer; 616 struct timer_list scan_timer; /* detect scan timeout */ 617 struct list_head pending_wmi_ev; 618 /* 619 * protect pending_wmi_ev 620 * - fill in IRQ from wil6210_irq_misc, 621 * - consumed in thread by wmi_event_worker 622 */ 623 spinlock_t wmi_ev_lock; 624 struct napi_struct napi_rx; 625 struct napi_struct napi_tx; 626 /* keep alive */ 627 struct list_head probe_client_pending; 628 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 629 struct work_struct probe_client_worker; 630 /* DMA related */ 631 struct vring vring_rx; 632 struct vring vring_tx[WIL6210_MAX_TX_RINGS]; 633 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS]; 634 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 635 struct wil_sta_info sta[WIL6210_MAX_CID]; 636 int bcast_vring; 637 /* scan */ 638 struct cfg80211_scan_request *scan_request; 639 640 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 641 /* statistics */ 642 atomic_t isr_count_rx, isr_count_tx; 643 /* debugfs */ 644 struct dentry *debug; 645 struct wil_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)]; 646 u8 discovery_mode; 647 648 void *platform_handle; 649 struct wil_platform_ops platform_ops; 650 651 struct pmc_ctx pmc; 652 653 bool pbss; 654 655 struct wil_p2p_info p2p; 656 657 /* P2P_DEVICE vif */ 658 struct wireless_dev *p2p_wdev; 659 struct mutex p2p_wdev_mutex; /* protect @p2p_wdev */ 660 struct wireless_dev *radio_wdev; 661 662 /* High Access Latency Policy voting */ 663 struct wil_halp halp; 664 665 }; 666 667 #define wil_to_wiphy(i) (i->wdev->wiphy) 668 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 669 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 670 #define wil_to_wdev(i) (i->wdev) 671 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 672 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev) 673 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 674 675 __printf(2, 3) 676 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 677 __printf(2, 3) 678 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 679 __printf(2, 3) 680 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 681 __printf(2, 3) 682 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 683 __printf(2, 3) 684 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 685 #define wil_dbg(wil, fmt, arg...) do { \ 686 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \ 687 wil_dbg_trace(wil, fmt, ##arg); \ 688 } while (0) 689 690 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 691 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 692 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 693 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 694 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 695 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 696 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 697 #define wil_err_ratelimited(wil, fmt, arg...) \ 698 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 699 700 /* target operations */ 701 /* register read */ 702 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 703 { 704 return readl(wil->csr + HOSTADDR(reg)); 705 } 706 707 /* register write. wmb() to make sure it is completed */ 708 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 709 { 710 writel(val, wil->csr + HOSTADDR(reg)); 711 wmb(); /* wait for write to propagate to the HW */ 712 } 713 714 /* register set = read, OR, write */ 715 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 716 { 717 wil_w(wil, reg, wil_r(wil, reg) | val); 718 } 719 720 /* register clear = read, AND with inverted, write */ 721 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 722 { 723 wil_w(wil, reg, wil_r(wil, reg) & ~val); 724 } 725 726 #if defined(CONFIG_DYNAMIC_DEBUG) 727 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 728 groupsize, buf, len, ascii) \ 729 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 730 prefix_type, rowsize, \ 731 groupsize, buf, len, ascii) 732 733 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 734 groupsize, buf, len, ascii) \ 735 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 736 prefix_type, rowsize, \ 737 groupsize, buf, len, ascii) 738 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 739 static inline 740 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 741 int groupsize, const void *buf, size_t len, bool ascii) 742 { 743 } 744 745 static inline 746 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 747 int groupsize, const void *buf, size_t len, bool ascii) 748 { 749 } 750 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 751 752 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 753 size_t count); 754 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 755 size_t count); 756 void wil_memcpy_fromio_halp_vote(struct wil6210_priv *wil, void *dst, 757 const volatile void __iomem *src, 758 size_t count); 759 void wil_memcpy_toio_halp_vote(struct wil6210_priv *wil, 760 volatile void __iomem *dst, 761 const void *src, size_t count); 762 763 void *wil_if_alloc(struct device *dev); 764 void wil_if_free(struct wil6210_priv *wil); 765 int wil_if_add(struct wil6210_priv *wil); 766 void wil_if_remove(struct wil6210_priv *wil); 767 int wil_priv_init(struct wil6210_priv *wil); 768 void wil_priv_deinit(struct wil6210_priv *wil); 769 int wil_reset(struct wil6210_priv *wil, bool no_fw); 770 void wil_fw_error_recovery(struct wil6210_priv *wil); 771 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 772 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 773 int wil_up(struct wil6210_priv *wil); 774 int __wil_up(struct wil6210_priv *wil); 775 int wil_down(struct wil6210_priv *wil); 776 int __wil_down(struct wil6210_priv *wil); 777 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 778 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac); 779 void wil_set_ethtoolops(struct net_device *ndev); 780 781 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 782 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 783 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 784 struct wil6210_mbox_hdr *hdr); 785 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len); 786 void wmi_recv_cmd(struct wil6210_priv *wil); 787 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len, 788 u16 reply_id, void *reply, u8 reply_size, int to_msec); 789 void wmi_event_worker(struct work_struct *work); 790 void wmi_event_flush(struct wil6210_priv *wil); 791 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid); 792 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid); 793 int wmi_set_channel(struct wil6210_priv *wil, int channel); 794 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 795 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index, 796 const void *mac_addr, int key_usage); 797 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index, 798 const void *mac_addr, int key_len, const void *key, 799 int key_usage); 800 int wmi_echo(struct wil6210_priv *wil); 801 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie); 802 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring); 803 int wmi_rxon(struct wil6210_priv *wil, bool on); 804 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 805 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason, 806 bool full_disconnect); 807 int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout); 808 int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason); 809 int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason); 810 int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token, 811 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 812 int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid, 813 u8 dialog_token, __le16 ba_param_set, 814 __le16 ba_timeout, __le16 ba_seq_ctrl); 815 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 816 817 void wil6210_clear_irq(struct wil6210_priv *wil); 818 int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi); 819 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 820 void wil_mask_irq(struct wil6210_priv *wil); 821 void wil_unmask_irq(struct wil6210_priv *wil); 822 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 823 void wil_disable_irq(struct wil6210_priv *wil); 824 void wil_enable_irq(struct wil6210_priv *wil); 825 826 /* P2P */ 827 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 828 void wil_p2p_discovery_timer_fn(ulong x); 829 int wil_p2p_search(struct wil6210_priv *wil, 830 struct cfg80211_scan_request *request); 831 int wil_p2p_listen(struct wil6210_priv *wil, unsigned int duration, 832 struct ieee80211_channel *chan, u64 *cookie); 833 u8 wil_p2p_stop_discovery(struct wil6210_priv *wil); 834 int wil_p2p_cancel_listen(struct wil6210_priv *wil, u64 cookie); 835 void wil_p2p_listen_expired(struct work_struct *work); 836 void wil_p2p_search_expired(struct work_struct *work); 837 838 /* WMI for P2P */ 839 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel, int bi); 840 int wmi_start_listen(struct wil6210_priv *wil); 841 int wmi_start_search(struct wil6210_priv *wil); 842 int wmi_stop_discovery(struct wil6210_priv *wil); 843 844 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 845 struct cfg80211_mgmt_tx_params *params, 846 u64 *cookie); 847 848 int wil6210_debugfs_init(struct wil6210_priv *wil); 849 void wil6210_debugfs_remove(struct wil6210_priv *wil); 850 int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid, 851 struct station_info *sinfo); 852 853 struct wireless_dev *wil_cfg80211_init(struct device *dev); 854 void wil_wdev_free(struct wil6210_priv *wil); 855 void wil_p2p_wdev_free(struct wil6210_priv *wil); 856 857 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 858 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, 859 u8 chan, u8 hidden_ssid, u8 is_go); 860 int wmi_pcp_stop(struct wil6210_priv *wil); 861 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 862 void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid, 863 u16 reason_code, bool from_event); 864 void wil_probe_client_flush(struct wil6210_priv *wil); 865 void wil_probe_client_worker(struct work_struct *work); 866 867 int wil_rx_init(struct wil6210_priv *wil, u16 size); 868 void wil_rx_fini(struct wil6210_priv *wil); 869 870 /* TX API */ 871 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size, 872 int cid, int tid); 873 void wil_vring_fini_tx(struct wil6210_priv *wil, int id); 874 int wil_tx_init(struct wil6210_priv *wil, int cid); 875 int wil_vring_init_bcast(struct wil6210_priv *wil, int id, int size); 876 int wil_bcast_init(struct wil6210_priv *wil); 877 void wil_bcast_fini(struct wil6210_priv *wil); 878 879 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 880 int wil_tx_complete(struct wil6210_priv *wil, int ringid); 881 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 882 883 /* RX API */ 884 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 885 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 886 887 int wil_iftype_nl2wmi(enum nl80211_iftype type); 888 889 int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd); 890 int wil_request_firmware(struct wil6210_priv *wil, const char *name); 891 892 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 893 int wil_suspend(struct wil6210_priv *wil, bool is_runtime); 894 int wil_resume(struct wil6210_priv *wil, bool is_runtime); 895 896 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 897 void wil_fw_core_dump(struct wil6210_priv *wil); 898 899 void wil_halp_vote(struct wil6210_priv *wil); 900 void wil_halp_unvote(struct wil6210_priv *wil); 901 void wil6210_set_halp(struct wil6210_priv *wil); 902 void wil6210_clear_halp(struct wil6210_priv *wil); 903 904 #endif /* __WIL6210_H__ */ 905