xref: /linux/drivers/net/wireless/ath/wil6210/wil6210.h (revision 005438a8eef063495ac059d128eea71b58de50e5)
1 /*
2  * Copyright (c) 2012-2015 Qualcomm Atheros, Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef __WIL6210_H__
18 #define __WIL6210_H__
19 
20 #include <linux/netdevice.h>
21 #include <linux/wireless.h>
22 #include <net/cfg80211.h>
23 #include <linux/timex.h>
24 #include <linux/types.h>
25 #include "wil_platform.h"
26 
27 extern bool no_fw_recovery;
28 extern unsigned int mtu_max;
29 extern unsigned short rx_ring_overflow_thrsh;
30 extern int agg_wsize;
31 extern u32 vring_idle_trsh;
32 extern bool rx_align_2;
33 extern bool debug_fw;
34 
35 #define WIL_NAME "wil6210"
36 #define WIL_FW_NAME "wil6210.fw" /* code */
37 #define WIL_FW2_NAME "wil6210.brd" /* board & radio parameters */
38 
39 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */
40 
41 /**
42  * extract bits [@b0:@b1] (inclusive) from the value @x
43  * it should be @b0 <= @b1, or result is incorrect
44  */
45 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
46 {
47 	return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
48 }
49 
50 #define WIL6210_MEM_SIZE (2*1024*1024UL)
51 
52 #define WIL_TX_Q_LEN_DEFAULT		(4000)
53 #define WIL_RX_RING_SIZE_ORDER_DEFAULT	(10)
54 #define WIL_TX_RING_SIZE_ORDER_DEFAULT	(10)
55 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT	(7)
56 #define WIL_BCAST_MCS0_LIMIT		(1024) /* limit for MCS0 frame size */
57 /* limit ring size in range [32..32k] */
58 #define WIL_RING_SIZE_ORDER_MIN	(5)
59 #define WIL_RING_SIZE_ORDER_MAX	(15)
60 #define WIL6210_MAX_TX_RINGS	(24) /* HW limit */
61 #define WIL6210_MAX_CID		(8) /* HW limit */
62 #define WIL6210_NAPI_BUDGET	(16) /* arbitrary */
63 #define WIL_MAX_AMPDU_SIZE	(64 * 1024) /* FW/HW limit */
64 #define WIL_MAX_AGG_WSIZE	(32) /* FW/HW limit */
65 /* Hardware offload block adds the following:
66  * 26 bytes - 3-address QoS data header
67  *  8 bytes - IV + EIV (for GCMP)
68  *  8 bytes - SNAP
69  * 16 bytes - MIC (for GCMP)
70  *  4 bytes - CRC
71  */
72 #define WIL_MAX_MPDU_OVERHEAD	(62)
73 
74 /* Calculate MAC buffer size for the firmware. It includes all overhead,
75  * as it will go over the air, and need to be 8 byte aligned
76  */
77 static inline u32 wil_mtu2macbuf(u32 mtu)
78 {
79 	return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8);
80 }
81 
82 /* MTU for Ethernet need to take into account 8-byte SNAP header
83  * to be added when encapsulating Ethernet frame into 802.11
84  */
85 #define WIL_MAX_ETH_MTU		(IEEE80211_MAX_DATA_LEN_DMG - 8)
86 /* Max supported by wil6210 value for interrupt threshold is 5sec. */
87 #define WIL6210_ITR_TRSH_MAX (5000000)
88 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
89 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
90 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
91 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
92 #define WIL6210_FW_RECOVERY_RETRIES	(5) /* try to recover this many times */
93 #define WIL6210_FW_RECOVERY_TO	msecs_to_jiffies(5000)
94 #define WIL6210_SCAN_TO		msecs_to_jiffies(10000)
95 #define WIL6210_RX_HIGH_TRSH_INIT		(0)
96 #define WIL6210_RX_HIGH_TRSH_DEFAULT \
97 				(1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3))
98 /* Hardware definitions begin */
99 
100 /*
101  * Mapping
102  * RGF File      | Host addr    |  FW addr
103  *               |              |
104  * user_rgf      | 0x000000     | 0x880000
105  *  dma_rgf      | 0x001000     | 0x881000
106  * pcie_rgf      | 0x002000     | 0x882000
107  *               |              |
108  */
109 
110 /* Where various structures placed in host address space */
111 #define WIL6210_FW_HOST_OFF      (0x880000UL)
112 
113 #define HOSTADDR(fwaddr)        (fwaddr - WIL6210_FW_HOST_OFF)
114 
115 /*
116  * Interrupt control registers block
117  *
118  * each interrupt controlled by the same bit in all registers
119  */
120 struct RGF_ICR {
121 	u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
122 	u32 ICR; /* Cause, W1C/COR depending on ICC */
123 	u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
124 	u32 ICS; /* Cause Set, WO */
125 	u32 IMV; /* Mask, RW+S/C */
126 	u32 IMS; /* Mask Set, write 1 to set */
127 	u32 IMC; /* Mask Clear, write 1 to clear */
128 } __packed;
129 
130 struct RGF_BL {
131 	u32 ready;		/* 0x880A3C bit [0] */
132 #define BIT_BL_READY	BIT(0)
133 	u32 version;		/* 0x880A40 version of the BL struct */
134 	u32 rf_type;		/* 0x880A44 ID of the connected RF */
135 	u32 baseband_type;	/* 0x880A48 ID of the baseband */
136 	u8  mac_address[ETH_ALEN]; /* 0x880A4C permanent MAC */
137 	u8 pad[2];
138 } __packed;
139 
140 /* registers - FW addresses */
141 #define RGF_USER_USAGE_1		(0x880004)
142 #define RGF_USER_USAGE_6		(0x880018)
143 #define RGF_USER_HW_MACHINE_STATE	(0x8801dc)
144 	#define HW_MACHINE_BOOT_DONE	(0x3fffffd)
145 #define RGF_USER_USER_CPU_0		(0x8801e0)
146 	#define BIT_USER_USER_CPU_MAN_RST	BIT(1) /* user_cpu_man_rst */
147 #define RGF_USER_MAC_CPU_0		(0x8801fc)
148 	#define BIT_USER_MAC_CPU_MAN_RST	BIT(1) /* mac_cpu_man_rst */
149 #define RGF_USER_USER_SCRATCH_PAD	(0x8802bc)
150 #define RGF_USER_BL			(0x880A3C) /* Boot Loader */
151 #define RGF_USER_FW_REV_ID		(0x880a8c) /* chip revision */
152 #define RGF_USER_CLKS_CTL_0		(0x880abc)
153 	#define BIT_USER_CLKS_CAR_AHB_SW_SEL	BIT(1) /* ref clk/PLL */
154 	#define BIT_USER_CLKS_RST_PWGD	BIT(11) /* reset on "power good" */
155 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0	(0x880b04)
156 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1	(0x880b08)
157 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2	(0x880b0c)
158 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3	(0x880b10)
159 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0	(0x880b14)
160 	#define BIT_HPAL_PERST_FROM_PAD	BIT(6)
161 	#define BIT_CAR_PERST_RST	BIT(7)
162 #define RGF_USER_USER_ICR		(0x880b4c) /* struct RGF_ICR */
163 	#define BIT_USER_USER_ICR_SW_INT_2	BIT(18)
164 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0	(0x880c18)
165 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1	(0x880c2c)
166 #define RGF_USER_SPARROW_M_4			(0x880c50) /* Sparrow */
167 	#define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF	BIT(2)
168 
169 #define RGF_DMA_EP_TX_ICR		(0x881bb4) /* struct RGF_ICR */
170 	#define BIT_DMA_EP_TX_ICR_TX_DONE	BIT(0)
171 	#define BIT_DMA_EP_TX_ICR_TX_DONE_N(n)	BIT(n+1) /* n = [0..23] */
172 #define RGF_DMA_EP_RX_ICR		(0x881bd0) /* struct RGF_ICR */
173 	#define BIT_DMA_EP_RX_ICR_RX_DONE	BIT(0)
174 	#define BIT_DMA_EP_RX_ICR_RX_HTRSH	BIT(1)
175 #define RGF_DMA_EP_MISC_ICR		(0x881bec) /* struct RGF_ICR */
176 	#define BIT_DMA_EP_MISC_ICR_RX_HTRSH	BIT(0)
177 	#define BIT_DMA_EP_MISC_ICR_TX_NO_ACT	BIT(1)
178 	#define BIT_DMA_EP_MISC_ICR_FW_INT(n)	BIT(28+n) /* n = [0..3] */
179 
180 /* Legacy interrupt moderation control (before Sparrow v2)*/
181 #define RGF_DMA_ITR_CNT_TRSH		(0x881c5c)
182 #define RGF_DMA_ITR_CNT_DATA		(0x881c60)
183 #define RGF_DMA_ITR_CNT_CRL		(0x881c64)
184 	#define BIT_DMA_ITR_CNT_CRL_EN		BIT(0)
185 	#define BIT_DMA_ITR_CNT_CRL_EXT_TICK	BIT(1)
186 	#define BIT_DMA_ITR_CNT_CRL_FOREVER	BIT(2)
187 	#define BIT_DMA_ITR_CNT_CRL_CLR		BIT(3)
188 	#define BIT_DMA_ITR_CNT_CRL_REACH_TRSH	BIT(4)
189 
190 /* Offload control (Sparrow B0+) */
191 #define RGF_DMA_OFUL_NID_0		(0x881cd4)
192 	#define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN		BIT(0)
193 	#define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN		BIT(1)
194 	#define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC	BIT(2)
195 	#define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC	BIT(3)
196 
197 /* New (sparrow v2+) interrupt moderation control */
198 #define RGF_DMA_ITR_TX_DESQ_NO_MOD		(0x881d40)
199 #define RGF_DMA_ITR_TX_CNT_TRSH			(0x881d34)
200 #define RGF_DMA_ITR_TX_CNT_DATA			(0x881d38)
201 #define RGF_DMA_ITR_TX_CNT_CTL			(0x881d3c)
202 	#define BIT_DMA_ITR_TX_CNT_CTL_EN		BIT(0)
203 	#define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL	BIT(1)
204 	#define BIT_DMA_ITR_TX_CNT_CTL_FOREVER		BIT(2)
205 	#define BIT_DMA_ITR_TX_CNT_CTL_CLR		BIT(3)
206 	#define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH	BIT(4)
207 	#define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN		BIT(5)
208 	#define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG	BIT(6)
209 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH			(0x881d60)
210 #define RGF_DMA_ITR_TX_IDL_CNT_DATA			(0x881d64)
211 #define RGF_DMA_ITR_TX_IDL_CNT_CTL			(0x881d68)
212 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN			BIT(0)
213 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL		BIT(1)
214 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER		BIT(2)
215 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR			BIT(3)
216 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH	BIT(4)
217 #define RGF_DMA_ITR_RX_DESQ_NO_MOD		(0x881d50)
218 #define RGF_DMA_ITR_RX_CNT_TRSH			(0x881d44)
219 #define RGF_DMA_ITR_RX_CNT_DATA			(0x881d48)
220 #define RGF_DMA_ITR_RX_CNT_CTL			(0x881d4c)
221 	#define BIT_DMA_ITR_RX_CNT_CTL_EN		BIT(0)
222 	#define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL	BIT(1)
223 	#define BIT_DMA_ITR_RX_CNT_CTL_FOREVER		BIT(2)
224 	#define BIT_DMA_ITR_RX_CNT_CTL_CLR		BIT(3)
225 	#define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH	BIT(4)
226 	#define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN		BIT(5)
227 	#define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG	BIT(6)
228 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH			(0x881d54)
229 #define RGF_DMA_ITR_RX_IDL_CNT_DATA			(0x881d58)
230 #define RGF_DMA_ITR_RX_IDL_CNT_CTL			(0x881d5c)
231 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN			BIT(0)
232 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL		BIT(1)
233 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER		BIT(2)
234 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR			BIT(3)
235 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH	BIT(4)
236 
237 #define RGF_DMA_PSEUDO_CAUSE		(0x881c68)
238 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW	(0x881c6c)
239 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW	(0x881c70)
240 	#define BIT_DMA_PSEUDO_CAUSE_RX		BIT(0)
241 	#define BIT_DMA_PSEUDO_CAUSE_TX		BIT(1)
242 	#define BIT_DMA_PSEUDO_CAUSE_MISC	BIT(2)
243 
244 #define RGF_HP_CTRL			(0x88265c)
245 #define RGF_PCIE_LOS_COUNTER_CTL	(0x882dc4)
246 
247 /* MAC timer, usec, for packet lifetime */
248 #define RGF_MAC_MTRL_COUNTER_0		(0x886aa8)
249 
250 #define RGF_CAF_ICR			(0x88946c) /* struct RGF_ICR */
251 #define RGF_CAF_OSC_CONTROL		(0x88afa4)
252 	#define BIT_CAF_OSC_XTAL_EN		BIT(0)
253 #define RGF_CAF_PLL_LOCK_STATUS		(0x88afec)
254 	#define BIT_CAF_OSC_DIG_XTAL_STABLE	BIT(0)
255 
256 #define RGF_USER_JTAG_DEV_ID	(0x880b34) /* device ID */
257 	#define JTAG_DEV_ID_SPARROW_B0	(0x2632072f)
258 
259 enum {
260 	HW_VER_UNKNOWN,
261 	HW_VER_SPARROW_B0, /* JTAG_DEV_ID_SPARROW_B0 */
262 };
263 
264 /* popular locations */
265 #define HOST_MBOX   HOSTADDR(RGF_USER_USER_SCRATCH_PAD)
266 #define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \
267 	offsetof(struct RGF_ICR, ICS))
268 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
269 
270 /* ISR register bits */
271 #define ISR_MISC_FW_READY	BIT_DMA_EP_MISC_ICR_FW_INT(0)
272 #define ISR_MISC_MBOX_EVT	BIT_DMA_EP_MISC_ICR_FW_INT(1)
273 #define ISR_MISC_FW_ERROR	BIT_DMA_EP_MISC_ICR_FW_INT(3)
274 
275 /* Hardware definitions end */
276 struct fw_map {
277 	u32 from; /* linker address - from, inclusive */
278 	u32 to;   /* linker address - to, exclusive */
279 	u32 host; /* PCI/Host address - BAR0 + 0x880000 */
280 	const char *name; /* for debugfs */
281 };
282 
283 /* array size should be in sync with actual definition in the wmi.c */
284 extern const struct fw_map fw_mapping[8];
285 
286 /**
287  * mk_cidxtid - construct @cidxtid field
288  * @cid: CID value
289  * @tid: TID value
290  *
291  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
292  */
293 static inline u8 mk_cidxtid(u8 cid, u8 tid)
294 {
295 	return ((tid & 0xf) << 4) | (cid & 0xf);
296 }
297 
298 /**
299  * parse_cidxtid - parse @cidxtid field
300  * @cid: store CID value here
301  * @tid: store TID value here
302  *
303  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
304  */
305 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid)
306 {
307 	*cid = cidxtid & 0xf;
308 	*tid = (cidxtid >> 4) & 0xf;
309 }
310 
311 struct wil6210_mbox_ring {
312 	u32 base;
313 	u16 entry_size; /* max. size of mbox entry, incl. all headers */
314 	u16 size;
315 	u32 tail;
316 	u32 head;
317 } __packed;
318 
319 struct wil6210_mbox_ring_desc {
320 	__le32 sync;
321 	__le32 addr;
322 } __packed;
323 
324 /* at HOST_OFF_WIL6210_MBOX_CTL */
325 struct wil6210_mbox_ctl {
326 	struct wil6210_mbox_ring tx;
327 	struct wil6210_mbox_ring rx;
328 } __packed;
329 
330 struct wil6210_mbox_hdr {
331 	__le16 seq;
332 	__le16 len; /* payload, bytes after this header */
333 	__le16 type;
334 	u8 flags;
335 	u8 reserved;
336 } __packed;
337 
338 #define WIL_MBOX_HDR_TYPE_WMI (0)
339 
340 /* max. value for wil6210_mbox_hdr.len */
341 #define MAX_MBOXITEM_SIZE   (240)
342 
343 /**
344  * struct wil6210_mbox_hdr_wmi - WMI header
345  *
346  * @mid: MAC ID
347  *	00 - default, created by FW
348  *	01..0f - WiFi ports, driver to create
349  *	10..fe - debug
350  *	ff - broadcast
351  * @id: command/event ID
352  * @timestamp: FW fills for events, free-running msec timer
353  */
354 struct wil6210_mbox_hdr_wmi {
355 	u8 mid;
356 	u8 reserved;
357 	__le16 id;
358 	__le32 timestamp;
359 } __packed;
360 
361 struct pending_wmi_event {
362 	struct list_head list;
363 	struct {
364 		struct wil6210_mbox_hdr hdr;
365 		struct wil6210_mbox_hdr_wmi wmi;
366 		u8 data[0];
367 	} __packed event;
368 };
369 
370 enum { /* for wil_ctx.mapped_as */
371 	wil_mapped_as_none = 0,
372 	wil_mapped_as_single = 1,
373 	wil_mapped_as_page = 2,
374 };
375 
376 /**
377  * struct wil_ctx - software context for Vring descriptor
378  */
379 struct wil_ctx {
380 	struct sk_buff *skb;
381 	u8 nr_frags;
382 	u8 mapped_as;
383 };
384 
385 union vring_desc;
386 
387 struct vring {
388 	dma_addr_t pa;
389 	volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */
390 	u16 size; /* number of vring_desc elements */
391 	u32 swtail;
392 	u32 swhead;
393 	u32 hwtail; /* write here to inform hw */
394 	struct wil_ctx *ctx; /* ctx[size] - software context */
395 };
396 
397 /**
398  * Additional data for Tx Vring
399  */
400 struct vring_tx_data {
401 	bool dot1x_open;
402 	int enabled;
403 	cycles_t idle, last_idle, begin;
404 	u8 agg_wsize; /* agreed aggregation window, 0 - no agg */
405 	u16 agg_timeout;
406 	u8 agg_amsdu;
407 	bool addba_in_progress; /* if set, agg_xxx is for request in progress */
408 	spinlock_t lock;
409 };
410 
411 enum { /* for wil6210_priv.status */
412 	wil_status_fwready = 0,
413 	wil_status_fwconnecting,
414 	wil_status_fwconnected,
415 	wil_status_dontscan,
416 	wil_status_reset_done,
417 	wil_status_irqen, /* FIXME: interrupts enabled - for debug */
418 	wil_status_napi_en, /* NAPI enabled protected by wil->mutex */
419 	wil_status_last /* keep last */
420 };
421 
422 struct pci_dev;
423 
424 /**
425  * struct tid_ampdu_rx - TID aggregation information (Rx).
426  *
427  * @reorder_buf: buffer to reorder incoming aggregated MPDUs
428  * @reorder_time: jiffies when skb was added
429  * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value)
430  * @reorder_timer: releases expired frames from the reorder buffer.
431  * @last_rx: jiffies of last rx activity
432  * @head_seq_num: head sequence number in reordering buffer.
433  * @stored_mpdu_num: number of MPDUs in reordering buffer
434  * @ssn: Starting Sequence Number expected to be aggregated.
435  * @buf_size: buffer size for incoming A-MPDUs
436  * @timeout: reset timer value (in TUs).
437  * @dialog_token: dialog token for aggregation session
438  * @rcu_head: RCU head used for freeing this struct
439  *
440  * This structure's lifetime is managed by RCU, assignments to
441  * the array holding it must hold the aggregation mutex.
442  *
443  */
444 struct wil_tid_ampdu_rx {
445 	struct sk_buff **reorder_buf;
446 	unsigned long *reorder_time;
447 	struct timer_list session_timer;
448 	struct timer_list reorder_timer;
449 	unsigned long last_rx;
450 	u16 head_seq_num;
451 	u16 stored_mpdu_num;
452 	u16 ssn;
453 	u16 buf_size;
454 	u16 timeout;
455 	u16 ssn_last_drop;
456 	u8 dialog_token;
457 	bool first_time; /* is it 1-st time this buffer used? */
458 };
459 
460 enum wil_sta_status {
461 	wil_sta_unused = 0,
462 	wil_sta_conn_pending = 1,
463 	wil_sta_connected = 2,
464 };
465 
466 #define WIL_STA_TID_NUM (16)
467 #define WIL_MCS_MAX (12) /* Maximum MCS supported */
468 
469 struct wil_net_stats {
470 	unsigned long	rx_packets;
471 	unsigned long	tx_packets;
472 	unsigned long	rx_bytes;
473 	unsigned long	tx_bytes;
474 	unsigned long	tx_errors;
475 	unsigned long	rx_dropped;
476 	u16 last_mcs_rx;
477 	u64 rx_per_mcs[WIL_MCS_MAX + 1];
478 };
479 
480 /**
481  * struct wil_sta_info - data for peer
482  *
483  * Peer identified by its CID (connection ID)
484  * NIC performs beam forming for each peer;
485  * if no beam forming done, frame exchange is not
486  * possible.
487  */
488 struct wil_sta_info {
489 	u8 addr[ETH_ALEN];
490 	enum wil_sta_status status;
491 	struct wil_net_stats stats;
492 	/* Rx BACK */
493 	struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM];
494 	spinlock_t tid_rx_lock; /* guarding tid_rx array */
495 	unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)];
496 	unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)];
497 };
498 
499 enum {
500 	fw_recovery_idle = 0,
501 	fw_recovery_pending = 1,
502 	fw_recovery_running = 2,
503 };
504 
505 enum {
506 	hw_capability_last
507 };
508 
509 struct wil_back_rx {
510 	struct list_head list;
511 	/* request params, converted to CPU byte order - what we asked for */
512 	u8 cidxtid;
513 	u8 dialog_token;
514 	u16 ba_param_set;
515 	u16 ba_timeout;
516 	u16 ba_seq_ctrl;
517 };
518 
519 struct wil_back_tx {
520 	struct list_head list;
521 	/* request params, converted to CPU byte order - what we asked for */
522 	u8 ringid;
523 	u8 agg_wsize;
524 	u16 agg_timeout;
525 };
526 
527 struct wil_probe_client_req {
528 	struct list_head list;
529 	u64 cookie;
530 	u8 cid;
531 };
532 
533 struct pmc_ctx {
534 	/* alloc, free, and read operations must own the lock */
535 	struct mutex		lock;
536 	struct vring_tx_desc	*pring_va;
537 	dma_addr_t		pring_pa;
538 	struct desc_alloc_info  *descriptors;
539 	int			last_cmd_status;
540 	int			num_descriptors;
541 	int			descriptor_size;
542 };
543 
544 struct wil6210_priv {
545 	struct pci_dev *pdev;
546 	int n_msi;
547 	struct wireless_dev *wdev;
548 	void __iomem *csr;
549 	DECLARE_BITMAP(status, wil_status_last);
550 	u32 fw_version;
551 	u32 hw_version;
552 	const char *hw_name;
553 	DECLARE_BITMAP(hw_capabilities, hw_capability_last);
554 	u8 n_mids; /* number of additional MIDs as reported by FW */
555 	u32 recovery_count; /* num of FW recovery attempts in a short time */
556 	u32 recovery_state; /* FW recovery state machine */
557 	unsigned long last_fw_recovery; /* jiffies of last fw recovery */
558 	wait_queue_head_t wq; /* for all wait_event() use */
559 	/* profile */
560 	u32 monitor_flags;
561 	u32 privacy; /* secure connection? */
562 	int sinfo_gen;
563 	u32 ap_isolate; /* no intra-BSS communication */
564 	/* interrupt moderation */
565 	u32 tx_max_burst_duration;
566 	u32 tx_interframe_timeout;
567 	u32 rx_max_burst_duration;
568 	u32 rx_interframe_timeout;
569 	/* cached ISR registers */
570 	u32 isr_misc;
571 	/* mailbox related */
572 	struct mutex wmi_mutex;
573 	struct wil6210_mbox_ctl mbox_ctl;
574 	struct completion wmi_ready;
575 	struct completion wmi_call;
576 	u16 wmi_seq;
577 	u16 reply_id; /**< wait for this WMI event */
578 	void *reply_buf;
579 	u16 reply_size;
580 	struct workqueue_struct *wmi_wq; /* for deferred calls */
581 	struct work_struct wmi_event_worker;
582 	struct workqueue_struct *wq_service;
583 	struct work_struct connect_worker;
584 	struct work_struct disconnect_worker;
585 	struct work_struct fw_error_worker;	/* for FW error recovery */
586 	struct timer_list connect_timer;
587 	struct timer_list scan_timer; /* detect scan timeout */
588 	int pending_connect_cid;
589 	struct list_head pending_wmi_ev;
590 	/*
591 	 * protect pending_wmi_ev
592 	 * - fill in IRQ from wil6210_irq_misc,
593 	 * - consumed in thread by wmi_event_worker
594 	 */
595 	spinlock_t wmi_ev_lock;
596 	struct napi_struct napi_rx;
597 	struct napi_struct napi_tx;
598 	/* BACK */
599 	struct list_head back_rx_pending;
600 	struct mutex back_rx_mutex; /* protect @back_rx_pending */
601 	struct work_struct back_rx_worker;
602 	struct list_head back_tx_pending;
603 	struct mutex back_tx_mutex; /* protect @back_tx_pending */
604 	struct work_struct back_tx_worker;
605 	/* keep alive */
606 	struct list_head probe_client_pending;
607 	struct mutex probe_client_mutex; /* protect @probe_client_pending */
608 	struct work_struct probe_client_worker;
609 	/* DMA related */
610 	struct vring vring_rx;
611 	struct vring vring_tx[WIL6210_MAX_TX_RINGS];
612 	struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS];
613 	u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */
614 	struct wil_sta_info sta[WIL6210_MAX_CID];
615 	int bcast_vring;
616 	/* scan */
617 	struct cfg80211_scan_request *scan_request;
618 
619 	struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
620 	/* statistics */
621 	atomic_t isr_count_rx, isr_count_tx;
622 	/* debugfs */
623 	struct dentry *debug;
624 	struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)];
625 
626 	void *platform_handle;
627 	struct wil_platform_ops platform_ops;
628 
629 	struct pmc_ctx pmc;
630 };
631 
632 #define wil_to_wiphy(i) (i->wdev->wiphy)
633 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
634 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
635 #define wil_to_wdev(i) (i->wdev)
636 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
637 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
638 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
639 
640 __printf(2, 3)
641 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...);
642 __printf(2, 3)
643 void wil_err(struct wil6210_priv *wil, const char *fmt, ...);
644 __printf(2, 3)
645 void wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...);
646 __printf(2, 3)
647 void wil_info(struct wil6210_priv *wil, const char *fmt, ...);
648 #define wil_dbg(wil, fmt, arg...) do { \
649 	netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \
650 	wil_dbg_trace(wil, fmt, ##arg); \
651 } while (0)
652 
653 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
654 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
655 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
656 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
657 
658 #if defined(CONFIG_DYNAMIC_DEBUG)
659 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize,	\
660 			  groupsize, buf, len, ascii)		\
661 			  print_hex_dump_debug("DBG[TXRX]" prefix_str,\
662 					 prefix_type, rowsize,	\
663 					 groupsize, buf, len, ascii)
664 
665 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize,	\
666 			 groupsize, buf, len, ascii)		\
667 			 print_hex_dump_debug("DBG[ WMI]" prefix_str,\
668 					prefix_type, rowsize,	\
669 					groupsize, buf, len, ascii)
670 #else /* defined(CONFIG_DYNAMIC_DEBUG) */
671 static inline
672 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize,
673 		       int groupsize, const void *buf, size_t len, bool ascii)
674 {
675 }
676 
677 static inline
678 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize,
679 		      int groupsize, const void *buf, size_t len, bool ascii)
680 {
681 }
682 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */
683 
684 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
685 			  size_t count);
686 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
687 			size_t count);
688 
689 void *wil_if_alloc(struct device *dev);
690 void wil_if_free(struct wil6210_priv *wil);
691 int wil_if_add(struct wil6210_priv *wil);
692 void wil_if_remove(struct wil6210_priv *wil);
693 int wil_priv_init(struct wil6210_priv *wil);
694 void wil_priv_deinit(struct wil6210_priv *wil);
695 int wil_reset(struct wil6210_priv *wil, bool no_fw);
696 void wil_fw_error_recovery(struct wil6210_priv *wil);
697 void wil_set_recovery_state(struct wil6210_priv *wil, int state);
698 int wil_up(struct wil6210_priv *wil);
699 int __wil_up(struct wil6210_priv *wil);
700 int wil_down(struct wil6210_priv *wil);
701 int __wil_down(struct wil6210_priv *wil);
702 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
703 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac);
704 void wil_set_ethtoolops(struct net_device *ndev);
705 
706 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
707 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
708 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
709 		 struct wil6210_mbox_hdr *hdr);
710 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len);
711 void wmi_recv_cmd(struct wil6210_priv *wil);
712 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
713 	     u16 reply_id, void *reply, u8 reply_size, int to_msec);
714 void wmi_event_worker(struct work_struct *work);
715 void wmi_event_flush(struct wil6210_priv *wil);
716 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid);
717 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid);
718 int wmi_set_channel(struct wil6210_priv *wil, int channel);
719 int wmi_get_channel(struct wil6210_priv *wil, int *channel);
720 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index,
721 		       const void *mac_addr, int key_usage);
722 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index,
723 		       const void *mac_addr, int key_len, const void *key,
724 		       int key_usage);
725 int wmi_echo(struct wil6210_priv *wil);
726 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie);
727 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring);
728 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel);
729 int wmi_rxon(struct wil6210_priv *wil, bool on);
730 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r);
731 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason);
732 int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout);
733 int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason);
734 int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason);
735 int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token,
736 		      u16 status, bool amsdu, u16 agg_wsize, u16 timeout);
737 int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid,
738 			 u8 dialog_token, __le16 ba_param_set,
739 			 __le16 ba_timeout, __le16 ba_seq_ctrl);
740 void wil_back_rx_worker(struct work_struct *work);
741 void wil_back_rx_flush(struct wil6210_priv *wil);
742 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize);
743 void wil_back_tx_worker(struct work_struct *work);
744 void wil_back_tx_flush(struct wil6210_priv *wil);
745 
746 void wil6210_clear_irq(struct wil6210_priv *wil);
747 int wil6210_init_irq(struct wil6210_priv *wil, int irq);
748 void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
749 void wil_mask_irq(struct wil6210_priv *wil);
750 void wil_unmask_irq(struct wil6210_priv *wil);
751 void wil_configure_interrupt_moderation(struct wil6210_priv *wil);
752 void wil_disable_irq(struct wil6210_priv *wil);
753 void wil_enable_irq(struct wil6210_priv *wil);
754 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
755 			 struct cfg80211_mgmt_tx_params *params,
756 			 u64 *cookie);
757 
758 int wil6210_debugfs_init(struct wil6210_priv *wil);
759 void wil6210_debugfs_remove(struct wil6210_priv *wil);
760 int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid,
761 		       struct station_info *sinfo);
762 
763 struct wireless_dev *wil_cfg80211_init(struct device *dev);
764 void wil_wdev_free(struct wil6210_priv *wil);
765 
766 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr);
767 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype,
768 		  u8 chan, u8 hidden_ssid);
769 int wmi_pcp_stop(struct wil6210_priv *wil);
770 void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid,
771 			u16 reason_code, bool from_event);
772 void wil_probe_client_flush(struct wil6210_priv *wil);
773 void wil_probe_client_worker(struct work_struct *work);
774 
775 int wil_rx_init(struct wil6210_priv *wil, u16 size);
776 void wil_rx_fini(struct wil6210_priv *wil);
777 
778 /* TX API */
779 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
780 		      int cid, int tid);
781 void wil_vring_fini_tx(struct wil6210_priv *wil, int id);
782 int wil_vring_init_bcast(struct wil6210_priv *wil, int id, int size);
783 int wil_bcast_init(struct wil6210_priv *wil);
784 void wil_bcast_fini(struct wil6210_priv *wil);
785 
786 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
787 int wil_tx_complete(struct wil6210_priv *wil, int ringid);
788 void wil6210_unmask_irq_tx(struct wil6210_priv *wil);
789 
790 /* RX API */
791 void wil_rx_handle(struct wil6210_priv *wil, int *quota);
792 void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
793 
794 int wil_iftype_nl2wmi(enum nl80211_iftype type);
795 
796 int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd);
797 int wil_request_firmware(struct wil6210_priv *wil, const char *name);
798 
799 #endif /* __WIL6210_H__ */
800