1 /* 2 * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/etherdevice.h> 18 #include <linux/moduleparam.h> 19 #include <linux/prefetch.h> 20 #include <linux/types.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include "wil6210.h" 25 #include "txrx_edma.h" 26 #include "txrx.h" 27 #include "trace.h" 28 29 #define WIL_EDMA_MAX_DATA_OFFSET (2) 30 /* RX buffer size must be aligned to 4 bytes */ 31 #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048) 32 #define MAX_INVALID_BUFF_ID_RETRY (3) 33 34 static void wil_tx_desc_unmap_edma(struct device *dev, 35 union wil_tx_desc *desc, 36 struct wil_ctx *ctx) 37 { 38 struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc; 39 dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma); 40 u16 dmalen = le16_to_cpu(d->dma.length); 41 42 switch (ctx->mapped_as) { 43 case wil_mapped_as_single: 44 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE); 45 break; 46 case wil_mapped_as_page: 47 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE); 48 break; 49 default: 50 break; 51 } 52 } 53 54 static int wil_find_free_sring(struct wil6210_priv *wil) 55 { 56 int i; 57 58 for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) { 59 if (!wil->srings[i].va) 60 return i; 61 } 62 63 return -EINVAL; 64 } 65 66 static void wil_sring_free(struct wil6210_priv *wil, 67 struct wil_status_ring *sring) 68 { 69 struct device *dev = wil_to_dev(wil); 70 size_t sz; 71 72 if (!sring || !sring->va) 73 return; 74 75 sz = sring->elem_size * sring->size; 76 77 wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n", 78 sz, sring->va, &sring->pa); 79 80 dma_free_coherent(dev, sz, (void *)sring->va, sring->pa); 81 sring->pa = 0; 82 sring->va = NULL; 83 } 84 85 static int wil_sring_alloc(struct wil6210_priv *wil, 86 struct wil_status_ring *sring) 87 { 88 struct device *dev = wil_to_dev(wil); 89 size_t sz = sring->elem_size * sring->size; 90 91 wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz); 92 93 if (sz == 0) { 94 wil_err(wil, "Cannot allocate a zero size status ring\n"); 95 return -EINVAL; 96 } 97 98 sring->swhead = 0; 99 100 /* Status messages are allocated and initialized to 0. This is necessary 101 * since DR bit should be initialized to 0. 102 */ 103 sring->va = dma_alloc_coherent(dev, sz, &sring->pa, GFP_KERNEL); 104 if (!sring->va) 105 return -ENOMEM; 106 107 wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va, 108 &sring->pa); 109 110 return 0; 111 } 112 113 static int wil_tx_init_edma(struct wil6210_priv *wil) 114 { 115 int ring_id = wil_find_free_sring(wil); 116 struct wil_status_ring *sring; 117 int rc; 118 u16 status_ring_size; 119 120 if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 121 wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 122 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT; 123 124 status_ring_size = 1 << wil->tx_status_ring_order; 125 126 wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n", 127 status_ring_size, ring_id); 128 129 if (ring_id < 0) 130 return ring_id; 131 132 /* Allocate Tx status ring. Tx descriptor rings will be 133 * allocated on WMI connect event 134 */ 135 sring = &wil->srings[ring_id]; 136 137 sring->is_rx = false; 138 sring->size = status_ring_size; 139 sring->elem_size = sizeof(struct wil_ring_tx_status); 140 rc = wil_sring_alloc(wil, sring); 141 if (rc) 142 return rc; 143 144 rc = wil_wmi_tx_sring_cfg(wil, ring_id); 145 if (rc) 146 goto out_free; 147 148 sring->desc_rdy_pol = 1; 149 wil->tx_sring_idx = ring_id; 150 151 return 0; 152 out_free: 153 wil_sring_free(wil, sring); 154 return rc; 155 } 156 157 /** 158 * Allocate one skb for Rx descriptor RING 159 */ 160 static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil, 161 struct wil_ring *ring, u32 i) 162 { 163 struct device *dev = wil_to_dev(wil); 164 unsigned int sz = wil->rx_buf_len; 165 dma_addr_t pa; 166 u16 buff_id; 167 struct list_head *active = &wil->rx_buff_mgmt.active; 168 struct list_head *free = &wil->rx_buff_mgmt.free; 169 struct wil_rx_buff *rx_buff; 170 struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr; 171 struct sk_buff *skb; 172 struct wil_rx_enhanced_desc dd, *d = ⅆ 173 struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *) 174 &ring->va[i].rx.enhanced; 175 176 if (unlikely(list_empty(free))) { 177 wil->rx_buff_mgmt.free_list_empty_cnt++; 178 return -EAGAIN; 179 } 180 181 skb = dev_alloc_skb(sz); 182 if (unlikely(!skb)) 183 return -ENOMEM; 184 185 skb_put(skb, sz); 186 187 /** 188 * Make sure that the network stack calculates checksum for packets 189 * which failed the HW checksum calculation 190 */ 191 skb->ip_summed = CHECKSUM_NONE; 192 193 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE); 194 if (unlikely(dma_mapping_error(dev, pa))) { 195 kfree_skb(skb); 196 return -ENOMEM; 197 } 198 199 /* Get the buffer ID - the index of the rx buffer in the buff_arr */ 200 rx_buff = list_first_entry(free, struct wil_rx_buff, list); 201 buff_id = rx_buff->id; 202 203 /* Move a buffer from the free list to the active list */ 204 list_move(&rx_buff->list, active); 205 206 buff_arr[buff_id].skb = skb; 207 208 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 209 d->dma.length = cpu_to_le16(sz); 210 d->mac.buff_id = cpu_to_le16(buff_id); 211 *_d = *d; 212 213 /* Save the physical address in skb->cb for later use in dma_unmap */ 214 memcpy(skb->cb, &pa, sizeof(pa)); 215 216 return 0; 217 } 218 219 static inline 220 void wil_get_next_rx_status_msg(struct wil_status_ring *sring, void *msg) 221 { 222 memcpy(msg, (void *)(sring->va + (sring->elem_size * sring->swhead)), 223 sring->elem_size); 224 } 225 226 static inline void wil_sring_advance_swhead(struct wil_status_ring *sring) 227 { 228 sring->swhead = (sring->swhead + 1) % sring->size; 229 if (sring->swhead == 0) 230 sring->desc_rdy_pol = 1 - sring->desc_rdy_pol; 231 } 232 233 static int wil_rx_refill_edma(struct wil6210_priv *wil) 234 { 235 struct wil_ring *ring = &wil->ring_rx; 236 u32 next_head; 237 int rc = 0; 238 ring->swtail = *ring->edma_rx_swtail.va; 239 240 for (; next_head = wil_ring_next_head(ring), 241 (next_head != ring->swtail); 242 ring->swhead = next_head) { 243 rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead); 244 if (unlikely(rc)) { 245 if (rc == -EAGAIN) 246 wil_dbg_txrx(wil, "No free buffer ID found\n"); 247 else 248 wil_err_ratelimited(wil, 249 "Error %d in refill desc[%d]\n", 250 rc, ring->swhead); 251 break; 252 } 253 } 254 255 /* make sure all writes to descriptors (shared memory) are done before 256 * committing them to HW 257 */ 258 wmb(); 259 260 wil_w(wil, ring->hwtail, ring->swhead); 261 262 return rc; 263 } 264 265 static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil, 266 struct wil_ring *ring) 267 { 268 struct device *dev = wil_to_dev(wil); 269 struct list_head *active = &wil->rx_buff_mgmt.active; 270 dma_addr_t pa; 271 272 if (!wil->rx_buff_mgmt.buff_arr) 273 return; 274 275 while (!list_empty(active)) { 276 struct wil_rx_buff *rx_buff = 277 list_first_entry(active, struct wil_rx_buff, list); 278 struct sk_buff *skb = rx_buff->skb; 279 280 if (unlikely(!skb)) { 281 wil_err(wil, "No Rx skb at buff_id %d\n", rx_buff->id); 282 } else { 283 rx_buff->skb = NULL; 284 memcpy(&pa, skb->cb, sizeof(pa)); 285 dma_unmap_single(dev, pa, wil->rx_buf_len, 286 DMA_FROM_DEVICE); 287 kfree_skb(skb); 288 } 289 290 /* Move the buffer from the active to the free list */ 291 list_move(&rx_buff->list, &wil->rx_buff_mgmt.free); 292 } 293 } 294 295 static void wil_free_rx_buff_arr(struct wil6210_priv *wil) 296 { 297 struct wil_ring *ring = &wil->ring_rx; 298 299 if (!wil->rx_buff_mgmt.buff_arr) 300 return; 301 302 /* Move all the buffers to the free list in case active list is 303 * not empty in order to release all SKBs before deleting the array 304 */ 305 wil_move_all_rx_buff_to_free_list(wil, ring); 306 307 kfree(wil->rx_buff_mgmt.buff_arr); 308 wil->rx_buff_mgmt.buff_arr = NULL; 309 } 310 311 static int wil_init_rx_buff_arr(struct wil6210_priv *wil, 312 size_t size) 313 { 314 struct wil_rx_buff *buff_arr; 315 struct list_head *active = &wil->rx_buff_mgmt.active; 316 struct list_head *free = &wil->rx_buff_mgmt.free; 317 int i; 318 319 wil->rx_buff_mgmt.buff_arr = kcalloc(size + 1, 320 sizeof(struct wil_rx_buff), 321 GFP_KERNEL); 322 if (!wil->rx_buff_mgmt.buff_arr) 323 return -ENOMEM; 324 325 /* Set list heads */ 326 INIT_LIST_HEAD(active); 327 INIT_LIST_HEAD(free); 328 329 /* Linkify the list. 330 * buffer id 0 should not be used (marks invalid id). 331 */ 332 buff_arr = wil->rx_buff_mgmt.buff_arr; 333 for (i = 1; i <= size; i++) { 334 list_add(&buff_arr[i].list, free); 335 buff_arr[i].id = i; 336 } 337 338 wil->rx_buff_mgmt.size = size + 1; 339 340 return 0; 341 } 342 343 static int wil_init_rx_sring(struct wil6210_priv *wil, 344 u16 status_ring_size, 345 size_t elem_size, 346 u16 ring_id) 347 { 348 struct wil_status_ring *sring = &wil->srings[ring_id]; 349 int rc; 350 351 wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", 352 status_ring_size, ring_id); 353 354 memset(&sring->rx_data, 0, sizeof(sring->rx_data)); 355 356 sring->is_rx = true; 357 sring->size = status_ring_size; 358 sring->elem_size = elem_size; 359 rc = wil_sring_alloc(wil, sring); 360 if (rc) 361 return rc; 362 363 rc = wil_wmi_rx_sring_add(wil, ring_id); 364 if (rc) 365 goto out_free; 366 367 sring->desc_rdy_pol = 1; 368 369 return 0; 370 out_free: 371 wil_sring_free(wil, sring); 372 return rc; 373 } 374 375 static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil, 376 struct wil_ring *ring) 377 { 378 struct device *dev = wil_to_dev(wil); 379 size_t sz = ring->size * sizeof(ring->va[0]); 380 381 wil_dbg_misc(wil, "alloc_desc_ring:\n"); 382 383 BUILD_BUG_ON(sizeof(ring->va[0]) != 32); 384 385 ring->swhead = 0; 386 ring->swtail = 0; 387 ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL); 388 if (!ring->ctx) 389 goto err; 390 391 ring->va = dma_alloc_coherent(dev, sz, &ring->pa, GFP_KERNEL); 392 if (!ring->va) 393 goto err_free_ctx; 394 395 if (ring->is_rx) { 396 sz = sizeof(*ring->edma_rx_swtail.va); 397 ring->edma_rx_swtail.va = 398 dma_alloc_coherent(dev, sz, &ring->edma_rx_swtail.pa, 399 GFP_KERNEL); 400 if (!ring->edma_rx_swtail.va) 401 goto err_free_va; 402 } 403 404 wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n", 405 ring->is_rx ? "RX" : "TX", 406 ring->size, ring->va, &ring->pa, ring->ctx); 407 408 return 0; 409 err_free_va: 410 dma_free_coherent(dev, ring->size * sizeof(ring->va[0]), 411 (void *)ring->va, ring->pa); 412 ring->va = NULL; 413 err_free_ctx: 414 kfree(ring->ctx); 415 ring->ctx = NULL; 416 err: 417 return -ENOMEM; 418 } 419 420 static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring) 421 { 422 struct device *dev = wil_to_dev(wil); 423 size_t sz; 424 int ring_index = 0; 425 426 if (!ring->va) 427 return; 428 429 sz = ring->size * sizeof(ring->va[0]); 430 431 lockdep_assert_held(&wil->mutex); 432 if (ring->is_rx) { 433 wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n", 434 ring->size, ring->va, 435 &ring->pa, ring->ctx); 436 437 wil_move_all_rx_buff_to_free_list(wil, ring); 438 dma_free_coherent(dev, sizeof(*ring->edma_rx_swtail.va), 439 ring->edma_rx_swtail.va, 440 ring->edma_rx_swtail.pa); 441 goto out; 442 } 443 444 /* TX ring */ 445 ring_index = ring - wil->ring_tx; 446 447 wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n", 448 ring_index, ring->size, ring->va, 449 &ring->pa, ring->ctx); 450 451 while (!wil_ring_is_empty(ring)) { 452 struct wil_ctx *ctx; 453 454 struct wil_tx_enhanced_desc dd, *d = ⅆ 455 struct wil_tx_enhanced_desc *_d = 456 (struct wil_tx_enhanced_desc *) 457 &ring->va[ring->swtail].tx.enhanced; 458 459 ctx = &ring->ctx[ring->swtail]; 460 if (!ctx) { 461 wil_dbg_txrx(wil, 462 "ctx(%d) was already completed\n", 463 ring->swtail); 464 ring->swtail = wil_ring_next_tail(ring); 465 continue; 466 } 467 *d = *_d; 468 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 469 if (ctx->skb) 470 dev_kfree_skb_any(ctx->skb); 471 ring->swtail = wil_ring_next_tail(ring); 472 } 473 474 out: 475 dma_free_coherent(dev, sz, (void *)ring->va, ring->pa); 476 kfree(ring->ctx); 477 ring->pa = 0; 478 ring->va = NULL; 479 ring->ctx = NULL; 480 } 481 482 static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size, 483 int status_ring_id) 484 { 485 struct wil_ring *ring = &wil->ring_rx; 486 int rc; 487 488 wil_dbg_misc(wil, "init RX desc ring\n"); 489 490 ring->size = desc_ring_size; 491 ring->is_rx = true; 492 rc = wil_ring_alloc_desc_ring(wil, ring); 493 if (rc) 494 return rc; 495 496 rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id); 497 if (rc) 498 goto out_free; 499 500 return 0; 501 out_free: 502 wil_ring_free_edma(wil, ring); 503 return rc; 504 } 505 506 static void wil_get_reorder_params_edma(struct wil6210_priv *wil, 507 struct sk_buff *skb, int *tid, 508 int *cid, int *mid, u16 *seq, 509 int *mcast, int *retry) 510 { 511 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 512 513 *tid = wil_rx_status_get_tid(s); 514 *cid = wil_rx_status_get_cid(s); 515 *mid = wil_rx_status_get_mid(s); 516 *seq = le16_to_cpu(wil_rx_status_get_seq(wil, s)); 517 *mcast = wil_rx_status_get_mcast(s); 518 *retry = wil_rx_status_get_retry(s); 519 } 520 521 static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid, 522 int *security) 523 { 524 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 525 526 *cid = wil_rx_status_get_cid(s); 527 *security = wil_rx_status_get_security(s); 528 } 529 530 static int wil_rx_crypto_check_edma(struct wil6210_priv *wil, 531 struct sk_buff *skb) 532 { 533 struct wil_rx_status_extended *st; 534 int cid, tid, key_id, mc; 535 struct wil_sta_info *s; 536 struct wil_tid_crypto_rx *c; 537 struct wil_tid_crypto_rx_single *cc; 538 const u8 *pn; 539 540 /* In HW reorder, HW is responsible for crypto check */ 541 if (wil->use_rx_hw_reordering) 542 return 0; 543 544 st = wil_skb_rxstatus(skb); 545 546 cid = wil_rx_status_get_cid(st); 547 tid = wil_rx_status_get_tid(st); 548 key_id = wil_rx_status_get_key_id(st); 549 mc = wil_rx_status_get_mcast(st); 550 s = &wil->sta[cid]; 551 c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid]; 552 cc = &c->key_id[key_id]; 553 pn = (u8 *)&st->ext.pn_15_0; 554 555 if (!cc->key_set) { 556 wil_err_ratelimited(wil, 557 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n", 558 cid, tid, mc, key_id); 559 return -EINVAL; 560 } 561 562 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) { 563 wil_err_ratelimited(wil, 564 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n", 565 cid, tid, mc, key_id, pn, cc->pn); 566 return -EINVAL; 567 } 568 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN); 569 570 return 0; 571 } 572 573 static bool wil_is_rx_idle_edma(struct wil6210_priv *wil) 574 { 575 struct wil_status_ring *sring; 576 struct wil_rx_status_extended msg1; 577 void *msg = &msg1; 578 u8 dr_bit; 579 int i; 580 581 for (i = 0; i < wil->num_rx_status_rings; i++) { 582 sring = &wil->srings[i]; 583 if (!sring->va) 584 continue; 585 586 wil_get_next_rx_status_msg(sring, msg); 587 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 588 589 /* Check if there are unhandled RX status messages */ 590 if (dr_bit == sring->desc_rdy_pol) 591 return false; 592 } 593 594 return true; 595 } 596 597 static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil) 598 { 599 /* RX buffer size must be aligned to 4 bytes */ 600 wil->rx_buf_len = rx_large_buf ? 601 WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT; 602 } 603 604 static int wil_rx_init_edma(struct wil6210_priv *wil, uint desc_ring_order) 605 { 606 u16 status_ring_size, desc_ring_size = 1 << desc_ring_order; 607 struct wil_ring *ring = &wil->ring_rx; 608 int rc; 609 size_t elem_size = wil->use_compressed_rx_status ? 610 sizeof(struct wil_rx_status_compressed) : 611 sizeof(struct wil_rx_status_extended); 612 int i; 613 614 /* In SW reorder one must use extended status messages */ 615 if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) { 616 wil_err(wil, 617 "compressed RX status cannot be used with SW reorder\n"); 618 return -EINVAL; 619 } 620 if (wil->rx_status_ring_order <= desc_ring_order) 621 /* make sure sring is larger than desc ring */ 622 wil->rx_status_ring_order = desc_ring_order + 1; 623 if (wil->rx_buff_id_count <= desc_ring_size) 624 /* make sure we will not run out of buff_ids */ 625 wil->rx_buff_id_count = desc_ring_size + 512; 626 if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 627 wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 628 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT; 629 630 status_ring_size = 1 << wil->rx_status_ring_order; 631 632 wil_dbg_misc(wil, 633 "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n", 634 desc_ring_size, status_ring_size, elem_size); 635 636 wil_rx_buf_len_init_edma(wil); 637 638 /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */ 639 if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1) 640 wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1; 641 642 wil_dbg_misc(wil, "rx_init: allocate %d status rings\n", 643 wil->num_rx_status_rings); 644 645 rc = wil_wmi_cfg_def_rx_offload(wil, wil->rx_buf_len); 646 if (rc) 647 return rc; 648 649 /* Allocate status ring */ 650 for (i = 0; i < wil->num_rx_status_rings; i++) { 651 int sring_id = wil_find_free_sring(wil); 652 653 if (sring_id < 0) { 654 rc = -EFAULT; 655 goto err_free_status; 656 } 657 rc = wil_init_rx_sring(wil, status_ring_size, elem_size, 658 sring_id); 659 if (rc) 660 goto err_free_status; 661 } 662 663 /* Allocate descriptor ring */ 664 rc = wil_init_rx_desc_ring(wil, desc_ring_size, 665 WIL_DEFAULT_RX_STATUS_RING_ID); 666 if (rc) 667 goto err_free_status; 668 669 if (wil->rx_buff_id_count >= status_ring_size) { 670 wil_info(wil, 671 "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n", 672 wil->rx_buff_id_count, status_ring_size, 673 status_ring_size - 1); 674 wil->rx_buff_id_count = status_ring_size - 1; 675 } 676 677 /* Allocate Rx buffer array */ 678 rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count); 679 if (rc) 680 goto err_free_desc; 681 682 /* Fill descriptor ring with credits */ 683 rc = wil_rx_refill_edma(wil); 684 if (rc) 685 goto err_free_rx_buff_arr; 686 687 return 0; 688 err_free_rx_buff_arr: 689 wil_free_rx_buff_arr(wil); 690 err_free_desc: 691 wil_ring_free_edma(wil, ring); 692 err_free_status: 693 for (i = 0; i < wil->num_rx_status_rings; i++) 694 wil_sring_free(wil, &wil->srings[i]); 695 696 return rc; 697 } 698 699 static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id, 700 int size, int cid, int tid) 701 { 702 struct wil6210_priv *wil = vif_to_wil(vif); 703 int rc; 704 struct wil_ring *ring = &wil->ring_tx[ring_id]; 705 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 706 707 lockdep_assert_held(&wil->mutex); 708 709 wil_dbg_misc(wil, 710 "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n", 711 ring_id, cid, tid, wil->tx_sring_idx); 712 713 wil_tx_data_init(txdata); 714 ring->size = size; 715 rc = wil_ring_alloc_desc_ring(wil, ring); 716 if (rc) 717 goto out; 718 719 wil->ring2cid_tid[ring_id][0] = cid; 720 wil->ring2cid_tid[ring_id][1] = tid; 721 if (!vif->privacy) 722 txdata->dot1x_open = true; 723 724 rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid); 725 if (rc) { 726 wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n"); 727 goto out_free; 728 } 729 730 if (txdata->dot1x_open && agg_wsize >= 0) 731 wil_addba_tx_request(wil, ring_id, agg_wsize); 732 733 return 0; 734 out_free: 735 spin_lock_bh(&txdata->lock); 736 txdata->dot1x_open = false; 737 txdata->enabled = 0; 738 spin_unlock_bh(&txdata->lock); 739 wil_ring_free_edma(wil, ring); 740 wil->ring2cid_tid[ring_id][0] = wil->max_assoc_sta; 741 wil->ring2cid_tid[ring_id][1] = 0; 742 743 out: 744 return rc; 745 } 746 747 static int wil_tx_ring_modify_edma(struct wil6210_vif *vif, int ring_id, 748 int cid, int tid) 749 { 750 struct wil6210_priv *wil = vif_to_wil(vif); 751 752 wil_err(wil, "ring modify is not supported for EDMA\n"); 753 754 return -EOPNOTSUPP; 755 } 756 757 /* This function is used only for RX SW reorder */ 758 static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid, 759 struct sk_buff *skb, struct wil_net_stats *stats) 760 { 761 u8 ftype; 762 u8 fc1; 763 int mid; 764 int tid; 765 u16 seq; 766 struct wil6210_vif *vif; 767 768 ftype = wil_rx_status_get_frame_type(wil, msg); 769 if (ftype == IEEE80211_FTYPE_DATA) 770 return 0; 771 772 fc1 = wil_rx_status_get_fc1(wil, msg); 773 mid = wil_rx_status_get_mid(msg); 774 tid = wil_rx_status_get_tid(msg); 775 seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg)); 776 vif = wil->vifs[mid]; 777 778 if (unlikely(!vif)) { 779 wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid); 780 return -EAGAIN; 781 } 782 783 wil_dbg_txrx(wil, 784 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 785 fc1, mid, cid, tid, seq); 786 if (stats) 787 stats->rx_non_data_frame++; 788 if (wil_is_back_req(fc1)) { 789 wil_dbg_txrx(wil, 790 "BAR: MID %d CID %d TID %d Seq 0x%03x\n", 791 mid, cid, tid, seq); 792 wil_rx_bar(wil, vif, cid, tid, seq); 793 } else { 794 u32 sz = wil->use_compressed_rx_status ? 795 sizeof(struct wil_rx_status_compressed) : 796 sizeof(struct wil_rx_status_extended); 797 798 /* print again all info. One can enable only this 799 * without overhead for printing every Rx frame 800 */ 801 wil_dbg_txrx(wil, 802 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 803 fc1, mid, cid, tid, seq); 804 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 805 (const void *)msg, sz, false); 806 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 807 skb->data, skb_headlen(skb), false); 808 } 809 810 return -EAGAIN; 811 } 812 813 static int wil_rx_error_check_edma(struct wil6210_priv *wil, 814 struct sk_buff *skb, 815 struct wil_net_stats *stats) 816 { 817 int l2_rx_status; 818 void *msg = wil_skb_rxstatus(skb); 819 820 l2_rx_status = wil_rx_status_get_l2_rx_status(msg); 821 if (l2_rx_status != 0) { 822 wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n", 823 l2_rx_status); 824 /* Due to HW issue, KEY error will trigger a MIC error */ 825 if (l2_rx_status == WIL_RX_EDMA_ERROR_MIC) { 826 wil_err_ratelimited(wil, 827 "L2 MIC/KEY error, dropping packet\n"); 828 stats->rx_mic_error++; 829 } 830 if (l2_rx_status == WIL_RX_EDMA_ERROR_KEY) { 831 wil_err_ratelimited(wil, 832 "L2 KEY error, dropping packet\n"); 833 stats->rx_key_error++; 834 } 835 if (l2_rx_status == WIL_RX_EDMA_ERROR_REPLAY) { 836 wil_err_ratelimited(wil, 837 "L2 REPLAY error, dropping packet\n"); 838 stats->rx_replay++; 839 } 840 if (l2_rx_status == WIL_RX_EDMA_ERROR_AMSDU) { 841 wil_err_ratelimited(wil, 842 "L2 AMSDU error, dropping packet\n"); 843 stats->rx_amsdu_error++; 844 } 845 return -EFAULT; 846 } 847 848 skb->ip_summed = wil_rx_status_get_checksum(msg, stats); 849 850 return 0; 851 } 852 853 static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, 854 struct wil_status_ring *sring) 855 { 856 struct device *dev = wil_to_dev(wil); 857 struct wil_rx_status_extended msg1; 858 void *msg = &msg1; 859 u16 buff_id; 860 struct sk_buff *skb; 861 dma_addr_t pa; 862 struct wil_ring_rx_data *rxdata = &sring->rx_data; 863 unsigned int sz = wil->rx_buf_len; 864 struct wil_net_stats *stats = NULL; 865 u16 dmalen; 866 int cid; 867 bool eop, headstolen; 868 int delta; 869 u8 dr_bit; 870 u8 data_offset; 871 struct wil_rx_status_extended *s; 872 u16 sring_idx = sring - wil->srings; 873 874 BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb)); 875 876 again: 877 wil_get_next_rx_status_msg(sring, msg); 878 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 879 880 /* Completed handling all the ready status messages */ 881 if (dr_bit != sring->desc_rdy_pol) 882 return NULL; 883 884 /* Extract the buffer ID from the status message */ 885 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 886 887 while (!buff_id) { 888 struct wil_rx_status_extended *s; 889 int invalid_buff_id_retry = 0; 890 891 wil_dbg_txrx(wil, 892 "buff_id is not updated yet by HW, (swhead 0x%x)\n", 893 sring->swhead); 894 if (++invalid_buff_id_retry > MAX_INVALID_BUFF_ID_RETRY) 895 break; 896 897 /* Read the status message again */ 898 s = (struct wil_rx_status_extended *) 899 (sring->va + (sring->elem_size * sring->swhead)); 900 *(struct wil_rx_status_extended *)msg = *s; 901 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 902 } 903 904 if (unlikely(!wil_val_in_range(buff_id, 1, wil->rx_buff_mgmt.size))) { 905 wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n", 906 buff_id, sring->swhead); 907 wil_rx_status_reset_buff_id(sring); 908 wil_sring_advance_swhead(sring); 909 sring->invalid_buff_id_cnt++; 910 goto again; 911 } 912 913 /* Extract the SKB from the rx_buff management array */ 914 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 915 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 916 if (!skb) { 917 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 918 wil_rx_status_reset_buff_id(sring); 919 /* Move the buffer from the active list to the free list */ 920 list_move_tail(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 921 &wil->rx_buff_mgmt.free); 922 wil_sring_advance_swhead(sring); 923 sring->invalid_buff_id_cnt++; 924 goto again; 925 } 926 927 wil_rx_status_reset_buff_id(sring); 928 wil_sring_advance_swhead(sring); 929 930 memcpy(&pa, skb->cb, sizeof(pa)); 931 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); 932 dmalen = le16_to_cpu(wil_rx_status_get_length(msg)); 933 934 trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id, 935 msg); 936 wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n", 937 buff_id, sring_idx, dmalen); 938 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 939 (const void *)msg, wil->use_compressed_rx_status ? 940 sizeof(struct wil_rx_status_compressed) : 941 sizeof(struct wil_rx_status_extended), false); 942 943 /* Move the buffer from the active list to the free list */ 944 list_move_tail(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 945 &wil->rx_buff_mgmt.free); 946 947 eop = wil_rx_status_get_eop(msg); 948 949 cid = wil_rx_status_get_cid(msg); 950 if (unlikely(!wil_val_in_range(cid, 0, wil->max_assoc_sta))) { 951 wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n", 952 cid, sring->swhead); 953 rxdata->skipping = true; 954 goto skipping; 955 } 956 stats = &wil->sta[cid].stats; 957 958 if (unlikely(skb->len < ETH_HLEN)) { 959 wil_dbg_txrx(wil, "Short frame, len = %d\n", skb->len); 960 stats->rx_short_frame++; 961 rxdata->skipping = true; 962 goto skipping; 963 } 964 965 if (unlikely(dmalen > sz)) { 966 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen); 967 stats->rx_large_frame++; 968 rxdata->skipping = true; 969 } 970 971 skipping: 972 /* skipping indicates if a certain SKB should be dropped. 973 * It is set in case there is an error on the current SKB or in case 974 * of RX chaining: as long as we manage to merge the SKBs it will 975 * be false. once we have a bad SKB or we don't manage to merge SKBs 976 * it will be set to the !EOP value of the current SKB. 977 * This guarantees that all the following SKBs until EOP will also 978 * get dropped. 979 */ 980 if (unlikely(rxdata->skipping)) { 981 kfree_skb(skb); 982 if (rxdata->skb) { 983 kfree_skb(rxdata->skb); 984 rxdata->skb = NULL; 985 } 986 rxdata->skipping = !eop; 987 goto again; 988 } 989 990 skb_trim(skb, dmalen); 991 992 prefetch(skb->data); 993 994 if (!rxdata->skb) { 995 rxdata->skb = skb; 996 } else { 997 if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen, 998 &delta))) { 999 kfree_skb_partial(skb, headstolen); 1000 } else { 1001 wil_err(wil, "failed to merge skbs!\n"); 1002 kfree_skb(skb); 1003 kfree_skb(rxdata->skb); 1004 rxdata->skb = NULL; 1005 rxdata->skipping = !eop; 1006 goto again; 1007 } 1008 } 1009 1010 if (!eop) 1011 goto again; 1012 1013 /* reaching here rxdata->skb always contains a full packet */ 1014 skb = rxdata->skb; 1015 rxdata->skb = NULL; 1016 rxdata->skipping = false; 1017 1018 if (stats) { 1019 stats->last_mcs_rx = wil_rx_status_get_mcs(msg); 1020 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs)) 1021 stats->rx_per_mcs[stats->last_mcs_rx]++; 1022 } 1023 1024 if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status && 1025 wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) { 1026 kfree_skb(skb); 1027 goto again; 1028 } 1029 1030 /* Compensate for the HW data alignment according to the status 1031 * message 1032 */ 1033 data_offset = wil_rx_status_get_data_offset(msg); 1034 if (data_offset == 0xFF || 1035 data_offset > WIL_EDMA_MAX_DATA_OFFSET) { 1036 wil_err(wil, "Unexpected data offset %d\n", data_offset); 1037 kfree_skb(skb); 1038 goto again; 1039 } 1040 1041 skb_pull(skb, data_offset); 1042 1043 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 1044 skb->data, skb_headlen(skb), false); 1045 1046 /* Has to be done after dma_unmap_single as skb->cb is also 1047 * used for holding the pa 1048 */ 1049 s = wil_skb_rxstatus(skb); 1050 memcpy(s, msg, sring->elem_size); 1051 1052 return skb; 1053 } 1054 1055 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota) 1056 { 1057 struct net_device *ndev; 1058 struct wil_ring *ring = &wil->ring_rx; 1059 struct wil_status_ring *sring; 1060 struct sk_buff *skb; 1061 int i; 1062 1063 if (unlikely(!ring->va)) { 1064 wil_err(wil, "Rx IRQ while Rx not yet initialized\n"); 1065 return; 1066 } 1067 wil_dbg_txrx(wil, "rx_handle\n"); 1068 1069 for (i = 0; i < wil->num_rx_status_rings; i++) { 1070 sring = &wil->srings[i]; 1071 if (unlikely(!sring->va)) { 1072 wil_err(wil, 1073 "Rx IRQ while Rx status ring %d not yet initialized\n", 1074 i); 1075 continue; 1076 } 1077 1078 while ((*quota > 0) && 1079 (NULL != (skb = 1080 wil_sring_reap_rx_edma(wil, sring)))) { 1081 (*quota)--; 1082 if (wil->use_rx_hw_reordering) { 1083 void *msg = wil_skb_rxstatus(skb); 1084 int mid = wil_rx_status_get_mid(msg); 1085 struct wil6210_vif *vif = wil->vifs[mid]; 1086 1087 if (unlikely(!vif)) { 1088 wil_dbg_txrx(wil, 1089 "RX desc invalid mid %d", 1090 mid); 1091 kfree_skb(skb); 1092 continue; 1093 } 1094 ndev = vif_to_ndev(vif); 1095 wil_netif_rx_any(skb, ndev); 1096 } else { 1097 wil_rx_reorder(wil, skb); 1098 } 1099 } 1100 1101 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1102 } 1103 1104 wil_rx_refill_edma(wil); 1105 } 1106 1107 static int wil_tx_desc_map_edma(union wil_tx_desc *desc, 1108 dma_addr_t pa, 1109 u32 len, 1110 int ring_index) 1111 { 1112 struct wil_tx_enhanced_desc *d = 1113 (struct wil_tx_enhanced_desc *)&desc->enhanced; 1114 1115 memset(d, 0, sizeof(struct wil_tx_enhanced_desc)); 1116 1117 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 1118 1119 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/ 1120 d->dma.length = cpu_to_le16((u16)len); 1121 d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS); 1122 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi; 1123 * 3 - eth mode 1124 */ 1125 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | 1126 (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS); 1127 1128 return 0; 1129 } 1130 1131 static inline void 1132 wil_get_next_tx_status_msg(struct wil_status_ring *sring, 1133 struct wil_ring_tx_status *msg) 1134 { 1135 struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *) 1136 (sring->va + (sring->elem_size * sring->swhead)); 1137 1138 *msg = *_msg; 1139 } 1140 1141 /** 1142 * Clean up transmitted skb's from the Tx descriptor RING. 1143 * Return number of descriptors cleared. 1144 */ 1145 int wil_tx_sring_handler(struct wil6210_priv *wil, 1146 struct wil_status_ring *sring) 1147 { 1148 struct net_device *ndev; 1149 struct device *dev = wil_to_dev(wil); 1150 struct wil_ring *ring = NULL; 1151 struct wil_ring_tx_data *txdata; 1152 /* Total number of completed descriptors in all descriptor rings */ 1153 int desc_cnt = 0; 1154 int cid; 1155 struct wil_net_stats *stats; 1156 struct wil_tx_enhanced_desc *_d; 1157 unsigned int ring_id; 1158 unsigned int num_descs; 1159 int i; 1160 u8 dr_bit; /* Descriptor Ready bit */ 1161 struct wil_ring_tx_status msg; 1162 struct wil6210_vif *vif; 1163 int used_before_complete; 1164 int used_new; 1165 1166 wil_get_next_tx_status_msg(sring, &msg); 1167 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1168 1169 /* Process completion messages while DR bit has the expected polarity */ 1170 while (dr_bit == sring->desc_rdy_pol) { 1171 num_descs = msg.num_descriptors; 1172 if (!num_descs) { 1173 wil_err(wil, "invalid num_descs 0\n"); 1174 goto again; 1175 } 1176 1177 /* Find the corresponding descriptor ring */ 1178 ring_id = msg.ring_id; 1179 1180 if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) { 1181 wil_err(wil, "invalid ring id %d\n", ring_id); 1182 goto again; 1183 } 1184 ring = &wil->ring_tx[ring_id]; 1185 if (unlikely(!ring->va)) { 1186 wil_err(wil, "Tx irq[%d]: ring not initialized\n", 1187 ring_id); 1188 goto again; 1189 } 1190 txdata = &wil->ring_tx_data[ring_id]; 1191 if (unlikely(!txdata->enabled)) { 1192 wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id); 1193 goto again; 1194 } 1195 vif = wil->vifs[txdata->mid]; 1196 if (unlikely(!vif)) { 1197 wil_dbg_txrx(wil, "invalid MID %d for ring %d\n", 1198 txdata->mid, ring_id); 1199 goto again; 1200 } 1201 1202 ndev = vif_to_ndev(vif); 1203 1204 cid = wil->ring2cid_tid[ring_id][0]; 1205 stats = (cid < wil->max_assoc_sta) ? &wil->sta[cid].stats : 1206 NULL; 1207 1208 wil_dbg_txrx(wil, 1209 "tx_status: completed desc_ring (%d), num_descs (%d)\n", 1210 ring_id, num_descs); 1211 1212 used_before_complete = wil_ring_used_tx(ring); 1213 1214 for (i = 0 ; i < num_descs; ++i) { 1215 struct wil_ctx *ctx = &ring->ctx[ring->swtail]; 1216 struct wil_tx_enhanced_desc dd, *d = ⅆ 1217 u16 dmalen; 1218 struct sk_buff *skb = ctx->skb; 1219 1220 _d = (struct wil_tx_enhanced_desc *) 1221 &ring->va[ring->swtail].tx.enhanced; 1222 *d = *_d; 1223 1224 dmalen = le16_to_cpu(d->dma.length); 1225 trace_wil6210_tx_status(&msg, ring->swtail, dmalen); 1226 wil_dbg_txrx(wil, 1227 "TxC[%2d][%3d] : %d bytes, status 0x%02x\n", 1228 ring_id, ring->swtail, dmalen, 1229 msg.status); 1230 wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4, 1231 (const void *)&msg, sizeof(msg), 1232 false); 1233 1234 wil_tx_desc_unmap_edma(dev, 1235 (union wil_tx_desc *)d, 1236 ctx); 1237 1238 if (skb) { 1239 if (likely(msg.status == 0)) { 1240 ndev->stats.tx_packets++; 1241 ndev->stats.tx_bytes += skb->len; 1242 if (stats) { 1243 stats->tx_packets++; 1244 stats->tx_bytes += skb->len; 1245 1246 wil_tx_latency_calc(wil, skb, 1247 &wil->sta[cid]); 1248 } 1249 } else { 1250 ndev->stats.tx_errors++; 1251 if (stats) 1252 stats->tx_errors++; 1253 } 1254 wil_consume_skb(skb, msg.status == 0); 1255 } 1256 memset(ctx, 0, sizeof(*ctx)); 1257 /* Make sure the ctx is zeroed before updating the tail 1258 * to prevent a case where wil_tx_ring will see 1259 * this descriptor as used and handle it before ctx zero 1260 * is completed. 1261 */ 1262 wmb(); 1263 1264 ring->swtail = wil_ring_next_tail(ring); 1265 1266 desc_cnt++; 1267 } 1268 1269 /* performance monitoring */ 1270 used_new = wil_ring_used_tx(ring); 1271 if (wil_val_in_range(wil->ring_idle_trsh, 1272 used_new, used_before_complete)) { 1273 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n", 1274 ring_id, used_before_complete, used_new); 1275 txdata->last_idle = get_cycles(); 1276 } 1277 1278 again: 1279 wil_sring_advance_swhead(sring); 1280 1281 wil_get_next_tx_status_msg(sring, &msg); 1282 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1283 } 1284 1285 /* shall we wake net queues? */ 1286 if (desc_cnt) 1287 wil_update_net_queues(wil, vif, NULL, false); 1288 1289 /* Update the HW tail ptr (RD ptr) */ 1290 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1291 1292 return desc_cnt; 1293 } 1294 1295 /** 1296 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding 1297 * @skb is used to obtain the protocol and headers length. 1298 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data, 1299 * 2 - middle, 3 - last descriptor. 1300 */ 1301 static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d, 1302 int tso_desc_type, bool is_ipv4, 1303 int tcp_hdr_len, 1304 int skb_net_hdr_len, 1305 int mss) 1306 { 1307 /* Number of descriptors */ 1308 d->mac.d[2] |= 1; 1309 /* Maximum Segment Size */ 1310 d->mac.tso_mss |= cpu_to_le16(mss >> 2); 1311 /* L4 header len: TCP header length */ 1312 d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK; 1313 /* EOP, TSO desc type, Segmentation enable, 1314 * Insert IPv4 and TCP / UDP Checksum 1315 */ 1316 d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) | 1317 tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS | 1318 BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) | 1319 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) | 1320 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS); 1321 /* Calculate pseudo-header */ 1322 d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) | 1323 BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS); 1324 /* IP Header Length */ 1325 d->dma.ip_length |= skb_net_hdr_len; 1326 /* MAC header length and IP address family*/ 1327 d->dma.b11 |= ETH_HLEN | 1328 is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; 1329 } 1330 1331 static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr, 1332 int len, uint i, int tso_desc_type, 1333 skb_frag_t *frag, struct wil_ring *ring, 1334 struct sk_buff *skb, bool is_ipv4, 1335 int tcp_hdr_len, int skb_net_hdr_len, 1336 int mss, int *descs_used) 1337 { 1338 struct device *dev = wil_to_dev(wil); 1339 struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *) 1340 &ring->va[i].tx.enhanced; 1341 struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem; 1342 int ring_index = ring - wil->ring_tx; 1343 dma_addr_t pa; 1344 1345 if (len == 0) 1346 return 0; 1347 1348 if (!frag) { 1349 pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE); 1350 ring->ctx[i].mapped_as = wil_mapped_as_single; 1351 } else { 1352 pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE); 1353 ring->ctx[i].mapped_as = wil_mapped_as_page; 1354 } 1355 if (unlikely(dma_mapping_error(dev, pa))) { 1356 wil_err(wil, "TSO: Skb DMA map error\n"); 1357 return -EINVAL; 1358 } 1359 1360 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, 1361 len, ring_index); 1362 wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4, 1363 tcp_hdr_len, 1364 skb_net_hdr_len, mss); 1365 1366 /* hold reference to skb 1367 * to prevent skb release before accounting 1368 * in case of immediate "tx done" 1369 */ 1370 if (tso_desc_type == wil_tso_type_lst) 1371 ring->ctx[i].skb = skb_get(skb); 1372 1373 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1374 (const void *)d, sizeof(*d), false); 1375 1376 *_desc = *d; 1377 (*descs_used)++; 1378 1379 return 0; 1380 } 1381 1382 static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil, 1383 struct wil6210_vif *vif, 1384 struct wil_ring *ring, 1385 struct sk_buff *skb) 1386 { 1387 int ring_index = ring - wil->ring_tx; 1388 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1389 int nr_frags = skb_shinfo(skb)->nr_frags; 1390 int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */ 1391 int used, avail = wil_ring_avail_tx(ring); 1392 int f, hdrlen, headlen; 1393 int gso_type; 1394 bool is_ipv4; 1395 u32 swhead = ring->swhead; 1396 int descs_used = 0; /* total number of used descriptors */ 1397 int rc = -EINVAL; 1398 int tcp_hdr_len; 1399 int skb_net_hdr_len; 1400 int mss = skb_shinfo(skb)->gso_size; 1401 1402 wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len, 1403 ring_index); 1404 1405 if (unlikely(!txdata->enabled)) 1406 return -EINVAL; 1407 1408 if (unlikely(avail < min_desc_required)) { 1409 wil_err_ratelimited(wil, 1410 "TSO: Tx ring[%2d] full. No space for %d fragments\n", 1411 ring_index, min_desc_required); 1412 return -ENOMEM; 1413 } 1414 1415 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4); 1416 switch (gso_type) { 1417 case SKB_GSO_TCPV4: 1418 is_ipv4 = true; 1419 break; 1420 case SKB_GSO_TCPV6: 1421 is_ipv4 = false; 1422 break; 1423 default: 1424 return -EINVAL; 1425 } 1426 1427 if (skb->ip_summed != CHECKSUM_PARTIAL) 1428 return -EINVAL; 1429 1430 /* tcp header length and skb network header length are fixed for all 1431 * packet's descriptors - read them once here 1432 */ 1433 tcp_hdr_len = tcp_hdrlen(skb); 1434 skb_net_hdr_len = skb_network_header_len(skb); 1435 1436 /* First descriptor must contain the header only 1437 * Header Length = MAC header len + IP header len + TCP header len 1438 */ 1439 hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len; 1440 wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n", 1441 hdrlen); 1442 rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead, 1443 wil_tso_type_hdr, NULL, ring, skb, 1444 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1445 mss, &descs_used); 1446 if (rc) 1447 return -EINVAL; 1448 1449 /* Second descriptor contains the head */ 1450 headlen = skb_headlen(skb) - hdrlen; 1451 wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen); 1452 rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen, 1453 (swhead + descs_used) % ring->size, 1454 (nr_frags != 0) ? wil_tso_type_first : 1455 wil_tso_type_lst, NULL, ring, skb, 1456 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1457 mss, &descs_used); 1458 if (rc) 1459 goto mem_error; 1460 1461 /* Rest of the descriptors are from the SKB fragments */ 1462 for (f = 0; f < nr_frags; f++) { 1463 skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1464 int len = frag->size; 1465 1466 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f, 1467 len, descs_used); 1468 1469 rc = wil_tx_tso_gen_desc(wil, NULL, len, 1470 (swhead + descs_used) % ring->size, 1471 (f != nr_frags - 1) ? 1472 wil_tso_type_mid : wil_tso_type_lst, 1473 frag, ring, skb, is_ipv4, 1474 tcp_hdr_len, skb_net_hdr_len, 1475 mss, &descs_used); 1476 if (rc) 1477 goto mem_error; 1478 } 1479 1480 /* performance monitoring */ 1481 used = wil_ring_used_tx(ring); 1482 if (wil_val_in_range(wil->ring_idle_trsh, 1483 used, used + descs_used)) { 1484 txdata->idle += get_cycles() - txdata->last_idle; 1485 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1486 ring_index, used, used + descs_used); 1487 } 1488 1489 /* advance swhead */ 1490 wil_ring_advance_head(ring, descs_used); 1491 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead); 1492 1493 /* make sure all writes to descriptors (shared memory) are done before 1494 * committing them to HW 1495 */ 1496 wmb(); 1497 1498 if (wil->tx_latency) 1499 *(ktime_t *)&skb->cb = ktime_get(); 1500 else 1501 memset(skb->cb, 0, sizeof(ktime_t)); 1502 1503 wil_w(wil, ring->hwtail, ring->swhead); 1504 1505 return 0; 1506 1507 mem_error: 1508 while (descs_used > 0) { 1509 struct device *dev = wil_to_dev(wil); 1510 struct wil_ctx *ctx; 1511 int i = (swhead + descs_used - 1) % ring->size; 1512 struct wil_tx_enhanced_desc dd, *d = ⅆ 1513 struct wil_tx_enhanced_desc *_desc = 1514 (struct wil_tx_enhanced_desc *) 1515 &ring->va[i].tx.enhanced; 1516 1517 *d = *_desc; 1518 ctx = &ring->ctx[i]; 1519 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 1520 memset(ctx, 0, sizeof(*ctx)); 1521 descs_used--; 1522 } 1523 return rc; 1524 } 1525 1526 static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id, 1527 int size) 1528 { 1529 struct wil6210_priv *wil = vif_to_wil(vif); 1530 struct wil_ring *ring = &wil->ring_tx[ring_id]; 1531 int rc; 1532 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 1533 1534 wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n", 1535 ring_id, wil->tx_sring_idx); 1536 1537 lockdep_assert_held(&wil->mutex); 1538 1539 wil_tx_data_init(txdata); 1540 ring->size = size; 1541 ring->is_rx = false; 1542 rc = wil_ring_alloc_desc_ring(wil, ring); 1543 if (rc) 1544 goto out; 1545 1546 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */ 1547 wil->ring2cid_tid[ring_id][1] = 0; /* TID */ 1548 if (!vif->privacy) 1549 txdata->dot1x_open = true; 1550 1551 rc = wil_wmi_bcast_desc_ring_add(vif, ring_id); 1552 if (rc) 1553 goto out_free; 1554 1555 return 0; 1556 1557 out_free: 1558 spin_lock_bh(&txdata->lock); 1559 txdata->enabled = 0; 1560 txdata->dot1x_open = false; 1561 spin_unlock_bh(&txdata->lock); 1562 wil_ring_free_edma(wil, ring); 1563 1564 out: 1565 return rc; 1566 } 1567 1568 static void wil_tx_fini_edma(struct wil6210_priv *wil) 1569 { 1570 struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx]; 1571 1572 wil_dbg_misc(wil, "free TX sring\n"); 1573 1574 wil_sring_free(wil, sring); 1575 } 1576 1577 static void wil_rx_data_free(struct wil_status_ring *sring) 1578 { 1579 if (!sring) 1580 return; 1581 1582 kfree_skb(sring->rx_data.skb); 1583 sring->rx_data.skb = NULL; 1584 } 1585 1586 static void wil_rx_fini_edma(struct wil6210_priv *wil) 1587 { 1588 struct wil_ring *ring = &wil->ring_rx; 1589 int i; 1590 1591 wil_dbg_misc(wil, "rx_fini_edma\n"); 1592 1593 wil_ring_free_edma(wil, ring); 1594 1595 for (i = 0; i < wil->num_rx_status_rings; i++) { 1596 wil_rx_data_free(&wil->srings[i]); 1597 wil_sring_free(wil, &wil->srings[i]); 1598 } 1599 1600 wil_free_rx_buff_arr(wil); 1601 } 1602 1603 void wil_init_txrx_ops_edma(struct wil6210_priv *wil) 1604 { 1605 wil->txrx_ops.configure_interrupt_moderation = 1606 wil_configure_interrupt_moderation_edma; 1607 /* TX ops */ 1608 wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma; 1609 wil->txrx_ops.ring_fini_tx = wil_ring_free_edma; 1610 wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma; 1611 wil->txrx_ops.tx_init = wil_tx_init_edma; 1612 wil->txrx_ops.tx_fini = wil_tx_fini_edma; 1613 wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma; 1614 wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma; 1615 wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma; 1616 wil->txrx_ops.tx_ring_modify = wil_tx_ring_modify_edma; 1617 /* RX ops */ 1618 wil->txrx_ops.rx_init = wil_rx_init_edma; 1619 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma; 1620 wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma; 1621 wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma; 1622 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma; 1623 wil->txrx_ops.rx_error_check = wil_rx_error_check_edma; 1624 wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma; 1625 wil->txrx_ops.rx_fini = wil_rx_fini_edma; 1626 } 1627 1628