1 /* 2 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef WIL6210_TXRX_H 19 #define WIL6210_TXRX_H 20 21 #define BUF_SW_OWNED (1) 22 #define BUF_HW_OWNED (0) 23 24 /* default size of MAC Tx/Rx buffers */ 25 #define TXRX_BUF_LEN_DEFAULT (2048) 26 27 /* how many bytes to reserve for rtap header? */ 28 #define WIL6210_RTAP_SIZE (128) 29 30 /* Tx/Rx path */ 31 32 /* Common representation of physical address in Vring */ 33 struct vring_dma_addr { 34 __le32 addr_low; 35 __le16 addr_high; 36 } __packed; 37 38 static inline dma_addr_t wil_desc_addr(struct vring_dma_addr *addr) 39 { 40 return le32_to_cpu(addr->addr_low) | 41 ((u64)le16_to_cpu(addr->addr_high) << 32); 42 } 43 44 static inline void wil_desc_addr_set(struct vring_dma_addr *addr, 45 dma_addr_t pa) 46 { 47 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); 48 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); 49 } 50 51 /* Tx descriptor - MAC part 52 * [dword 0] 53 * bit 0.. 9 : lifetime_expiry_value:10 54 * bit 10 : interrupt_en:1 55 * bit 11 : status_en:1 56 * bit 12..13 : txss_override:2 57 * bit 14 : timestamp_insertion:1 58 * bit 15 : duration_preserve:1 59 * bit 16..21 : reserved0:6 60 * bit 22..26 : mcs_index:5 61 * bit 27 : mcs_en:1 62 * bit 28..30 : reserved1:3 63 * bit 31 : sn_preserved:1 64 * [dword 1] 65 * bit 0.. 3 : pkt_mode:4 66 * bit 4 : pkt_mode_en:1 67 * bit 5 : mac_id_en:1 68 * bit 6..7 : mac_id:2 69 * bit 8..14 : reserved0:7 70 * bit 15 : ack_policy_en:1 71 * bit 16..19 : dst_index:4 72 * bit 20 : dst_index_en:1 73 * bit 21..22 : ack_policy:2 74 * bit 23 : lifetime_en:1 75 * bit 24..30 : max_retry:7 76 * bit 31 : max_retry_en:1 77 * [dword 2] 78 * bit 0.. 7 : num_of_descriptors:8 79 * bit 8..17 : reserved:10 80 * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11 81 * bit 20 : snap_hdr_insertion_en:1 82 * bit 21 : vlan_removal_en:1 83 * bit 22..31 : reserved0:10 84 * [dword 3] 85 * bit 0.. 31: ucode_cmd:32 86 */ 87 struct vring_tx_mac { 88 u32 d[3]; 89 u32 ucode_cmd; 90 } __packed; 91 92 /* TX MAC Dword 0 */ 93 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0 94 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10 95 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF 96 97 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10 98 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1 99 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400 100 101 #define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11 102 #define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1 103 #define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800 104 105 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12 106 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2 107 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000 108 109 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14 110 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1 111 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000 112 113 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15 114 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1 115 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000 116 117 #define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22 118 #define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5 119 #define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000 120 121 #define MAC_CFG_DESC_TX_0_MCS_EN_POS 27 122 #define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1 123 #define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000 124 125 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31 126 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1 127 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000 128 129 /* TX MAC Dword 1 */ 130 #define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0 131 #define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4 132 #define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF 133 134 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4 135 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1 136 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10 137 138 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_POS 5 139 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_LEN 1 140 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_MSK 0x20 141 142 #define MAC_CFG_DESC_TX_1_MAC_ID_POS 6 143 #define MAC_CFG_DESC_TX_1_MAC_ID_LEN 2 144 #define MAC_CFG_DESC_TX_1_MAC_ID_MSK 0xc0 145 146 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15 147 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1 148 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000 149 150 #define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16 151 #define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4 152 #define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000 153 154 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20 155 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1 156 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000 157 158 #define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21 159 #define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2 160 #define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000 161 162 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23 163 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1 164 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000 165 166 #define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24 167 #define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7 168 #define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000 169 170 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31 171 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1 172 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000 173 174 /* TX MAC Dword 2 */ 175 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0 176 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8 177 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF 178 179 #define MAC_CFG_DESC_TX_2_RESERVED_POS 8 180 #define MAC_CFG_DESC_TX_2_RESERVED_LEN 10 181 #define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00 182 183 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18 184 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2 185 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000 186 187 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20 188 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1 189 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000 190 191 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21 192 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1 193 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000 194 195 /* TX MAC Dword 3 */ 196 #define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0 197 #define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32 198 #define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF 199 200 /* TX DMA Dword 0 */ 201 #define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0 202 #define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8 203 #define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF 204 205 #define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8 206 #define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1 207 #define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100 208 209 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS 9 210 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN 1 211 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_MSK 0x200 212 213 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10 214 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1 215 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400 216 217 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11 218 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2 219 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800 220 221 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13 222 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1 223 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000 224 225 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14 226 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1 227 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000 228 229 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15 230 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1 231 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000 232 233 #define DMA_CFG_DESC_TX_0_QID_POS 16 234 #define DMA_CFG_DESC_TX_0_QID_LEN 5 235 #define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000 236 237 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21 238 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1 239 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000 240 241 #define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30 242 #define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2 243 #define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000 /* L4 type: 0-UDP, 2-TCP */ 244 245 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_POS 0 246 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_LEN 7 247 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_MSK 0x7F /* MAC hdr len */ 248 249 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS 7 250 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN 1 251 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK 0x80 /* 1-IPv4, 0-IPv6 */ 252 253 #define TX_DMA_STATUS_DU BIT(0) 254 255 /* Tx descriptor - DMA part 256 * [dword 0] 257 * bit 0.. 7 : l4_length:8 layer 4 length 258 * bit 8 : cmd_eop:1 This descriptor is the last one in the packet 259 * bit 9 : reserved 260 * bit 10 : cmd_dma_it:1 immediate interrupt 261 * bit 11..12 : SBD - Segment Buffer Details 262 * 00 - Header Segment 263 * 01 - First Data Segment 264 * 10 - Medium Data Segment 265 * 11 - Last Data Segment 266 * bit 13 : TSE - TCP Segmentation Enable 267 * bit 14 : IIC - Directs the HW to Insert IPv4 Checksum 268 * bit 15 : ITC - Directs the HW to Insert TCP/UDP Checksum 269 * bit 16..20 : QID - The target QID that the packet should be stored 270 * in the MAC. 271 * bit 21 : PO - Pseudo header Offload: 272 * 0 - Use the pseudo header value from the TCP checksum field 273 * 1- Calculate Pseudo header Checksum 274 * bit 22 : NC - No UDP Checksum 275 * bit 23..29 : reserved 276 * bit 30..31 : L4T - Layer 4 Type: 00 - UDP , 10 - TCP , 10, 11 - Reserved 277 * If L4Len equal 0, no L4 at all 278 * [dword 1] 279 * bit 0..31 : addr_low:32 The payload buffer low address 280 * [dword 2] 281 * bit 0..15 : addr_high:16 The payload buffer high address 282 * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum 283 * offload feature 284 * bit 24..30 : mac_length:7 285 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6 286 * [dword 3] 287 * [byte 12] error 288 * bit 0 2 : mac_status:3 289 * bit 3 7 : reserved:5 290 * [byte 13] status 291 * bit 0 : DU:1 Descriptor Used 292 * bit 1 7 : reserved:7 293 * [word 7] length 294 */ 295 struct vring_tx_dma { 296 u32 d0; 297 struct vring_dma_addr addr; 298 u8 ip_length; 299 u8 b11; /* 0..6: mac_length; 7:ip_version */ 300 u8 error; /* 0..2: err; 3..7: reserved; */ 301 u8 status; /* 0: used; 1..7; reserved */ 302 __le16 length; 303 } __packed; 304 305 /* TSO type used in dma descriptor d0 bits 11-12 */ 306 enum { 307 wil_tso_type_hdr = 0, 308 wil_tso_type_first = 1, 309 wil_tso_type_mid = 2, 310 wil_tso_type_lst = 3, 311 }; 312 313 /* Rx descriptor - MAC part 314 * [dword 0] 315 * bit 0.. 3 : tid:4 The QoS (b3-0) TID Field 316 * bit 4.. 6 : cid:3 The Source index that was found during parsing the TA. 317 * This field is used to define the source of the packet 318 * bit 7 : MAC_id_valid:1, 1 if MAC virtual number is valid. 319 * bit 8.. 9 : mid:2 The MAC virtual number 320 * bit 10..11 : frame_type:2 : The FC (b3-2) - MPDU Type 321 * (management, data, control and extension) 322 * bit 12..15 : frame_subtype:4 : The FC (b7-4) - Frame Subtype 323 * bit 16..27 : seq_number:12 The received Sequence number field 324 * bit 28..31 : extended:4 extended subtype 325 * [dword 1] 326 * bit 0.. 3 : reserved 327 * bit 4.. 5 : key_id:2 328 * bit 6 : decrypt_bypass:1 329 * bit 7 : security:1 FC (b14) 330 * bit 8.. 9 : ds_bits:2 FC (b9-8) 331 * bit 10 : a_msdu_present:1 QoS (b7) 332 * bit 11 : a_msdu_type:1 QoS (b8) 333 * bit 12 : a_mpdu:1 part of AMPDU aggregation 334 * bit 13 : broadcast:1 335 * bit 14 : mutlicast:1 336 * bit 15 : reserved:1 337 * bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet 338 * is received from 339 * bit 21..24 : mcs:4 340 * bit 25..28 : mic_icr:4 this signal tells the DMA to assert an interrupt 341 * after it writes the packet 342 * bit 29..31 : reserved:3 343 * [dword 2] 344 * bit 0.. 2 : time_slot:3 The timeslot that the MPDU is received 345 * bit 3.. 4 : fc_protocol_ver:1 The FC (b1-0) - Protocol Version 346 * bit 5 : fc_order:1 The FC Control (b15) -Order 347 * bit 6.. 7 : qos_ack_policy:2 The QoS (b6-5) ack policy Field 348 * bit 8 : esop:1 The QoS (b4) ESOP field 349 * bit 9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field 350 * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field 351 * bit 15 : qos_ac_constraint:1 QoS (b15) 352 * bit 16..31 : pn_15_0:16 low 2 bytes of PN 353 * [dword 3] 354 * bit 0..31 : pn_47_16:32 high 4 bytes of PN 355 */ 356 struct vring_rx_mac { 357 u32 d0; 358 u32 d1; 359 u16 w4; 360 u16 pn_15_0; 361 u32 pn_47_16; 362 } __packed; 363 364 /* Rx descriptor - DMA part 365 * [dword 0] 366 * bit 0.. 7 : l4_length:8 layer 4 length. The field is only valid if 367 * L4I bit is set 368 * bit 8 : cmd_eop:1 set to 1 369 * bit 9 : cmd_rt:1 set to 1 370 * bit 10 : cmd_dma_it:1 immediate interrupt 371 * bit 11..15 : reserved:5 372 * bit 16..29 : phy_info_length:14 It is valid when the PII is set. 373 * When the FFM bit is set bits 29-27 are used for for 374 * Flex Filter Match. Matching Index to one of the L2 375 * EtherType Flex Filter 376 * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field 377 * 00 - UDP, 01 - TCP, 10, 11 - reserved 378 * [dword 1] 379 * bit 0..31 : addr_low:32 The payload buffer low address 380 * [dword 2] 381 * bit 0..15 : addr_high:16 The payload buffer high address 382 * bit 16..23 : ip_length:8 The filed is valid only if the L3I bit is set 383 * bit 24..30 : mac_length:7 384 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6 385 * [dword 3] 386 * [byte 12] error 387 * bit 0 : FCS:1 388 * bit 1 : MIC:1 389 * bit 2 : Key miss:1 390 * bit 3 : Replay:1 391 * bit 4 : L3:1 IPv4 checksum 392 * bit 5 : L4:1 TCP/UDP checksum 393 * bit 6 7 : reserved:2 394 * [byte 13] status 395 * bit 0 : DU:1 Descriptor Used 396 * bit 1 : EOP:1 The descriptor indicates the End of Packet 397 * bit 2 : error:1 398 * bit 3 : MI:1 MAC Interrupt is asserted (according to parser decision) 399 * bit 4 : L3I:1 L3 identified and checksum calculated 400 * bit 5 : L4I:1 L4 identified and checksum calculated 401 * bit 6 : PII:1 PHY Info Included in the packet 402 * bit 7 : FFM:1 EtherType Flex Filter Match 403 * [word 7] length 404 */ 405 406 #define RX_DMA_D0_CMD_DMA_EOP BIT(8) 407 #define RX_DMA_D0_CMD_DMA_RT BIT(9) /* always 1 */ 408 #define RX_DMA_D0_CMD_DMA_IT BIT(10) /* interrupt */ 409 #define RX_MAC_D0_MAC_ID_VALID BIT(7) 410 411 /* Error field */ 412 #define RX_DMA_ERROR_FCS BIT(0) 413 #define RX_DMA_ERROR_MIC BIT(1) 414 #define RX_DMA_ERROR_KEY BIT(2) /* Key missing */ 415 #define RX_DMA_ERROR_REPLAY BIT(3) 416 #define RX_DMA_ERROR_L3_ERR BIT(4) 417 #define RX_DMA_ERROR_L4_ERR BIT(5) 418 419 /* Status field */ 420 #define RX_DMA_STATUS_DU BIT(0) 421 #define RX_DMA_STATUS_EOP BIT(1) 422 #define RX_DMA_STATUS_ERROR BIT(2) 423 #define RX_DMA_STATUS_MI BIT(3) /* MAC Interrupt is asserted */ 424 #define RX_DMA_STATUS_L3I BIT(4) 425 #define RX_DMA_STATUS_L4I BIT(5) 426 #define RX_DMA_STATUS_PHY_INFO BIT(6) 427 #define RX_DMA_STATUS_FFM BIT(7) /* EtherType Flex Filter Match */ 428 429 struct vring_rx_dma { 430 u32 d0; 431 struct vring_dma_addr addr; 432 u8 ip_length; 433 u8 b11; 434 u8 error; 435 u8 status; 436 __le16 length; 437 } __packed; 438 439 struct vring_tx_desc { 440 struct vring_tx_mac mac; 441 struct vring_tx_dma dma; 442 } __packed; 443 444 struct vring_rx_desc { 445 struct vring_rx_mac mac; 446 struct vring_rx_dma dma; 447 } __packed; 448 449 union vring_desc { 450 struct vring_tx_desc tx; 451 struct vring_rx_desc rx; 452 } __packed; 453 454 static inline int wil_rxdesc_tid(struct vring_rx_desc *d) 455 { 456 return WIL_GET_BITS(d->mac.d0, 0, 3); 457 } 458 459 static inline int wil_rxdesc_cid(struct vring_rx_desc *d) 460 { 461 return WIL_GET_BITS(d->mac.d0, 4, 6); 462 } 463 464 static inline int wil_rxdesc_mid(struct vring_rx_desc *d) 465 { 466 return (d->mac.d0 & RX_MAC_D0_MAC_ID_VALID) ? 467 WIL_GET_BITS(d->mac.d0, 8, 9) : 0; 468 } 469 470 static inline int wil_rxdesc_ftype(struct vring_rx_desc *d) 471 { 472 return WIL_GET_BITS(d->mac.d0, 10, 11); 473 } 474 475 static inline int wil_rxdesc_subtype(struct vring_rx_desc *d) 476 { 477 return WIL_GET_BITS(d->mac.d0, 12, 15); 478 } 479 480 /* 1-st byte (with frame type/subtype) of FC field */ 481 static inline u8 wil_rxdesc_fc1(struct vring_rx_desc *d) 482 { 483 return (u8)(WIL_GET_BITS(d->mac.d0, 10, 15) << 2); 484 } 485 486 static inline int wil_rxdesc_seq(struct vring_rx_desc *d) 487 { 488 return WIL_GET_BITS(d->mac.d0, 16, 27); 489 } 490 491 static inline int wil_rxdesc_ext_subtype(struct vring_rx_desc *d) 492 { 493 return WIL_GET_BITS(d->mac.d0, 28, 31); 494 } 495 496 static inline int wil_rxdesc_key_id(struct vring_rx_desc *d) 497 { 498 return WIL_GET_BITS(d->mac.d1, 4, 5); 499 } 500 501 static inline int wil_rxdesc_security(struct vring_rx_desc *d) 502 { 503 return WIL_GET_BITS(d->mac.d1, 7, 7); 504 } 505 506 static inline int wil_rxdesc_ds_bits(struct vring_rx_desc *d) 507 { 508 return WIL_GET_BITS(d->mac.d1, 8, 9); 509 } 510 511 static inline int wil_rxdesc_mcs(struct vring_rx_desc *d) 512 { 513 return WIL_GET_BITS(d->mac.d1, 21, 24); 514 } 515 516 static inline int wil_rxdesc_mcast(struct vring_rx_desc *d) 517 { 518 return WIL_GET_BITS(d->mac.d1, 13, 14); 519 } 520 521 static inline int wil_rxdesc_phy_length(struct vring_rx_desc *d) 522 { 523 return WIL_GET_BITS(d->dma.d0, 16, 29); 524 } 525 526 static inline struct vring_rx_desc *wil_skb_rxdesc(struct sk_buff *skb) 527 { 528 return (void *)skb->cb; 529 } 530 531 void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev); 532 void wil_rx_reorder(struct wil6210_priv *wil, struct sk_buff *skb); 533 void wil_rx_bar(struct wil6210_priv *wil, struct wil6210_vif *vif, 534 u8 cid, u8 tid, u16 seq); 535 struct wil_tid_ampdu_rx *wil_tid_ampdu_rx_alloc(struct wil6210_priv *wil, 536 int size, u16 ssn); 537 void wil_tid_ampdu_rx_free(struct wil6210_priv *wil, 538 struct wil_tid_ampdu_rx *r); 539 540 #endif /* WIL6210_TXRX_H */ 541