1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/interrupt.h> 19 20 #include "wil6210.h" 21 #include "trace.h" 22 23 /** 24 * Theory of operation: 25 * 26 * There is ISR pseudo-cause register, 27 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE 28 * Its bits represents OR'ed bits from 3 real ISR registers: 29 * TX, RX, and MISC. 30 * 31 * Registers may be configured to either "write 1 to clear" or 32 * "clear on read" mode 33 * 34 * When handling interrupt, one have to mask/unmask interrupts for the 35 * real ISR registers, or hardware may malfunction. 36 * 37 */ 38 39 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL) 40 #define WIL6210_IRQ_DISABLE_NO_HALP (0xF7FFFFFFUL) 41 #define WIL6210_IMC_RX (BIT_DMA_EP_RX_ICR_RX_DONE | \ 42 BIT_DMA_EP_RX_ICR_RX_HTRSH) 43 #define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \ 44 (~(BIT_DMA_EP_RX_ICR_RX_HTRSH))) 45 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \ 46 BIT_DMA_EP_TX_ICR_TX_DONE_N(0)) 47 #define WIL6210_IMC_MISC_NO_HALP (ISR_MISC_FW_READY | \ 48 ISR_MISC_MBOX_EVT | \ 49 ISR_MISC_FW_ERROR) 50 #define WIL6210_IMC_MISC (WIL6210_IMC_MISC_NO_HALP | \ 51 BIT_DMA_EP_MISC_ICR_HALP) 52 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \ 53 BIT_DMA_PSEUDO_CAUSE_TX | \ 54 BIT_DMA_PSEUDO_CAUSE_MISC)) 55 56 #if defined(CONFIG_WIL6210_ISR_COR) 57 /* configure to Clear-On-Read mode */ 58 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL) 59 #define WIL_ICR_ICC_MISC_VALUE (0xF7FFFFFFUL) 60 61 static inline void wil_icr_clear(u32 x, void __iomem *addr) 62 { 63 } 64 #else /* defined(CONFIG_WIL6210_ISR_COR) */ 65 /* configure to Write-1-to-Clear mode */ 66 #define WIL_ICR_ICC_VALUE (0UL) 67 #define WIL_ICR_ICC_MISC_VALUE (0UL) 68 69 static inline void wil_icr_clear(u32 x, void __iomem *addr) 70 { 71 writel(x, addr); 72 } 73 #endif /* defined(CONFIG_WIL6210_ISR_COR) */ 74 75 static inline u32 wil_ioread32_and_clear(void __iomem *addr) 76 { 77 u32 x = readl(addr); 78 79 wil_icr_clear(x, addr); 80 81 return x; 82 } 83 84 static void wil6210_mask_irq_tx(struct wil6210_priv *wil) 85 { 86 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS), 87 WIL6210_IRQ_DISABLE); 88 } 89 90 static void wil6210_mask_irq_rx(struct wil6210_priv *wil) 91 { 92 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS), 93 WIL6210_IRQ_DISABLE); 94 } 95 96 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp) 97 { 98 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n", 99 mask_halp ? "true" : "false"); 100 101 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), 102 mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP); 103 } 104 105 void wil6210_mask_halp(struct wil6210_priv *wil) 106 { 107 wil_dbg_irq(wil, "mask_halp\n"); 108 109 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), 110 BIT_DMA_EP_MISC_ICR_HALP); 111 } 112 113 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil) 114 { 115 wil_dbg_irq(wil, "mask_irq_pseudo\n"); 116 117 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE); 118 119 clear_bit(wil_status_irqen, wil->status); 120 } 121 122 void wil6210_unmask_irq_tx(struct wil6210_priv *wil) 123 { 124 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC), 125 WIL6210_IMC_TX); 126 } 127 128 void wil6210_unmask_irq_rx(struct wil6210_priv *wil) 129 { 130 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0; 131 132 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC), 133 unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH); 134 } 135 136 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp) 137 { 138 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n", 139 unmask_halp ? "true" : "false"); 140 141 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), 142 unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP); 143 } 144 145 static void wil6210_unmask_halp(struct wil6210_priv *wil) 146 { 147 wil_dbg_irq(wil, "unmask_halp\n"); 148 149 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), 150 BIT_DMA_EP_MISC_ICR_HALP); 151 } 152 153 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) 154 { 155 wil_dbg_irq(wil, "unmask_irq_pseudo\n"); 156 157 set_bit(wil_status_irqen, wil->status); 158 159 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK); 160 } 161 162 void wil_mask_irq(struct wil6210_priv *wil) 163 { 164 wil_dbg_irq(wil, "mask_irq\n"); 165 166 wil6210_mask_irq_tx(wil); 167 wil6210_mask_irq_rx(wil); 168 wil6210_mask_irq_misc(wil, true); 169 wil6210_mask_irq_pseudo(wil); 170 } 171 172 void wil_unmask_irq(struct wil6210_priv *wil) 173 { 174 wil_dbg_irq(wil, "unmask_irq\n"); 175 176 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC), 177 WIL_ICR_ICC_VALUE); 178 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC), 179 WIL_ICR_ICC_VALUE); 180 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC), 181 WIL_ICR_ICC_MISC_VALUE); 182 183 wil6210_unmask_irq_pseudo(wil); 184 wil6210_unmask_irq_tx(wil); 185 wil6210_unmask_irq_rx(wil); 186 wil6210_unmask_irq_misc(wil, true); 187 } 188 189 void wil_configure_interrupt_moderation(struct wil6210_priv *wil) 190 { 191 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr; 192 193 wil_dbg_irq(wil, "configure_interrupt_moderation\n"); 194 195 /* disable interrupt moderation for monitor 196 * to get better timestamp precision 197 */ 198 if (wdev->iftype == NL80211_IFTYPE_MONITOR) 199 return; 200 201 /* Disable and clear tx counter before (re)configuration */ 202 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR); 203 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration); 204 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n", 205 wil->tx_max_burst_duration); 206 /* Configure TX max burst duration timer to use usec units */ 207 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, 208 BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL); 209 210 /* Disable and clear tx idle counter before (re)configuration */ 211 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR); 212 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout); 213 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n", 214 wil->tx_interframe_timeout); 215 /* Configure TX max burst duration timer to use usec units */ 216 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN | 217 BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL); 218 219 /* Disable and clear rx counter before (re)configuration */ 220 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR); 221 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration); 222 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n", 223 wil->rx_max_burst_duration); 224 /* Configure TX max burst duration timer to use usec units */ 225 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, 226 BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL); 227 228 /* Disable and clear rx idle counter before (re)configuration */ 229 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR); 230 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout); 231 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n", 232 wil->rx_interframe_timeout); 233 /* Configure TX max burst duration timer to use usec units */ 234 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN | 235 BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL); 236 } 237 238 static irqreturn_t wil6210_irq_rx(int irq, void *cookie) 239 { 240 struct wil6210_priv *wil = cookie; 241 u32 isr = wil_ioread32_and_clear(wil->csr + 242 HOSTADDR(RGF_DMA_EP_RX_ICR) + 243 offsetof(struct RGF_ICR, ICR)); 244 bool need_unmask = true; 245 246 trace_wil6210_irq_rx(isr); 247 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); 248 249 if (unlikely(!isr)) { 250 wil_err_ratelimited(wil, "spurious IRQ: RX\n"); 251 return IRQ_NONE; 252 } 253 254 wil6210_mask_irq_rx(wil); 255 256 /* RX_DONE and RX_HTRSH interrupts are the same if interrupt 257 * moderation is not used. Interrupt moderation may cause RX 258 * buffer overflow while RX_DONE is delayed. The required 259 * action is always the same - should empty the accumulated 260 * packets from the RX ring. 261 */ 262 if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE | 263 BIT_DMA_EP_RX_ICR_RX_HTRSH))) { 264 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n", 265 isr); 266 267 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE | 268 BIT_DMA_EP_RX_ICR_RX_HTRSH); 269 if (likely(test_bit(wil_status_fwready, wil->status))) { 270 if (likely(test_bit(wil_status_napi_en, wil->status))) { 271 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); 272 need_unmask = false; 273 napi_schedule(&wil->napi_rx); 274 } else { 275 wil_err_ratelimited( 276 wil, 277 "Got Rx interrupt while stopping interface\n"); 278 } 279 } else { 280 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n"); 281 } 282 } 283 284 if (unlikely(isr)) 285 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); 286 287 /* Rx IRQ will be enabled when NAPI processing finished */ 288 289 atomic_inc(&wil->isr_count_rx); 290 291 if (unlikely(need_unmask)) 292 wil6210_unmask_irq_rx(wil); 293 294 return IRQ_HANDLED; 295 } 296 297 static irqreturn_t wil6210_irq_tx(int irq, void *cookie) 298 { 299 struct wil6210_priv *wil = cookie; 300 u32 isr = wil_ioread32_and_clear(wil->csr + 301 HOSTADDR(RGF_DMA_EP_TX_ICR) + 302 offsetof(struct RGF_ICR, ICR)); 303 bool need_unmask = true; 304 305 trace_wil6210_irq_tx(isr); 306 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); 307 308 if (unlikely(!isr)) { 309 wil_err_ratelimited(wil, "spurious IRQ: TX\n"); 310 return IRQ_NONE; 311 } 312 313 wil6210_mask_irq_tx(wil); 314 315 if (likely(isr & BIT_DMA_EP_TX_ICR_TX_DONE)) { 316 wil_dbg_irq(wil, "TX done\n"); 317 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE; 318 /* clear also all VRING interrupts */ 319 isr &= ~(BIT(25) - 1UL); 320 if (likely(test_bit(wil_status_fwready, wil->status))) { 321 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); 322 need_unmask = false; 323 napi_schedule(&wil->napi_tx); 324 } else { 325 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n"); 326 } 327 } 328 329 if (unlikely(isr)) 330 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n", 331 isr); 332 333 /* Tx IRQ will be enabled when NAPI processing finished */ 334 335 atomic_inc(&wil->isr_count_tx); 336 337 if (unlikely(need_unmask)) 338 wil6210_unmask_irq_tx(wil); 339 340 return IRQ_HANDLED; 341 } 342 343 static void wil_notify_fw_error(struct wil6210_priv *wil) 344 { 345 struct device *dev = &wil->main_ndev->dev; 346 char *envp[3] = { 347 [0] = "SOURCE=wil6210", 348 [1] = "EVENT=FW_ERROR", 349 [2] = NULL, 350 }; 351 wil_err(wil, "Notify about firmware error\n"); 352 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp); 353 } 354 355 static void wil_cache_mbox_regs(struct wil6210_priv *wil) 356 { 357 /* make shadow copy of registers that should not change on run time */ 358 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, 359 sizeof(struct wil6210_mbox_ctl)); 360 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx); 361 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx); 362 } 363 364 static bool wil_validate_mbox_regs(struct wil6210_priv *wil) 365 { 366 size_t min_size = sizeof(struct wil6210_mbox_hdr) + 367 sizeof(struct wmi_cmd_hdr); 368 369 if (wil->mbox_ctl.rx.entry_size < min_size) { 370 wil_err(wil, "rx mbox entry too small (%d)\n", 371 wil->mbox_ctl.rx.entry_size); 372 return false; 373 } 374 if (wil->mbox_ctl.tx.entry_size < min_size) { 375 wil_err(wil, "tx mbox entry too small (%d)\n", 376 wil->mbox_ctl.tx.entry_size); 377 return false; 378 } 379 380 return true; 381 } 382 383 static irqreturn_t wil6210_irq_misc(int irq, void *cookie) 384 { 385 struct wil6210_priv *wil = cookie; 386 u32 isr = wil_ioread32_and_clear(wil->csr + 387 HOSTADDR(RGF_DMA_EP_MISC_ICR) + 388 offsetof(struct RGF_ICR, ICR)); 389 390 trace_wil6210_irq_misc(isr); 391 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr); 392 393 if (!isr) { 394 wil_err(wil, "spurious IRQ: MISC\n"); 395 return IRQ_NONE; 396 } 397 398 wil6210_mask_irq_misc(wil, false); 399 400 if (isr & ISR_MISC_FW_ERROR) { 401 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr); 402 u32 ucode_assert_code = 403 wil_r(wil, wil->rgf_ucode_assert_code_addr); 404 405 wil_err(wil, 406 "Firmware error detected, assert codes FW 0x%08x, UCODE 0x%08x\n", 407 fw_assert_code, ucode_assert_code); 408 clear_bit(wil_status_fwready, wil->status); 409 /* 410 * do not clear @isr here - we do 2-nd part in thread 411 * there, user space get notified, and it should be done 412 * in non-atomic context 413 */ 414 } 415 416 if (isr & ISR_MISC_FW_READY) { 417 wil_dbg_irq(wil, "IRQ: FW ready\n"); 418 wil_cache_mbox_regs(wil); 419 if (wil_validate_mbox_regs(wil)) 420 set_bit(wil_status_mbox_ready, wil->status); 421 /** 422 * Actual FW ready indicated by the 423 * WMI_FW_READY_EVENTID 424 */ 425 isr &= ~ISR_MISC_FW_READY; 426 } 427 428 if (isr & BIT_DMA_EP_MISC_ICR_HALP) { 429 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n"); 430 wil6210_mask_halp(wil); 431 isr &= ~BIT_DMA_EP_MISC_ICR_HALP; 432 complete(&wil->halp.comp); 433 } 434 435 wil->isr_misc = isr; 436 437 if (isr) { 438 return IRQ_WAKE_THREAD; 439 } else { 440 wil6210_unmask_irq_misc(wil, false); 441 return IRQ_HANDLED; 442 } 443 } 444 445 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie) 446 { 447 struct wil6210_priv *wil = cookie; 448 u32 isr = wil->isr_misc; 449 450 trace_wil6210_irq_misc_thread(isr); 451 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr); 452 453 if (isr & ISR_MISC_FW_ERROR) { 454 wil->recovery_state = fw_recovery_pending; 455 wil_fw_core_dump(wil); 456 wil_notify_fw_error(wil); 457 isr &= ~ISR_MISC_FW_ERROR; 458 if (wil->platform_ops.notify) { 459 wil_err(wil, "notify platform driver about FW crash"); 460 wil->platform_ops.notify(wil->platform_handle, 461 WIL_PLATFORM_EVT_FW_CRASH); 462 } else { 463 wil_fw_error_recovery(wil); 464 } 465 } 466 if (isr & ISR_MISC_MBOX_EVT) { 467 wil_dbg_irq(wil, "MBOX event\n"); 468 wmi_recv_cmd(wil); 469 isr &= ~ISR_MISC_MBOX_EVT; 470 } 471 472 if (isr) 473 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); 474 475 wil->isr_misc = 0; 476 477 wil6210_unmask_irq_misc(wil, false); 478 479 return IRQ_HANDLED; 480 } 481 482 /** 483 * thread IRQ handler 484 */ 485 static irqreturn_t wil6210_thread_irq(int irq, void *cookie) 486 { 487 struct wil6210_priv *wil = cookie; 488 489 wil_dbg_irq(wil, "Thread IRQ\n"); 490 /* Discover real IRQ cause */ 491 if (wil->isr_misc) 492 wil6210_irq_misc_thread(irq, cookie); 493 494 wil6210_unmask_irq_pseudo(wil); 495 496 if (wil->suspend_resp_rcvd) { 497 wil_dbg_irq(wil, "set suspend_resp_comp to true\n"); 498 wil->suspend_resp_comp = true; 499 wake_up_interruptible(&wil->wq); 500 } 501 502 return IRQ_HANDLED; 503 } 504 505 /* DEBUG 506 * There is subtle bug in hardware that causes IRQ to raise when it should be 507 * masked. It is quite rare and hard to debug. 508 * 509 * Catch irq issue if it happens and print all I can. 510 */ 511 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) 512 { 513 if (!test_bit(wil_status_irqen, wil->status)) { 514 u32 icm_rx = wil_ioread32_and_clear(wil->csr + 515 HOSTADDR(RGF_DMA_EP_RX_ICR) + 516 offsetof(struct RGF_ICR, ICM)); 517 u32 icr_rx = wil_ioread32_and_clear(wil->csr + 518 HOSTADDR(RGF_DMA_EP_RX_ICR) + 519 offsetof(struct RGF_ICR, ICR)); 520 u32 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR + 521 offsetof(struct RGF_ICR, IMV)); 522 u32 icm_tx = wil_ioread32_and_clear(wil->csr + 523 HOSTADDR(RGF_DMA_EP_TX_ICR) + 524 offsetof(struct RGF_ICR, ICM)); 525 u32 icr_tx = wil_ioread32_and_clear(wil->csr + 526 HOSTADDR(RGF_DMA_EP_TX_ICR) + 527 offsetof(struct RGF_ICR, ICR)); 528 u32 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR + 529 offsetof(struct RGF_ICR, IMV)); 530 u32 icm_misc = wil_ioread32_and_clear(wil->csr + 531 HOSTADDR(RGF_DMA_EP_MISC_ICR) + 532 offsetof(struct RGF_ICR, ICM)); 533 u32 icr_misc = wil_ioread32_and_clear(wil->csr + 534 HOSTADDR(RGF_DMA_EP_MISC_ICR) + 535 offsetof(struct RGF_ICR, ICR)); 536 u32 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR + 537 offsetof(struct RGF_ICR, IMV)); 538 539 /* HALP interrupt can be unmasked when misc interrupts are 540 * masked 541 */ 542 if (icr_misc & BIT_DMA_EP_MISC_ICR_HALP) 543 return 0; 544 545 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n" 546 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" 547 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" 548 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n", 549 pseudo_cause, 550 icm_rx, icr_rx, imv_rx, 551 icm_tx, icr_tx, imv_tx, 552 icm_misc, icr_misc, imv_misc); 553 554 return -EINVAL; 555 } 556 557 return 0; 558 } 559 560 static irqreturn_t wil6210_hardirq(int irq, void *cookie) 561 { 562 irqreturn_t rc = IRQ_HANDLED; 563 struct wil6210_priv *wil = cookie; 564 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE); 565 566 /** 567 * pseudo_cause is Clear-On-Read, no need to ACK 568 */ 569 if (unlikely((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))) 570 return IRQ_NONE; 571 572 /* IRQ mask debug */ 573 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause))) 574 return IRQ_NONE; 575 576 trace_wil6210_irq_pseudo(pseudo_cause); 577 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause); 578 579 wil6210_mask_irq_pseudo(wil); 580 581 /* Discover real IRQ cause 582 * There are 2 possible phases for every IRQ: 583 * - hard IRQ handler called right here 584 * - threaded handler called later 585 * 586 * Hard IRQ handler reads and clears ISR. 587 * 588 * If threaded handler requested, hard IRQ handler 589 * returns IRQ_WAKE_THREAD and saves ISR register value 590 * for the threaded handler use. 591 * 592 * voting for wake thread - need at least 1 vote 593 */ 594 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) && 595 (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD)) 596 rc = IRQ_WAKE_THREAD; 597 598 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) && 599 (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD)) 600 rc = IRQ_WAKE_THREAD; 601 602 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) && 603 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD)) 604 rc = IRQ_WAKE_THREAD; 605 606 /* if thread is requested, it will unmask IRQ */ 607 if (rc != IRQ_WAKE_THREAD) 608 wil6210_unmask_irq_pseudo(wil); 609 610 return rc; 611 } 612 613 /* can't use wil_ioread32_and_clear because ICC value is not set yet */ 614 static inline void wil_clear32(void __iomem *addr) 615 { 616 u32 x = readl(addr); 617 618 writel(x, addr); 619 } 620 621 void wil6210_clear_irq(struct wil6210_priv *wil) 622 { 623 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + 624 offsetof(struct RGF_ICR, ICR)); 625 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + 626 offsetof(struct RGF_ICR, ICR)); 627 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + 628 offsetof(struct RGF_ICR, ICR)); 629 wmb(); /* make sure write completed */ 630 } 631 632 void wil6210_set_halp(struct wil6210_priv *wil) 633 { 634 wil_dbg_irq(wil, "set_halp\n"); 635 636 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS), 637 BIT_DMA_EP_MISC_ICR_HALP); 638 } 639 640 void wil6210_clear_halp(struct wil6210_priv *wil) 641 { 642 wil_dbg_irq(wil, "clear_halp\n"); 643 644 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR), 645 BIT_DMA_EP_MISC_ICR_HALP); 646 wil6210_unmask_halp(wil); 647 } 648 649 int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi) 650 { 651 int rc; 652 653 wil_dbg_misc(wil, "init_irq: %s\n", use_msi ? "MSI" : "INTx"); 654 655 rc = request_threaded_irq(irq, wil6210_hardirq, 656 wil6210_thread_irq, 657 use_msi ? 0 : IRQF_SHARED, 658 WIL_NAME, wil); 659 return rc; 660 } 661 662 void wil6210_fini_irq(struct wil6210_priv *wil, int irq) 663 { 664 wil_dbg_misc(wil, "fini_irq:\n"); 665 666 wil_mask_irq(wil); 667 free_irq(irq, wil); 668 } 669