1 /* 2 * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /* DXE - DMA transfer engine 18 * we have 2 channels(High prio and Low prio) for TX and 2 channels for RX. 19 * through low channels data packets are transfered 20 * through high channels managment packets are transfered 21 */ 22 23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 24 25 #include <linux/interrupt.h> 26 #include <linux/soc/qcom/smem_state.h> 27 #include "wcn36xx.h" 28 #include "txrx.h" 29 30 static void wcn36xx_ccu_write_register(struct wcn36xx *wcn, int addr, int data) 31 { 32 wcn36xx_dbg(WCN36XX_DBG_DXE, 33 "wcn36xx_ccu_write_register: addr=%x, data=%x\n", 34 addr, data); 35 36 writel(data, wcn->ccu_base + addr); 37 } 38 39 static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data) 40 { 41 wcn36xx_dbg(WCN36XX_DBG_DXE, 42 "wcn36xx_dxe_write_register: addr=%x, data=%x\n", 43 addr, data); 44 45 writel(data, wcn->dxe_base + addr); 46 } 47 48 static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data) 49 { 50 *data = readl(wcn->dxe_base + addr); 51 52 wcn36xx_dbg(WCN36XX_DBG_DXE, 53 "wcn36xx_dxe_read_register: addr=%x, data=%x\n", 54 addr, *data); 55 } 56 57 static void wcn36xx_dxe_free_ctl_block(struct wcn36xx_dxe_ch *ch) 58 { 59 struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl, *next; 60 int i; 61 62 for (i = 0; i < ch->desc_num && ctl; i++) { 63 next = ctl->next; 64 kfree(ctl); 65 ctl = next; 66 } 67 } 68 69 static int wcn36xx_dxe_allocate_ctl_block(struct wcn36xx_dxe_ch *ch) 70 { 71 struct wcn36xx_dxe_ctl *prev_ctl = NULL; 72 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 73 int i; 74 75 spin_lock_init(&ch->lock); 76 for (i = 0; i < ch->desc_num; i++) { 77 cur_ctl = kzalloc(sizeof(*cur_ctl), GFP_KERNEL); 78 if (!cur_ctl) 79 goto out_fail; 80 81 cur_ctl->ctl_blk_order = i; 82 if (i == 0) { 83 ch->head_blk_ctl = cur_ctl; 84 ch->tail_blk_ctl = cur_ctl; 85 } else if (ch->desc_num - 1 == i) { 86 prev_ctl->next = cur_ctl; 87 cur_ctl->next = ch->head_blk_ctl; 88 } else { 89 prev_ctl->next = cur_ctl; 90 } 91 prev_ctl = cur_ctl; 92 } 93 94 return 0; 95 96 out_fail: 97 wcn36xx_dxe_free_ctl_block(ch); 98 return -ENOMEM; 99 } 100 101 int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn) 102 { 103 int ret; 104 105 wcn->dxe_tx_l_ch.ch_type = WCN36XX_DXE_CH_TX_L; 106 wcn->dxe_tx_h_ch.ch_type = WCN36XX_DXE_CH_TX_H; 107 wcn->dxe_rx_l_ch.ch_type = WCN36XX_DXE_CH_RX_L; 108 wcn->dxe_rx_h_ch.ch_type = WCN36XX_DXE_CH_RX_H; 109 110 wcn->dxe_tx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_L; 111 wcn->dxe_tx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_H; 112 wcn->dxe_rx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_L; 113 wcn->dxe_rx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_H; 114 115 wcn->dxe_tx_l_ch.dxe_wq = WCN36XX_DXE_WQ_TX_L; 116 wcn->dxe_tx_h_ch.dxe_wq = WCN36XX_DXE_WQ_TX_H; 117 118 wcn->dxe_tx_l_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_L_BD; 119 wcn->dxe_tx_h_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_H_BD; 120 121 wcn->dxe_tx_l_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_L_SKB; 122 wcn->dxe_tx_h_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_H_SKB; 123 124 wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L; 125 wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H; 126 127 wcn->dxe_tx_l_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_L; 128 wcn->dxe_tx_h_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_H; 129 130 /* DXE control block allocation */ 131 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_l_ch); 132 if (ret) 133 goto out_err; 134 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_h_ch); 135 if (ret) 136 goto out_err; 137 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_l_ch); 138 if (ret) 139 goto out_err; 140 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_h_ch); 141 if (ret) 142 goto out_err; 143 144 /* Initialize SMSM state Clear TX Enable RING EMPTY STATE */ 145 ret = qcom_smem_state_update_bits(wcn->tx_enable_state, 146 WCN36XX_SMSM_WLAN_TX_ENABLE | 147 WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY, 148 WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY); 149 if (ret) 150 goto out_err; 151 152 return 0; 153 154 out_err: 155 wcn36xx_err("Failed to allocate DXE control blocks\n"); 156 wcn36xx_dxe_free_ctl_blks(wcn); 157 return -ENOMEM; 158 } 159 160 void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn) 161 { 162 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_l_ch); 163 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_h_ch); 164 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_l_ch); 165 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_h_ch); 166 } 167 168 static int wcn36xx_dxe_init_descs(struct device *dev, struct wcn36xx_dxe_ch *wcn_ch) 169 { 170 struct wcn36xx_dxe_desc *cur_dxe = NULL; 171 struct wcn36xx_dxe_desc *prev_dxe = NULL; 172 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 173 size_t size; 174 int i; 175 176 size = wcn_ch->desc_num * sizeof(struct wcn36xx_dxe_desc); 177 wcn_ch->cpu_addr = dma_alloc_coherent(dev, size, &wcn_ch->dma_addr, 178 GFP_KERNEL); 179 if (!wcn_ch->cpu_addr) 180 return -ENOMEM; 181 182 cur_dxe = (struct wcn36xx_dxe_desc *)wcn_ch->cpu_addr; 183 cur_ctl = wcn_ch->head_blk_ctl; 184 185 for (i = 0; i < wcn_ch->desc_num; i++) { 186 cur_ctl->desc = cur_dxe; 187 cur_ctl->desc_phy_addr = wcn_ch->dma_addr + 188 i * sizeof(struct wcn36xx_dxe_desc); 189 190 switch (wcn_ch->ch_type) { 191 case WCN36XX_DXE_CH_TX_L: 192 cur_dxe->ctrl = WCN36XX_DXE_CTRL_TX_L; 193 cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_L; 194 break; 195 case WCN36XX_DXE_CH_TX_H: 196 cur_dxe->ctrl = WCN36XX_DXE_CTRL_TX_H; 197 cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_H; 198 break; 199 case WCN36XX_DXE_CH_RX_L: 200 cur_dxe->ctrl = WCN36XX_DXE_CTRL_RX_L; 201 cur_dxe->src_addr_l = WCN36XX_DXE_WQ_RX_L; 202 break; 203 case WCN36XX_DXE_CH_RX_H: 204 cur_dxe->ctrl = WCN36XX_DXE_CTRL_RX_H; 205 cur_dxe->src_addr_l = WCN36XX_DXE_WQ_RX_H; 206 break; 207 } 208 if (0 == i) { 209 cur_dxe->phy_next_l = 0; 210 } else if ((0 < i) && (i < wcn_ch->desc_num - 1)) { 211 prev_dxe->phy_next_l = 212 cur_ctl->desc_phy_addr; 213 } else if (i == (wcn_ch->desc_num - 1)) { 214 prev_dxe->phy_next_l = 215 cur_ctl->desc_phy_addr; 216 cur_dxe->phy_next_l = 217 wcn_ch->head_blk_ctl->desc_phy_addr; 218 } 219 cur_ctl = cur_ctl->next; 220 prev_dxe = cur_dxe; 221 cur_dxe++; 222 } 223 224 return 0; 225 } 226 227 static void wcn36xx_dxe_deinit_descs(struct device *dev, struct wcn36xx_dxe_ch *wcn_ch) 228 { 229 size_t size; 230 231 size = wcn_ch->desc_num * sizeof(struct wcn36xx_dxe_desc); 232 dma_free_coherent(dev, size,wcn_ch->cpu_addr, wcn_ch->dma_addr); 233 } 234 235 static void wcn36xx_dxe_init_tx_bd(struct wcn36xx_dxe_ch *ch, 236 struct wcn36xx_dxe_mem_pool *pool) 237 { 238 int i, chunk_size = pool->chunk_size; 239 dma_addr_t bd_phy_addr = pool->phy_addr; 240 void *bd_cpu_addr = pool->virt_addr; 241 struct wcn36xx_dxe_ctl *cur = ch->head_blk_ctl; 242 243 for (i = 0; i < ch->desc_num; i++) { 244 /* Only every second dxe needs a bd pointer, 245 the other will point to the skb data */ 246 if (!(i & 1)) { 247 cur->bd_phy_addr = bd_phy_addr; 248 cur->bd_cpu_addr = bd_cpu_addr; 249 bd_phy_addr += chunk_size; 250 bd_cpu_addr += chunk_size; 251 } else { 252 cur->bd_phy_addr = 0; 253 cur->bd_cpu_addr = NULL; 254 } 255 cur = cur->next; 256 } 257 } 258 259 static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch) 260 { 261 int reg_data = 0; 262 263 wcn36xx_dxe_read_register(wcn, 264 WCN36XX_DXE_INT_MASK_REG, 265 ®_data); 266 267 reg_data |= wcn_ch; 268 269 wcn36xx_dxe_write_register(wcn, 270 WCN36XX_DXE_INT_MASK_REG, 271 (int)reg_data); 272 return 0; 273 } 274 275 static int wcn36xx_dxe_fill_skb(struct device *dev, 276 struct wcn36xx_dxe_ctl *ctl, 277 gfp_t gfp) 278 { 279 struct wcn36xx_dxe_desc *dxe = ctl->desc; 280 struct sk_buff *skb; 281 282 skb = alloc_skb(WCN36XX_PKT_SIZE, gfp); 283 if (skb == NULL) 284 return -ENOMEM; 285 286 dxe->dst_addr_l = dma_map_single(dev, 287 skb_tail_pointer(skb), 288 WCN36XX_PKT_SIZE, 289 DMA_FROM_DEVICE); 290 if (dma_mapping_error(dev, dxe->dst_addr_l)) { 291 dev_err(dev, "unable to map skb\n"); 292 kfree_skb(skb); 293 return -ENOMEM; 294 } 295 ctl->skb = skb; 296 297 return 0; 298 } 299 300 static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn, 301 struct wcn36xx_dxe_ch *wcn_ch) 302 { 303 int i; 304 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 305 306 cur_ctl = wcn_ch->head_blk_ctl; 307 308 for (i = 0; i < wcn_ch->desc_num; i++) { 309 wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl, GFP_KERNEL); 310 cur_ctl = cur_ctl->next; 311 } 312 313 return 0; 314 } 315 316 static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn, 317 struct wcn36xx_dxe_ch *wcn_ch) 318 { 319 struct wcn36xx_dxe_ctl *cur = wcn_ch->head_blk_ctl; 320 int i; 321 322 for (i = 0; i < wcn_ch->desc_num; i++) { 323 kfree_skb(cur->skb); 324 cur = cur->next; 325 } 326 } 327 328 void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status) 329 { 330 struct ieee80211_tx_info *info; 331 struct sk_buff *skb; 332 unsigned long flags; 333 334 spin_lock_irqsave(&wcn->dxe_lock, flags); 335 skb = wcn->tx_ack_skb; 336 wcn->tx_ack_skb = NULL; 337 del_timer(&wcn->tx_ack_timer); 338 spin_unlock_irqrestore(&wcn->dxe_lock, flags); 339 340 if (!skb) { 341 wcn36xx_warn("Spurious TX complete indication\n"); 342 return; 343 } 344 345 info = IEEE80211_SKB_CB(skb); 346 347 if (status == 1) 348 info->flags |= IEEE80211_TX_STAT_ACK; 349 else 350 info->flags &= ~IEEE80211_TX_STAT_ACK; 351 352 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ack status: %d\n", status); 353 354 ieee80211_tx_status_irqsafe(wcn->hw, skb); 355 ieee80211_wake_queues(wcn->hw); 356 } 357 358 static void wcn36xx_dxe_tx_timer(struct timer_list *t) 359 { 360 struct wcn36xx *wcn = from_timer(wcn, t, tx_ack_timer); 361 struct ieee80211_tx_info *info; 362 unsigned long flags; 363 struct sk_buff *skb; 364 365 /* TX Timeout */ 366 wcn36xx_dbg(WCN36XX_DBG_DXE, "TX timeout\n"); 367 368 spin_lock_irqsave(&wcn->dxe_lock, flags); 369 skb = wcn->tx_ack_skb; 370 wcn->tx_ack_skb = NULL; 371 spin_unlock_irqrestore(&wcn->dxe_lock, flags); 372 373 if (!skb) 374 return; 375 376 info = IEEE80211_SKB_CB(skb); 377 info->flags &= ~IEEE80211_TX_STAT_ACK; 378 info->flags &= ~IEEE80211_TX_STAT_NOACK_TRANSMITTED; 379 380 ieee80211_tx_status_irqsafe(wcn->hw, skb); 381 ieee80211_wake_queues(wcn->hw); 382 } 383 384 static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch) 385 { 386 struct wcn36xx_dxe_ctl *ctl; 387 struct ieee80211_tx_info *info; 388 unsigned long flags; 389 390 /* 391 * Make at least one loop of do-while because in case ring is 392 * completely full head and tail are pointing to the same element 393 * and while-do will not make any cycles. 394 */ 395 spin_lock_irqsave(&ch->lock, flags); 396 ctl = ch->tail_blk_ctl; 397 do { 398 if (READ_ONCE(ctl->desc->ctrl) & WCN36xx_DXE_CTRL_VLD) 399 break; 400 401 if (ctl->skb && 402 READ_ONCE(ctl->desc->ctrl) & WCN36xx_DXE_CTRL_EOP) { 403 dma_unmap_single(wcn->dev, ctl->desc->src_addr_l, 404 ctl->skb->len, DMA_TO_DEVICE); 405 info = IEEE80211_SKB_CB(ctl->skb); 406 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 407 if (info->flags & IEEE80211_TX_CTL_NO_ACK) { 408 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 409 ieee80211_tx_status_irqsafe(wcn->hw, ctl->skb); 410 } else { 411 /* Wait for the TX ack indication or timeout... */ 412 spin_lock(&wcn->dxe_lock); 413 if (WARN_ON(wcn->tx_ack_skb)) 414 ieee80211_free_txskb(wcn->hw, wcn->tx_ack_skb); 415 wcn->tx_ack_skb = ctl->skb; /* Tracking ref */ 416 mod_timer(&wcn->tx_ack_timer, jiffies + HZ / 10); 417 spin_unlock(&wcn->dxe_lock); 418 } 419 /* do not free, ownership transferred to mac80211 status cb */ 420 } else { 421 ieee80211_free_txskb(wcn->hw, ctl->skb); 422 } 423 424 if (wcn->queues_stopped) { 425 wcn->queues_stopped = false; 426 ieee80211_wake_queues(wcn->hw); 427 } 428 429 ctl->skb = NULL; 430 } 431 ctl = ctl->next; 432 } while (ctl != ch->head_blk_ctl); 433 434 ch->tail_blk_ctl = ctl; 435 spin_unlock_irqrestore(&ch->lock, flags); 436 } 437 438 static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev) 439 { 440 struct wcn36xx *wcn = (struct wcn36xx *)dev; 441 int int_src, int_reason; 442 443 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src); 444 445 if (int_src & WCN36XX_INT_MASK_CHAN_TX_H) { 446 wcn36xx_dxe_read_register(wcn, 447 WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H, 448 &int_reason); 449 450 wcn36xx_dxe_write_register(wcn, 451 WCN36XX_DXE_0_INT_CLR, 452 WCN36XX_INT_MASK_CHAN_TX_H); 453 454 if (int_reason & WCN36XX_CH_STAT_INT_ERR_MASK ) { 455 wcn36xx_dxe_write_register(wcn, 456 WCN36XX_DXE_0_INT_ERR_CLR, 457 WCN36XX_INT_MASK_CHAN_TX_H); 458 459 wcn36xx_err("DXE IRQ reported error: 0x%x in high TX channel\n", 460 int_src); 461 } 462 463 if (int_reason & WCN36XX_CH_STAT_INT_DONE_MASK) { 464 wcn36xx_dxe_write_register(wcn, 465 WCN36XX_DXE_0_INT_DONE_CLR, 466 WCN36XX_INT_MASK_CHAN_TX_H); 467 } 468 469 if (int_reason & WCN36XX_CH_STAT_INT_ED_MASK) { 470 wcn36xx_dxe_write_register(wcn, 471 WCN36XX_DXE_0_INT_ED_CLR, 472 WCN36XX_INT_MASK_CHAN_TX_H); 473 } 474 475 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high, reason %08x\n", 476 int_reason); 477 478 if (int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK | 479 WCN36XX_CH_STAT_INT_ED_MASK)) { 480 reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch); 481 } 482 } 483 484 if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) { 485 wcn36xx_dxe_read_register(wcn, 486 WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L, 487 &int_reason); 488 489 wcn36xx_dxe_write_register(wcn, 490 WCN36XX_DXE_0_INT_CLR, 491 WCN36XX_INT_MASK_CHAN_TX_L); 492 493 if (int_reason & WCN36XX_CH_STAT_INT_ERR_MASK ) { 494 wcn36xx_dxe_write_register(wcn, 495 WCN36XX_DXE_0_INT_ERR_CLR, 496 WCN36XX_INT_MASK_CHAN_TX_L); 497 498 wcn36xx_err("DXE IRQ reported error: 0x%x in low TX channel\n", 499 int_src); 500 } 501 502 if (int_reason & WCN36XX_CH_STAT_INT_DONE_MASK) { 503 wcn36xx_dxe_write_register(wcn, 504 WCN36XX_DXE_0_INT_DONE_CLR, 505 WCN36XX_INT_MASK_CHAN_TX_L); 506 } 507 508 if (int_reason & WCN36XX_CH_STAT_INT_ED_MASK) { 509 wcn36xx_dxe_write_register(wcn, 510 WCN36XX_DXE_0_INT_ED_CLR, 511 WCN36XX_INT_MASK_CHAN_TX_L); 512 } 513 514 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low, reason %08x\n", 515 int_reason); 516 517 if (int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK | 518 WCN36XX_CH_STAT_INT_ED_MASK)) { 519 reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch); 520 } 521 } 522 523 return IRQ_HANDLED; 524 } 525 526 static irqreturn_t wcn36xx_irq_rx_ready(int irq, void *dev) 527 { 528 struct wcn36xx *wcn = (struct wcn36xx *)dev; 529 530 wcn36xx_dxe_rx_frame(wcn); 531 532 return IRQ_HANDLED; 533 } 534 535 static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn) 536 { 537 int ret; 538 539 ret = request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete, 540 IRQF_TRIGGER_HIGH, "wcn36xx_tx", wcn); 541 if (ret) { 542 wcn36xx_err("failed to alloc tx irq\n"); 543 goto out_err; 544 } 545 546 ret = request_irq(wcn->rx_irq, wcn36xx_irq_rx_ready, IRQF_TRIGGER_HIGH, 547 "wcn36xx_rx", wcn); 548 if (ret) { 549 wcn36xx_err("failed to alloc rx irq\n"); 550 goto out_txirq; 551 } 552 553 enable_irq_wake(wcn->rx_irq); 554 555 return 0; 556 557 out_txirq: 558 free_irq(wcn->tx_irq, wcn); 559 out_err: 560 return ret; 561 562 } 563 564 static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn, 565 struct wcn36xx_dxe_ch *ch, 566 u32 ctrl, 567 u32 en_mask, 568 u32 int_mask, 569 u32 status_reg) 570 { 571 struct wcn36xx_dxe_desc *dxe; 572 struct wcn36xx_dxe_ctl *ctl; 573 dma_addr_t dma_addr; 574 struct sk_buff *skb; 575 u32 int_reason; 576 int ret; 577 578 wcn36xx_dxe_read_register(wcn, status_reg, &int_reason); 579 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR, int_mask); 580 581 if (int_reason & WCN36XX_CH_STAT_INT_ERR_MASK) { 582 wcn36xx_dxe_write_register(wcn, 583 WCN36XX_DXE_0_INT_ERR_CLR, 584 int_mask); 585 586 wcn36xx_err("DXE IRQ reported error on RX channel\n"); 587 } 588 589 if (int_reason & WCN36XX_CH_STAT_INT_DONE_MASK) 590 wcn36xx_dxe_write_register(wcn, 591 WCN36XX_DXE_0_INT_DONE_CLR, 592 int_mask); 593 594 if (int_reason & WCN36XX_CH_STAT_INT_ED_MASK) 595 wcn36xx_dxe_write_register(wcn, 596 WCN36XX_DXE_0_INT_ED_CLR, 597 int_mask); 598 599 if (!(int_reason & (WCN36XX_CH_STAT_INT_DONE_MASK | 600 WCN36XX_CH_STAT_INT_ED_MASK))) 601 return 0; 602 603 spin_lock(&ch->lock); 604 605 ctl = ch->head_blk_ctl; 606 dxe = ctl->desc; 607 608 while (!(READ_ONCE(dxe->ctrl) & WCN36xx_DXE_CTRL_VLD)) { 609 /* do not read until we own DMA descriptor */ 610 dma_rmb(); 611 612 /* read/modify DMA descriptor */ 613 skb = ctl->skb; 614 dma_addr = dxe->dst_addr_l; 615 ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl, GFP_ATOMIC); 616 if (0 == ret) { 617 /* new skb allocation ok. Use the new one and queue 618 * the old one to network system. 619 */ 620 dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE, 621 DMA_FROM_DEVICE); 622 wcn36xx_rx_skb(wcn, skb); 623 } 624 /* else keep old skb not submitted and reuse it for rx DMA 625 * (dropping the packet that it contained) 626 */ 627 628 /* flush descriptor changes before re-marking as valid */ 629 dma_wmb(); 630 dxe->ctrl = ctrl; 631 632 ctl = ctl->next; 633 dxe = ctl->desc; 634 } 635 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR, en_mask); 636 637 ch->head_blk_ctl = ctl; 638 639 spin_unlock(&ch->lock); 640 641 return 0; 642 } 643 644 void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn) 645 { 646 int int_src; 647 648 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src); 649 650 /* RX_LOW_PRI */ 651 if (int_src & WCN36XX_DXE_INT_CH1_MASK) 652 wcn36xx_rx_handle_packets(wcn, &wcn->dxe_rx_l_ch, 653 WCN36XX_DXE_CTRL_RX_L, 654 WCN36XX_DXE_INT_CH1_MASK, 655 WCN36XX_INT_MASK_CHAN_RX_L, 656 WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L); 657 658 /* RX_HIGH_PRI */ 659 if (int_src & WCN36XX_DXE_INT_CH3_MASK) 660 wcn36xx_rx_handle_packets(wcn, &wcn->dxe_rx_h_ch, 661 WCN36XX_DXE_CTRL_RX_H, 662 WCN36XX_DXE_INT_CH3_MASK, 663 WCN36XX_INT_MASK_CHAN_RX_H, 664 WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H); 665 666 if (!int_src) 667 wcn36xx_warn("No DXE interrupt pending\n"); 668 } 669 670 int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn) 671 { 672 size_t s; 673 void *cpu_addr; 674 675 /* Allocate BD headers for MGMT frames */ 676 677 /* Where this come from ask QC */ 678 wcn->mgmt_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE + 679 16 - (WCN36XX_BD_CHUNK_SIZE % 8); 680 681 s = wcn->mgmt_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_H; 682 cpu_addr = dma_alloc_coherent(wcn->dev, s, 683 &wcn->mgmt_mem_pool.phy_addr, 684 GFP_KERNEL); 685 if (!cpu_addr) 686 goto out_err; 687 688 wcn->mgmt_mem_pool.virt_addr = cpu_addr; 689 690 /* Allocate BD headers for DATA frames */ 691 692 /* Where this come from ask QC */ 693 wcn->data_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE + 694 16 - (WCN36XX_BD_CHUNK_SIZE % 8); 695 696 s = wcn->data_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_L; 697 cpu_addr = dma_alloc_coherent(wcn->dev, s, 698 &wcn->data_mem_pool.phy_addr, 699 GFP_KERNEL); 700 if (!cpu_addr) 701 goto out_err; 702 703 wcn->data_mem_pool.virt_addr = cpu_addr; 704 705 return 0; 706 707 out_err: 708 wcn36xx_dxe_free_mem_pools(wcn); 709 wcn36xx_err("Failed to allocate BD mempool\n"); 710 return -ENOMEM; 711 } 712 713 void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn) 714 { 715 if (wcn->mgmt_mem_pool.virt_addr) 716 dma_free_coherent(wcn->dev, wcn->mgmt_mem_pool.chunk_size * 717 WCN36XX_DXE_CH_DESC_NUMB_TX_H, 718 wcn->mgmt_mem_pool.virt_addr, 719 wcn->mgmt_mem_pool.phy_addr); 720 721 if (wcn->data_mem_pool.virt_addr) { 722 dma_free_coherent(wcn->dev, wcn->data_mem_pool.chunk_size * 723 WCN36XX_DXE_CH_DESC_NUMB_TX_L, 724 wcn->data_mem_pool.virt_addr, 725 wcn->data_mem_pool.phy_addr); 726 } 727 } 728 729 int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn, 730 struct wcn36xx_vif *vif_priv, 731 struct wcn36xx_tx_bd *bd, 732 struct sk_buff *skb, 733 bool is_low) 734 { 735 struct wcn36xx_dxe_desc *desc_bd, *desc_skb; 736 struct wcn36xx_dxe_ctl *ctl_bd, *ctl_skb; 737 struct wcn36xx_dxe_ch *ch = NULL; 738 unsigned long flags; 739 int ret; 740 741 ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch; 742 743 spin_lock_irqsave(&ch->lock, flags); 744 ctl_bd = ch->head_blk_ctl; 745 ctl_skb = ctl_bd->next; 746 747 /* 748 * If skb is not null that means that we reached the tail of the ring 749 * hence ring is full. Stop queues to let mac80211 back off until ring 750 * has an empty slot again. 751 */ 752 if (NULL != ctl_skb->skb) { 753 ieee80211_stop_queues(wcn->hw); 754 wcn->queues_stopped = true; 755 spin_unlock_irqrestore(&ch->lock, flags); 756 return -EBUSY; 757 } 758 759 if (unlikely(ctl_skb->bd_cpu_addr)) { 760 wcn36xx_err("bd_cpu_addr cannot be NULL for skb DXE\n"); 761 ret = -EINVAL; 762 goto unlock; 763 } 764 765 desc_bd = ctl_bd->desc; 766 desc_skb = ctl_skb->desc; 767 768 ctl_bd->skb = NULL; 769 770 /* write buffer descriptor */ 771 memcpy(ctl_bd->bd_cpu_addr, bd, sizeof(*bd)); 772 773 /* Set source address of the BD we send */ 774 desc_bd->src_addr_l = ctl_bd->bd_phy_addr; 775 desc_bd->dst_addr_l = ch->dxe_wq; 776 desc_bd->fr_len = sizeof(struct wcn36xx_tx_bd); 777 778 wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX\n"); 779 780 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC1 >>> ", 781 (char *)desc_bd, sizeof(*desc_bd)); 782 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, 783 "BD >>> ", (char *)ctl_bd->bd_cpu_addr, 784 sizeof(struct wcn36xx_tx_bd)); 785 786 desc_skb->src_addr_l = dma_map_single(wcn->dev, 787 skb->data, 788 skb->len, 789 DMA_TO_DEVICE); 790 if (dma_mapping_error(wcn->dev, desc_skb->src_addr_l)) { 791 dev_err(wcn->dev, "unable to DMA map src_addr_l\n"); 792 ret = -ENOMEM; 793 goto unlock; 794 } 795 796 ctl_skb->skb = skb; 797 desc_skb->dst_addr_l = ch->dxe_wq; 798 desc_skb->fr_len = ctl_skb->skb->len; 799 800 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC2 >>> ", 801 (char *)desc_skb, sizeof(*desc_skb)); 802 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "SKB >>> ", 803 (char *)ctl_skb->skb->data, ctl_skb->skb->len); 804 805 /* Move the head of the ring to the next empty descriptor */ 806 ch->head_blk_ctl = ctl_skb->next; 807 808 /* Commit all previous writes and set descriptors to VALID */ 809 wmb(); 810 desc_skb->ctrl = ch->ctrl_skb; 811 wmb(); 812 desc_bd->ctrl = ch->ctrl_bd; 813 814 /* 815 * When connected and trying to send data frame chip can be in sleep 816 * mode and writing to the register will not wake up the chip. Instead 817 * notify chip about new frame through SMSM bus. 818 */ 819 if (is_low && vif_priv->pw_state == WCN36XX_BMPS) { 820 qcom_smem_state_update_bits(wcn->tx_rings_empty_state, 821 WCN36XX_SMSM_WLAN_TX_ENABLE, 822 WCN36XX_SMSM_WLAN_TX_ENABLE); 823 } else { 824 /* indicate End Of Packet and generate interrupt on descriptor 825 * done. 826 */ 827 wcn36xx_dxe_write_register(wcn, 828 ch->reg_ctrl, ch->def_ctrl); 829 } 830 831 ret = 0; 832 unlock: 833 spin_unlock_irqrestore(&ch->lock, flags); 834 return ret; 835 } 836 837 int wcn36xx_dxe_init(struct wcn36xx *wcn) 838 { 839 int reg_data = 0, ret; 840 841 reg_data = WCN36XX_DXE_REG_RESET; 842 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data); 843 844 /* Select channels for rx avail and xfer done interrupts... */ 845 reg_data = (WCN36XX_DXE_INT_CH3_MASK | WCN36XX_DXE_INT_CH1_MASK) << 16 | 846 WCN36XX_DXE_INT_CH0_MASK | WCN36XX_DXE_INT_CH4_MASK; 847 if (wcn->is_pronto) 848 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data); 849 else 850 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data); 851 852 /***************************************/ 853 /* Init descriptors for TX LOW channel */ 854 /***************************************/ 855 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_l_ch); 856 if (ret) { 857 dev_err(wcn->dev, "Error allocating descriptor\n"); 858 return ret; 859 } 860 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_l_ch, &wcn->data_mem_pool); 861 862 /* Write channel head to a NEXT register */ 863 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L, 864 wcn->dxe_tx_l_ch.head_blk_ctl->desc_phy_addr); 865 866 /* Program DMA destination addr for TX LOW */ 867 wcn36xx_dxe_write_register(wcn, 868 WCN36XX_DXE_CH_DEST_ADDR_TX_L, 869 WCN36XX_DXE_WQ_TX_L); 870 871 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data); 872 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L); 873 874 /***************************************/ 875 /* Init descriptors for TX HIGH channel */ 876 /***************************************/ 877 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_h_ch); 878 if (ret) { 879 dev_err(wcn->dev, "Error allocating descriptor\n"); 880 goto out_err_txh_ch; 881 } 882 883 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_h_ch, &wcn->mgmt_mem_pool); 884 885 /* Write channel head to a NEXT register */ 886 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H, 887 wcn->dxe_tx_h_ch.head_blk_ctl->desc_phy_addr); 888 889 /* Program DMA destination addr for TX HIGH */ 890 wcn36xx_dxe_write_register(wcn, 891 WCN36XX_DXE_CH_DEST_ADDR_TX_H, 892 WCN36XX_DXE_WQ_TX_H); 893 894 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data); 895 896 /* Enable channel interrupts */ 897 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H); 898 899 /***************************************/ 900 /* Init descriptors for RX LOW channel */ 901 /***************************************/ 902 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_l_ch); 903 if (ret) { 904 dev_err(wcn->dev, "Error allocating descriptor\n"); 905 goto out_err_rxl_ch; 906 } 907 908 909 /* For RX we need to preallocated buffers */ 910 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_l_ch); 911 912 /* Write channel head to a NEXT register */ 913 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L, 914 wcn->dxe_rx_l_ch.head_blk_ctl->desc_phy_addr); 915 916 /* Write DMA source address */ 917 wcn36xx_dxe_write_register(wcn, 918 WCN36XX_DXE_CH_SRC_ADDR_RX_L, 919 WCN36XX_DXE_WQ_RX_L); 920 921 /* Program preallocated destination address */ 922 wcn36xx_dxe_write_register(wcn, 923 WCN36XX_DXE_CH_DEST_ADDR_RX_L, 924 wcn->dxe_rx_l_ch.head_blk_ctl->desc->phy_next_l); 925 926 /* Enable default control registers */ 927 wcn36xx_dxe_write_register(wcn, 928 WCN36XX_DXE_REG_CTL_RX_L, 929 WCN36XX_DXE_CH_DEFAULT_CTL_RX_L); 930 931 /* Enable channel interrupts */ 932 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L); 933 934 /***************************************/ 935 /* Init descriptors for RX HIGH channel */ 936 /***************************************/ 937 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_h_ch); 938 if (ret) { 939 dev_err(wcn->dev, "Error allocating descriptor\n"); 940 goto out_err_rxh_ch; 941 } 942 943 /* For RX we need to prealocat buffers */ 944 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_h_ch); 945 946 /* Write chanel head to a NEXT register */ 947 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H, 948 wcn->dxe_rx_h_ch.head_blk_ctl->desc_phy_addr); 949 950 /* Write DMA source address */ 951 wcn36xx_dxe_write_register(wcn, 952 WCN36XX_DXE_CH_SRC_ADDR_RX_H, 953 WCN36XX_DXE_WQ_RX_H); 954 955 /* Program preallocated destination address */ 956 wcn36xx_dxe_write_register(wcn, 957 WCN36XX_DXE_CH_DEST_ADDR_RX_H, 958 wcn->dxe_rx_h_ch.head_blk_ctl->desc->phy_next_l); 959 960 /* Enable default control registers */ 961 wcn36xx_dxe_write_register(wcn, 962 WCN36XX_DXE_REG_CTL_RX_H, 963 WCN36XX_DXE_CH_DEFAULT_CTL_RX_H); 964 965 /* Enable channel interrupts */ 966 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H); 967 968 ret = wcn36xx_dxe_request_irqs(wcn); 969 if (ret < 0) 970 goto out_err_irq; 971 972 timer_setup(&wcn->tx_ack_timer, wcn36xx_dxe_tx_timer, 0); 973 974 return 0; 975 976 out_err_irq: 977 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch); 978 out_err_rxh_ch: 979 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch); 980 out_err_rxl_ch: 981 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch); 982 out_err_txh_ch: 983 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch); 984 985 return ret; 986 } 987 988 void wcn36xx_dxe_deinit(struct wcn36xx *wcn) 989 { 990 free_irq(wcn->tx_irq, wcn); 991 free_irq(wcn->rx_irq, wcn); 992 del_timer(&wcn->tx_ack_timer); 993 994 if (wcn->tx_ack_skb) { 995 ieee80211_tx_status_irqsafe(wcn->hw, wcn->tx_ack_skb); 996 wcn->tx_ack_skb = NULL; 997 } 998 999 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_l_ch); 1000 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_h_ch); 1001 } 1002