1 /* 2 * Shared Atheros AR9170 Header 3 * 4 * RX/TX meta descriptor format 5 * 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> 7 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, see 20 * http://www.gnu.org/licenses/. 21 * 22 * This file incorporates work covered by the following copyright and 23 * permission notice: 24 * Copyright (c) 2007-2008 Atheros Communications, Inc. 25 * 26 * Permission to use, copy, modify, and/or distribute this software for any 27 * purpose with or without fee is hereby granted, provided that the above 28 * copyright notice and this permission notice appear in all copies. 29 * 30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 37 */ 38 39 #ifndef __CARL9170_SHARED_WLAN_H 40 #define __CARL9170_SHARED_WLAN_H 41 42 #include "fwcmd.h" 43 44 #define AR9170_RX_PHY_RATE_CCK_1M 0x0a 45 #define AR9170_RX_PHY_RATE_CCK_2M 0x14 46 #define AR9170_RX_PHY_RATE_CCK_5M 0x37 47 #define AR9170_RX_PHY_RATE_CCK_11M 0x6e 48 49 #define AR9170_ENC_ALG_NONE 0x0 50 #define AR9170_ENC_ALG_WEP64 0x1 51 #define AR9170_ENC_ALG_TKIP 0x2 52 #define AR9170_ENC_ALG_AESCCMP 0x4 53 #define AR9170_ENC_ALG_WEP128 0x5 54 #define AR9170_ENC_ALG_WEP256 0x6 55 #define AR9170_ENC_ALG_CENC 0x7 56 57 #define AR9170_RX_ENC_SOFTWARE 0x8 58 59 #define AR9170_RX_STATUS_MODULATION 0x03 60 #define AR9170_RX_STATUS_MODULATION_S 0 61 #define AR9170_RX_STATUS_MODULATION_CCK 0x00 62 #define AR9170_RX_STATUS_MODULATION_OFDM 0x01 63 #define AR9170_RX_STATUS_MODULATION_HT 0x02 64 #define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03 65 66 /* depends on modulation */ 67 #define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08 68 #define AR9170_RX_STATUS_GREENFIELD 0x08 69 70 #define AR9170_RX_STATUS_MPDU 0x30 71 #define AR9170_RX_STATUS_MPDU_S 4 72 #define AR9170_RX_STATUS_MPDU_SINGLE 0x00 73 #define AR9170_RX_STATUS_MPDU_FIRST 0x20 74 #define AR9170_RX_STATUS_MPDU_MIDDLE 0x30 75 #define AR9170_RX_STATUS_MPDU_LAST 0x10 76 77 #define AR9170_RX_STATUS_CONT_AGGR 0x40 78 #define AR9170_RX_STATUS_TOTAL_ERROR 0x80 79 80 #define AR9170_RX_ERROR_RXTO 0x01 81 #define AR9170_RX_ERROR_OVERRUN 0x02 82 #define AR9170_RX_ERROR_DECRYPT 0x04 83 #define AR9170_RX_ERROR_FCS 0x08 84 #define AR9170_RX_ERROR_WRONG_RA 0x10 85 #define AR9170_RX_ERROR_PLCP 0x20 86 #define AR9170_RX_ERROR_MMIC 0x40 87 88 /* these are either-or */ 89 #define AR9170_TX_MAC_PROT_RTS 0x0001 90 #define AR9170_TX_MAC_PROT_CTS 0x0002 91 #define AR9170_TX_MAC_PROT 0x0003 92 93 #define AR9170_TX_MAC_NO_ACK 0x0004 94 /* if unset, MAC will only do SIFS space before frame */ 95 #define AR9170_TX_MAC_BACKOFF 0x0008 96 #define AR9170_TX_MAC_BURST 0x0010 97 #define AR9170_TX_MAC_AGGR 0x0020 98 99 /* encryption is a two-bit field */ 100 #define AR9170_TX_MAC_ENCR_NONE 0x0000 101 #define AR9170_TX_MAC_ENCR_RC4 0x0040 102 #define AR9170_TX_MAC_ENCR_CENC 0x0080 103 #define AR9170_TX_MAC_ENCR_AES 0x00c0 104 105 #define AR9170_TX_MAC_MMIC 0x0100 106 #define AR9170_TX_MAC_HW_DURATION 0x0200 107 #define AR9170_TX_MAC_QOS_S 10 108 #define AR9170_TX_MAC_QOS 0x0c00 109 #define AR9170_TX_MAC_DISABLE_TXOP 0x1000 110 #define AR9170_TX_MAC_TXOP_RIFS 0x2000 111 #define AR9170_TX_MAC_IMM_BA 0x4000 112 113 /* either-or */ 114 #define AR9170_TX_PHY_MOD_CCK 0x00000000 115 #define AR9170_TX_PHY_MOD_OFDM 0x00000001 116 #define AR9170_TX_PHY_MOD_HT 0x00000002 117 118 /* depends on modulation */ 119 #define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004 120 #define AR9170_TX_PHY_GREENFIELD 0x00000004 121 122 #define AR9170_TX_PHY_BW_S 3 123 #define AR9170_TX_PHY_BW (3 << AR9170_TX_PHY_BW_SHIFT) 124 #define AR9170_TX_PHY_BW_20MHZ 0 125 #define AR9170_TX_PHY_BW_40MHZ 2 126 #define AR9170_TX_PHY_BW_40MHZ_DUP 3 127 128 #define AR9170_TX_PHY_TX_HEAVY_CLIP_S 6 129 #define AR9170_TX_PHY_TX_HEAVY_CLIP (7 << \ 130 AR9170_TX_PHY_TX_HEAVY_CLIP_S) 131 132 #define AR9170_TX_PHY_TX_PWR_S 9 133 #define AR9170_TX_PHY_TX_PWR (0x3f << \ 134 AR9170_TX_PHY_TX_PWR_S) 135 136 #define AR9170_TX_PHY_TXCHAIN_S 15 137 #define AR9170_TX_PHY_TXCHAIN (7 << \ 138 AR9170_TX_PHY_TXCHAIN_S) 139 #define AR9170_TX_PHY_TXCHAIN_1 1 140 /* use for cck, ofdm 6/9/12/18/24 and HT if capable */ 141 #define AR9170_TX_PHY_TXCHAIN_2 5 142 143 #define AR9170_TX_PHY_MCS_S 18 144 #define AR9170_TX_PHY_MCS (0x7f << \ 145 AR9170_TX_PHY_MCS_S) 146 147 #define AR9170_TX_PHY_RATE_CCK_1M 0x0 148 #define AR9170_TX_PHY_RATE_CCK_2M 0x1 149 #define AR9170_TX_PHY_RATE_CCK_5M 0x2 150 #define AR9170_TX_PHY_RATE_CCK_11M 0x3 151 152 /* same as AR9170_RX_PHY_RATE */ 153 #define AR9170_TXRX_PHY_RATE_OFDM_6M 0xb 154 #define AR9170_TXRX_PHY_RATE_OFDM_9M 0xf 155 #define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa 156 #define AR9170_TXRX_PHY_RATE_OFDM_18M 0xe 157 #define AR9170_TXRX_PHY_RATE_OFDM_24M 0x9 158 #define AR9170_TXRX_PHY_RATE_OFDM_36M 0xd 159 #define AR9170_TXRX_PHY_RATE_OFDM_48M 0x8 160 #define AR9170_TXRX_PHY_RATE_OFDM_54M 0xc 161 162 #define AR9170_TXRX_PHY_RATE_HT_MCS0 0x0 163 #define AR9170_TXRX_PHY_RATE_HT_MCS1 0x1 164 #define AR9170_TXRX_PHY_RATE_HT_MCS2 0x2 165 #define AR9170_TXRX_PHY_RATE_HT_MCS3 0x3 166 #define AR9170_TXRX_PHY_RATE_HT_MCS4 0x4 167 #define AR9170_TXRX_PHY_RATE_HT_MCS5 0x5 168 #define AR9170_TXRX_PHY_RATE_HT_MCS6 0x6 169 #define AR9170_TXRX_PHY_RATE_HT_MCS7 0x7 170 #define AR9170_TXRX_PHY_RATE_HT_MCS8 0x8 171 #define AR9170_TXRX_PHY_RATE_HT_MCS9 0x9 172 #define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa 173 #define AR9170_TXRX_PHY_RATE_HT_MCS11 0xb 174 #define AR9170_TXRX_PHY_RATE_HT_MCS12 0xc 175 #define AR9170_TXRX_PHY_RATE_HT_MCS13 0xd 176 #define AR9170_TXRX_PHY_RATE_HT_MCS14 0xe 177 #define AR9170_TXRX_PHY_RATE_HT_MCS15 0xf 178 179 #define AR9170_TX_PHY_SHORT_GI 0x80000000 180 181 #ifdef __CARL9170FW__ 182 struct ar9170_tx_hw_mac_control { 183 union { 184 struct { 185 /* 186 * Beware of compiler bugs in all gcc pre 4.4! 187 */ 188 189 u8 erp_prot:2; 190 u8 no_ack:1; 191 u8 backoff:1; 192 u8 burst:1; 193 u8 ampdu:1; 194 195 u8 enc_mode:2; 196 197 u8 hw_mmic:1; 198 u8 hw_duration:1; 199 200 u8 qos_queue:2; 201 202 u8 disable_txop:1; 203 u8 txop_rifs:1; 204 205 u8 ba_end:1; 206 u8 probe:1; 207 } __packed; 208 209 __le16 set; 210 } __packed; 211 } __packed; 212 213 struct ar9170_tx_hw_phy_control { 214 union { 215 struct { 216 /* 217 * Beware of compiler bugs in all gcc pre 4.4! 218 */ 219 220 u8 modulation:2; 221 u8 preamble:1; 222 u8 bandwidth:2; 223 u8:1; 224 u8 heavy_clip:3; 225 u8 tx_power:6; 226 u8 chains:3; 227 u8 mcs:7; 228 u8:6; 229 u8 short_gi:1; 230 } __packed; 231 232 __le32 set; 233 } __packed; 234 } __packed; 235 236 struct ar9170_tx_rate_info { 237 u8 tries:3; 238 u8 erp_prot:2; 239 u8 ampdu:1; 240 u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */ 241 } __packed; 242 243 struct carl9170_tx_superdesc { 244 __le16 len; 245 u8 rix; 246 u8 cnt; 247 u8 cookie; 248 u8 ampdu_density:3; 249 u8 ampdu_factor:2; 250 u8 ampdu_commit_density:1; 251 u8 ampdu_commit_factor:1; 252 u8 ampdu_unused_bit:1; 253 u8 queue:2; 254 u8 assign_seq:1; 255 u8 vif_id:3; 256 u8 fill_in_tsf:1; 257 u8 cab:1; 258 u8 padding2; 259 struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES]; 260 struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES]; 261 } __packed; 262 263 struct ar9170_tx_hwdesc { 264 __le16 length; 265 struct ar9170_tx_hw_mac_control mac; 266 struct ar9170_tx_hw_phy_control phy; 267 } __packed; 268 269 struct ar9170_tx_frame { 270 struct ar9170_tx_hwdesc hdr; 271 272 union { 273 struct ieee80211_hdr i3e; 274 u8 payload[0]; 275 } data; 276 } __packed; 277 278 struct carl9170_tx_superframe { 279 struct carl9170_tx_superdesc s; 280 struct ar9170_tx_frame f; 281 } __packed __aligned(4); 282 283 #endif /* __CARL9170FW__ */ 284 285 struct _ar9170_tx_hwdesc { 286 __le16 length; 287 __le16 mac_control; 288 __le32 phy_control; 289 } __packed; 290 291 #define CARL9170_TX_SUPER_AMPDU_DENSITY_S 0 292 #define CARL9170_TX_SUPER_AMPDU_DENSITY 0x7 293 #define CARL9170_TX_SUPER_AMPDU_FACTOR 0x18 294 #define CARL9170_TX_SUPER_AMPDU_FACTOR_S 3 295 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY 0x20 296 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S 5 297 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40 298 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S 6 299 300 #define CARL9170_TX_SUPER_MISC_QUEUE 0x3 301 #define CARL9170_TX_SUPER_MISC_QUEUE_S 0 302 #define CARL9170_TX_SUPER_MISC_ASSIGN_SEQ 0x4 303 #define CARL9170_TX_SUPER_MISC_VIF_ID 0x38 304 #define CARL9170_TX_SUPER_MISC_VIF_ID_S 3 305 #define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40 306 #define CARL9170_TX_SUPER_MISC_CAB 0x80 307 308 #define CARL9170_TX_SUPER_RI_TRIES 0x7 309 #define CARL9170_TX_SUPER_RI_TRIES_S 0 310 #define CARL9170_TX_SUPER_RI_ERP_PROT 0x18 311 #define CARL9170_TX_SUPER_RI_ERP_PROT_S 3 312 #define CARL9170_TX_SUPER_RI_AMPDU 0x20 313 #define CARL9170_TX_SUPER_RI_AMPDU_S 5 314 315 struct _carl9170_tx_superdesc { 316 __le16 len; 317 u8 rix; 318 u8 cnt; 319 u8 cookie; 320 u8 ampdu_settings; 321 u8 misc; 322 u8 padding; 323 u8 ri[CARL9170_TX_MAX_RATES]; 324 __le32 rr[CARL9170_TX_MAX_RETRY_RATES]; 325 } __packed; 326 327 struct _carl9170_tx_superframe { 328 struct _carl9170_tx_superdesc s; 329 struct _ar9170_tx_hwdesc f; 330 u8 frame_data[0]; 331 } __packed __aligned(4); 332 333 #define CARL9170_TX_SUPERDESC_LEN 24 334 #define AR9170_TX_HWDESC_LEN 8 335 #define CARL9170_TX_SUPERFRAME_LEN (CARL9170_TX_SUPERDESC_LEN + \ 336 AR9170_TX_HWDESC_LEN) 337 338 struct ar9170_rx_head { 339 u8 plcp[12]; 340 } __packed; 341 342 #define AR9170_RX_HEAD_LEN 12 343 344 struct ar9170_rx_phystatus { 345 union { 346 struct { 347 u8 rssi_ant0, rssi_ant1, rssi_ant2, 348 rssi_ant0x, rssi_ant1x, rssi_ant2x, 349 rssi_combined; 350 } __packed; 351 u8 rssi[7]; 352 } __packed; 353 354 u8 evm_stream0[6], evm_stream1[6]; 355 u8 phy_err; 356 } __packed; 357 358 #define AR9170_RX_PHYSTATUS_LEN 20 359 360 struct ar9170_rx_macstatus { 361 u8 SAidx, DAidx; 362 u8 error; 363 u8 status; 364 } __packed; 365 366 #define AR9170_RX_MACSTATUS_LEN 4 367 368 struct ar9170_rx_frame_single { 369 struct ar9170_rx_head phy_head; 370 struct ieee80211_hdr i3e; 371 struct ar9170_rx_phystatus phy_tail; 372 struct ar9170_rx_macstatus macstatus; 373 } __packed; 374 375 struct ar9170_rx_frame_head { 376 struct ar9170_rx_head phy_head; 377 struct ieee80211_hdr i3e; 378 struct ar9170_rx_macstatus macstatus; 379 } __packed; 380 381 struct ar9170_rx_frame_middle { 382 struct ieee80211_hdr i3e; 383 struct ar9170_rx_macstatus macstatus; 384 } __packed; 385 386 struct ar9170_rx_frame_tail { 387 struct ieee80211_hdr i3e; 388 struct ar9170_rx_phystatus phy_tail; 389 struct ar9170_rx_macstatus macstatus; 390 } __packed; 391 392 struct ar9170_rx_frame { 393 union { 394 struct ar9170_rx_frame_single single; 395 struct ar9170_rx_frame_head head; 396 struct ar9170_rx_frame_middle middle; 397 struct ar9170_rx_frame_tail tail; 398 } __packed; 399 } __packed; 400 401 static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t) 402 { 403 return (t->SAidx & 0xc0) >> 4 | 404 (t->DAidx & 0xc0) >> 6; 405 } 406 407 /* 408 * This is an workaround for several undocumented bugs. 409 * Don't mess with the QoS/AC <-> HW Queue map, if you don't 410 * know what you are doing. 411 * 412 * Known problems [hardware]: 413 * * The MAC does not aggregate frames on anything other 414 * than the first HW queue. 415 * * when an AMPDU is placed [in the first hw queue] and 416 * additional frames are already queued on a different 417 * hw queue, the MAC will ALWAYS freeze. 418 * 419 * In a nutshell: The hardware can either do QoS or 420 * Aggregation but not both at the same time. As a 421 * result, this makes the device pretty much useless 422 * for any serious 802.11n setup. 423 */ 424 enum ar9170_txq { 425 AR9170_TXQ_BK = 0, /* TXQ0 */ 426 AR9170_TXQ_BE, /* TXQ1 */ 427 AR9170_TXQ_VI, /* TXQ2 */ 428 AR9170_TXQ_VO, /* TXQ3 */ 429 430 __AR9170_NUM_TXQ, 431 }; 432 433 #define AR9170_TXQ_DEPTH 32 434 435 #endif /* __CARL9170_SHARED_WLAN_H */ 436