1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/nl80211.h> 20 #include <linux/pci.h> 21 #include <linux/pci-aspm.h> 22 #include <linux/ath9k_platform.h> 23 #include <linux/module.h> 24 #include "ath9k.h" 25 26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 32 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 33 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 34 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 35 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 36 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 37 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 38 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 39 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ 40 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */ 41 { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */ 42 { 0 } 43 }; 44 45 46 /* return bus cachesize in 4B word units */ 47 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 48 { 49 struct ath_softc *sc = (struct ath_softc *) common->priv; 50 u8 u8tmp; 51 52 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 53 *csz = (int)u8tmp; 54 55 /* 56 * This check was put in to avoid "unpleasant" consequences if 57 * the bootrom has not fully initialized all PCI devices. 58 * Sometimes the cache line size register is not set 59 */ 60 61 if (*csz == 0) 62 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 63 } 64 65 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 66 { 67 struct ath_softc *sc = (struct ath_softc *) common->priv; 68 struct ath9k_platform_data *pdata = sc->dev->platform_data; 69 70 if (pdata) { 71 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 72 ath_err(common, 73 "%s: eeprom read failed, offset %08x is out of range\n", 74 __func__, off); 75 } 76 77 *data = pdata->eeprom_data[off]; 78 } else { 79 struct ath_hw *ah = (struct ath_hw *) common->ah; 80 81 common->ops->read(ah, AR5416_EEPROM_OFFSET + 82 (off << AR5416_EEPROM_S)); 83 84 if (!ath9k_hw_wait(ah, 85 AR_EEPROM_STATUS_DATA, 86 AR_EEPROM_STATUS_DATA_BUSY | 87 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 88 AH_WAIT_TIMEOUT)) { 89 return false; 90 } 91 92 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 93 AR_EEPROM_STATUS_DATA_VAL); 94 } 95 96 return true; 97 } 98 99 static void ath_pci_extn_synch_enable(struct ath_common *common) 100 { 101 struct ath_softc *sc = (struct ath_softc *) common->priv; 102 struct pci_dev *pdev = to_pci_dev(sc->dev); 103 u8 lnkctl; 104 105 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl); 106 lnkctl |= PCI_EXP_LNKCTL_ES; 107 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl); 108 } 109 110 /* Need to be called after we discover btcoex capabilities */ 111 static void ath_pci_aspm_init(struct ath_common *common) 112 { 113 struct ath_softc *sc = (struct ath_softc *) common->priv; 114 struct ath_hw *ah = sc->sc_ah; 115 struct pci_dev *pdev = to_pci_dev(sc->dev); 116 struct pci_dev *parent; 117 u16 aspm; 118 119 if (!ah->is_pciexpress) 120 return; 121 122 parent = pdev->bus->self; 123 if (!parent) 124 return; 125 126 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && 127 (AR_SREV_9285(ah))) { 128 /* Bluetooth coexistance requires disabling ASPM. */ 129 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, 130 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 131 132 /* 133 * Both upstream and downstream PCIe components should 134 * have the same ASPM settings. 135 */ 136 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 137 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 138 139 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); 140 return; 141 } 142 143 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); 144 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { 145 ah->aspm_enabled = true; 146 /* Initialize PCIe PM and SERDES registers. */ 147 ath9k_hw_configpcipowersave(ah, false); 148 ath_info(common, "ASPM enabled: 0x%x\n", aspm); 149 } 150 } 151 152 static const struct ath_bus_ops ath_pci_bus_ops = { 153 .ath_bus_type = ATH_PCI, 154 .read_cachesize = ath_pci_read_cachesize, 155 .eeprom_read = ath_pci_eeprom_read, 156 .extn_synch_en = ath_pci_extn_synch_enable, 157 .aspm_init = ath_pci_aspm_init, 158 }; 159 160 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 161 { 162 void __iomem *mem; 163 struct ath_softc *sc; 164 struct ieee80211_hw *hw; 165 u8 csz; 166 u32 val; 167 int ret = 0; 168 char hw_name[64]; 169 170 if (pci_enable_device(pdev)) 171 return -EIO; 172 173 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 174 if (ret) { 175 pr_err("32-bit DMA not available\n"); 176 goto err_dma; 177 } 178 179 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 180 if (ret) { 181 pr_err("32-bit DMA consistent DMA enable failed\n"); 182 goto err_dma; 183 } 184 185 /* 186 * Cache line size is used to size and align various 187 * structures used to communicate with the hardware. 188 */ 189 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 190 if (csz == 0) { 191 /* 192 * Linux 2.4.18 (at least) writes the cache line size 193 * register as a 16-bit wide register which is wrong. 194 * We must have this setup properly for rx buffer 195 * DMA to work so force a reasonable value here if it 196 * comes up zero. 197 */ 198 csz = L1_CACHE_BYTES / sizeof(u32); 199 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 200 } 201 /* 202 * The default setting of latency timer yields poor results, 203 * set it to the value used by other systems. It may be worth 204 * tweaking this setting more. 205 */ 206 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 207 208 pci_set_master(pdev); 209 210 /* 211 * Disable the RETRY_TIMEOUT register (0x41) to keep 212 * PCI Tx retries from interfering with C3 CPU state. 213 */ 214 pci_read_config_dword(pdev, 0x40, &val); 215 if ((val & 0x0000ff00) != 0) 216 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 217 218 ret = pci_request_region(pdev, 0, "ath9k"); 219 if (ret) { 220 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 221 ret = -ENODEV; 222 goto err_region; 223 } 224 225 mem = pci_iomap(pdev, 0, 0); 226 if (!mem) { 227 pr_err("PCI memory map error\n") ; 228 ret = -EIO; 229 goto err_iomap; 230 } 231 232 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); 233 if (!hw) { 234 dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); 235 ret = -ENOMEM; 236 goto err_alloc_hw; 237 } 238 239 SET_IEEE80211_DEV(hw, &pdev->dev); 240 pci_set_drvdata(pdev, hw); 241 242 sc = hw->priv; 243 sc->hw = hw; 244 sc->dev = &pdev->dev; 245 sc->mem = mem; 246 247 /* Will be cleared in ath9k_start() */ 248 set_bit(SC_OP_INVALID, &sc->sc_flags); 249 250 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 251 if (ret) { 252 dev_err(&pdev->dev, "request_irq failed\n"); 253 goto err_irq; 254 } 255 256 sc->irq = pdev->irq; 257 258 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); 259 if (ret) { 260 dev_err(&pdev->dev, "Failed to initialize device\n"); 261 goto err_init; 262 } 263 264 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); 265 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", 266 hw_name, (unsigned long)mem, pdev->irq); 267 268 return 0; 269 270 err_init: 271 free_irq(sc->irq, sc); 272 err_irq: 273 ieee80211_free_hw(hw); 274 err_alloc_hw: 275 pci_iounmap(pdev, mem); 276 err_iomap: 277 pci_release_region(pdev, 0); 278 err_region: 279 /* Nothing */ 280 err_dma: 281 pci_disable_device(pdev); 282 return ret; 283 } 284 285 static void ath_pci_remove(struct pci_dev *pdev) 286 { 287 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 288 struct ath_softc *sc = hw->priv; 289 void __iomem *mem = sc->mem; 290 291 if (!is_ath9k_unloaded) 292 sc->sc_ah->ah_flags |= AH_UNPLUGGED; 293 ath9k_deinit_device(sc); 294 free_irq(sc->irq, sc); 295 ieee80211_free_hw(sc->hw); 296 297 pci_iounmap(pdev, mem); 298 pci_disable_device(pdev); 299 pci_release_region(pdev, 0); 300 } 301 302 #ifdef CONFIG_PM 303 304 static int ath_pci_suspend(struct device *device) 305 { 306 struct pci_dev *pdev = to_pci_dev(device); 307 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 308 struct ath_softc *sc = hw->priv; 309 310 if (sc->wow_enabled) 311 return 0; 312 313 /* The device has to be moved to FULLSLEEP forcibly. 314 * Otherwise the chip never moved to full sleep, 315 * when no interface is up. 316 */ 317 ath9k_stop_btcoex(sc); 318 ath9k_hw_disable(sc->sc_ah); 319 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 320 321 return 0; 322 } 323 324 static int ath_pci_resume(struct device *device) 325 { 326 struct pci_dev *pdev = to_pci_dev(device); 327 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 328 struct ath_softc *sc = hw->priv; 329 struct ath_hw *ah = sc->sc_ah; 330 struct ath_common *common = ath9k_hw_common(ah); 331 u32 val; 332 333 /* 334 * Suspend/Resume resets the PCI configuration space, so we have to 335 * re-disable the RETRY_TIMEOUT register (0x41) to keep 336 * PCI Tx retries from interfering with C3 CPU state 337 */ 338 pci_read_config_dword(pdev, 0x40, &val); 339 if ((val & 0x0000ff00) != 0) 340 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 341 342 ath_pci_aspm_init(common); 343 ah->reset_power_on = false; 344 345 return 0; 346 } 347 348 static const struct dev_pm_ops ath9k_pm_ops = { 349 .suspend = ath_pci_suspend, 350 .resume = ath_pci_resume, 351 .freeze = ath_pci_suspend, 352 .thaw = ath_pci_resume, 353 .poweroff = ath_pci_suspend, 354 .restore = ath_pci_resume, 355 }; 356 357 #define ATH9K_PM_OPS (&ath9k_pm_ops) 358 359 #else /* !CONFIG_PM */ 360 361 #define ATH9K_PM_OPS NULL 362 363 #endif /* !CONFIG_PM */ 364 365 366 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 367 368 static struct pci_driver ath_pci_driver = { 369 .name = "ath9k", 370 .id_table = ath_pci_id_table, 371 .probe = ath_pci_probe, 372 .remove = ath_pci_remove, 373 .driver.pm = ATH9K_PM_OPS, 374 }; 375 376 int ath_pci_init(void) 377 { 378 return pci_register_driver(&ath_pci_driver); 379 } 380 381 void ath_pci_exit(void) 382 { 383 pci_unregister_driver(&ath_pci_driver); 384 } 385