1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/pci.h> 19 #include "ath9k.h" 20 21 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 28 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 29 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 30 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 31 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 32 { 0 } 33 }; 34 35 /* return bus cachesize in 4B word units */ 36 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 37 { 38 struct ath_softc *sc = (struct ath_softc *) common->priv; 39 u8 u8tmp; 40 41 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 42 *csz = (int)u8tmp; 43 44 /* 45 * This check was put in to avoid "unplesant" consequences if 46 * the bootrom has not fully initialized all PCI devices. 47 * Sometimes the cache line size register is not set 48 */ 49 50 if (*csz == 0) 51 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 52 } 53 54 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 55 { 56 struct ath_hw *ah = (struct ath_hw *) common->ah; 57 58 common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 59 60 if (!ath9k_hw_wait(ah, 61 AR_EEPROM_STATUS_DATA, 62 AR_EEPROM_STATUS_DATA_BUSY | 63 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 64 AH_WAIT_TIMEOUT)) { 65 return false; 66 } 67 68 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 69 AR_EEPROM_STATUS_DATA_VAL); 70 71 return true; 72 } 73 74 /* 75 * Bluetooth coexistance requires disabling ASPM. 76 */ 77 static void ath_pci_bt_coex_prep(struct ath_common *common) 78 { 79 struct ath_softc *sc = (struct ath_softc *) common->priv; 80 struct pci_dev *pdev = to_pci_dev(sc->dev); 81 u8 aspm; 82 83 if (!pdev->is_pcie) 84 return; 85 86 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm); 87 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1); 88 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm); 89 } 90 91 static const struct ath_bus_ops ath_pci_bus_ops = { 92 .ath_bus_type = ATH_PCI, 93 .read_cachesize = ath_pci_read_cachesize, 94 .eeprom_read = ath_pci_eeprom_read, 95 .bt_coex_prep = ath_pci_bt_coex_prep, 96 }; 97 98 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 99 { 100 void __iomem *mem; 101 struct ath_wiphy *aphy; 102 struct ath_softc *sc; 103 struct ieee80211_hw *hw; 104 u8 csz; 105 u16 subsysid; 106 u32 val; 107 int ret = 0; 108 char hw_name[64]; 109 110 if (pci_enable_device(pdev)) 111 return -EIO; 112 113 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 114 if (ret) { 115 printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); 116 goto err_dma; 117 } 118 119 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 120 if (ret) { 121 printk(KERN_ERR "ath9k: 32-bit DMA consistent " 122 "DMA enable failed\n"); 123 goto err_dma; 124 } 125 126 /* 127 * Cache line size is used to size and align various 128 * structures used to communicate with the hardware. 129 */ 130 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 131 if (csz == 0) { 132 /* 133 * Linux 2.4.18 (at least) writes the cache line size 134 * register as a 16-bit wide register which is wrong. 135 * We must have this setup properly for rx buffer 136 * DMA to work so force a reasonable value here if it 137 * comes up zero. 138 */ 139 csz = L1_CACHE_BYTES / sizeof(u32); 140 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 141 } 142 /* 143 * The default setting of latency timer yields poor results, 144 * set it to the value used by other systems. It may be worth 145 * tweaking this setting more. 146 */ 147 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 148 149 pci_set_master(pdev); 150 151 /* 152 * Disable the RETRY_TIMEOUT register (0x41) to keep 153 * PCI Tx retries from interfering with C3 CPU state. 154 */ 155 pci_read_config_dword(pdev, 0x40, &val); 156 if ((val & 0x0000ff00) != 0) 157 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 158 159 ret = pci_request_region(pdev, 0, "ath9k"); 160 if (ret) { 161 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 162 ret = -ENODEV; 163 goto err_region; 164 } 165 166 mem = pci_iomap(pdev, 0, 0); 167 if (!mem) { 168 printk(KERN_ERR "PCI memory map error\n") ; 169 ret = -EIO; 170 goto err_iomap; 171 } 172 173 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) + 174 sizeof(struct ath_softc), &ath9k_ops); 175 if (!hw) { 176 dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); 177 ret = -ENOMEM; 178 goto err_alloc_hw; 179 } 180 181 SET_IEEE80211_DEV(hw, &pdev->dev); 182 pci_set_drvdata(pdev, hw); 183 184 aphy = hw->priv; 185 sc = (struct ath_softc *) (aphy + 1); 186 aphy->sc = sc; 187 aphy->hw = hw; 188 sc->pri_wiphy = aphy; 189 sc->hw = hw; 190 sc->dev = &pdev->dev; 191 sc->mem = mem; 192 193 /* Will be cleared in ath9k_start() */ 194 sc->sc_flags |= SC_OP_INVALID; 195 196 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 197 if (ret) { 198 dev_err(&pdev->dev, "request_irq failed\n"); 199 goto err_irq; 200 } 201 202 sc->irq = pdev->irq; 203 204 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid); 205 ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops); 206 if (ret) { 207 dev_err(&pdev->dev, "Failed to initialize device\n"); 208 goto err_init; 209 } 210 211 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); 212 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", 213 hw_name, (unsigned long)mem, pdev->irq); 214 215 return 0; 216 217 err_init: 218 free_irq(sc->irq, sc); 219 err_irq: 220 ieee80211_free_hw(hw); 221 err_alloc_hw: 222 pci_iounmap(pdev, mem); 223 err_iomap: 224 pci_release_region(pdev, 0); 225 err_region: 226 /* Nothing */ 227 err_dma: 228 pci_disable_device(pdev); 229 return ret; 230 } 231 232 static void ath_pci_remove(struct pci_dev *pdev) 233 { 234 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 235 struct ath_wiphy *aphy = hw->priv; 236 struct ath_softc *sc = aphy->sc; 237 void __iomem *mem = sc->mem; 238 239 ath9k_deinit_device(sc); 240 free_irq(sc->irq, sc); 241 ieee80211_free_hw(sc->hw); 242 243 pci_iounmap(pdev, mem); 244 pci_disable_device(pdev); 245 pci_release_region(pdev, 0); 246 } 247 248 #ifdef CONFIG_PM 249 250 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) 251 { 252 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 253 struct ath_wiphy *aphy = hw->priv; 254 struct ath_softc *sc = aphy->sc; 255 256 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); 257 258 pci_save_state(pdev); 259 pci_disable_device(pdev); 260 pci_set_power_state(pdev, PCI_D3hot); 261 262 return 0; 263 } 264 265 static int ath_pci_resume(struct pci_dev *pdev) 266 { 267 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 268 struct ath_wiphy *aphy = hw->priv; 269 struct ath_softc *sc = aphy->sc; 270 u32 val; 271 int err; 272 273 pci_restore_state(pdev); 274 275 err = pci_enable_device(pdev); 276 if (err) 277 return err; 278 279 /* 280 * Suspend/Resume resets the PCI configuration space, so we have to 281 * re-disable the RETRY_TIMEOUT register (0x41) to keep 282 * PCI Tx retries from interfering with C3 CPU state 283 */ 284 pci_read_config_dword(pdev, 0x40, &val); 285 if ((val & 0x0000ff00) != 0) 286 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 287 288 /* Enable LED */ 289 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, 290 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 291 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); 292 293 return 0; 294 } 295 296 #endif /* CONFIG_PM */ 297 298 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 299 300 static struct pci_driver ath_pci_driver = { 301 .name = "ath9k", 302 .id_table = ath_pci_id_table, 303 .probe = ath_pci_probe, 304 .remove = ath_pci_remove, 305 #ifdef CONFIG_PM 306 .suspend = ath_pci_suspend, 307 .resume = ath_pci_resume, 308 #endif /* CONFIG_PM */ 309 }; 310 311 int ath_pci_init(void) 312 { 313 return pci_register_driver(&ath_pci_driver); 314 } 315 316 void ath_pci_exit(void) 317 { 318 pci_unregister_driver(&ath_pci_driver); 319 } 320