1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/pci.h> 19 #include <linux/pci-aspm.h> 20 #include <linux/ath9k_platform.h> 21 #include <linux/module.h> 22 #include "ath9k.h" 23 24 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 25 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 26 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 27 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 28 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 29 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 30 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 31 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 32 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 33 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 34 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 35 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 36 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 37 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ 38 { 0 } 39 }; 40 41 42 /* return bus cachesize in 4B word units */ 43 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 44 { 45 struct ath_softc *sc = (struct ath_softc *) common->priv; 46 u8 u8tmp; 47 48 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 49 *csz = (int)u8tmp; 50 51 /* 52 * This check was put in to avoid "unpleasant" consequences if 53 * the bootrom has not fully initialized all PCI devices. 54 * Sometimes the cache line size register is not set 55 */ 56 57 if (*csz == 0) 58 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 59 } 60 61 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 62 { 63 struct ath_softc *sc = (struct ath_softc *) common->priv; 64 struct ath9k_platform_data *pdata = sc->dev->platform_data; 65 66 if (pdata) { 67 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 68 ath_err(common, 69 "%s: eeprom read failed, offset %08x is out of range\n", 70 __func__, off); 71 } 72 73 *data = pdata->eeprom_data[off]; 74 } else { 75 struct ath_hw *ah = (struct ath_hw *) common->ah; 76 77 common->ops->read(ah, AR5416_EEPROM_OFFSET + 78 (off << AR5416_EEPROM_S)); 79 80 if (!ath9k_hw_wait(ah, 81 AR_EEPROM_STATUS_DATA, 82 AR_EEPROM_STATUS_DATA_BUSY | 83 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 84 AH_WAIT_TIMEOUT)) { 85 return false; 86 } 87 88 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 89 AR_EEPROM_STATUS_DATA_VAL); 90 } 91 92 return true; 93 } 94 95 static void ath_pci_extn_synch_enable(struct ath_common *common) 96 { 97 struct ath_softc *sc = (struct ath_softc *) common->priv; 98 struct pci_dev *pdev = to_pci_dev(sc->dev); 99 u8 lnkctl; 100 101 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl); 102 lnkctl |= PCI_EXP_LNKCTL_ES; 103 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl); 104 } 105 106 /* Need to be called after we discover btcoex capabilities */ 107 static void ath_pci_aspm_init(struct ath_common *common) 108 { 109 struct ath_softc *sc = (struct ath_softc *) common->priv; 110 struct ath_hw *ah = sc->sc_ah; 111 struct pci_dev *pdev = to_pci_dev(sc->dev); 112 struct pci_dev *parent; 113 int pos; 114 u8 aspm; 115 116 pos = pci_pcie_cap(pdev); 117 if (!pos) 118 return; 119 120 parent = pdev->bus->self; 121 if (!parent) 122 return; 123 124 if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { 125 /* Bluetooth coexistance requires disabling ASPM. */ 126 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm); 127 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 128 pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm); 129 130 /* 131 * Both upstream and downstream PCIe components should 132 * have the same ASPM settings. 133 */ 134 pos = pci_pcie_cap(parent); 135 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 136 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 137 pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm); 138 139 return; 140 } 141 142 pos = pci_pcie_cap(parent); 143 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 144 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { 145 ah->aspm_enabled = true; 146 /* Initialize PCIe PM and SERDES registers. */ 147 ath9k_hw_configpcipowersave(ah, false); 148 } 149 } 150 151 static const struct ath_bus_ops ath_pci_bus_ops = { 152 .ath_bus_type = ATH_PCI, 153 .read_cachesize = ath_pci_read_cachesize, 154 .eeprom_read = ath_pci_eeprom_read, 155 .extn_synch_en = ath_pci_extn_synch_enable, 156 .aspm_init = ath_pci_aspm_init, 157 }; 158 159 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 160 { 161 void __iomem *mem; 162 struct ath_softc *sc; 163 struct ieee80211_hw *hw; 164 u8 csz; 165 u32 val; 166 int ret = 0; 167 char hw_name[64]; 168 169 if (pci_enable_device(pdev)) 170 return -EIO; 171 172 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 173 if (ret) { 174 printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); 175 goto err_dma; 176 } 177 178 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 179 if (ret) { 180 printk(KERN_ERR "ath9k: 32-bit DMA consistent " 181 "DMA enable failed\n"); 182 goto err_dma; 183 } 184 185 /* 186 * Cache line size is used to size and align various 187 * structures used to communicate with the hardware. 188 */ 189 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 190 if (csz == 0) { 191 /* 192 * Linux 2.4.18 (at least) writes the cache line size 193 * register as a 16-bit wide register which is wrong. 194 * We must have this setup properly for rx buffer 195 * DMA to work so force a reasonable value here if it 196 * comes up zero. 197 */ 198 csz = L1_CACHE_BYTES / sizeof(u32); 199 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 200 } 201 /* 202 * The default setting of latency timer yields poor results, 203 * set it to the value used by other systems. It may be worth 204 * tweaking this setting more. 205 */ 206 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 207 208 pci_set_master(pdev); 209 210 /* 211 * Disable the RETRY_TIMEOUT register (0x41) to keep 212 * PCI Tx retries from interfering with C3 CPU state. 213 */ 214 pci_read_config_dword(pdev, 0x40, &val); 215 if ((val & 0x0000ff00) != 0) 216 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 217 218 ret = pci_request_region(pdev, 0, "ath9k"); 219 if (ret) { 220 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 221 ret = -ENODEV; 222 goto err_region; 223 } 224 225 mem = pci_iomap(pdev, 0, 0); 226 if (!mem) { 227 printk(KERN_ERR "PCI memory map error\n") ; 228 ret = -EIO; 229 goto err_iomap; 230 } 231 232 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); 233 if (!hw) { 234 dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); 235 ret = -ENOMEM; 236 goto err_alloc_hw; 237 } 238 239 SET_IEEE80211_DEV(hw, &pdev->dev); 240 pci_set_drvdata(pdev, hw); 241 242 sc = hw->priv; 243 sc->hw = hw; 244 sc->dev = &pdev->dev; 245 sc->mem = mem; 246 247 /* Will be cleared in ath9k_start() */ 248 sc->sc_flags |= SC_OP_INVALID; 249 250 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 251 if (ret) { 252 dev_err(&pdev->dev, "request_irq failed\n"); 253 goto err_irq; 254 } 255 256 sc->irq = pdev->irq; 257 258 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); 259 if (ret) { 260 dev_err(&pdev->dev, "Failed to initialize device\n"); 261 goto err_init; 262 } 263 264 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); 265 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", 266 hw_name, (unsigned long)mem, pdev->irq); 267 268 return 0; 269 270 err_init: 271 free_irq(sc->irq, sc); 272 err_irq: 273 ieee80211_free_hw(hw); 274 err_alloc_hw: 275 pci_iounmap(pdev, mem); 276 err_iomap: 277 pci_release_region(pdev, 0); 278 err_region: 279 /* Nothing */ 280 err_dma: 281 pci_disable_device(pdev); 282 return ret; 283 } 284 285 static void ath_pci_remove(struct pci_dev *pdev) 286 { 287 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 288 struct ath_softc *sc = hw->priv; 289 void __iomem *mem = sc->mem; 290 291 if (!is_ath9k_unloaded) 292 sc->sc_ah->ah_flags |= AH_UNPLUGGED; 293 ath9k_deinit_device(sc); 294 free_irq(sc->irq, sc); 295 ieee80211_free_hw(sc->hw); 296 297 pci_iounmap(pdev, mem); 298 pci_disable_device(pdev); 299 pci_release_region(pdev, 0); 300 } 301 302 #ifdef CONFIG_PM 303 304 static int ath_pci_suspend(struct device *device) 305 { 306 struct pci_dev *pdev = to_pci_dev(device); 307 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 308 struct ath_softc *sc = hw->priv; 309 310 /* The device has to be moved to FULLSLEEP forcibly. 311 * Otherwise the chip never moved to full sleep, 312 * when no interface is up. 313 */ 314 ath9k_hw_disable(sc->sc_ah); 315 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 316 317 return 0; 318 } 319 320 static int ath_pci_resume(struct device *device) 321 { 322 struct pci_dev *pdev = to_pci_dev(device); 323 u32 val; 324 325 /* 326 * Suspend/Resume resets the PCI configuration space, so we have to 327 * re-disable the RETRY_TIMEOUT register (0x41) to keep 328 * PCI Tx retries from interfering with C3 CPU state 329 */ 330 pci_read_config_dword(pdev, 0x40, &val); 331 if ((val & 0x0000ff00) != 0) 332 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 333 334 return 0; 335 } 336 337 static const struct dev_pm_ops ath9k_pm_ops = { 338 .suspend = ath_pci_suspend, 339 .resume = ath_pci_resume, 340 .freeze = ath_pci_suspend, 341 .thaw = ath_pci_resume, 342 .poweroff = ath_pci_suspend, 343 .restore = ath_pci_resume, 344 }; 345 346 #define ATH9K_PM_OPS (&ath9k_pm_ops) 347 348 #else /* !CONFIG_PM */ 349 350 #define ATH9K_PM_OPS NULL 351 352 #endif /* !CONFIG_PM */ 353 354 355 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 356 357 static struct pci_driver ath_pci_driver = { 358 .name = "ath9k", 359 .id_table = ath_pci_id_table, 360 .probe = ath_pci_probe, 361 .remove = ath_pci_remove, 362 .driver.pm = ATH9K_PM_OPS, 363 }; 364 365 int ath_pci_init(void) 366 { 367 return pci_register_driver(&ath_pci_driver); 368 } 369 370 void ath_pci_exit(void) 371 { 372 pci_unregister_driver(&ath_pci_driver); 373 } 374