1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static u8 parse_mpdudensity(u8 mpdudensity) 23 { 24 /* 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 26 * 0 for no restriction 27 * 1 for 1/4 us 28 * 2 for 1/2 us 29 * 3 for 1 us 30 * 4 for 2 us 31 * 5 for 4 us 32 * 6 for 8 us 33 * 7 for 16 us 34 */ 35 switch (mpdudensity) { 36 case 0: 37 return 0; 38 case 1: 39 case 2: 40 case 3: 41 /* Our lower layer calculations limit our precision to 42 1 microsecond */ 43 return 1; 44 case 4: 45 return 2; 46 case 5: 47 return 4; 48 case 6: 49 return 8; 50 case 7: 51 return 16; 52 default: 53 return 0; 54 } 55 } 56 57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 58 { 59 bool pending = false; 60 61 spin_lock_bh(&txq->axq_lock); 62 63 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 64 pending = true; 65 66 spin_unlock_bh(&txq->axq_lock); 67 return pending; 68 } 69 70 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 71 { 72 unsigned long flags; 73 bool ret; 74 75 spin_lock_irqsave(&sc->sc_pm_lock, flags); 76 ret = ath9k_hw_setpower(sc->sc_ah, mode); 77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 78 79 return ret; 80 } 81 82 void ath9k_ps_wakeup(struct ath_softc *sc) 83 { 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 85 unsigned long flags; 86 enum ath9k_power_mode power_mode; 87 88 spin_lock_irqsave(&sc->sc_pm_lock, flags); 89 if (++sc->ps_usecount != 1) 90 goto unlock; 91 92 power_mode = sc->sc_ah->power_mode; 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 94 95 /* 96 * While the hardware is asleep, the cycle counters contain no 97 * useful data. Better clear them now so that they don't mess up 98 * survey data results. 99 */ 100 if (power_mode != ATH9K_PM_AWAKE) { 101 spin_lock(&common->cc_lock); 102 ath_hw_cycle_counters_update(common); 103 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 104 spin_unlock(&common->cc_lock); 105 } 106 107 unlock: 108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 109 } 110 111 void ath9k_ps_restore(struct ath_softc *sc) 112 { 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 114 enum ath9k_power_mode mode; 115 unsigned long flags; 116 bool reset; 117 118 spin_lock_irqsave(&sc->sc_pm_lock, flags); 119 if (--sc->ps_usecount != 0) 120 goto unlock; 121 122 if (sc->ps_idle) { 123 ath9k_hw_setrxabort(sc->sc_ah, 1); 124 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 125 mode = ATH9K_PM_FULL_SLEEP; 126 } else if (sc->ps_enabled && 127 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 128 PS_WAIT_FOR_CAB | 129 PS_WAIT_FOR_PSPOLL_DATA | 130 PS_WAIT_FOR_TX_ACK))) { 131 mode = ATH9K_PM_NETWORK_SLEEP; 132 } else { 133 goto unlock; 134 } 135 136 spin_lock(&common->cc_lock); 137 ath_hw_cycle_counters_update(common); 138 spin_unlock(&common->cc_lock); 139 140 ath9k_hw_setpower(sc->sc_ah, mode); 141 142 unlock: 143 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 144 } 145 146 void ath_start_ani(struct ath_common *common) 147 { 148 struct ath_hw *ah = common->ah; 149 unsigned long timestamp = jiffies_to_msecs(jiffies); 150 struct ath_softc *sc = (struct ath_softc *) common->priv; 151 152 if (!(sc->sc_flags & SC_OP_ANI_RUN)) 153 return; 154 155 if (sc->sc_flags & SC_OP_OFFCHANNEL) 156 return; 157 158 common->ani.longcal_timer = timestamp; 159 common->ani.shortcal_timer = timestamp; 160 common->ani.checkani_timer = timestamp; 161 162 mod_timer(&common->ani.timer, 163 jiffies + 164 msecs_to_jiffies((u32)ah->config.ani_poll_interval)); 165 } 166 167 static void ath_update_survey_nf(struct ath_softc *sc, int channel) 168 { 169 struct ath_hw *ah = sc->sc_ah; 170 struct ath9k_channel *chan = &ah->channels[channel]; 171 struct survey_info *survey = &sc->survey[channel]; 172 173 if (chan->noisefloor) { 174 survey->filled |= SURVEY_INFO_NOISE_DBM; 175 survey->noise = ath9k_hw_getchan_noise(ah, chan); 176 } 177 } 178 179 /* 180 * Updates the survey statistics and returns the busy time since last 181 * update in %, if the measurement duration was long enough for the 182 * result to be useful, -1 otherwise. 183 */ 184 static int ath_update_survey_stats(struct ath_softc *sc) 185 { 186 struct ath_hw *ah = sc->sc_ah; 187 struct ath_common *common = ath9k_hw_common(ah); 188 int pos = ah->curchan - &ah->channels[0]; 189 struct survey_info *survey = &sc->survey[pos]; 190 struct ath_cycle_counters *cc = &common->cc_survey; 191 unsigned int div = common->clockrate * 1000; 192 int ret = 0; 193 194 if (!ah->curchan) 195 return -1; 196 197 if (ah->power_mode == ATH9K_PM_AWAKE) 198 ath_hw_cycle_counters_update(common); 199 200 if (cc->cycles > 0) { 201 survey->filled |= SURVEY_INFO_CHANNEL_TIME | 202 SURVEY_INFO_CHANNEL_TIME_BUSY | 203 SURVEY_INFO_CHANNEL_TIME_RX | 204 SURVEY_INFO_CHANNEL_TIME_TX; 205 survey->channel_time += cc->cycles / div; 206 survey->channel_time_busy += cc->rx_busy / div; 207 survey->channel_time_rx += cc->rx_frame / div; 208 survey->channel_time_tx += cc->tx_frame / div; 209 } 210 211 if (cc->cycles < div) 212 return -1; 213 214 if (cc->cycles > 0) 215 ret = cc->rx_busy * 100 / cc->cycles; 216 217 memset(cc, 0, sizeof(*cc)); 218 219 ath_update_survey_nf(sc, pos); 220 221 return ret; 222 } 223 224 static void __ath_cancel_work(struct ath_softc *sc) 225 { 226 cancel_work_sync(&sc->paprd_work); 227 cancel_work_sync(&sc->hw_check_work); 228 cancel_delayed_work_sync(&sc->tx_complete_work); 229 cancel_delayed_work_sync(&sc->hw_pll_work); 230 } 231 232 static void ath_cancel_work(struct ath_softc *sc) 233 { 234 __ath_cancel_work(sc); 235 cancel_work_sync(&sc->hw_reset_work); 236 } 237 238 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) 239 { 240 struct ath_hw *ah = sc->sc_ah; 241 struct ath_common *common = ath9k_hw_common(ah); 242 bool ret; 243 244 ieee80211_stop_queues(sc->hw); 245 246 sc->hw_busy_count = 0; 247 del_timer_sync(&common->ani.timer); 248 del_timer_sync(&sc->rx_poll_timer); 249 250 ath9k_debug_samp_bb_mac(sc); 251 ath9k_hw_disable_interrupts(ah); 252 253 ret = ath_drain_all_txq(sc, retry_tx); 254 255 if (!ath_stoprecv(sc)) 256 ret = false; 257 258 if (!flush) { 259 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 260 ath_rx_tasklet(sc, 1, true); 261 ath_rx_tasklet(sc, 1, false); 262 } else { 263 ath_flushrecv(sc); 264 } 265 266 return ret; 267 } 268 269 static bool ath_complete_reset(struct ath_softc *sc, bool start) 270 { 271 struct ath_hw *ah = sc->sc_ah; 272 struct ath_common *common = ath9k_hw_common(ah); 273 274 if (ath_startrecv(sc) != 0) { 275 ath_err(common, "Unable to restart recv logic\n"); 276 return false; 277 } 278 279 ath9k_cmn_update_txpow(ah, sc->curtxpow, 280 sc->config.txpowlimit, &sc->curtxpow); 281 ath9k_hw_set_interrupts(ah); 282 ath9k_hw_enable_interrupts(ah); 283 284 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) { 285 if (sc->sc_flags & SC_OP_BEACONS) 286 ath_set_beacon(sc); 287 288 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 289 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); 290 ath_start_rx_poll(sc, 3); 291 if (!common->disable_ani) 292 ath_start_ani(common); 293 } 294 295 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) { 296 struct ath_hw_antcomb_conf div_ant_conf; 297 u8 lna_conf; 298 299 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf); 300 301 if (sc->ant_rx == 1) 302 lna_conf = ATH_ANT_DIV_COMB_LNA1; 303 else 304 lna_conf = ATH_ANT_DIV_COMB_LNA2; 305 div_ant_conf.main_lna_conf = lna_conf; 306 div_ant_conf.alt_lna_conf = lna_conf; 307 308 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf); 309 } 310 311 ieee80211_wake_queues(sc->hw); 312 313 return true; 314 } 315 316 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, 317 bool retry_tx) 318 { 319 struct ath_hw *ah = sc->sc_ah; 320 struct ath_common *common = ath9k_hw_common(ah); 321 struct ath9k_hw_cal_data *caldata = NULL; 322 bool fastcc = true; 323 bool flush = false; 324 int r; 325 326 __ath_cancel_work(sc); 327 328 spin_lock_bh(&sc->sc_pcu_lock); 329 330 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) { 331 fastcc = false; 332 caldata = &sc->caldata; 333 } 334 335 if (!hchan) { 336 fastcc = false; 337 flush = true; 338 hchan = ah->curchan; 339 } 340 341 if (!ath_prepare_reset(sc, retry_tx, flush)) 342 fastcc = false; 343 344 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 345 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 346 347 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 348 if (r) { 349 ath_err(common, 350 "Unable to reset channel, reset status %d\n", r); 351 goto out; 352 } 353 354 if (!ath_complete_reset(sc, true)) 355 r = -EIO; 356 357 out: 358 spin_unlock_bh(&sc->sc_pcu_lock); 359 return r; 360 } 361 362 363 /* 364 * Set/change channels. If the channel is really being changed, it's done 365 * by reseting the chip. To accomplish this we must first cleanup any pending 366 * DMA, then restart stuff. 367 */ 368 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 369 struct ath9k_channel *hchan) 370 { 371 int r; 372 373 if (sc->sc_flags & SC_OP_INVALID) 374 return -EIO; 375 376 r = ath_reset_internal(sc, hchan, false); 377 378 return r; 379 } 380 381 static void ath_paprd_activate(struct ath_softc *sc) 382 { 383 struct ath_hw *ah = sc->sc_ah; 384 struct ath9k_hw_cal_data *caldata = ah->caldata; 385 int chain; 386 387 if (!caldata || !caldata->paprd_done) 388 return; 389 390 ath9k_ps_wakeup(sc); 391 ar9003_paprd_enable(ah, false); 392 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 393 if (!(ah->txchainmask & BIT(chain))) 394 continue; 395 396 ar9003_paprd_populate_single_table(ah, caldata, chain); 397 } 398 399 ar9003_paprd_enable(ah, true); 400 ath9k_ps_restore(sc); 401 } 402 403 static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) 404 { 405 struct ieee80211_hw *hw = sc->hw; 406 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 407 struct ath_hw *ah = sc->sc_ah; 408 struct ath_common *common = ath9k_hw_common(ah); 409 struct ath_tx_control txctl; 410 int time_left; 411 412 memset(&txctl, 0, sizeof(txctl)); 413 txctl.txq = sc->tx.txq_map[WME_AC_BE]; 414 415 memset(tx_info, 0, sizeof(*tx_info)); 416 tx_info->band = hw->conf.channel->band; 417 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; 418 tx_info->control.rates[0].idx = 0; 419 tx_info->control.rates[0].count = 1; 420 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; 421 tx_info->control.rates[1].idx = -1; 422 423 init_completion(&sc->paprd_complete); 424 txctl.paprd = BIT(chain); 425 426 if (ath_tx_start(hw, skb, &txctl) != 0) { 427 ath_dbg(common, CALIBRATE, "PAPRD TX failed\n"); 428 dev_kfree_skb_any(skb); 429 return false; 430 } 431 432 time_left = wait_for_completion_timeout(&sc->paprd_complete, 433 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); 434 435 if (!time_left) 436 ath_dbg(common, CALIBRATE, 437 "Timeout waiting for paprd training on TX chain %d\n", 438 chain); 439 440 return !!time_left; 441 } 442 443 void ath_paprd_calibrate(struct work_struct *work) 444 { 445 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); 446 struct ieee80211_hw *hw = sc->hw; 447 struct ath_hw *ah = sc->sc_ah; 448 struct ieee80211_hdr *hdr; 449 struct sk_buff *skb = NULL; 450 struct ath9k_hw_cal_data *caldata = ah->caldata; 451 struct ath_common *common = ath9k_hw_common(ah); 452 int ftype; 453 int chain_ok = 0; 454 int chain; 455 int len = 1800; 456 457 if (!caldata) 458 return; 459 460 ath9k_ps_wakeup(sc); 461 462 if (ar9003_paprd_init_table(ah) < 0) 463 goto fail_paprd; 464 465 skb = alloc_skb(len, GFP_KERNEL); 466 if (!skb) 467 goto fail_paprd; 468 469 skb_put(skb, len); 470 memset(skb->data, 0, len); 471 hdr = (struct ieee80211_hdr *)skb->data; 472 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; 473 hdr->frame_control = cpu_to_le16(ftype); 474 hdr->duration_id = cpu_to_le16(10); 475 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); 476 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); 477 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); 478 479 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 480 if (!(ah->txchainmask & BIT(chain))) 481 continue; 482 483 chain_ok = 0; 484 485 ath_dbg(common, CALIBRATE, 486 "Sending PAPRD frame for thermal measurement on chain %d\n", 487 chain); 488 if (!ath_paprd_send_frame(sc, skb, chain)) 489 goto fail_paprd; 490 491 ar9003_paprd_setup_gain_table(ah, chain); 492 493 ath_dbg(common, CALIBRATE, 494 "Sending PAPRD training frame on chain %d\n", chain); 495 if (!ath_paprd_send_frame(sc, skb, chain)) 496 goto fail_paprd; 497 498 if (!ar9003_paprd_is_done(ah)) { 499 ath_dbg(common, CALIBRATE, 500 "PAPRD not yet done on chain %d\n", chain); 501 break; 502 } 503 504 if (ar9003_paprd_create_curve(ah, caldata, chain)) { 505 ath_dbg(common, CALIBRATE, 506 "PAPRD create curve failed on chain %d\n", 507 chain); 508 break; 509 } 510 511 chain_ok = 1; 512 } 513 kfree_skb(skb); 514 515 if (chain_ok) { 516 caldata->paprd_done = true; 517 ath_paprd_activate(sc); 518 } 519 520 fail_paprd: 521 ath9k_ps_restore(sc); 522 } 523 524 /* 525 * This routine performs the periodic noise floor calibration function 526 * that is used to adjust and optimize the chip performance. This 527 * takes environmental changes (location, temperature) into account. 528 * When the task is complete, it reschedules itself depending on the 529 * appropriate interval that was calculated. 530 */ 531 void ath_ani_calibrate(unsigned long data) 532 { 533 struct ath_softc *sc = (struct ath_softc *)data; 534 struct ath_hw *ah = sc->sc_ah; 535 struct ath_common *common = ath9k_hw_common(ah); 536 bool longcal = false; 537 bool shortcal = false; 538 bool aniflag = false; 539 unsigned int timestamp = jiffies_to_msecs(jiffies); 540 u32 cal_interval, short_cal_interval, long_cal_interval; 541 unsigned long flags; 542 543 if (ah->caldata && ah->caldata->nfcal_interference) 544 long_cal_interval = ATH_LONG_CALINTERVAL_INT; 545 else 546 long_cal_interval = ATH_LONG_CALINTERVAL; 547 548 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? 549 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; 550 551 /* Only calibrate if awake */ 552 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) 553 goto set_timer; 554 555 ath9k_ps_wakeup(sc); 556 557 /* Long calibration runs independently of short calibration. */ 558 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { 559 longcal = true; 560 common->ani.longcal_timer = timestamp; 561 } 562 563 /* Short calibration applies only while caldone is false */ 564 if (!common->ani.caldone) { 565 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { 566 shortcal = true; 567 common->ani.shortcal_timer = timestamp; 568 common->ani.resetcal_timer = timestamp; 569 } 570 } else { 571 if ((timestamp - common->ani.resetcal_timer) >= 572 ATH_RESTART_CALINTERVAL) { 573 common->ani.caldone = ath9k_hw_reset_calvalid(ah); 574 if (common->ani.caldone) 575 common->ani.resetcal_timer = timestamp; 576 } 577 } 578 579 /* Verify whether we must check ANI */ 580 if (sc->sc_ah->config.enable_ani 581 && (timestamp - common->ani.checkani_timer) >= 582 ah->config.ani_poll_interval) { 583 aniflag = true; 584 common->ani.checkani_timer = timestamp; 585 } 586 587 /* Call ANI routine if necessary */ 588 if (aniflag) { 589 spin_lock_irqsave(&common->cc_lock, flags); 590 ath9k_hw_ani_monitor(ah, ah->curchan); 591 ath_update_survey_stats(sc); 592 spin_unlock_irqrestore(&common->cc_lock, flags); 593 } 594 595 /* Perform calibration if necessary */ 596 if (longcal || shortcal) { 597 common->ani.caldone = 598 ath9k_hw_calibrate(ah, ah->curchan, 599 ah->rxchainmask, longcal); 600 } 601 602 ath_dbg(common, ANI, 603 "Calibration @%lu finished: %s %s %s, caldone: %s\n", 604 jiffies, 605 longcal ? "long" : "", shortcal ? "short" : "", 606 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false"); 607 608 ath9k_ps_restore(sc); 609 610 set_timer: 611 /* 612 * Set timer interval based on previous results. 613 * The interval must be the shortest necessary to satisfy ANI, 614 * short calibration and long calibration. 615 */ 616 ath9k_debug_samp_bb_mac(sc); 617 cal_interval = ATH_LONG_CALINTERVAL; 618 if (sc->sc_ah->config.enable_ani) 619 cal_interval = min(cal_interval, 620 (u32)ah->config.ani_poll_interval); 621 if (!common->ani.caldone) 622 cal_interval = min(cal_interval, (u32)short_cal_interval); 623 624 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); 625 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { 626 if (!ah->caldata->paprd_done) 627 ieee80211_queue_work(sc->hw, &sc->paprd_work); 628 else if (!ah->paprd_table_write_done) 629 ath_paprd_activate(sc); 630 } 631 } 632 633 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 634 struct ieee80211_vif *vif) 635 { 636 struct ath_node *an; 637 an = (struct ath_node *)sta->drv_priv; 638 639 #ifdef CONFIG_ATH9K_DEBUGFS 640 spin_lock(&sc->nodes_lock); 641 list_add(&an->list, &sc->nodes); 642 spin_unlock(&sc->nodes_lock); 643 #endif 644 an->sta = sta; 645 an->vif = vif; 646 647 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 648 ath_tx_node_init(sc, an); 649 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 650 sta->ht_cap.ampdu_factor); 651 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); 652 } 653 } 654 655 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 656 { 657 struct ath_node *an = (struct ath_node *)sta->drv_priv; 658 659 #ifdef CONFIG_ATH9K_DEBUGFS 660 spin_lock(&sc->nodes_lock); 661 list_del(&an->list); 662 spin_unlock(&sc->nodes_lock); 663 an->sta = NULL; 664 #endif 665 666 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 667 ath_tx_node_cleanup(sc, an); 668 } 669 670 671 void ath9k_tasklet(unsigned long data) 672 { 673 struct ath_softc *sc = (struct ath_softc *)data; 674 struct ath_hw *ah = sc->sc_ah; 675 struct ath_common *common = ath9k_hw_common(ah); 676 677 u32 status = sc->intrstatus; 678 u32 rxmask; 679 680 ath9k_ps_wakeup(sc); 681 spin_lock(&sc->sc_pcu_lock); 682 683 if ((status & ATH9K_INT_FATAL) || 684 (status & ATH9K_INT_BB_WATCHDOG)) { 685 #ifdef CONFIG_ATH9K_DEBUGFS 686 enum ath_reset_type type; 687 688 if (status & ATH9K_INT_FATAL) 689 type = RESET_TYPE_FATAL_INT; 690 else 691 type = RESET_TYPE_BB_WATCHDOG; 692 693 RESET_STAT_INC(sc, type); 694 #endif 695 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 696 goto out; 697 } 698 699 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 700 /* 701 * TSF sync does not look correct; remain awake to sync with 702 * the next Beacon. 703 */ 704 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 705 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 706 } 707 708 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 709 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 710 ATH9K_INT_RXORN); 711 else 712 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 713 714 if (status & rxmask) { 715 /* Check for high priority Rx first */ 716 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 717 (status & ATH9K_INT_RXHP)) 718 ath_rx_tasklet(sc, 0, true); 719 720 ath_rx_tasklet(sc, 0, false); 721 } 722 723 if (status & ATH9K_INT_TX) { 724 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 725 ath_tx_edma_tasklet(sc); 726 else 727 ath_tx_tasklet(sc); 728 } 729 730 ath9k_btcoex_handle_interrupt(sc, status); 731 732 out: 733 /* re-enable hardware interrupt */ 734 ath9k_hw_enable_interrupts(ah); 735 736 spin_unlock(&sc->sc_pcu_lock); 737 ath9k_ps_restore(sc); 738 } 739 740 irqreturn_t ath_isr(int irq, void *dev) 741 { 742 #define SCHED_INTR ( \ 743 ATH9K_INT_FATAL | \ 744 ATH9K_INT_BB_WATCHDOG | \ 745 ATH9K_INT_RXORN | \ 746 ATH9K_INT_RXEOL | \ 747 ATH9K_INT_RX | \ 748 ATH9K_INT_RXLP | \ 749 ATH9K_INT_RXHP | \ 750 ATH9K_INT_TX | \ 751 ATH9K_INT_BMISS | \ 752 ATH9K_INT_CST | \ 753 ATH9K_INT_TSFOOR | \ 754 ATH9K_INT_GENTIMER | \ 755 ATH9K_INT_MCI) 756 757 struct ath_softc *sc = dev; 758 struct ath_hw *ah = sc->sc_ah; 759 struct ath_common *common = ath9k_hw_common(ah); 760 enum ath9k_int status; 761 bool sched = false; 762 763 /* 764 * The hardware is not ready/present, don't 765 * touch anything. Note this can happen early 766 * on if the IRQ is shared. 767 */ 768 if (sc->sc_flags & SC_OP_INVALID) 769 return IRQ_NONE; 770 771 772 /* shared irq, not for us */ 773 774 if (!ath9k_hw_intrpend(ah)) 775 return IRQ_NONE; 776 777 /* 778 * Figure out the reason(s) for the interrupt. Note 779 * that the hal returns a pseudo-ISR that may include 780 * bits we haven't explicitly enabled so we mask the 781 * value to insure we only process bits we requested. 782 */ 783 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 784 status &= ah->imask; /* discard unasked-for bits */ 785 786 /* 787 * If there are no status bits set, then this interrupt was not 788 * for me (should have been caught above). 789 */ 790 if (!status) 791 return IRQ_NONE; 792 793 /* Cache the status */ 794 sc->intrstatus = status; 795 796 if (status & SCHED_INTR) 797 sched = true; 798 799 /* 800 * If a FATAL or RXORN interrupt is received, we have to reset the 801 * chip immediately. 802 */ 803 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 804 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 805 goto chip_reset; 806 807 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 808 (status & ATH9K_INT_BB_WATCHDOG)) { 809 810 spin_lock(&common->cc_lock); 811 ath_hw_cycle_counters_update(common); 812 ar9003_hw_bb_watchdog_dbg_info(ah); 813 spin_unlock(&common->cc_lock); 814 815 goto chip_reset; 816 } 817 818 if (status & ATH9K_INT_SWBA) 819 tasklet_schedule(&sc->bcon_tasklet); 820 821 if (status & ATH9K_INT_TXURN) 822 ath9k_hw_updatetxtriglevel(ah, true); 823 824 if (status & ATH9K_INT_RXEOL) { 825 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 826 ath9k_hw_set_interrupts(ah); 827 } 828 829 if (status & ATH9K_INT_MIB) { 830 /* 831 * Disable interrupts until we service the MIB 832 * interrupt; otherwise it will continue to 833 * fire. 834 */ 835 ath9k_hw_disable_interrupts(ah); 836 /* 837 * Let the hal handle the event. We assume 838 * it will clear whatever condition caused 839 * the interrupt. 840 */ 841 spin_lock(&common->cc_lock); 842 ath9k_hw_proc_mib_event(ah); 843 spin_unlock(&common->cc_lock); 844 ath9k_hw_enable_interrupts(ah); 845 } 846 847 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 848 if (status & ATH9K_INT_TIM_TIMER) { 849 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 850 goto chip_reset; 851 /* Clear RxAbort bit so that we can 852 * receive frames */ 853 ath9k_setpower(sc, ATH9K_PM_AWAKE); 854 ath9k_hw_setrxabort(sc->sc_ah, 0); 855 sc->ps_flags |= PS_WAIT_FOR_BEACON; 856 } 857 858 chip_reset: 859 860 ath_debug_stat_interrupt(sc, status); 861 862 if (sched) { 863 /* turn off every interrupt */ 864 ath9k_hw_disable_interrupts(ah); 865 tasklet_schedule(&sc->intr_tq); 866 } 867 868 return IRQ_HANDLED; 869 870 #undef SCHED_INTR 871 } 872 873 static int ath_reset(struct ath_softc *sc, bool retry_tx) 874 { 875 int r; 876 877 ath9k_ps_wakeup(sc); 878 879 r = ath_reset_internal(sc, NULL, retry_tx); 880 881 if (retry_tx) { 882 int i; 883 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 884 if (ATH_TXQ_SETUP(sc, i)) { 885 spin_lock_bh(&sc->tx.txq[i].axq_lock); 886 ath_txq_schedule(sc, &sc->tx.txq[i]); 887 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 888 } 889 } 890 } 891 892 ath9k_ps_restore(sc); 893 894 return r; 895 } 896 897 void ath_reset_work(struct work_struct *work) 898 { 899 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 900 901 ath_reset(sc, true); 902 } 903 904 void ath_hw_check(struct work_struct *work) 905 { 906 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); 907 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 908 unsigned long flags; 909 int busy; 910 u8 is_alive, nbeacon = 1; 911 912 ath9k_ps_wakeup(sc); 913 is_alive = ath9k_hw_check_alive(sc->sc_ah); 914 915 if (is_alive && !AR_SREV_9300(sc->sc_ah)) 916 goto out; 917 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) { 918 ath_dbg(common, RESET, 919 "DCU stuck is detected. Schedule chip reset\n"); 920 RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG); 921 goto sched_reset; 922 } 923 924 spin_lock_irqsave(&common->cc_lock, flags); 925 busy = ath_update_survey_stats(sc); 926 spin_unlock_irqrestore(&common->cc_lock, flags); 927 928 ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n", 929 busy, sc->hw_busy_count + 1); 930 if (busy >= 99) { 931 if (++sc->hw_busy_count >= 3) { 932 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG); 933 goto sched_reset; 934 } 935 } else if (busy >= 0) { 936 sc->hw_busy_count = 0; 937 nbeacon = 3; 938 } 939 940 ath_start_rx_poll(sc, nbeacon); 941 goto out; 942 943 sched_reset: 944 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 945 out: 946 ath9k_ps_restore(sc); 947 } 948 949 static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) 950 { 951 static int count; 952 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 953 954 if (pll_sqsum >= 0x40000) { 955 count++; 956 if (count == 3) { 957 /* Rx is hung for more than 500ms. Reset it */ 958 ath_dbg(common, RESET, "Possible RX hang, resetting\n"); 959 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG); 960 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 961 count = 0; 962 } 963 } else 964 count = 0; 965 } 966 967 void ath_hw_pll_work(struct work_struct *work) 968 { 969 struct ath_softc *sc = container_of(work, struct ath_softc, 970 hw_pll_work.work); 971 u32 pll_sqsum; 972 973 if (AR_SREV_9485(sc->sc_ah)) { 974 975 ath9k_ps_wakeup(sc); 976 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah); 977 ath9k_ps_restore(sc); 978 979 ath_hw_pll_rx_hang_check(sc, pll_sqsum); 980 981 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5); 982 } 983 } 984 985 /**********************/ 986 /* mac80211 callbacks */ 987 /**********************/ 988 989 static int ath9k_start(struct ieee80211_hw *hw) 990 { 991 struct ath_softc *sc = hw->priv; 992 struct ath_hw *ah = sc->sc_ah; 993 struct ath_common *common = ath9k_hw_common(ah); 994 struct ieee80211_channel *curchan = hw->conf.channel; 995 struct ath9k_channel *init_channel; 996 int r; 997 998 ath_dbg(common, CONFIG, 999 "Starting driver with initial channel: %d MHz\n", 1000 curchan->center_freq); 1001 1002 ath9k_ps_wakeup(sc); 1003 mutex_lock(&sc->mutex); 1004 1005 init_channel = ath9k_cmn_get_curchannel(hw, ah); 1006 1007 /* Reset SERDES registers */ 1008 ath9k_hw_configpcipowersave(ah, false); 1009 1010 /* 1011 * The basic interface to setting the hardware in a good 1012 * state is ``reset''. On return the hardware is known to 1013 * be powered up and with interrupts disabled. This must 1014 * be followed by initialization of the appropriate bits 1015 * and then setup of the interrupt mask. 1016 */ 1017 spin_lock_bh(&sc->sc_pcu_lock); 1018 1019 atomic_set(&ah->intr_ref_cnt, -1); 1020 1021 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 1022 if (r) { 1023 ath_err(common, 1024 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 1025 r, curchan->center_freq); 1026 spin_unlock_bh(&sc->sc_pcu_lock); 1027 goto mutex_unlock; 1028 } 1029 1030 /* Setup our intr mask. */ 1031 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 1032 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 1033 ATH9K_INT_GLOBAL; 1034 1035 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 1036 ah->imask |= ATH9K_INT_RXHP | 1037 ATH9K_INT_RXLP | 1038 ATH9K_INT_BB_WATCHDOG; 1039 else 1040 ah->imask |= ATH9K_INT_RX; 1041 1042 ah->imask |= ATH9K_INT_GTT; 1043 1044 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 1045 ah->imask |= ATH9K_INT_CST; 1046 1047 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 1048 ah->imask |= ATH9K_INT_MCI; 1049 1050 sc->sc_flags &= ~SC_OP_INVALID; 1051 sc->sc_ah->is_monitoring = false; 1052 1053 if (!ath_complete_reset(sc, false)) { 1054 r = -EIO; 1055 spin_unlock_bh(&sc->sc_pcu_lock); 1056 goto mutex_unlock; 1057 } 1058 1059 if (ah->led_pin >= 0) { 1060 ath9k_hw_cfg_output(ah, ah->led_pin, 1061 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1062 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 1063 } 1064 1065 /* 1066 * Reset key cache to sane defaults (all entries cleared) instead of 1067 * semi-random values after suspend/resume. 1068 */ 1069 ath9k_cmn_init_crypto(sc->sc_ah); 1070 1071 spin_unlock_bh(&sc->sc_pcu_lock); 1072 1073 ath9k_start_btcoex(sc); 1074 1075 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) 1076 common->bus_ops->extn_synch_en(common); 1077 1078 mutex_unlock: 1079 mutex_unlock(&sc->mutex); 1080 1081 ath9k_ps_restore(sc); 1082 1083 return r; 1084 } 1085 1086 static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 1087 { 1088 struct ath_softc *sc = hw->priv; 1089 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1090 struct ath_tx_control txctl; 1091 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1092 1093 if (sc->ps_enabled) { 1094 /* 1095 * mac80211 does not set PM field for normal data frames, so we 1096 * need to update that based on the current PS mode. 1097 */ 1098 if (ieee80211_is_data(hdr->frame_control) && 1099 !ieee80211_is_nullfunc(hdr->frame_control) && 1100 !ieee80211_has_pm(hdr->frame_control)) { 1101 ath_dbg(common, PS, 1102 "Add PM=1 for a TX frame while in PS mode\n"); 1103 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1104 } 1105 } 1106 1107 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 1108 /* 1109 * We are using PS-Poll and mac80211 can request TX while in 1110 * power save mode. Need to wake up hardware for the TX to be 1111 * completed and if needed, also for RX of buffered frames. 1112 */ 1113 ath9k_ps_wakeup(sc); 1114 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 1115 ath9k_hw_setrxabort(sc->sc_ah, 0); 1116 if (ieee80211_is_pspoll(hdr->frame_control)) { 1117 ath_dbg(common, PS, 1118 "Sending PS-Poll to pick a buffered frame\n"); 1119 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 1120 } else { 1121 ath_dbg(common, PS, "Wake up to complete TX\n"); 1122 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 1123 } 1124 /* 1125 * The actual restore operation will happen only after 1126 * the ps_flags bit is cleared. We are just dropping 1127 * the ps_usecount here. 1128 */ 1129 ath9k_ps_restore(sc); 1130 } 1131 1132 /* 1133 * Cannot tx while the hardware is in full sleep, it first needs a full 1134 * chip reset to recover from that 1135 */ 1136 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 1137 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 1138 goto exit; 1139 } 1140 1141 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1142 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 1143 1144 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 1145 1146 if (ath_tx_start(hw, skb, &txctl) != 0) { 1147 ath_dbg(common, XMIT, "TX failed\n"); 1148 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 1149 goto exit; 1150 } 1151 1152 return; 1153 exit: 1154 dev_kfree_skb_any(skb); 1155 } 1156 1157 static void ath9k_stop(struct ieee80211_hw *hw) 1158 { 1159 struct ath_softc *sc = hw->priv; 1160 struct ath_hw *ah = sc->sc_ah; 1161 struct ath_common *common = ath9k_hw_common(ah); 1162 bool prev_idle; 1163 1164 mutex_lock(&sc->mutex); 1165 1166 ath_cancel_work(sc); 1167 del_timer_sync(&sc->rx_poll_timer); 1168 1169 if (sc->sc_flags & SC_OP_INVALID) { 1170 ath_dbg(common, ANY, "Device not present\n"); 1171 mutex_unlock(&sc->mutex); 1172 return; 1173 } 1174 1175 /* Ensure HW is awake when we try to shut it down. */ 1176 ath9k_ps_wakeup(sc); 1177 1178 ath9k_stop_btcoex(sc); 1179 1180 spin_lock_bh(&sc->sc_pcu_lock); 1181 1182 /* prevent tasklets to enable interrupts once we disable them */ 1183 ah->imask &= ~ATH9K_INT_GLOBAL; 1184 1185 /* make sure h/w will not generate any interrupt 1186 * before setting the invalid flag. */ 1187 ath9k_hw_disable_interrupts(ah); 1188 1189 spin_unlock_bh(&sc->sc_pcu_lock); 1190 1191 /* we can now sync irq and kill any running tasklets, since we already 1192 * disabled interrupts and not holding a spin lock */ 1193 synchronize_irq(sc->irq); 1194 tasklet_kill(&sc->intr_tq); 1195 tasklet_kill(&sc->bcon_tasklet); 1196 1197 prev_idle = sc->ps_idle; 1198 sc->ps_idle = true; 1199 1200 spin_lock_bh(&sc->sc_pcu_lock); 1201 1202 if (ah->led_pin >= 0) { 1203 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 1204 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 1205 } 1206 1207 ath_prepare_reset(sc, false, true); 1208 1209 if (sc->rx.frag) { 1210 dev_kfree_skb_any(sc->rx.frag); 1211 sc->rx.frag = NULL; 1212 } 1213 1214 if (!ah->curchan) 1215 ah->curchan = ath9k_cmn_get_curchannel(hw, ah); 1216 1217 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 1218 ath9k_hw_phy_disable(ah); 1219 1220 ath9k_hw_configpcipowersave(ah, true); 1221 1222 spin_unlock_bh(&sc->sc_pcu_lock); 1223 1224 ath9k_ps_restore(sc); 1225 1226 sc->sc_flags |= SC_OP_INVALID; 1227 sc->ps_idle = prev_idle; 1228 1229 mutex_unlock(&sc->mutex); 1230 1231 ath_dbg(common, CONFIG, "Driver halt\n"); 1232 } 1233 1234 bool ath9k_uses_beacons(int type) 1235 { 1236 switch (type) { 1237 case NL80211_IFTYPE_AP: 1238 case NL80211_IFTYPE_ADHOC: 1239 case NL80211_IFTYPE_MESH_POINT: 1240 return true; 1241 default: 1242 return false; 1243 } 1244 } 1245 1246 static void ath9k_reclaim_beacon(struct ath_softc *sc, 1247 struct ieee80211_vif *vif) 1248 { 1249 struct ath_vif *avp = (void *)vif->drv_priv; 1250 1251 ath9k_set_beaconing_status(sc, false); 1252 ath_beacon_return(sc, avp); 1253 ath9k_set_beaconing_status(sc, true); 1254 } 1255 1256 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1257 { 1258 struct ath9k_vif_iter_data *iter_data = data; 1259 int i; 1260 1261 if (iter_data->hw_macaddr) 1262 for (i = 0; i < ETH_ALEN; i++) 1263 iter_data->mask[i] &= 1264 ~(iter_data->hw_macaddr[i] ^ mac[i]); 1265 1266 switch (vif->type) { 1267 case NL80211_IFTYPE_AP: 1268 iter_data->naps++; 1269 break; 1270 case NL80211_IFTYPE_STATION: 1271 iter_data->nstations++; 1272 break; 1273 case NL80211_IFTYPE_ADHOC: 1274 iter_data->nadhocs++; 1275 break; 1276 case NL80211_IFTYPE_MESH_POINT: 1277 iter_data->nmeshes++; 1278 break; 1279 case NL80211_IFTYPE_WDS: 1280 iter_data->nwds++; 1281 break; 1282 default: 1283 break; 1284 } 1285 } 1286 1287 /* Called with sc->mutex held. */ 1288 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 1289 struct ieee80211_vif *vif, 1290 struct ath9k_vif_iter_data *iter_data) 1291 { 1292 struct ath_softc *sc = hw->priv; 1293 struct ath_hw *ah = sc->sc_ah; 1294 struct ath_common *common = ath9k_hw_common(ah); 1295 1296 /* 1297 * Use the hardware MAC address as reference, the hardware uses it 1298 * together with the BSSID mask when matching addresses. 1299 */ 1300 memset(iter_data, 0, sizeof(*iter_data)); 1301 iter_data->hw_macaddr = common->macaddr; 1302 memset(&iter_data->mask, 0xff, ETH_ALEN); 1303 1304 if (vif) 1305 ath9k_vif_iter(iter_data, vif->addr, vif); 1306 1307 /* Get list of all active MAC addresses */ 1308 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, 1309 iter_data); 1310 } 1311 1312 /* Called with sc->mutex held. */ 1313 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 1314 struct ieee80211_vif *vif) 1315 { 1316 struct ath_softc *sc = hw->priv; 1317 struct ath_hw *ah = sc->sc_ah; 1318 struct ath_common *common = ath9k_hw_common(ah); 1319 struct ath9k_vif_iter_data iter_data; 1320 1321 ath9k_calculate_iter_data(hw, vif, &iter_data); 1322 1323 /* Set BSSID mask. */ 1324 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1325 ath_hw_setbssidmask(common); 1326 1327 /* Set op-mode & TSF */ 1328 if (iter_data.naps > 0) { 1329 ath9k_hw_set_tsfadjust(ah, 1); 1330 sc->sc_flags |= SC_OP_TSF_RESET; 1331 ah->opmode = NL80211_IFTYPE_AP; 1332 } else { 1333 ath9k_hw_set_tsfadjust(ah, 0); 1334 sc->sc_flags &= ~SC_OP_TSF_RESET; 1335 1336 if (iter_data.nmeshes) 1337 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1338 else if (iter_data.nwds) 1339 ah->opmode = NL80211_IFTYPE_AP; 1340 else if (iter_data.nadhocs) 1341 ah->opmode = NL80211_IFTYPE_ADHOC; 1342 else 1343 ah->opmode = NL80211_IFTYPE_STATION; 1344 } 1345 1346 /* 1347 * Enable MIB interrupts when there are hardware phy counters. 1348 */ 1349 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { 1350 if (ah->config.enable_ani) 1351 ah->imask |= ATH9K_INT_MIB; 1352 ah->imask |= ATH9K_INT_TSFOOR; 1353 } else { 1354 ah->imask &= ~ATH9K_INT_MIB; 1355 ah->imask &= ~ATH9K_INT_TSFOOR; 1356 } 1357 1358 ath9k_hw_set_interrupts(ah); 1359 1360 /* Set up ANI */ 1361 if (iter_data.naps > 0) { 1362 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1363 1364 if (!common->disable_ani) { 1365 sc->sc_flags |= SC_OP_ANI_RUN; 1366 ath_start_ani(common); 1367 } 1368 1369 } else { 1370 sc->sc_flags &= ~SC_OP_ANI_RUN; 1371 del_timer_sync(&common->ani.timer); 1372 } 1373 } 1374 1375 /* Called with sc->mutex held, vif counts set up properly. */ 1376 static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, 1377 struct ieee80211_vif *vif) 1378 { 1379 struct ath_softc *sc = hw->priv; 1380 1381 ath9k_calculate_summary_state(hw, vif); 1382 1383 if (ath9k_uses_beacons(vif->type)) { 1384 /* Reserve a beacon slot for the vif */ 1385 ath9k_set_beaconing_status(sc, false); 1386 ath_beacon_alloc(sc, vif); 1387 ath9k_set_beaconing_status(sc, true); 1388 } 1389 } 1390 1391 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon) 1392 { 1393 if (!AR_SREV_9300(sc->sc_ah)) 1394 return; 1395 1396 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) 1397 return; 1398 1399 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies 1400 (nbeacon * sc->cur_beacon_conf.beacon_interval)); 1401 } 1402 1403 void ath_rx_poll(unsigned long data) 1404 { 1405 struct ath_softc *sc = (struct ath_softc *)data; 1406 1407 ieee80211_queue_work(sc->hw, &sc->hw_check_work); 1408 } 1409 1410 static int ath9k_add_interface(struct ieee80211_hw *hw, 1411 struct ieee80211_vif *vif) 1412 { 1413 struct ath_softc *sc = hw->priv; 1414 struct ath_hw *ah = sc->sc_ah; 1415 struct ath_common *common = ath9k_hw_common(ah); 1416 int ret = 0; 1417 1418 ath9k_ps_wakeup(sc); 1419 mutex_lock(&sc->mutex); 1420 1421 switch (vif->type) { 1422 case NL80211_IFTYPE_STATION: 1423 case NL80211_IFTYPE_WDS: 1424 case NL80211_IFTYPE_ADHOC: 1425 case NL80211_IFTYPE_AP: 1426 case NL80211_IFTYPE_MESH_POINT: 1427 break; 1428 default: 1429 ath_err(common, "Interface type %d not yet supported\n", 1430 vif->type); 1431 ret = -EOPNOTSUPP; 1432 goto out; 1433 } 1434 1435 if (ath9k_uses_beacons(vif->type)) { 1436 if (sc->nbcnvifs >= ATH_BCBUF) { 1437 ath_err(common, "Not enough beacon buffers when adding" 1438 " new interface of type: %i\n", 1439 vif->type); 1440 ret = -ENOBUFS; 1441 goto out; 1442 } 1443 } 1444 1445 if ((ah->opmode == NL80211_IFTYPE_ADHOC) || 1446 ((vif->type == NL80211_IFTYPE_ADHOC) && 1447 sc->nvifs > 0)) { 1448 ath_err(common, "Cannot create ADHOC interface when other" 1449 " interfaces already exist.\n"); 1450 ret = -EINVAL; 1451 goto out; 1452 } 1453 1454 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1455 1456 sc->nvifs++; 1457 1458 ath9k_do_vif_add_setup(hw, vif); 1459 out: 1460 mutex_unlock(&sc->mutex); 1461 ath9k_ps_restore(sc); 1462 return ret; 1463 } 1464 1465 static int ath9k_change_interface(struct ieee80211_hw *hw, 1466 struct ieee80211_vif *vif, 1467 enum nl80211_iftype new_type, 1468 bool p2p) 1469 { 1470 struct ath_softc *sc = hw->priv; 1471 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1472 int ret = 0; 1473 1474 ath_dbg(common, CONFIG, "Change Interface\n"); 1475 mutex_lock(&sc->mutex); 1476 ath9k_ps_wakeup(sc); 1477 1478 /* See if new interface type is valid. */ 1479 if ((new_type == NL80211_IFTYPE_ADHOC) && 1480 (sc->nvifs > 1)) { 1481 ath_err(common, "When using ADHOC, it must be the only" 1482 " interface.\n"); 1483 ret = -EINVAL; 1484 goto out; 1485 } 1486 1487 if (ath9k_uses_beacons(new_type) && 1488 !ath9k_uses_beacons(vif->type)) { 1489 if (sc->nbcnvifs >= ATH_BCBUF) { 1490 ath_err(common, "No beacon slot available\n"); 1491 ret = -ENOBUFS; 1492 goto out; 1493 } 1494 } 1495 1496 /* Clean up old vif stuff */ 1497 if (ath9k_uses_beacons(vif->type)) 1498 ath9k_reclaim_beacon(sc, vif); 1499 1500 /* Add new settings */ 1501 vif->type = new_type; 1502 vif->p2p = p2p; 1503 1504 ath9k_do_vif_add_setup(hw, vif); 1505 out: 1506 ath9k_ps_restore(sc); 1507 mutex_unlock(&sc->mutex); 1508 return ret; 1509 } 1510 1511 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1512 struct ieee80211_vif *vif) 1513 { 1514 struct ath_softc *sc = hw->priv; 1515 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1516 1517 ath_dbg(common, CONFIG, "Detach Interface\n"); 1518 1519 ath9k_ps_wakeup(sc); 1520 mutex_lock(&sc->mutex); 1521 1522 sc->nvifs--; 1523 1524 /* Reclaim beacon resources */ 1525 if (ath9k_uses_beacons(vif->type)) 1526 ath9k_reclaim_beacon(sc, vif); 1527 1528 ath9k_calculate_summary_state(hw, NULL); 1529 1530 mutex_unlock(&sc->mutex); 1531 ath9k_ps_restore(sc); 1532 } 1533 1534 static void ath9k_enable_ps(struct ath_softc *sc) 1535 { 1536 struct ath_hw *ah = sc->sc_ah; 1537 struct ath_common *common = ath9k_hw_common(ah); 1538 1539 sc->ps_enabled = true; 1540 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1541 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1542 ah->imask |= ATH9K_INT_TIM_TIMER; 1543 ath9k_hw_set_interrupts(ah); 1544 } 1545 ath9k_hw_setrxabort(ah, 1); 1546 } 1547 ath_dbg(common, PS, "PowerSave enabled\n"); 1548 } 1549 1550 static void ath9k_disable_ps(struct ath_softc *sc) 1551 { 1552 struct ath_hw *ah = sc->sc_ah; 1553 struct ath_common *common = ath9k_hw_common(ah); 1554 1555 sc->ps_enabled = false; 1556 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1557 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1558 ath9k_hw_setrxabort(ah, 0); 1559 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1560 PS_WAIT_FOR_CAB | 1561 PS_WAIT_FOR_PSPOLL_DATA | 1562 PS_WAIT_FOR_TX_ACK); 1563 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1564 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1565 ath9k_hw_set_interrupts(ah); 1566 } 1567 } 1568 ath_dbg(common, PS, "PowerSave disabled\n"); 1569 } 1570 1571 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1572 { 1573 struct ath_softc *sc = hw->priv; 1574 struct ath_hw *ah = sc->sc_ah; 1575 struct ath_common *common = ath9k_hw_common(ah); 1576 struct ieee80211_conf *conf = &hw->conf; 1577 bool reset_channel = false; 1578 1579 ath9k_ps_wakeup(sc); 1580 mutex_lock(&sc->mutex); 1581 1582 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1583 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1584 if (sc->ps_idle) 1585 ath_cancel_work(sc); 1586 else 1587 /* 1588 * The chip needs a reset to properly wake up from 1589 * full sleep 1590 */ 1591 reset_channel = ah->chip_fullsleep; 1592 } 1593 1594 /* 1595 * We just prepare to enable PS. We have to wait until our AP has 1596 * ACK'd our null data frame to disable RX otherwise we'll ignore 1597 * those ACKs and end up retransmitting the same null data frames. 1598 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1599 */ 1600 if (changed & IEEE80211_CONF_CHANGE_PS) { 1601 unsigned long flags; 1602 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1603 if (conf->flags & IEEE80211_CONF_PS) 1604 ath9k_enable_ps(sc); 1605 else 1606 ath9k_disable_ps(sc); 1607 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1608 } 1609 1610 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1611 if (conf->flags & IEEE80211_CONF_MONITOR) { 1612 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1613 sc->sc_ah->is_monitoring = true; 1614 } else { 1615 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1616 sc->sc_ah->is_monitoring = false; 1617 } 1618 } 1619 1620 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1621 struct ieee80211_channel *curchan = hw->conf.channel; 1622 int pos = curchan->hw_value; 1623 int old_pos = -1; 1624 unsigned long flags; 1625 1626 if (ah->curchan) 1627 old_pos = ah->curchan - &ah->channels[0]; 1628 1629 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 1630 sc->sc_flags |= SC_OP_OFFCHANNEL; 1631 else 1632 sc->sc_flags &= ~SC_OP_OFFCHANNEL; 1633 1634 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", 1635 curchan->center_freq, conf->channel_type); 1636 1637 /* update survey stats for the old channel before switching */ 1638 spin_lock_irqsave(&common->cc_lock, flags); 1639 ath_update_survey_stats(sc); 1640 spin_unlock_irqrestore(&common->cc_lock, flags); 1641 1642 /* 1643 * Preserve the current channel values, before updating 1644 * the same channel 1645 */ 1646 if (ah->curchan && (old_pos == pos)) 1647 ath9k_hw_getnf(ah, ah->curchan); 1648 1649 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], 1650 curchan, conf->channel_type); 1651 1652 /* 1653 * If the operating channel changes, change the survey in-use flags 1654 * along with it. 1655 * Reset the survey data for the new channel, unless we're switching 1656 * back to the operating channel from an off-channel operation. 1657 */ 1658 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && 1659 sc->cur_survey != &sc->survey[pos]) { 1660 1661 if (sc->cur_survey) 1662 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 1663 1664 sc->cur_survey = &sc->survey[pos]; 1665 1666 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 1667 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 1668 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 1669 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 1670 } 1671 1672 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1673 ath_err(common, "Unable to set channel\n"); 1674 mutex_unlock(&sc->mutex); 1675 return -EINVAL; 1676 } 1677 1678 /* 1679 * The most recent snapshot of channel->noisefloor for the old 1680 * channel is only available after the hardware reset. Copy it to 1681 * the survey stats now. 1682 */ 1683 if (old_pos >= 0) 1684 ath_update_survey_nf(sc, old_pos); 1685 } 1686 1687 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1688 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1689 sc->config.txpowlimit = 2 * conf->power_level; 1690 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1691 sc->config.txpowlimit, &sc->curtxpow); 1692 } 1693 1694 mutex_unlock(&sc->mutex); 1695 ath9k_ps_restore(sc); 1696 1697 return 0; 1698 } 1699 1700 #define SUPPORTED_FILTERS \ 1701 (FIF_PROMISC_IN_BSS | \ 1702 FIF_ALLMULTI | \ 1703 FIF_CONTROL | \ 1704 FIF_PSPOLL | \ 1705 FIF_OTHER_BSS | \ 1706 FIF_BCN_PRBRESP_PROMISC | \ 1707 FIF_PROBE_REQ | \ 1708 FIF_FCSFAIL) 1709 1710 /* FIXME: sc->sc_full_reset ? */ 1711 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1712 unsigned int changed_flags, 1713 unsigned int *total_flags, 1714 u64 multicast) 1715 { 1716 struct ath_softc *sc = hw->priv; 1717 u32 rfilt; 1718 1719 changed_flags &= SUPPORTED_FILTERS; 1720 *total_flags &= SUPPORTED_FILTERS; 1721 1722 sc->rx.rxfilter = *total_flags; 1723 ath9k_ps_wakeup(sc); 1724 rfilt = ath_calcrxfilter(sc); 1725 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1726 ath9k_ps_restore(sc); 1727 1728 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1729 rfilt); 1730 } 1731 1732 static int ath9k_sta_add(struct ieee80211_hw *hw, 1733 struct ieee80211_vif *vif, 1734 struct ieee80211_sta *sta) 1735 { 1736 struct ath_softc *sc = hw->priv; 1737 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1738 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1739 struct ieee80211_key_conf ps_key = { }; 1740 1741 ath_node_attach(sc, sta, vif); 1742 1743 if (vif->type != NL80211_IFTYPE_AP && 1744 vif->type != NL80211_IFTYPE_AP_VLAN) 1745 return 0; 1746 1747 an->ps_key = ath_key_config(common, vif, sta, &ps_key); 1748 1749 return 0; 1750 } 1751 1752 static void ath9k_del_ps_key(struct ath_softc *sc, 1753 struct ieee80211_vif *vif, 1754 struct ieee80211_sta *sta) 1755 { 1756 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1757 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1758 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1759 1760 if (!an->ps_key) 1761 return; 1762 1763 ath_key_delete(common, &ps_key); 1764 } 1765 1766 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1767 struct ieee80211_vif *vif, 1768 struct ieee80211_sta *sta) 1769 { 1770 struct ath_softc *sc = hw->priv; 1771 1772 ath9k_del_ps_key(sc, vif, sta); 1773 ath_node_detach(sc, sta); 1774 1775 return 0; 1776 } 1777 1778 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1779 struct ieee80211_vif *vif, 1780 enum sta_notify_cmd cmd, 1781 struct ieee80211_sta *sta) 1782 { 1783 struct ath_softc *sc = hw->priv; 1784 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1785 1786 if (!sta->ht_cap.ht_supported) 1787 return; 1788 1789 switch (cmd) { 1790 case STA_NOTIFY_SLEEP: 1791 an->sleeping = true; 1792 ath_tx_aggr_sleep(sta, sc, an); 1793 break; 1794 case STA_NOTIFY_AWAKE: 1795 an->sleeping = false; 1796 ath_tx_aggr_wakeup(sc, an); 1797 break; 1798 } 1799 } 1800 1801 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1802 struct ieee80211_vif *vif, u16 queue, 1803 const struct ieee80211_tx_queue_params *params) 1804 { 1805 struct ath_softc *sc = hw->priv; 1806 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1807 struct ath_txq *txq; 1808 struct ath9k_tx_queue_info qi; 1809 int ret = 0; 1810 1811 if (queue >= WME_NUM_AC) 1812 return 0; 1813 1814 txq = sc->tx.txq_map[queue]; 1815 1816 ath9k_ps_wakeup(sc); 1817 mutex_lock(&sc->mutex); 1818 1819 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1820 1821 qi.tqi_aifs = params->aifs; 1822 qi.tqi_cwmin = params->cw_min; 1823 qi.tqi_cwmax = params->cw_max; 1824 qi.tqi_burstTime = params->txop; 1825 1826 ath_dbg(common, CONFIG, 1827 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1828 queue, txq->axq_qnum, params->aifs, params->cw_min, 1829 params->cw_max, params->txop); 1830 1831 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1832 if (ret) 1833 ath_err(common, "TXQ Update failed\n"); 1834 1835 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) 1836 if (queue == WME_AC_BE && !ret) 1837 ath_beaconq_config(sc); 1838 1839 mutex_unlock(&sc->mutex); 1840 ath9k_ps_restore(sc); 1841 1842 return ret; 1843 } 1844 1845 static int ath9k_set_key(struct ieee80211_hw *hw, 1846 enum set_key_cmd cmd, 1847 struct ieee80211_vif *vif, 1848 struct ieee80211_sta *sta, 1849 struct ieee80211_key_conf *key) 1850 { 1851 struct ath_softc *sc = hw->priv; 1852 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1853 int ret = 0; 1854 1855 if (ath9k_modparam_nohwcrypt) 1856 return -ENOSPC; 1857 1858 if ((vif->type == NL80211_IFTYPE_ADHOC || 1859 vif->type == NL80211_IFTYPE_MESH_POINT) && 1860 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1861 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1862 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1863 /* 1864 * For now, disable hw crypto for the RSN IBSS group keys. This 1865 * could be optimized in the future to use a modified key cache 1866 * design to support per-STA RX GTK, but until that gets 1867 * implemented, use of software crypto for group addressed 1868 * frames is a acceptable to allow RSN IBSS to be used. 1869 */ 1870 return -EOPNOTSUPP; 1871 } 1872 1873 mutex_lock(&sc->mutex); 1874 ath9k_ps_wakeup(sc); 1875 ath_dbg(common, CONFIG, "Set HW Key\n"); 1876 1877 switch (cmd) { 1878 case SET_KEY: 1879 if (sta) 1880 ath9k_del_ps_key(sc, vif, sta); 1881 1882 ret = ath_key_config(common, vif, sta, key); 1883 if (ret >= 0) { 1884 key->hw_key_idx = ret; 1885 /* push IV and Michael MIC generation to stack */ 1886 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1887 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1888 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1889 if (sc->sc_ah->sw_mgmt_crypto && 1890 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1891 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; 1892 ret = 0; 1893 } 1894 break; 1895 case DISABLE_KEY: 1896 ath_key_delete(common, key); 1897 break; 1898 default: 1899 ret = -EINVAL; 1900 } 1901 1902 ath9k_ps_restore(sc); 1903 mutex_unlock(&sc->mutex); 1904 1905 return ret; 1906 } 1907 static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1908 { 1909 struct ath_softc *sc = data; 1910 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1911 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1912 struct ath_vif *avp = (void *)vif->drv_priv; 1913 1914 /* 1915 * Skip iteration if primary station vif's bss info 1916 * was not changed 1917 */ 1918 if (sc->sc_flags & SC_OP_PRIM_STA_VIF) 1919 return; 1920 1921 if (bss_conf->assoc) { 1922 sc->sc_flags |= SC_OP_PRIM_STA_VIF; 1923 avp->primary_sta_vif = true; 1924 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1925 common->curaid = bss_conf->aid; 1926 ath9k_hw_write_associd(sc->sc_ah); 1927 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", 1928 bss_conf->aid, common->curbssid); 1929 ath_beacon_config(sc, vif); 1930 /* 1931 * Request a re-configuration of Beacon related timers 1932 * on the receipt of the first Beacon frame (i.e., 1933 * after time sync with the AP). 1934 */ 1935 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1936 /* Reset rssi stats */ 1937 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1938 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1939 1940 ath_start_rx_poll(sc, 3); 1941 1942 if (!common->disable_ani) { 1943 sc->sc_flags |= SC_OP_ANI_RUN; 1944 ath_start_ani(common); 1945 } 1946 1947 } 1948 } 1949 1950 static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif) 1951 { 1952 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1953 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1954 struct ath_vif *avp = (void *)vif->drv_priv; 1955 1956 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1957 return; 1958 1959 /* Reconfigure bss info */ 1960 if (avp->primary_sta_vif && !bss_conf->assoc) { 1961 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n", 1962 common->curaid, common->curbssid); 1963 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); 1964 avp->primary_sta_vif = false; 1965 memset(common->curbssid, 0, ETH_ALEN); 1966 common->curaid = 0; 1967 } 1968 1969 ieee80211_iterate_active_interfaces_atomic( 1970 sc->hw, ath9k_bss_iter, sc); 1971 1972 /* 1973 * None of station vifs are associated. 1974 * Clear bssid & aid 1975 */ 1976 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) { 1977 ath9k_hw_write_associd(sc->sc_ah); 1978 /* Stop ANI */ 1979 sc->sc_flags &= ~SC_OP_ANI_RUN; 1980 del_timer_sync(&common->ani.timer); 1981 del_timer_sync(&sc->rx_poll_timer); 1982 memset(&sc->caldata, 0, sizeof(sc->caldata)); 1983 } 1984 } 1985 1986 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1987 struct ieee80211_vif *vif, 1988 struct ieee80211_bss_conf *bss_conf, 1989 u32 changed) 1990 { 1991 struct ath_softc *sc = hw->priv; 1992 struct ath_hw *ah = sc->sc_ah; 1993 struct ath_common *common = ath9k_hw_common(ah); 1994 struct ath_vif *avp = (void *)vif->drv_priv; 1995 int slottime; 1996 1997 ath9k_ps_wakeup(sc); 1998 mutex_lock(&sc->mutex); 1999 2000 if (changed & BSS_CHANGED_ASSOC) { 2001 ath9k_config_bss(sc, vif); 2002 2003 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n", 2004 common->curbssid, common->curaid); 2005 } 2006 2007 if (changed & BSS_CHANGED_IBSS) { 2008 /* There can be only one vif available */ 2009 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 2010 common->curaid = bss_conf->aid; 2011 ath9k_hw_write_associd(sc->sc_ah); 2012 2013 if (bss_conf->ibss_joined) { 2014 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 2015 2016 if (!common->disable_ani) { 2017 sc->sc_flags |= SC_OP_ANI_RUN; 2018 ath_start_ani(common); 2019 } 2020 2021 } else { 2022 sc->sc_flags &= ~SC_OP_ANI_RUN; 2023 del_timer_sync(&common->ani.timer); 2024 del_timer_sync(&sc->rx_poll_timer); 2025 } 2026 } 2027 2028 /* 2029 * In case of AP mode, the HW TSF has to be reset 2030 * when the beacon interval changes. 2031 */ 2032 if ((changed & BSS_CHANGED_BEACON_INT) && 2033 (vif->type == NL80211_IFTYPE_AP)) 2034 sc->sc_flags |= SC_OP_TSF_RESET; 2035 2036 /* Configure beaconing (AP, IBSS, MESH) */ 2037 if (ath9k_uses_beacons(vif->type) && 2038 ((changed & BSS_CHANGED_BEACON) || 2039 (changed & BSS_CHANGED_BEACON_ENABLED) || 2040 (changed & BSS_CHANGED_BEACON_INT))) { 2041 ath9k_set_beaconing_status(sc, false); 2042 if (bss_conf->enable_beacon) 2043 ath_beacon_alloc(sc, vif); 2044 else 2045 avp->is_bslot_active = false; 2046 ath_beacon_config(sc, vif); 2047 ath9k_set_beaconing_status(sc, true); 2048 } 2049 2050 if (changed & BSS_CHANGED_ERP_SLOT) { 2051 if (bss_conf->use_short_slot) 2052 slottime = 9; 2053 else 2054 slottime = 20; 2055 if (vif->type == NL80211_IFTYPE_AP) { 2056 /* 2057 * Defer update, so that connected stations can adjust 2058 * their settings at the same time. 2059 * See beacon.c for more details 2060 */ 2061 sc->beacon.slottime = slottime; 2062 sc->beacon.updateslot = UPDATE; 2063 } else { 2064 ah->slottime = slottime; 2065 ath9k_hw_init_global_settings(ah); 2066 } 2067 } 2068 2069 mutex_unlock(&sc->mutex); 2070 ath9k_ps_restore(sc); 2071 } 2072 2073 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 2074 { 2075 struct ath_softc *sc = hw->priv; 2076 u64 tsf; 2077 2078 mutex_lock(&sc->mutex); 2079 ath9k_ps_wakeup(sc); 2080 tsf = ath9k_hw_gettsf64(sc->sc_ah); 2081 ath9k_ps_restore(sc); 2082 mutex_unlock(&sc->mutex); 2083 2084 return tsf; 2085 } 2086 2087 static void ath9k_set_tsf(struct ieee80211_hw *hw, 2088 struct ieee80211_vif *vif, 2089 u64 tsf) 2090 { 2091 struct ath_softc *sc = hw->priv; 2092 2093 mutex_lock(&sc->mutex); 2094 ath9k_ps_wakeup(sc); 2095 ath9k_hw_settsf64(sc->sc_ah, tsf); 2096 ath9k_ps_restore(sc); 2097 mutex_unlock(&sc->mutex); 2098 } 2099 2100 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 2101 { 2102 struct ath_softc *sc = hw->priv; 2103 2104 mutex_lock(&sc->mutex); 2105 2106 ath9k_ps_wakeup(sc); 2107 ath9k_hw_reset_tsf(sc->sc_ah); 2108 ath9k_ps_restore(sc); 2109 2110 mutex_unlock(&sc->mutex); 2111 } 2112 2113 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 2114 struct ieee80211_vif *vif, 2115 enum ieee80211_ampdu_mlme_action action, 2116 struct ieee80211_sta *sta, 2117 u16 tid, u16 *ssn, u8 buf_size) 2118 { 2119 struct ath_softc *sc = hw->priv; 2120 int ret = 0; 2121 2122 local_bh_disable(); 2123 2124 switch (action) { 2125 case IEEE80211_AMPDU_RX_START: 2126 break; 2127 case IEEE80211_AMPDU_RX_STOP: 2128 break; 2129 case IEEE80211_AMPDU_TX_START: 2130 ath9k_ps_wakeup(sc); 2131 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 2132 if (!ret) 2133 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2134 ath9k_ps_restore(sc); 2135 break; 2136 case IEEE80211_AMPDU_TX_STOP: 2137 ath9k_ps_wakeup(sc); 2138 ath_tx_aggr_stop(sc, sta, tid); 2139 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2140 ath9k_ps_restore(sc); 2141 break; 2142 case IEEE80211_AMPDU_TX_OPERATIONAL: 2143 ath9k_ps_wakeup(sc); 2144 ath_tx_aggr_resume(sc, sta, tid); 2145 ath9k_ps_restore(sc); 2146 break; 2147 default: 2148 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 2149 } 2150 2151 local_bh_enable(); 2152 2153 return ret; 2154 } 2155 2156 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 2157 struct survey_info *survey) 2158 { 2159 struct ath_softc *sc = hw->priv; 2160 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2161 struct ieee80211_supported_band *sband; 2162 struct ieee80211_channel *chan; 2163 unsigned long flags; 2164 int pos; 2165 2166 spin_lock_irqsave(&common->cc_lock, flags); 2167 if (idx == 0) 2168 ath_update_survey_stats(sc); 2169 2170 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 2171 if (sband && idx >= sband->n_channels) { 2172 idx -= sband->n_channels; 2173 sband = NULL; 2174 } 2175 2176 if (!sband) 2177 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 2178 2179 if (!sband || idx >= sband->n_channels) { 2180 spin_unlock_irqrestore(&common->cc_lock, flags); 2181 return -ENOENT; 2182 } 2183 2184 chan = &sband->channels[idx]; 2185 pos = chan->hw_value; 2186 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 2187 survey->channel = chan; 2188 spin_unlock_irqrestore(&common->cc_lock, flags); 2189 2190 return 0; 2191 } 2192 2193 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 2194 { 2195 struct ath_softc *sc = hw->priv; 2196 struct ath_hw *ah = sc->sc_ah; 2197 2198 mutex_lock(&sc->mutex); 2199 ah->coverage_class = coverage_class; 2200 2201 ath9k_ps_wakeup(sc); 2202 ath9k_hw_init_global_settings(ah); 2203 ath9k_ps_restore(sc); 2204 2205 mutex_unlock(&sc->mutex); 2206 } 2207 2208 static void ath9k_flush(struct ieee80211_hw *hw, bool drop) 2209 { 2210 struct ath_softc *sc = hw->priv; 2211 struct ath_hw *ah = sc->sc_ah; 2212 struct ath_common *common = ath9k_hw_common(ah); 2213 int timeout = 200; /* ms */ 2214 int i, j; 2215 bool drain_txq; 2216 2217 mutex_lock(&sc->mutex); 2218 cancel_delayed_work_sync(&sc->tx_complete_work); 2219 2220 if (ah->ah_flags & AH_UNPLUGGED) { 2221 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2222 mutex_unlock(&sc->mutex); 2223 return; 2224 } 2225 2226 if (sc->sc_flags & SC_OP_INVALID) { 2227 ath_dbg(common, ANY, "Device not present\n"); 2228 mutex_unlock(&sc->mutex); 2229 return; 2230 } 2231 2232 for (j = 0; j < timeout; j++) { 2233 bool npend = false; 2234 2235 if (j) 2236 usleep_range(1000, 2000); 2237 2238 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2239 if (!ATH_TXQ_SETUP(sc, i)) 2240 continue; 2241 2242 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 2243 2244 if (npend) 2245 break; 2246 } 2247 2248 if (!npend) 2249 break; 2250 } 2251 2252 if (drop) { 2253 ath9k_ps_wakeup(sc); 2254 spin_lock_bh(&sc->sc_pcu_lock); 2255 drain_txq = ath_drain_all_txq(sc, false); 2256 spin_unlock_bh(&sc->sc_pcu_lock); 2257 2258 if (!drain_txq) 2259 ath_reset(sc, false); 2260 2261 ath9k_ps_restore(sc); 2262 ieee80211_wake_queues(hw); 2263 } 2264 2265 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 2266 mutex_unlock(&sc->mutex); 2267 } 2268 2269 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2270 { 2271 struct ath_softc *sc = hw->priv; 2272 int i; 2273 2274 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2275 if (!ATH_TXQ_SETUP(sc, i)) 2276 continue; 2277 2278 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 2279 return true; 2280 } 2281 return false; 2282 } 2283 2284 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2285 { 2286 struct ath_softc *sc = hw->priv; 2287 struct ath_hw *ah = sc->sc_ah; 2288 struct ieee80211_vif *vif; 2289 struct ath_vif *avp; 2290 struct ath_buf *bf; 2291 struct ath_tx_status ts; 2292 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2293 int status; 2294 2295 vif = sc->beacon.bslot[0]; 2296 if (!vif) 2297 return 0; 2298 2299 avp = (void *)vif->drv_priv; 2300 if (!avp->is_bslot_active) 2301 return 0; 2302 2303 if (!sc->beacon.tx_processed && !edma) { 2304 tasklet_disable(&sc->bcon_tasklet); 2305 2306 bf = avp->av_bcbuf; 2307 if (!bf || !bf->bf_mpdu) 2308 goto skip; 2309 2310 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2311 if (status == -EINPROGRESS) 2312 goto skip; 2313 2314 sc->beacon.tx_processed = true; 2315 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2316 2317 skip: 2318 tasklet_enable(&sc->bcon_tasklet); 2319 } 2320 2321 return sc->beacon.tx_last; 2322 } 2323 2324 static int ath9k_get_stats(struct ieee80211_hw *hw, 2325 struct ieee80211_low_level_stats *stats) 2326 { 2327 struct ath_softc *sc = hw->priv; 2328 struct ath_hw *ah = sc->sc_ah; 2329 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2330 2331 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2332 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2333 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2334 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2335 return 0; 2336 } 2337 2338 static u32 fill_chainmask(u32 cap, u32 new) 2339 { 2340 u32 filled = 0; 2341 int i; 2342 2343 for (i = 0; cap && new; i++, cap >>= 1) { 2344 if (!(cap & BIT(0))) 2345 continue; 2346 2347 if (new & BIT(0)) 2348 filled |= BIT(i); 2349 2350 new >>= 1; 2351 } 2352 2353 return filled; 2354 } 2355 2356 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2357 { 2358 struct ath_softc *sc = hw->priv; 2359 struct ath_hw *ah = sc->sc_ah; 2360 2361 if (!rx_ant || !tx_ant) 2362 return -EINVAL; 2363 2364 sc->ant_rx = rx_ant; 2365 sc->ant_tx = tx_ant; 2366 2367 if (ah->caps.rx_chainmask == 1) 2368 return 0; 2369 2370 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2371 if (AR_SREV_9100(ah)) 2372 ah->rxchainmask = 0x7; 2373 else 2374 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2375 2376 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2377 ath9k_reload_chainmask_settings(sc); 2378 2379 return 0; 2380 } 2381 2382 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2383 { 2384 struct ath_softc *sc = hw->priv; 2385 2386 *tx_ant = sc->ant_tx; 2387 *rx_ant = sc->ant_rx; 2388 return 0; 2389 } 2390 2391 struct ieee80211_ops ath9k_ops = { 2392 .tx = ath9k_tx, 2393 .start = ath9k_start, 2394 .stop = ath9k_stop, 2395 .add_interface = ath9k_add_interface, 2396 .change_interface = ath9k_change_interface, 2397 .remove_interface = ath9k_remove_interface, 2398 .config = ath9k_config, 2399 .configure_filter = ath9k_configure_filter, 2400 .sta_add = ath9k_sta_add, 2401 .sta_remove = ath9k_sta_remove, 2402 .sta_notify = ath9k_sta_notify, 2403 .conf_tx = ath9k_conf_tx, 2404 .bss_info_changed = ath9k_bss_info_changed, 2405 .set_key = ath9k_set_key, 2406 .get_tsf = ath9k_get_tsf, 2407 .set_tsf = ath9k_set_tsf, 2408 .reset_tsf = ath9k_reset_tsf, 2409 .ampdu_action = ath9k_ampdu_action, 2410 .get_survey = ath9k_get_survey, 2411 .rfkill_poll = ath9k_rfkill_poll_state, 2412 .set_coverage_class = ath9k_set_coverage_class, 2413 .flush = ath9k_flush, 2414 .tx_frames_pending = ath9k_tx_frames_pending, 2415 .tx_last_beacon = ath9k_tx_last_beacon, 2416 .get_stats = ath9k_get_stats, 2417 .set_antenna = ath9k_set_antenna, 2418 .get_antenna = ath9k_get_antenna, 2419 }; 2420