1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_set_assoc_state(struct ath_softc *sc, 23 struct ieee80211_vif *vif); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 61 { 62 bool pending = false; 63 64 spin_lock_bh(&txq->axq_lock); 65 66 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 67 pending = true; 68 69 spin_unlock_bh(&txq->axq_lock); 70 return pending; 71 } 72 73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 74 { 75 unsigned long flags; 76 bool ret; 77 78 spin_lock_irqsave(&sc->sc_pm_lock, flags); 79 ret = ath9k_hw_setpower(sc->sc_ah, mode); 80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 81 82 return ret; 83 } 84 85 void ath9k_ps_wakeup(struct ath_softc *sc) 86 { 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 88 unsigned long flags; 89 enum ath9k_power_mode power_mode; 90 91 spin_lock_irqsave(&sc->sc_pm_lock, flags); 92 if (++sc->ps_usecount != 1) 93 goto unlock; 94 95 power_mode = sc->sc_ah->power_mode; 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 97 98 /* 99 * While the hardware is asleep, the cycle counters contain no 100 * useful data. Better clear them now so that they don't mess up 101 * survey data results. 102 */ 103 if (power_mode != ATH9K_PM_AWAKE) { 104 spin_lock(&common->cc_lock); 105 ath_hw_cycle_counters_update(common); 106 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 108 spin_unlock(&common->cc_lock); 109 } 110 111 unlock: 112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 113 } 114 115 void ath9k_ps_restore(struct ath_softc *sc) 116 { 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 118 enum ath9k_power_mode mode; 119 unsigned long flags; 120 bool reset; 121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags); 123 if (--sc->ps_usecount != 0) 124 goto unlock; 125 126 if (sc->ps_idle) { 127 ath9k_hw_setrxabort(sc->sc_ah, 1); 128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 129 mode = ATH9K_PM_FULL_SLEEP; 130 } else if (sc->ps_enabled && 131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 132 PS_WAIT_FOR_CAB | 133 PS_WAIT_FOR_PSPOLL_DATA | 134 PS_WAIT_FOR_TX_ACK))) { 135 mode = ATH9K_PM_NETWORK_SLEEP; 136 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 137 ath9k_btcoex_stop_gen_timer(sc); 138 } else { 139 goto unlock; 140 } 141 142 spin_lock(&common->cc_lock); 143 ath_hw_cycle_counters_update(common); 144 spin_unlock(&common->cc_lock); 145 146 ath9k_hw_setpower(sc->sc_ah, mode); 147 148 unlock: 149 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 150 } 151 152 static void __ath_cancel_work(struct ath_softc *sc) 153 { 154 cancel_work_sync(&sc->paprd_work); 155 cancel_work_sync(&sc->hw_check_work); 156 cancel_delayed_work_sync(&sc->tx_complete_work); 157 cancel_delayed_work_sync(&sc->hw_pll_work); 158 159 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 160 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 161 cancel_work_sync(&sc->mci_work); 162 #endif 163 } 164 165 static void ath_cancel_work(struct ath_softc *sc) 166 { 167 __ath_cancel_work(sc); 168 cancel_work_sync(&sc->hw_reset_work); 169 } 170 171 static void ath_restart_work(struct ath_softc *sc) 172 { 173 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 174 175 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || 176 AR_SREV_9550(sc->sc_ah)) 177 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 178 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 179 180 ath_start_rx_poll(sc, 3); 181 ath_start_ani(sc); 182 } 183 184 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) 185 { 186 struct ath_hw *ah = sc->sc_ah; 187 bool ret = true; 188 189 ieee80211_stop_queues(sc->hw); 190 191 sc->hw_busy_count = 0; 192 ath_stop_ani(sc); 193 del_timer_sync(&sc->rx_poll_timer); 194 195 ath9k_debug_samp_bb_mac(sc); 196 ath9k_hw_disable_interrupts(ah); 197 198 if (!ath_stoprecv(sc)) 199 ret = false; 200 201 if (!ath_drain_all_txq(sc, retry_tx)) 202 ret = false; 203 204 if (!flush) { 205 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 206 ath_rx_tasklet(sc, 1, true); 207 ath_rx_tasklet(sc, 1, false); 208 } else { 209 ath_flushrecv(sc); 210 } 211 212 return ret; 213 } 214 215 static bool ath_complete_reset(struct ath_softc *sc, bool start) 216 { 217 struct ath_hw *ah = sc->sc_ah; 218 struct ath_common *common = ath9k_hw_common(ah); 219 unsigned long flags; 220 221 if (ath_startrecv(sc) != 0) { 222 ath_err(common, "Unable to restart recv logic\n"); 223 return false; 224 } 225 226 ath9k_cmn_update_txpow(ah, sc->curtxpow, 227 sc->config.txpowlimit, &sc->curtxpow); 228 229 clear_bit(SC_OP_HW_RESET, &sc->sc_flags); 230 ath9k_hw_set_interrupts(ah); 231 ath9k_hw_enable_interrupts(ah); 232 233 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { 234 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) 235 goto work; 236 237 ath9k_set_beacon(sc); 238 239 if (ah->opmode == NL80211_IFTYPE_STATION && 240 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 241 spin_lock_irqsave(&sc->sc_pm_lock, flags); 242 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 243 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 244 } 245 work: 246 ath_restart_work(sc); 247 } 248 249 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) 250 ath_ant_comb_update(sc); 251 252 ieee80211_wake_queues(sc->hw); 253 254 return true; 255 } 256 257 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, 258 bool retry_tx) 259 { 260 struct ath_hw *ah = sc->sc_ah; 261 struct ath_common *common = ath9k_hw_common(ah); 262 struct ath9k_hw_cal_data *caldata = NULL; 263 bool fastcc = true; 264 bool flush = false; 265 int r; 266 267 __ath_cancel_work(sc); 268 269 spin_lock_bh(&sc->sc_pcu_lock); 270 271 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { 272 fastcc = false; 273 caldata = &sc->caldata; 274 } 275 276 if (!hchan) { 277 fastcc = false; 278 flush = true; 279 hchan = ah->curchan; 280 } 281 282 if (!ath_prepare_reset(sc, retry_tx, flush)) 283 fastcc = false; 284 285 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 286 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 287 288 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 289 if (r) { 290 ath_err(common, 291 "Unable to reset channel, reset status %d\n", r); 292 goto out; 293 } 294 295 if (!ath_complete_reset(sc, true)) 296 r = -EIO; 297 298 out: 299 spin_unlock_bh(&sc->sc_pcu_lock); 300 return r; 301 } 302 303 304 /* 305 * Set/change channels. If the channel is really being changed, it's done 306 * by reseting the chip. To accomplish this we must first cleanup any pending 307 * DMA, then restart stuff. 308 */ 309 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 310 struct ath9k_channel *hchan) 311 { 312 int r; 313 314 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 315 return -EIO; 316 317 r = ath_reset_internal(sc, hchan, false); 318 319 return r; 320 } 321 322 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 323 struct ieee80211_vif *vif) 324 { 325 struct ath_node *an; 326 u8 density; 327 an = (struct ath_node *)sta->drv_priv; 328 329 #ifdef CONFIG_ATH9K_DEBUGFS 330 spin_lock(&sc->nodes_lock); 331 list_add(&an->list, &sc->nodes); 332 spin_unlock(&sc->nodes_lock); 333 #endif 334 an->sta = sta; 335 an->vif = vif; 336 337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 338 ath_tx_node_init(sc, an); 339 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 340 sta->ht_cap.ampdu_factor); 341 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 342 an->mpdudensity = density; 343 } 344 } 345 346 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 347 { 348 struct ath_node *an = (struct ath_node *)sta->drv_priv; 349 350 #ifdef CONFIG_ATH9K_DEBUGFS 351 spin_lock(&sc->nodes_lock); 352 list_del(&an->list); 353 spin_unlock(&sc->nodes_lock); 354 an->sta = NULL; 355 #endif 356 357 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 358 ath_tx_node_cleanup(sc, an); 359 } 360 361 void ath9k_tasklet(unsigned long data) 362 { 363 struct ath_softc *sc = (struct ath_softc *)data; 364 struct ath_hw *ah = sc->sc_ah; 365 struct ath_common *common = ath9k_hw_common(ah); 366 enum ath_reset_type type; 367 unsigned long flags; 368 u32 status = sc->intrstatus; 369 u32 rxmask; 370 371 ath9k_ps_wakeup(sc); 372 spin_lock(&sc->sc_pcu_lock); 373 374 if ((status & ATH9K_INT_FATAL) || 375 (status & ATH9K_INT_BB_WATCHDOG)) { 376 377 if (status & ATH9K_INT_FATAL) 378 type = RESET_TYPE_FATAL_INT; 379 else 380 type = RESET_TYPE_BB_WATCHDOG; 381 382 ath9k_queue_reset(sc, type); 383 goto out; 384 } 385 386 spin_lock_irqsave(&sc->sc_pm_lock, flags); 387 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 388 /* 389 * TSF sync does not look correct; remain awake to sync with 390 * the next Beacon. 391 */ 392 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 393 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 394 } 395 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 396 397 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 398 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 399 ATH9K_INT_RXORN); 400 else 401 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 402 403 if (status & rxmask) { 404 /* Check for high priority Rx first */ 405 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 406 (status & ATH9K_INT_RXHP)) 407 ath_rx_tasklet(sc, 0, true); 408 409 ath_rx_tasklet(sc, 0, false); 410 } 411 412 if (status & ATH9K_INT_TX) { 413 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 414 ath_tx_edma_tasklet(sc); 415 else 416 ath_tx_tasklet(sc); 417 } 418 419 ath9k_btcoex_handle_interrupt(sc, status); 420 421 out: 422 /* re-enable hardware interrupt */ 423 ath9k_hw_enable_interrupts(ah); 424 425 spin_unlock(&sc->sc_pcu_lock); 426 ath9k_ps_restore(sc); 427 } 428 429 irqreturn_t ath_isr(int irq, void *dev) 430 { 431 #define SCHED_INTR ( \ 432 ATH9K_INT_FATAL | \ 433 ATH9K_INT_BB_WATCHDOG | \ 434 ATH9K_INT_RXORN | \ 435 ATH9K_INT_RXEOL | \ 436 ATH9K_INT_RX | \ 437 ATH9K_INT_RXLP | \ 438 ATH9K_INT_RXHP | \ 439 ATH9K_INT_TX | \ 440 ATH9K_INT_BMISS | \ 441 ATH9K_INT_CST | \ 442 ATH9K_INT_TSFOOR | \ 443 ATH9K_INT_GENTIMER | \ 444 ATH9K_INT_MCI) 445 446 struct ath_softc *sc = dev; 447 struct ath_hw *ah = sc->sc_ah; 448 struct ath_common *common = ath9k_hw_common(ah); 449 enum ath9k_int status; 450 bool sched = false; 451 452 /* 453 * The hardware is not ready/present, don't 454 * touch anything. Note this can happen early 455 * on if the IRQ is shared. 456 */ 457 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 458 return IRQ_NONE; 459 460 /* shared irq, not for us */ 461 462 if (!ath9k_hw_intrpend(ah)) 463 return IRQ_NONE; 464 465 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { 466 ath9k_hw_kill_interrupts(ah); 467 return IRQ_HANDLED; 468 } 469 470 /* 471 * Figure out the reason(s) for the interrupt. Note 472 * that the hal returns a pseudo-ISR that may include 473 * bits we haven't explicitly enabled so we mask the 474 * value to insure we only process bits we requested. 475 */ 476 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 477 status &= ah->imask; /* discard unasked-for bits */ 478 479 /* 480 * If there are no status bits set, then this interrupt was not 481 * for me (should have been caught above). 482 */ 483 if (!status) 484 return IRQ_NONE; 485 486 /* Cache the status */ 487 sc->intrstatus = status; 488 489 if (status & SCHED_INTR) 490 sched = true; 491 492 #ifdef CONFIG_PM_SLEEP 493 if (status & ATH9K_INT_BMISS) { 494 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 495 ath_dbg(common, ANY, "during WoW we got a BMISS\n"); 496 atomic_inc(&sc->wow_got_bmiss_intr); 497 atomic_dec(&sc->wow_sleep_proc_intr); 498 } 499 ath_dbg(common, INTERRUPT, "beacon miss interrupt\n"); 500 } 501 #endif 502 503 /* 504 * If a FATAL or RXORN interrupt is received, we have to reset the 505 * chip immediately. 506 */ 507 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 508 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 509 goto chip_reset; 510 511 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 512 (status & ATH9K_INT_BB_WATCHDOG)) { 513 514 spin_lock(&common->cc_lock); 515 ath_hw_cycle_counters_update(common); 516 ar9003_hw_bb_watchdog_dbg_info(ah); 517 spin_unlock(&common->cc_lock); 518 519 goto chip_reset; 520 } 521 522 if (status & ATH9K_INT_SWBA) 523 tasklet_schedule(&sc->bcon_tasklet); 524 525 if (status & ATH9K_INT_TXURN) 526 ath9k_hw_updatetxtriglevel(ah, true); 527 528 if (status & ATH9K_INT_RXEOL) { 529 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 530 ath9k_hw_set_interrupts(ah); 531 } 532 533 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 534 if (status & ATH9K_INT_TIM_TIMER) { 535 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 536 goto chip_reset; 537 /* Clear RxAbort bit so that we can 538 * receive frames */ 539 ath9k_setpower(sc, ATH9K_PM_AWAKE); 540 spin_lock(&sc->sc_pm_lock); 541 ath9k_hw_setrxabort(sc->sc_ah, 0); 542 sc->ps_flags |= PS_WAIT_FOR_BEACON; 543 spin_unlock(&sc->sc_pm_lock); 544 } 545 546 chip_reset: 547 548 ath_debug_stat_interrupt(sc, status); 549 550 if (sched) { 551 /* turn off every interrupt */ 552 ath9k_hw_disable_interrupts(ah); 553 tasklet_schedule(&sc->intr_tq); 554 } 555 556 return IRQ_HANDLED; 557 558 #undef SCHED_INTR 559 } 560 561 static int ath_reset(struct ath_softc *sc, bool retry_tx) 562 { 563 int r; 564 565 ath9k_ps_wakeup(sc); 566 567 r = ath_reset_internal(sc, NULL, retry_tx); 568 569 if (retry_tx) { 570 int i; 571 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 572 if (ATH_TXQ_SETUP(sc, i)) { 573 spin_lock_bh(&sc->tx.txq[i].axq_lock); 574 ath_txq_schedule(sc, &sc->tx.txq[i]); 575 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 576 } 577 } 578 } 579 580 ath9k_ps_restore(sc); 581 582 return r; 583 } 584 585 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 586 { 587 #ifdef CONFIG_ATH9K_DEBUGFS 588 RESET_STAT_INC(sc, type); 589 #endif 590 set_bit(SC_OP_HW_RESET, &sc->sc_flags); 591 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 592 } 593 594 void ath_reset_work(struct work_struct *work) 595 { 596 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 597 598 ath_reset(sc, true); 599 } 600 601 /**********************/ 602 /* mac80211 callbacks */ 603 /**********************/ 604 605 static int ath9k_start(struct ieee80211_hw *hw) 606 { 607 struct ath_softc *sc = hw->priv; 608 struct ath_hw *ah = sc->sc_ah; 609 struct ath_common *common = ath9k_hw_common(ah); 610 struct ieee80211_channel *curchan = hw->conf.channel; 611 struct ath9k_channel *init_channel; 612 int r; 613 614 ath_dbg(common, CONFIG, 615 "Starting driver with initial channel: %d MHz\n", 616 curchan->center_freq); 617 618 ath9k_ps_wakeup(sc); 619 mutex_lock(&sc->mutex); 620 621 init_channel = ath9k_cmn_get_curchannel(hw, ah); 622 623 /* Reset SERDES registers */ 624 ath9k_hw_configpcipowersave(ah, false); 625 626 /* 627 * The basic interface to setting the hardware in a good 628 * state is ``reset''. On return the hardware is known to 629 * be powered up and with interrupts disabled. This must 630 * be followed by initialization of the appropriate bits 631 * and then setup of the interrupt mask. 632 */ 633 spin_lock_bh(&sc->sc_pcu_lock); 634 635 atomic_set(&ah->intr_ref_cnt, -1); 636 637 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 638 if (r) { 639 ath_err(common, 640 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 641 r, curchan->center_freq); 642 spin_unlock_bh(&sc->sc_pcu_lock); 643 goto mutex_unlock; 644 } 645 646 /* Setup our intr mask. */ 647 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 648 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 649 ATH9K_INT_GLOBAL; 650 651 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 652 ah->imask |= ATH9K_INT_RXHP | 653 ATH9K_INT_RXLP | 654 ATH9K_INT_BB_WATCHDOG; 655 else 656 ah->imask |= ATH9K_INT_RX; 657 658 ah->imask |= ATH9K_INT_GTT; 659 660 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 661 ah->imask |= ATH9K_INT_CST; 662 663 ath_mci_enable(sc); 664 665 clear_bit(SC_OP_INVALID, &sc->sc_flags); 666 sc->sc_ah->is_monitoring = false; 667 668 if (!ath_complete_reset(sc, false)) { 669 r = -EIO; 670 spin_unlock_bh(&sc->sc_pcu_lock); 671 goto mutex_unlock; 672 } 673 674 if (ah->led_pin >= 0) { 675 ath9k_hw_cfg_output(ah, ah->led_pin, 676 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 677 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 678 } 679 680 /* 681 * Reset key cache to sane defaults (all entries cleared) instead of 682 * semi-random values after suspend/resume. 683 */ 684 ath9k_cmn_init_crypto(sc->sc_ah); 685 686 spin_unlock_bh(&sc->sc_pcu_lock); 687 688 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) 689 common->bus_ops->extn_synch_en(common); 690 691 mutex_unlock: 692 mutex_unlock(&sc->mutex); 693 694 ath9k_ps_restore(sc); 695 696 return r; 697 } 698 699 static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 700 { 701 struct ath_softc *sc = hw->priv; 702 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 703 struct ath_tx_control txctl; 704 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 705 unsigned long flags; 706 707 if (sc->ps_enabled) { 708 /* 709 * mac80211 does not set PM field for normal data frames, so we 710 * need to update that based on the current PS mode. 711 */ 712 if (ieee80211_is_data(hdr->frame_control) && 713 !ieee80211_is_nullfunc(hdr->frame_control) && 714 !ieee80211_has_pm(hdr->frame_control)) { 715 ath_dbg(common, PS, 716 "Add PM=1 for a TX frame while in PS mode\n"); 717 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 718 } 719 } 720 721 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 722 /* 723 * We are using PS-Poll and mac80211 can request TX while in 724 * power save mode. Need to wake up hardware for the TX to be 725 * completed and if needed, also for RX of buffered frames. 726 */ 727 ath9k_ps_wakeup(sc); 728 spin_lock_irqsave(&sc->sc_pm_lock, flags); 729 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 730 ath9k_hw_setrxabort(sc->sc_ah, 0); 731 if (ieee80211_is_pspoll(hdr->frame_control)) { 732 ath_dbg(common, PS, 733 "Sending PS-Poll to pick a buffered frame\n"); 734 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 735 } else { 736 ath_dbg(common, PS, "Wake up to complete TX\n"); 737 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 738 } 739 /* 740 * The actual restore operation will happen only after 741 * the ps_flags bit is cleared. We are just dropping 742 * the ps_usecount here. 743 */ 744 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 745 ath9k_ps_restore(sc); 746 } 747 748 /* 749 * Cannot tx while the hardware is in full sleep, it first needs a full 750 * chip reset to recover from that 751 */ 752 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 753 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 754 goto exit; 755 } 756 757 memset(&txctl, 0, sizeof(struct ath_tx_control)); 758 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 759 760 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 761 762 if (ath_tx_start(hw, skb, &txctl) != 0) { 763 ath_dbg(common, XMIT, "TX failed\n"); 764 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 765 goto exit; 766 } 767 768 return; 769 exit: 770 dev_kfree_skb_any(skb); 771 } 772 773 static void ath9k_stop(struct ieee80211_hw *hw) 774 { 775 struct ath_softc *sc = hw->priv; 776 struct ath_hw *ah = sc->sc_ah; 777 struct ath_common *common = ath9k_hw_common(ah); 778 bool prev_idle; 779 780 mutex_lock(&sc->mutex); 781 782 ath_cancel_work(sc); 783 del_timer_sync(&sc->rx_poll_timer); 784 785 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 786 ath_dbg(common, ANY, "Device not present\n"); 787 mutex_unlock(&sc->mutex); 788 return; 789 } 790 791 /* Ensure HW is awake when we try to shut it down. */ 792 ath9k_ps_wakeup(sc); 793 794 spin_lock_bh(&sc->sc_pcu_lock); 795 796 /* prevent tasklets to enable interrupts once we disable them */ 797 ah->imask &= ~ATH9K_INT_GLOBAL; 798 799 /* make sure h/w will not generate any interrupt 800 * before setting the invalid flag. */ 801 ath9k_hw_disable_interrupts(ah); 802 803 spin_unlock_bh(&sc->sc_pcu_lock); 804 805 /* we can now sync irq and kill any running tasklets, since we already 806 * disabled interrupts and not holding a spin lock */ 807 synchronize_irq(sc->irq); 808 tasklet_kill(&sc->intr_tq); 809 tasklet_kill(&sc->bcon_tasklet); 810 811 prev_idle = sc->ps_idle; 812 sc->ps_idle = true; 813 814 spin_lock_bh(&sc->sc_pcu_lock); 815 816 if (ah->led_pin >= 0) { 817 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 818 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 819 } 820 821 ath_prepare_reset(sc, false, true); 822 823 if (sc->rx.frag) { 824 dev_kfree_skb_any(sc->rx.frag); 825 sc->rx.frag = NULL; 826 } 827 828 if (!ah->curchan) 829 ah->curchan = ath9k_cmn_get_curchannel(hw, ah); 830 831 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 832 ath9k_hw_phy_disable(ah); 833 834 ath9k_hw_configpcipowersave(ah, true); 835 836 spin_unlock_bh(&sc->sc_pcu_lock); 837 838 ath9k_ps_restore(sc); 839 840 set_bit(SC_OP_INVALID, &sc->sc_flags); 841 sc->ps_idle = prev_idle; 842 843 mutex_unlock(&sc->mutex); 844 845 ath_dbg(common, CONFIG, "Driver halt\n"); 846 } 847 848 bool ath9k_uses_beacons(int type) 849 { 850 switch (type) { 851 case NL80211_IFTYPE_AP: 852 case NL80211_IFTYPE_ADHOC: 853 case NL80211_IFTYPE_MESH_POINT: 854 return true; 855 default: 856 return false; 857 } 858 } 859 860 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 861 { 862 struct ath9k_vif_iter_data *iter_data = data; 863 int i; 864 865 if (iter_data->hw_macaddr) 866 for (i = 0; i < ETH_ALEN; i++) 867 iter_data->mask[i] &= 868 ~(iter_data->hw_macaddr[i] ^ mac[i]); 869 870 switch (vif->type) { 871 case NL80211_IFTYPE_AP: 872 iter_data->naps++; 873 break; 874 case NL80211_IFTYPE_STATION: 875 iter_data->nstations++; 876 break; 877 case NL80211_IFTYPE_ADHOC: 878 iter_data->nadhocs++; 879 break; 880 case NL80211_IFTYPE_MESH_POINT: 881 iter_data->nmeshes++; 882 break; 883 case NL80211_IFTYPE_WDS: 884 iter_data->nwds++; 885 break; 886 default: 887 break; 888 } 889 } 890 891 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 892 { 893 struct ath_softc *sc = data; 894 struct ath_vif *avp = (void *)vif->drv_priv; 895 896 if (vif->type != NL80211_IFTYPE_STATION) 897 return; 898 899 if (avp->primary_sta_vif) 900 ath9k_set_assoc_state(sc, vif); 901 } 902 903 /* Called with sc->mutex held. */ 904 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 905 struct ieee80211_vif *vif, 906 struct ath9k_vif_iter_data *iter_data) 907 { 908 struct ath_softc *sc = hw->priv; 909 struct ath_hw *ah = sc->sc_ah; 910 struct ath_common *common = ath9k_hw_common(ah); 911 912 /* 913 * Use the hardware MAC address as reference, the hardware uses it 914 * together with the BSSID mask when matching addresses. 915 */ 916 memset(iter_data, 0, sizeof(*iter_data)); 917 iter_data->hw_macaddr = common->macaddr; 918 memset(&iter_data->mask, 0xff, ETH_ALEN); 919 920 if (vif) 921 ath9k_vif_iter(iter_data, vif->addr, vif); 922 923 /* Get list of all active MAC addresses */ 924 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, 925 iter_data); 926 } 927 928 /* Called with sc->mutex held. */ 929 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 930 struct ieee80211_vif *vif) 931 { 932 struct ath_softc *sc = hw->priv; 933 struct ath_hw *ah = sc->sc_ah; 934 struct ath_common *common = ath9k_hw_common(ah); 935 struct ath9k_vif_iter_data iter_data; 936 enum nl80211_iftype old_opmode = ah->opmode; 937 938 ath9k_calculate_iter_data(hw, vif, &iter_data); 939 940 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 941 ath_hw_setbssidmask(common); 942 943 if (iter_data.naps > 0) { 944 ath9k_hw_set_tsfadjust(ah, true); 945 ah->opmode = NL80211_IFTYPE_AP; 946 } else { 947 ath9k_hw_set_tsfadjust(ah, false); 948 949 if (iter_data.nmeshes) 950 ah->opmode = NL80211_IFTYPE_MESH_POINT; 951 else if (iter_data.nwds) 952 ah->opmode = NL80211_IFTYPE_AP; 953 else if (iter_data.nadhocs) 954 ah->opmode = NL80211_IFTYPE_ADHOC; 955 else 956 ah->opmode = NL80211_IFTYPE_STATION; 957 } 958 959 ath9k_hw_setopmode(ah); 960 961 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 962 ah->imask |= ATH9K_INT_TSFOOR; 963 else 964 ah->imask &= ~ATH9K_INT_TSFOOR; 965 966 ath9k_hw_set_interrupts(ah); 967 968 /* 969 * If we are changing the opmode to STATION, 970 * a beacon sync needs to be done. 971 */ 972 if (ah->opmode == NL80211_IFTYPE_STATION && 973 old_opmode == NL80211_IFTYPE_AP && 974 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 975 ieee80211_iterate_active_interfaces_atomic(sc->hw, 976 ath9k_sta_vif_iter, sc); 977 } 978 } 979 980 static int ath9k_add_interface(struct ieee80211_hw *hw, 981 struct ieee80211_vif *vif) 982 { 983 struct ath_softc *sc = hw->priv; 984 struct ath_hw *ah = sc->sc_ah; 985 struct ath_common *common = ath9k_hw_common(ah); 986 int ret = 0; 987 988 ath9k_ps_wakeup(sc); 989 mutex_lock(&sc->mutex); 990 991 switch (vif->type) { 992 case NL80211_IFTYPE_STATION: 993 case NL80211_IFTYPE_WDS: 994 case NL80211_IFTYPE_ADHOC: 995 case NL80211_IFTYPE_AP: 996 case NL80211_IFTYPE_MESH_POINT: 997 break; 998 default: 999 ath_err(common, "Interface type %d not yet supported\n", 1000 vif->type); 1001 ret = -EOPNOTSUPP; 1002 goto out; 1003 } 1004 1005 if (ath9k_uses_beacons(vif->type)) { 1006 if (sc->nbcnvifs >= ATH_BCBUF) { 1007 ath_err(common, "Not enough beacon buffers when adding" 1008 " new interface of type: %i\n", 1009 vif->type); 1010 ret = -ENOBUFS; 1011 goto out; 1012 } 1013 } 1014 1015 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1016 1017 sc->nvifs++; 1018 1019 ath9k_calculate_summary_state(hw, vif); 1020 if (ath9k_uses_beacons(vif->type)) 1021 ath9k_beacon_assign_slot(sc, vif); 1022 1023 out: 1024 mutex_unlock(&sc->mutex); 1025 ath9k_ps_restore(sc); 1026 return ret; 1027 } 1028 1029 static int ath9k_change_interface(struct ieee80211_hw *hw, 1030 struct ieee80211_vif *vif, 1031 enum nl80211_iftype new_type, 1032 bool p2p) 1033 { 1034 struct ath_softc *sc = hw->priv; 1035 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1036 int ret = 0; 1037 1038 ath_dbg(common, CONFIG, "Change Interface\n"); 1039 1040 mutex_lock(&sc->mutex); 1041 ath9k_ps_wakeup(sc); 1042 1043 if (ath9k_uses_beacons(new_type) && 1044 !ath9k_uses_beacons(vif->type)) { 1045 if (sc->nbcnvifs >= ATH_BCBUF) { 1046 ath_err(common, "No beacon slot available\n"); 1047 ret = -ENOBUFS; 1048 goto out; 1049 } 1050 } 1051 1052 if (ath9k_uses_beacons(vif->type)) 1053 ath9k_beacon_remove_slot(sc, vif); 1054 1055 vif->type = new_type; 1056 vif->p2p = p2p; 1057 1058 ath9k_calculate_summary_state(hw, vif); 1059 if (ath9k_uses_beacons(vif->type)) 1060 ath9k_beacon_assign_slot(sc, vif); 1061 1062 out: 1063 ath9k_ps_restore(sc); 1064 mutex_unlock(&sc->mutex); 1065 return ret; 1066 } 1067 1068 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1069 struct ieee80211_vif *vif) 1070 { 1071 struct ath_softc *sc = hw->priv; 1072 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1073 1074 ath_dbg(common, CONFIG, "Detach Interface\n"); 1075 1076 ath9k_ps_wakeup(sc); 1077 mutex_lock(&sc->mutex); 1078 1079 sc->nvifs--; 1080 1081 if (ath9k_uses_beacons(vif->type)) 1082 ath9k_beacon_remove_slot(sc, vif); 1083 1084 ath9k_calculate_summary_state(hw, NULL); 1085 1086 mutex_unlock(&sc->mutex); 1087 ath9k_ps_restore(sc); 1088 } 1089 1090 static void ath9k_enable_ps(struct ath_softc *sc) 1091 { 1092 struct ath_hw *ah = sc->sc_ah; 1093 struct ath_common *common = ath9k_hw_common(ah); 1094 1095 sc->ps_enabled = true; 1096 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1097 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1098 ah->imask |= ATH9K_INT_TIM_TIMER; 1099 ath9k_hw_set_interrupts(ah); 1100 } 1101 ath9k_hw_setrxabort(ah, 1); 1102 } 1103 ath_dbg(common, PS, "PowerSave enabled\n"); 1104 } 1105 1106 static void ath9k_disable_ps(struct ath_softc *sc) 1107 { 1108 struct ath_hw *ah = sc->sc_ah; 1109 struct ath_common *common = ath9k_hw_common(ah); 1110 1111 sc->ps_enabled = false; 1112 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1113 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1114 ath9k_hw_setrxabort(ah, 0); 1115 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1116 PS_WAIT_FOR_CAB | 1117 PS_WAIT_FOR_PSPOLL_DATA | 1118 PS_WAIT_FOR_TX_ACK); 1119 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1120 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1121 ath9k_hw_set_interrupts(ah); 1122 } 1123 } 1124 ath_dbg(common, PS, "PowerSave disabled\n"); 1125 } 1126 1127 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1128 { 1129 struct ath_softc *sc = hw->priv; 1130 struct ath_hw *ah = sc->sc_ah; 1131 struct ath_common *common = ath9k_hw_common(ah); 1132 struct ieee80211_conf *conf = &hw->conf; 1133 bool reset_channel = false; 1134 1135 ath9k_ps_wakeup(sc); 1136 mutex_lock(&sc->mutex); 1137 1138 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1139 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1140 if (sc->ps_idle) { 1141 ath_cancel_work(sc); 1142 ath9k_stop_btcoex(sc); 1143 } else { 1144 ath9k_start_btcoex(sc); 1145 /* 1146 * The chip needs a reset to properly wake up from 1147 * full sleep 1148 */ 1149 reset_channel = ah->chip_fullsleep; 1150 } 1151 } 1152 1153 /* 1154 * We just prepare to enable PS. We have to wait until our AP has 1155 * ACK'd our null data frame to disable RX otherwise we'll ignore 1156 * those ACKs and end up retransmitting the same null data frames. 1157 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1158 */ 1159 if (changed & IEEE80211_CONF_CHANGE_PS) { 1160 unsigned long flags; 1161 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1162 if (conf->flags & IEEE80211_CONF_PS) 1163 ath9k_enable_ps(sc); 1164 else 1165 ath9k_disable_ps(sc); 1166 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1167 } 1168 1169 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1170 if (conf->flags & IEEE80211_CONF_MONITOR) { 1171 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1172 sc->sc_ah->is_monitoring = true; 1173 } else { 1174 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1175 sc->sc_ah->is_monitoring = false; 1176 } 1177 } 1178 1179 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1180 struct ieee80211_channel *curchan = hw->conf.channel; 1181 int pos = curchan->hw_value; 1182 int old_pos = -1; 1183 unsigned long flags; 1184 1185 if (ah->curchan) 1186 old_pos = ah->curchan - &ah->channels[0]; 1187 1188 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", 1189 curchan->center_freq, conf->channel_type); 1190 1191 /* update survey stats for the old channel before switching */ 1192 spin_lock_irqsave(&common->cc_lock, flags); 1193 ath_update_survey_stats(sc); 1194 spin_unlock_irqrestore(&common->cc_lock, flags); 1195 1196 /* 1197 * Preserve the current channel values, before updating 1198 * the same channel 1199 */ 1200 if (ah->curchan && (old_pos == pos)) 1201 ath9k_hw_getnf(ah, ah->curchan); 1202 1203 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], 1204 curchan, conf->channel_type); 1205 1206 /* 1207 * If the operating channel changes, change the survey in-use flags 1208 * along with it. 1209 * Reset the survey data for the new channel, unless we're switching 1210 * back to the operating channel from an off-channel operation. 1211 */ 1212 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && 1213 sc->cur_survey != &sc->survey[pos]) { 1214 1215 if (sc->cur_survey) 1216 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 1217 1218 sc->cur_survey = &sc->survey[pos]; 1219 1220 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 1221 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 1222 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 1223 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 1224 } 1225 1226 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1227 ath_err(common, "Unable to set channel\n"); 1228 mutex_unlock(&sc->mutex); 1229 ath9k_ps_restore(sc); 1230 return -EINVAL; 1231 } 1232 1233 /* 1234 * The most recent snapshot of channel->noisefloor for the old 1235 * channel is only available after the hardware reset. Copy it to 1236 * the survey stats now. 1237 */ 1238 if (old_pos >= 0) 1239 ath_update_survey_nf(sc, old_pos); 1240 } 1241 1242 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1243 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1244 sc->config.txpowlimit = 2 * conf->power_level; 1245 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1246 sc->config.txpowlimit, &sc->curtxpow); 1247 } 1248 1249 mutex_unlock(&sc->mutex); 1250 ath9k_ps_restore(sc); 1251 1252 return 0; 1253 } 1254 1255 #define SUPPORTED_FILTERS \ 1256 (FIF_PROMISC_IN_BSS | \ 1257 FIF_ALLMULTI | \ 1258 FIF_CONTROL | \ 1259 FIF_PSPOLL | \ 1260 FIF_OTHER_BSS | \ 1261 FIF_BCN_PRBRESP_PROMISC | \ 1262 FIF_PROBE_REQ | \ 1263 FIF_FCSFAIL) 1264 1265 /* FIXME: sc->sc_full_reset ? */ 1266 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1267 unsigned int changed_flags, 1268 unsigned int *total_flags, 1269 u64 multicast) 1270 { 1271 struct ath_softc *sc = hw->priv; 1272 u32 rfilt; 1273 1274 changed_flags &= SUPPORTED_FILTERS; 1275 *total_flags &= SUPPORTED_FILTERS; 1276 1277 sc->rx.rxfilter = *total_flags; 1278 ath9k_ps_wakeup(sc); 1279 rfilt = ath_calcrxfilter(sc); 1280 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1281 ath9k_ps_restore(sc); 1282 1283 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1284 rfilt); 1285 } 1286 1287 static int ath9k_sta_add(struct ieee80211_hw *hw, 1288 struct ieee80211_vif *vif, 1289 struct ieee80211_sta *sta) 1290 { 1291 struct ath_softc *sc = hw->priv; 1292 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1293 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1294 struct ieee80211_key_conf ps_key = { }; 1295 1296 ath_node_attach(sc, sta, vif); 1297 1298 if (vif->type != NL80211_IFTYPE_AP && 1299 vif->type != NL80211_IFTYPE_AP_VLAN) 1300 return 0; 1301 1302 an->ps_key = ath_key_config(common, vif, sta, &ps_key); 1303 1304 return 0; 1305 } 1306 1307 static void ath9k_del_ps_key(struct ath_softc *sc, 1308 struct ieee80211_vif *vif, 1309 struct ieee80211_sta *sta) 1310 { 1311 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1312 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1313 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1314 1315 if (!an->ps_key) 1316 return; 1317 1318 ath_key_delete(common, &ps_key); 1319 } 1320 1321 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1322 struct ieee80211_vif *vif, 1323 struct ieee80211_sta *sta) 1324 { 1325 struct ath_softc *sc = hw->priv; 1326 1327 ath9k_del_ps_key(sc, vif, sta); 1328 ath_node_detach(sc, sta); 1329 1330 return 0; 1331 } 1332 1333 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1334 struct ieee80211_vif *vif, 1335 enum sta_notify_cmd cmd, 1336 struct ieee80211_sta *sta) 1337 { 1338 struct ath_softc *sc = hw->priv; 1339 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1340 1341 if (!sta->ht_cap.ht_supported) 1342 return; 1343 1344 switch (cmd) { 1345 case STA_NOTIFY_SLEEP: 1346 an->sleeping = true; 1347 ath_tx_aggr_sleep(sta, sc, an); 1348 break; 1349 case STA_NOTIFY_AWAKE: 1350 an->sleeping = false; 1351 ath_tx_aggr_wakeup(sc, an); 1352 break; 1353 } 1354 } 1355 1356 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1357 struct ieee80211_vif *vif, u16 queue, 1358 const struct ieee80211_tx_queue_params *params) 1359 { 1360 struct ath_softc *sc = hw->priv; 1361 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1362 struct ath_txq *txq; 1363 struct ath9k_tx_queue_info qi; 1364 int ret = 0; 1365 1366 if (queue >= WME_NUM_AC) 1367 return 0; 1368 1369 txq = sc->tx.txq_map[queue]; 1370 1371 ath9k_ps_wakeup(sc); 1372 mutex_lock(&sc->mutex); 1373 1374 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1375 1376 qi.tqi_aifs = params->aifs; 1377 qi.tqi_cwmin = params->cw_min; 1378 qi.tqi_cwmax = params->cw_max; 1379 qi.tqi_burstTime = params->txop * 32; 1380 1381 ath_dbg(common, CONFIG, 1382 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1383 queue, txq->axq_qnum, params->aifs, params->cw_min, 1384 params->cw_max, params->txop); 1385 1386 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1387 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1388 if (ret) 1389 ath_err(common, "TXQ Update failed\n"); 1390 1391 mutex_unlock(&sc->mutex); 1392 ath9k_ps_restore(sc); 1393 1394 return ret; 1395 } 1396 1397 static int ath9k_set_key(struct ieee80211_hw *hw, 1398 enum set_key_cmd cmd, 1399 struct ieee80211_vif *vif, 1400 struct ieee80211_sta *sta, 1401 struct ieee80211_key_conf *key) 1402 { 1403 struct ath_softc *sc = hw->priv; 1404 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1405 int ret = 0; 1406 1407 if (ath9k_modparam_nohwcrypt) 1408 return -ENOSPC; 1409 1410 if ((vif->type == NL80211_IFTYPE_ADHOC || 1411 vif->type == NL80211_IFTYPE_MESH_POINT) && 1412 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1413 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1414 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1415 /* 1416 * For now, disable hw crypto for the RSN IBSS group keys. This 1417 * could be optimized in the future to use a modified key cache 1418 * design to support per-STA RX GTK, but until that gets 1419 * implemented, use of software crypto for group addressed 1420 * frames is a acceptable to allow RSN IBSS to be used. 1421 */ 1422 return -EOPNOTSUPP; 1423 } 1424 1425 mutex_lock(&sc->mutex); 1426 ath9k_ps_wakeup(sc); 1427 ath_dbg(common, CONFIG, "Set HW Key\n"); 1428 1429 switch (cmd) { 1430 case SET_KEY: 1431 if (sta) 1432 ath9k_del_ps_key(sc, vif, sta); 1433 1434 ret = ath_key_config(common, vif, sta, key); 1435 if (ret >= 0) { 1436 key->hw_key_idx = ret; 1437 /* push IV and Michael MIC generation to stack */ 1438 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1439 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1440 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1441 if (sc->sc_ah->sw_mgmt_crypto && 1442 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1443 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; 1444 ret = 0; 1445 } 1446 break; 1447 case DISABLE_KEY: 1448 ath_key_delete(common, key); 1449 break; 1450 default: 1451 ret = -EINVAL; 1452 } 1453 1454 ath9k_ps_restore(sc); 1455 mutex_unlock(&sc->mutex); 1456 1457 return ret; 1458 } 1459 1460 static void ath9k_set_assoc_state(struct ath_softc *sc, 1461 struct ieee80211_vif *vif) 1462 { 1463 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1464 struct ath_vif *avp = (void *)vif->drv_priv; 1465 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1466 unsigned long flags; 1467 1468 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1469 avp->primary_sta_vif = true; 1470 1471 /* 1472 * Set the AID, BSSID and do beacon-sync only when 1473 * the HW opmode is STATION. 1474 * 1475 * But the primary bit is set above in any case. 1476 */ 1477 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1478 return; 1479 1480 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1481 common->curaid = bss_conf->aid; 1482 ath9k_hw_write_associd(sc->sc_ah); 1483 1484 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1485 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1486 1487 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1488 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1489 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1490 1491 ath_dbg(common, CONFIG, 1492 "Primary Station interface: %pM, BSSID: %pM\n", 1493 vif->addr, common->curbssid); 1494 } 1495 1496 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1497 { 1498 struct ath_softc *sc = data; 1499 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1500 1501 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) 1502 return; 1503 1504 if (bss_conf->assoc) 1505 ath9k_set_assoc_state(sc, vif); 1506 } 1507 1508 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1509 struct ieee80211_vif *vif, 1510 struct ieee80211_bss_conf *bss_conf, 1511 u32 changed) 1512 { 1513 #define CHECK_ANI \ 1514 (BSS_CHANGED_ASSOC | \ 1515 BSS_CHANGED_IBSS | \ 1516 BSS_CHANGED_BEACON_ENABLED) 1517 1518 struct ath_softc *sc = hw->priv; 1519 struct ath_hw *ah = sc->sc_ah; 1520 struct ath_common *common = ath9k_hw_common(ah); 1521 struct ath_vif *avp = (void *)vif->drv_priv; 1522 int slottime; 1523 1524 ath9k_ps_wakeup(sc); 1525 mutex_lock(&sc->mutex); 1526 1527 if (changed & BSS_CHANGED_ASSOC) { 1528 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1529 bss_conf->bssid, bss_conf->assoc); 1530 1531 if (avp->primary_sta_vif && !bss_conf->assoc) { 1532 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1533 avp->primary_sta_vif = false; 1534 1535 if (ah->opmode == NL80211_IFTYPE_STATION) 1536 clear_bit(SC_OP_BEACONS, &sc->sc_flags); 1537 } 1538 1539 ieee80211_iterate_active_interfaces_atomic(sc->hw, 1540 ath9k_bss_assoc_iter, sc); 1541 1542 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && 1543 ah->opmode == NL80211_IFTYPE_STATION) { 1544 memset(common->curbssid, 0, ETH_ALEN); 1545 common->curaid = 0; 1546 ath9k_hw_write_associd(sc->sc_ah); 1547 } 1548 } 1549 1550 if (changed & BSS_CHANGED_IBSS) { 1551 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1552 common->curaid = bss_conf->aid; 1553 ath9k_hw_write_associd(sc->sc_ah); 1554 } 1555 1556 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1557 (changed & BSS_CHANGED_BEACON_INT)) { 1558 if (ah->opmode == NL80211_IFTYPE_AP && 1559 bss_conf->enable_beacon) 1560 ath9k_set_tsfadjust(sc, vif); 1561 if (ath9k_allow_beacon_config(sc, vif)) 1562 ath9k_beacon_config(sc, vif, changed); 1563 } 1564 1565 if (changed & BSS_CHANGED_ERP_SLOT) { 1566 if (bss_conf->use_short_slot) 1567 slottime = 9; 1568 else 1569 slottime = 20; 1570 if (vif->type == NL80211_IFTYPE_AP) { 1571 /* 1572 * Defer update, so that connected stations can adjust 1573 * their settings at the same time. 1574 * See beacon.c for more details 1575 */ 1576 sc->beacon.slottime = slottime; 1577 sc->beacon.updateslot = UPDATE; 1578 } else { 1579 ah->slottime = slottime; 1580 ath9k_hw_init_global_settings(ah); 1581 } 1582 } 1583 1584 if (changed & CHECK_ANI) 1585 ath_check_ani(sc); 1586 1587 mutex_unlock(&sc->mutex); 1588 ath9k_ps_restore(sc); 1589 1590 #undef CHECK_ANI 1591 } 1592 1593 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1594 { 1595 struct ath_softc *sc = hw->priv; 1596 u64 tsf; 1597 1598 mutex_lock(&sc->mutex); 1599 ath9k_ps_wakeup(sc); 1600 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1601 ath9k_ps_restore(sc); 1602 mutex_unlock(&sc->mutex); 1603 1604 return tsf; 1605 } 1606 1607 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1608 struct ieee80211_vif *vif, 1609 u64 tsf) 1610 { 1611 struct ath_softc *sc = hw->priv; 1612 1613 mutex_lock(&sc->mutex); 1614 ath9k_ps_wakeup(sc); 1615 ath9k_hw_settsf64(sc->sc_ah, tsf); 1616 ath9k_ps_restore(sc); 1617 mutex_unlock(&sc->mutex); 1618 } 1619 1620 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1621 { 1622 struct ath_softc *sc = hw->priv; 1623 1624 mutex_lock(&sc->mutex); 1625 1626 ath9k_ps_wakeup(sc); 1627 ath9k_hw_reset_tsf(sc->sc_ah); 1628 ath9k_ps_restore(sc); 1629 1630 mutex_unlock(&sc->mutex); 1631 } 1632 1633 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1634 struct ieee80211_vif *vif, 1635 enum ieee80211_ampdu_mlme_action action, 1636 struct ieee80211_sta *sta, 1637 u16 tid, u16 *ssn, u8 buf_size) 1638 { 1639 struct ath_softc *sc = hw->priv; 1640 int ret = 0; 1641 1642 local_bh_disable(); 1643 1644 switch (action) { 1645 case IEEE80211_AMPDU_RX_START: 1646 break; 1647 case IEEE80211_AMPDU_RX_STOP: 1648 break; 1649 case IEEE80211_AMPDU_TX_START: 1650 ath9k_ps_wakeup(sc); 1651 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1652 if (!ret) 1653 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1654 ath9k_ps_restore(sc); 1655 break; 1656 case IEEE80211_AMPDU_TX_STOP: 1657 ath9k_ps_wakeup(sc); 1658 ath_tx_aggr_stop(sc, sta, tid); 1659 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1660 ath9k_ps_restore(sc); 1661 break; 1662 case IEEE80211_AMPDU_TX_OPERATIONAL: 1663 ath9k_ps_wakeup(sc); 1664 ath_tx_aggr_resume(sc, sta, tid); 1665 ath9k_ps_restore(sc); 1666 break; 1667 default: 1668 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1669 } 1670 1671 local_bh_enable(); 1672 1673 return ret; 1674 } 1675 1676 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1677 struct survey_info *survey) 1678 { 1679 struct ath_softc *sc = hw->priv; 1680 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1681 struct ieee80211_supported_band *sband; 1682 struct ieee80211_channel *chan; 1683 unsigned long flags; 1684 int pos; 1685 1686 spin_lock_irqsave(&common->cc_lock, flags); 1687 if (idx == 0) 1688 ath_update_survey_stats(sc); 1689 1690 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1691 if (sband && idx >= sband->n_channels) { 1692 idx -= sband->n_channels; 1693 sband = NULL; 1694 } 1695 1696 if (!sband) 1697 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1698 1699 if (!sband || idx >= sband->n_channels) { 1700 spin_unlock_irqrestore(&common->cc_lock, flags); 1701 return -ENOENT; 1702 } 1703 1704 chan = &sband->channels[idx]; 1705 pos = chan->hw_value; 1706 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1707 survey->channel = chan; 1708 spin_unlock_irqrestore(&common->cc_lock, flags); 1709 1710 return 0; 1711 } 1712 1713 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1714 { 1715 struct ath_softc *sc = hw->priv; 1716 struct ath_hw *ah = sc->sc_ah; 1717 1718 mutex_lock(&sc->mutex); 1719 ah->coverage_class = coverage_class; 1720 1721 ath9k_ps_wakeup(sc); 1722 ath9k_hw_init_global_settings(ah); 1723 ath9k_ps_restore(sc); 1724 1725 mutex_unlock(&sc->mutex); 1726 } 1727 1728 static void ath9k_flush(struct ieee80211_hw *hw, bool drop) 1729 { 1730 struct ath_softc *sc = hw->priv; 1731 struct ath_hw *ah = sc->sc_ah; 1732 struct ath_common *common = ath9k_hw_common(ah); 1733 int timeout = 200; /* ms */ 1734 int i, j; 1735 bool drain_txq; 1736 1737 mutex_lock(&sc->mutex); 1738 cancel_delayed_work_sync(&sc->tx_complete_work); 1739 1740 if (ah->ah_flags & AH_UNPLUGGED) { 1741 ath_dbg(common, ANY, "Device has been unplugged!\n"); 1742 mutex_unlock(&sc->mutex); 1743 return; 1744 } 1745 1746 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 1747 ath_dbg(common, ANY, "Device not present\n"); 1748 mutex_unlock(&sc->mutex); 1749 return; 1750 } 1751 1752 for (j = 0; j < timeout; j++) { 1753 bool npend = false; 1754 1755 if (j) 1756 usleep_range(1000, 2000); 1757 1758 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1759 if (!ATH_TXQ_SETUP(sc, i)) 1760 continue; 1761 1762 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1763 1764 if (npend) 1765 break; 1766 } 1767 1768 if (!npend) 1769 break; 1770 } 1771 1772 if (drop) { 1773 ath9k_ps_wakeup(sc); 1774 spin_lock_bh(&sc->sc_pcu_lock); 1775 drain_txq = ath_drain_all_txq(sc, false); 1776 spin_unlock_bh(&sc->sc_pcu_lock); 1777 1778 if (!drain_txq) 1779 ath_reset(sc, false); 1780 1781 ath9k_ps_restore(sc); 1782 ieee80211_wake_queues(hw); 1783 } 1784 1785 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 1786 mutex_unlock(&sc->mutex); 1787 } 1788 1789 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 1790 { 1791 struct ath_softc *sc = hw->priv; 1792 int i; 1793 1794 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1795 if (!ATH_TXQ_SETUP(sc, i)) 1796 continue; 1797 1798 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 1799 return true; 1800 } 1801 return false; 1802 } 1803 1804 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 1805 { 1806 struct ath_softc *sc = hw->priv; 1807 struct ath_hw *ah = sc->sc_ah; 1808 struct ieee80211_vif *vif; 1809 struct ath_vif *avp; 1810 struct ath_buf *bf; 1811 struct ath_tx_status ts; 1812 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1813 int status; 1814 1815 vif = sc->beacon.bslot[0]; 1816 if (!vif) 1817 return 0; 1818 1819 if (!vif->bss_conf.enable_beacon) 1820 return 0; 1821 1822 avp = (void *)vif->drv_priv; 1823 1824 if (!sc->beacon.tx_processed && !edma) { 1825 tasklet_disable(&sc->bcon_tasklet); 1826 1827 bf = avp->av_bcbuf; 1828 if (!bf || !bf->bf_mpdu) 1829 goto skip; 1830 1831 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 1832 if (status == -EINPROGRESS) 1833 goto skip; 1834 1835 sc->beacon.tx_processed = true; 1836 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 1837 1838 skip: 1839 tasklet_enable(&sc->bcon_tasklet); 1840 } 1841 1842 return sc->beacon.tx_last; 1843 } 1844 1845 static int ath9k_get_stats(struct ieee80211_hw *hw, 1846 struct ieee80211_low_level_stats *stats) 1847 { 1848 struct ath_softc *sc = hw->priv; 1849 struct ath_hw *ah = sc->sc_ah; 1850 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 1851 1852 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 1853 stats->dot11RTSFailureCount = mib_stats->rts_bad; 1854 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 1855 stats->dot11RTSSuccessCount = mib_stats->rts_good; 1856 return 0; 1857 } 1858 1859 static u32 fill_chainmask(u32 cap, u32 new) 1860 { 1861 u32 filled = 0; 1862 int i; 1863 1864 for (i = 0; cap && new; i++, cap >>= 1) { 1865 if (!(cap & BIT(0))) 1866 continue; 1867 1868 if (new & BIT(0)) 1869 filled |= BIT(i); 1870 1871 new >>= 1; 1872 } 1873 1874 return filled; 1875 } 1876 1877 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 1878 { 1879 switch (val & 0x7) { 1880 case 0x1: 1881 case 0x3: 1882 case 0x7: 1883 return true; 1884 case 0x2: 1885 return (ah->caps.rx_chainmask == 1); 1886 default: 1887 return false; 1888 } 1889 } 1890 1891 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 1892 { 1893 struct ath_softc *sc = hw->priv; 1894 struct ath_hw *ah = sc->sc_ah; 1895 1896 if (ah->caps.rx_chainmask != 1) 1897 rx_ant |= tx_ant; 1898 1899 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 1900 return -EINVAL; 1901 1902 sc->ant_rx = rx_ant; 1903 sc->ant_tx = tx_ant; 1904 1905 if (ah->caps.rx_chainmask == 1) 1906 return 0; 1907 1908 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 1909 if (AR_SREV_9100(ah)) 1910 ah->rxchainmask = 0x7; 1911 else 1912 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 1913 1914 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 1915 ath9k_reload_chainmask_settings(sc); 1916 1917 return 0; 1918 } 1919 1920 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 1921 { 1922 struct ath_softc *sc = hw->priv; 1923 1924 *tx_ant = sc->ant_tx; 1925 *rx_ant = sc->ant_rx; 1926 return 0; 1927 } 1928 1929 #ifdef CONFIG_ATH9K_DEBUGFS 1930 1931 /* Ethtool support for get-stats */ 1932 1933 #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO" 1934 static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = { 1935 "tx_pkts_nic", 1936 "tx_bytes_nic", 1937 "rx_pkts_nic", 1938 "rx_bytes_nic", 1939 AMKSTR(d_tx_pkts), 1940 AMKSTR(d_tx_bytes), 1941 AMKSTR(d_tx_mpdus_queued), 1942 AMKSTR(d_tx_mpdus_completed), 1943 AMKSTR(d_tx_mpdu_xretries), 1944 AMKSTR(d_tx_aggregates), 1945 AMKSTR(d_tx_ampdus_queued_hw), 1946 AMKSTR(d_tx_ampdus_queued_sw), 1947 AMKSTR(d_tx_ampdus_completed), 1948 AMKSTR(d_tx_ampdu_retries), 1949 AMKSTR(d_tx_ampdu_xretries), 1950 AMKSTR(d_tx_fifo_underrun), 1951 AMKSTR(d_tx_op_exceeded), 1952 AMKSTR(d_tx_timer_expiry), 1953 AMKSTR(d_tx_desc_cfg_err), 1954 AMKSTR(d_tx_data_underrun), 1955 AMKSTR(d_tx_delim_underrun), 1956 1957 "d_rx_decrypt_crc_err", 1958 "d_rx_phy_err", 1959 "d_rx_mic_err", 1960 "d_rx_pre_delim_crc_err", 1961 "d_rx_post_delim_crc_err", 1962 "d_rx_decrypt_busy_err", 1963 1964 "d_rx_phyerr_radar", 1965 "d_rx_phyerr_ofdm_timing", 1966 "d_rx_phyerr_cck_timing", 1967 1968 }; 1969 #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats) 1970 1971 static void ath9k_get_et_strings(struct ieee80211_hw *hw, 1972 struct ieee80211_vif *vif, 1973 u32 sset, u8 *data) 1974 { 1975 if (sset == ETH_SS_STATS) 1976 memcpy(data, *ath9k_gstrings_stats, 1977 sizeof(ath9k_gstrings_stats)); 1978 } 1979 1980 static int ath9k_get_et_sset_count(struct ieee80211_hw *hw, 1981 struct ieee80211_vif *vif, int sset) 1982 { 1983 if (sset == ETH_SS_STATS) 1984 return ATH9K_SSTATS_LEN; 1985 return 0; 1986 } 1987 1988 #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum) 1989 #define AWDATA(elem) \ 1990 do { \ 1991 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \ 1992 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \ 1993 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \ 1994 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \ 1995 } while (0) 1996 1997 #define AWDATA_RX(elem) \ 1998 do { \ 1999 data[i++] = sc->debug.stats.rxstats.elem; \ 2000 } while (0) 2001 2002 static void ath9k_get_et_stats(struct ieee80211_hw *hw, 2003 struct ieee80211_vif *vif, 2004 struct ethtool_stats *stats, u64 *data) 2005 { 2006 struct ath_softc *sc = hw->priv; 2007 int i = 0; 2008 2009 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all + 2010 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all + 2011 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all + 2012 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all); 2013 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all + 2014 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all + 2015 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all + 2016 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all); 2017 AWDATA_RX(rx_pkts_all); 2018 AWDATA_RX(rx_bytes_all); 2019 2020 AWDATA(tx_pkts_all); 2021 AWDATA(tx_bytes_all); 2022 AWDATA(queued); 2023 AWDATA(completed); 2024 AWDATA(xretries); 2025 AWDATA(a_aggr); 2026 AWDATA(a_queued_hw); 2027 AWDATA(a_queued_sw); 2028 AWDATA(a_completed); 2029 AWDATA(a_retries); 2030 AWDATA(a_xretries); 2031 AWDATA(fifo_underrun); 2032 AWDATA(xtxop); 2033 AWDATA(timer_exp); 2034 AWDATA(desc_cfg_err); 2035 AWDATA(data_underrun); 2036 AWDATA(delim_underrun); 2037 2038 AWDATA_RX(decrypt_crc_err); 2039 AWDATA_RX(phy_err); 2040 AWDATA_RX(mic_err); 2041 AWDATA_RX(pre_delim_crc_err); 2042 AWDATA_RX(post_delim_crc_err); 2043 AWDATA_RX(decrypt_busy_err); 2044 2045 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]); 2046 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]); 2047 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]); 2048 2049 WARN_ON(i != ATH9K_SSTATS_LEN); 2050 } 2051 2052 /* End of ethtool get-stats functions */ 2053 2054 #endif 2055 2056 2057 #ifdef CONFIG_PM_SLEEP 2058 2059 static void ath9k_wow_map_triggers(struct ath_softc *sc, 2060 struct cfg80211_wowlan *wowlan, 2061 u32 *wow_triggers) 2062 { 2063 if (wowlan->disconnect) 2064 *wow_triggers |= AH_WOW_LINK_CHANGE | 2065 AH_WOW_BEACON_MISS; 2066 if (wowlan->magic_pkt) 2067 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; 2068 2069 if (wowlan->n_patterns) 2070 *wow_triggers |= AH_WOW_USER_PATTERN_EN; 2071 2072 sc->wow_enabled = *wow_triggers; 2073 2074 } 2075 2076 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) 2077 { 2078 struct ath_hw *ah = sc->sc_ah; 2079 struct ath_common *common = ath9k_hw_common(ah); 2080 struct ath9k_hw_capabilities *pcaps = &ah->caps; 2081 int pattern_count = 0; 2082 int i, byte_cnt; 2083 u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; 2084 u8 dis_deauth_mask[MAX_PATTERN_SIZE]; 2085 2086 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); 2087 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); 2088 2089 /* 2090 * Create Dissassociate / Deauthenticate packet filter 2091 * 2092 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes 2093 * +--------------+----------+---------+--------+--------+---- 2094 * + Frame Control+ Duration + DA + SA + BSSID + 2095 * +--------------+----------+---------+--------+--------+---- 2096 * 2097 * The above is the management frame format for disassociate/ 2098 * deauthenticate pattern, from this we need to match the first byte 2099 * of 'Frame Control' and DA, SA, and BSSID fields 2100 * (skipping 2nd byte of FC and Duration feild. 2101 * 2102 * Disassociate pattern 2103 * -------------------- 2104 * Frame control = 00 00 1010 2105 * DA, SA, BSSID = x:x:x:x:x:x 2106 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x 2107 * | x:x:x:x:x:x -- 22 bytes 2108 * 2109 * Deauthenticate pattern 2110 * ---------------------- 2111 * Frame control = 00 00 1100 2112 * DA, SA, BSSID = x:x:x:x:x:x 2113 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x 2114 * | x:x:x:x:x:x -- 22 bytes 2115 */ 2116 2117 /* Create Disassociate Pattern first */ 2118 2119 byte_cnt = 0; 2120 2121 /* Fill out the mask with all FF's */ 2122 2123 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) 2124 dis_deauth_mask[i] = 0xff; 2125 2126 /* copy the first byte of frame control field */ 2127 dis_deauth_pattern[byte_cnt] = 0xa0; 2128 byte_cnt++; 2129 2130 /* skip 2nd byte of frame control and Duration field */ 2131 byte_cnt += 3; 2132 2133 /* 2134 * need not match the destination mac address, it can be a broadcast 2135 * mac address or an unicast to this station 2136 */ 2137 byte_cnt += 6; 2138 2139 /* copy the source mac address */ 2140 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 2141 2142 byte_cnt += 6; 2143 2144 /* copy the bssid, its same as the source mac address */ 2145 2146 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 2147 2148 /* Create Disassociate pattern mask */ 2149 2150 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { 2151 2152 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { 2153 /* 2154 * for AR9280, because of hardware limitation, the 2155 * first 4 bytes have to be matched for all patterns. 2156 * the mask for disassociation and de-auth pattern 2157 * matching need to enable the first 4 bytes. 2158 * also the duration field needs to be filled. 2159 */ 2160 dis_deauth_mask[0] = 0xf0; 2161 2162 /* 2163 * fill in duration field 2164 FIXME: what is the exact value ? 2165 */ 2166 dis_deauth_pattern[2] = 0xff; 2167 dis_deauth_pattern[3] = 0xff; 2168 } else { 2169 dis_deauth_mask[0] = 0xfe; 2170 } 2171 2172 dis_deauth_mask[1] = 0x03; 2173 dis_deauth_mask[2] = 0xc0; 2174 } else { 2175 dis_deauth_mask[0] = 0xef; 2176 dis_deauth_mask[1] = 0x3f; 2177 dis_deauth_mask[2] = 0x00; 2178 dis_deauth_mask[3] = 0xfc; 2179 } 2180 2181 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); 2182 2183 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2184 pattern_count, byte_cnt); 2185 2186 pattern_count++; 2187 /* 2188 * for de-authenticate pattern, only the first byte of the frame 2189 * control field gets changed from 0xA0 to 0xC0 2190 */ 2191 dis_deauth_pattern[0] = 0xC0; 2192 2193 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2194 pattern_count, byte_cnt); 2195 2196 } 2197 2198 static void ath9k_wow_add_pattern(struct ath_softc *sc, 2199 struct cfg80211_wowlan *wowlan) 2200 { 2201 struct ath_hw *ah = sc->sc_ah; 2202 struct ath9k_wow_pattern *wow_pattern = NULL; 2203 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; 2204 int mask_len; 2205 s8 i = 0; 2206 2207 if (!wowlan->n_patterns) 2208 return; 2209 2210 /* 2211 * Add the new user configured patterns 2212 */ 2213 for (i = 0; i < wowlan->n_patterns; i++) { 2214 2215 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); 2216 2217 if (!wow_pattern) 2218 return; 2219 2220 /* 2221 * TODO: convert the generic user space pattern to 2222 * appropriate chip specific/802.11 pattern. 2223 */ 2224 2225 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); 2226 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); 2227 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); 2228 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, 2229 patterns[i].pattern_len); 2230 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); 2231 wow_pattern->pattern_len = patterns[i].pattern_len; 2232 2233 /* 2234 * just need to take care of deauth and disssoc pattern, 2235 * make sure we don't overwrite them. 2236 */ 2237 2238 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, 2239 wow_pattern->mask_bytes, 2240 i + 2, 2241 wow_pattern->pattern_len); 2242 kfree(wow_pattern); 2243 2244 } 2245 2246 } 2247 2248 static int ath9k_suspend(struct ieee80211_hw *hw, 2249 struct cfg80211_wowlan *wowlan) 2250 { 2251 struct ath_softc *sc = hw->priv; 2252 struct ath_hw *ah = sc->sc_ah; 2253 struct ath_common *common = ath9k_hw_common(ah); 2254 u32 wow_triggers_enabled = 0; 2255 int ret = 0; 2256 2257 mutex_lock(&sc->mutex); 2258 2259 ath_cancel_work(sc); 2260 del_timer_sync(&common->ani.timer); 2261 del_timer_sync(&sc->rx_poll_timer); 2262 2263 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 2264 ath_dbg(common, ANY, "Device not present\n"); 2265 ret = -EINVAL; 2266 goto fail_wow; 2267 } 2268 2269 if (WARN_ON(!wowlan)) { 2270 ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); 2271 ret = -EINVAL; 2272 goto fail_wow; 2273 } 2274 2275 if (!device_can_wakeup(sc->dev)) { 2276 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); 2277 ret = 1; 2278 goto fail_wow; 2279 } 2280 2281 /* 2282 * none of the sta vifs are associated 2283 * and we are not currently handling multivif 2284 * cases, for instance we have to seperately 2285 * configure 'keep alive frame' for each 2286 * STA. 2287 */ 2288 2289 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 2290 ath_dbg(common, WOW, "None of the STA vifs are associated\n"); 2291 ret = 1; 2292 goto fail_wow; 2293 } 2294 2295 if (sc->nvifs > 1) { 2296 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); 2297 ret = 1; 2298 goto fail_wow; 2299 } 2300 2301 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); 2302 2303 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", 2304 wow_triggers_enabled); 2305 2306 ath9k_ps_wakeup(sc); 2307 2308 ath9k_stop_btcoex(sc); 2309 2310 /* 2311 * Enable wake up on recieving disassoc/deauth 2312 * frame by default. 2313 */ 2314 ath9k_wow_add_disassoc_deauth_pattern(sc); 2315 2316 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) 2317 ath9k_wow_add_pattern(sc, wowlan); 2318 2319 spin_lock_bh(&sc->sc_pcu_lock); 2320 /* 2321 * To avoid false wake, we enable beacon miss interrupt only 2322 * when we go to sleep. We save the current interrupt mask 2323 * so we can restore it after the system wakes up 2324 */ 2325 sc->wow_intr_before_sleep = ah->imask; 2326 ah->imask &= ~ATH9K_INT_GLOBAL; 2327 ath9k_hw_disable_interrupts(ah); 2328 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; 2329 ath9k_hw_set_interrupts(ah); 2330 ath9k_hw_enable_interrupts(ah); 2331 2332 spin_unlock_bh(&sc->sc_pcu_lock); 2333 2334 /* 2335 * we can now sync irq and kill any running tasklets, since we already 2336 * disabled interrupts and not holding a spin lock 2337 */ 2338 synchronize_irq(sc->irq); 2339 tasklet_kill(&sc->intr_tq); 2340 2341 ath9k_hw_wow_enable(ah, wow_triggers_enabled); 2342 2343 ath9k_ps_restore(sc); 2344 ath_dbg(common, ANY, "WoW enabled in ath9k\n"); 2345 atomic_inc(&sc->wow_sleep_proc_intr); 2346 2347 fail_wow: 2348 mutex_unlock(&sc->mutex); 2349 return ret; 2350 } 2351 2352 static int ath9k_resume(struct ieee80211_hw *hw) 2353 { 2354 struct ath_softc *sc = hw->priv; 2355 struct ath_hw *ah = sc->sc_ah; 2356 struct ath_common *common = ath9k_hw_common(ah); 2357 u32 wow_status; 2358 2359 mutex_lock(&sc->mutex); 2360 2361 ath9k_ps_wakeup(sc); 2362 2363 spin_lock_bh(&sc->sc_pcu_lock); 2364 2365 ath9k_hw_disable_interrupts(ah); 2366 ah->imask = sc->wow_intr_before_sleep; 2367 ath9k_hw_set_interrupts(ah); 2368 ath9k_hw_enable_interrupts(ah); 2369 2370 spin_unlock_bh(&sc->sc_pcu_lock); 2371 2372 wow_status = ath9k_hw_wow_wakeup(ah); 2373 2374 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { 2375 /* 2376 * some devices may not pick beacon miss 2377 * as the reason they woke up so we add 2378 * that here for that shortcoming. 2379 */ 2380 wow_status |= AH_WOW_BEACON_MISS; 2381 atomic_dec(&sc->wow_got_bmiss_intr); 2382 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); 2383 } 2384 2385 atomic_dec(&sc->wow_sleep_proc_intr); 2386 2387 if (wow_status) { 2388 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", 2389 ath9k_hw_wow_event_to_string(wow_status), wow_status); 2390 } 2391 2392 ath_restart_work(sc); 2393 ath9k_start_btcoex(sc); 2394 2395 ath9k_ps_restore(sc); 2396 mutex_unlock(&sc->mutex); 2397 2398 return 0; 2399 } 2400 2401 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) 2402 { 2403 struct ath_softc *sc = hw->priv; 2404 2405 mutex_lock(&sc->mutex); 2406 device_init_wakeup(sc->dev, 1); 2407 device_set_wakeup_enable(sc->dev, enabled); 2408 mutex_unlock(&sc->mutex); 2409 } 2410 2411 #endif 2412 2413 struct ieee80211_ops ath9k_ops = { 2414 .tx = ath9k_tx, 2415 .start = ath9k_start, 2416 .stop = ath9k_stop, 2417 .add_interface = ath9k_add_interface, 2418 .change_interface = ath9k_change_interface, 2419 .remove_interface = ath9k_remove_interface, 2420 .config = ath9k_config, 2421 .configure_filter = ath9k_configure_filter, 2422 .sta_add = ath9k_sta_add, 2423 .sta_remove = ath9k_sta_remove, 2424 .sta_notify = ath9k_sta_notify, 2425 .conf_tx = ath9k_conf_tx, 2426 .bss_info_changed = ath9k_bss_info_changed, 2427 .set_key = ath9k_set_key, 2428 .get_tsf = ath9k_get_tsf, 2429 .set_tsf = ath9k_set_tsf, 2430 .reset_tsf = ath9k_reset_tsf, 2431 .ampdu_action = ath9k_ampdu_action, 2432 .get_survey = ath9k_get_survey, 2433 .rfkill_poll = ath9k_rfkill_poll_state, 2434 .set_coverage_class = ath9k_set_coverage_class, 2435 .flush = ath9k_flush, 2436 .tx_frames_pending = ath9k_tx_frames_pending, 2437 .tx_last_beacon = ath9k_tx_last_beacon, 2438 .get_stats = ath9k_get_stats, 2439 .set_antenna = ath9k_set_antenna, 2440 .get_antenna = ath9k_get_antenna, 2441 2442 #ifdef CONFIG_PM_SLEEP 2443 .suspend = ath9k_suspend, 2444 .resume = ath9k_resume, 2445 .set_wakeup = ath9k_set_wakeup, 2446 #endif 2447 2448 #ifdef CONFIG_ATH9K_DEBUGFS 2449 .get_et_sset_count = ath9k_get_et_sset_count, 2450 .get_et_stats = ath9k_get_et_stats, 2451 .get_et_strings = ath9k_get_et_strings, 2452 #endif 2453 }; 2454