1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include "ath9k.h" 19 #include "btcoex.h" 20 21 static void ath_cache_conf_rate(struct ath_softc *sc, 22 struct ieee80211_conf *conf) 23 { 24 switch (conf->channel->band) { 25 case IEEE80211_BAND_2GHZ: 26 if (conf_is_ht20(conf)) 27 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; 28 else if (conf_is_ht40_minus(conf)) 29 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; 30 else if (conf_is_ht40_plus(conf)) 31 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; 32 else 33 sc->cur_rate_mode = ATH9K_MODE_11G; 34 break; 35 case IEEE80211_BAND_5GHZ: 36 if (conf_is_ht20(conf)) 37 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; 38 else if (conf_is_ht40_minus(conf)) 39 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; 40 else if (conf_is_ht40_plus(conf)) 41 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; 42 else 43 sc->cur_rate_mode = ATH9K_MODE_11A; 44 break; 45 default: 46 BUG_ON(1); 47 break; 48 } 49 } 50 51 static void ath_update_txpow(struct ath_softc *sc) 52 { 53 struct ath_hw *ah = sc->sc_ah; 54 u32 txpow; 55 56 if (sc->curtxpow != sc->config.txpowlimit) { 57 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); 58 /* read back in case value is clamped */ 59 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); 60 sc->curtxpow = txpow; 61 } 62 } 63 64 static u8 parse_mpdudensity(u8 mpdudensity) 65 { 66 /* 67 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 68 * 0 for no restriction 69 * 1 for 1/4 us 70 * 2 for 1/2 us 71 * 3 for 1 us 72 * 4 for 2 us 73 * 5 for 4 us 74 * 6 for 8 us 75 * 7 for 16 us 76 */ 77 switch (mpdudensity) { 78 case 0: 79 return 0; 80 case 1: 81 case 2: 82 case 3: 83 /* Our lower layer calculations limit our precision to 84 1 microsecond */ 85 return 1; 86 case 4: 87 return 2; 88 case 5: 89 return 4; 90 case 6: 91 return 8; 92 case 7: 93 return 16; 94 default: 95 return 0; 96 } 97 } 98 99 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, 100 struct ieee80211_hw *hw) 101 { 102 struct ieee80211_channel *curchan = hw->conf.channel; 103 struct ath9k_channel *channel; 104 u8 chan_idx; 105 106 chan_idx = curchan->hw_value; 107 channel = &sc->sc_ah->channels[chan_idx]; 108 ath9k_update_ichannel(sc, hw, channel); 109 return channel; 110 } 111 112 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 113 { 114 unsigned long flags; 115 bool ret; 116 117 spin_lock_irqsave(&sc->sc_pm_lock, flags); 118 ret = ath9k_hw_setpower(sc->sc_ah, mode); 119 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 120 121 return ret; 122 } 123 124 void ath9k_ps_wakeup(struct ath_softc *sc) 125 { 126 unsigned long flags; 127 128 spin_lock_irqsave(&sc->sc_pm_lock, flags); 129 if (++sc->ps_usecount != 1) 130 goto unlock; 131 132 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 133 134 unlock: 135 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 136 } 137 138 void ath9k_ps_restore(struct ath_softc *sc) 139 { 140 unsigned long flags; 141 142 spin_lock_irqsave(&sc->sc_pm_lock, flags); 143 if (--sc->ps_usecount != 0) 144 goto unlock; 145 146 if (sc->ps_idle) 147 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 148 else if (sc->ps_enabled && 149 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 150 PS_WAIT_FOR_CAB | 151 PS_WAIT_FOR_PSPOLL_DATA | 152 PS_WAIT_FOR_TX_ACK))) 153 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); 154 155 unlock: 156 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 157 } 158 159 /* 160 * Set/change channels. If the channel is really being changed, it's done 161 * by reseting the chip. To accomplish this we must first cleanup any pending 162 * DMA, then restart stuff. 163 */ 164 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 165 struct ath9k_channel *hchan) 166 { 167 struct ath_hw *ah = sc->sc_ah; 168 struct ath_common *common = ath9k_hw_common(ah); 169 struct ieee80211_conf *conf = &common->hw->conf; 170 bool fastcc = true, stopped; 171 struct ieee80211_channel *channel = hw->conf.channel; 172 int r; 173 174 if (sc->sc_flags & SC_OP_INVALID) 175 return -EIO; 176 177 ath9k_ps_wakeup(sc); 178 179 /* 180 * This is only performed if the channel settings have 181 * actually changed. 182 * 183 * To switch channels clear any pending DMA operations; 184 * wait long enough for the RX fifo to drain, reset the 185 * hardware at the new frequency, and then re-enable 186 * the relevant bits of the h/w. 187 */ 188 ath9k_hw_set_interrupts(ah, 0); 189 ath_drain_all_txq(sc, false); 190 stopped = ath_stoprecv(sc); 191 192 /* XXX: do not flush receive queue here. We don't want 193 * to flush data frames already in queue because of 194 * changing channel. */ 195 196 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) 197 fastcc = false; 198 199 ath_print(common, ATH_DBG_CONFIG, 200 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n", 201 sc->sc_ah->curchan->channel, 202 channel->center_freq, conf_is_ht40(conf)); 203 204 spin_lock_bh(&sc->sc_resetlock); 205 206 r = ath9k_hw_reset(ah, hchan, fastcc); 207 if (r) { 208 ath_print(common, ATH_DBG_FATAL, 209 "Unable to reset channel (%u MHz), " 210 "reset status %d\n", 211 channel->center_freq, r); 212 spin_unlock_bh(&sc->sc_resetlock); 213 goto ps_restore; 214 } 215 spin_unlock_bh(&sc->sc_resetlock); 216 217 sc->sc_flags &= ~SC_OP_FULL_RESET; 218 219 if (ath_startrecv(sc) != 0) { 220 ath_print(common, ATH_DBG_FATAL, 221 "Unable to restart recv logic\n"); 222 r = -EIO; 223 goto ps_restore; 224 } 225 226 ath_cache_conf_rate(sc, &hw->conf); 227 ath_update_txpow(sc); 228 ath9k_hw_set_interrupts(ah, ah->imask); 229 230 ps_restore: 231 ath9k_ps_restore(sc); 232 return r; 233 } 234 235 /* 236 * This routine performs the periodic noise floor calibration function 237 * that is used to adjust and optimize the chip performance. This 238 * takes environmental changes (location, temperature) into account. 239 * When the task is complete, it reschedules itself depending on the 240 * appropriate interval that was calculated. 241 */ 242 void ath_ani_calibrate(unsigned long data) 243 { 244 struct ath_softc *sc = (struct ath_softc *)data; 245 struct ath_hw *ah = sc->sc_ah; 246 struct ath_common *common = ath9k_hw_common(ah); 247 bool longcal = false; 248 bool shortcal = false; 249 bool aniflag = false; 250 unsigned int timestamp = jiffies_to_msecs(jiffies); 251 u32 cal_interval, short_cal_interval; 252 253 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? 254 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; 255 256 /* Only calibrate if awake */ 257 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) 258 goto set_timer; 259 260 ath9k_ps_wakeup(sc); 261 262 /* Long calibration runs independently of short calibration. */ 263 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { 264 longcal = true; 265 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 266 common->ani.longcal_timer = timestamp; 267 } 268 269 /* Short calibration applies only while caldone is false */ 270 if (!common->ani.caldone) { 271 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { 272 shortcal = true; 273 ath_print(common, ATH_DBG_ANI, 274 "shortcal @%lu\n", jiffies); 275 common->ani.shortcal_timer = timestamp; 276 common->ani.resetcal_timer = timestamp; 277 } 278 } else { 279 if ((timestamp - common->ani.resetcal_timer) >= 280 ATH_RESTART_CALINTERVAL) { 281 common->ani.caldone = ath9k_hw_reset_calvalid(ah); 282 if (common->ani.caldone) 283 common->ani.resetcal_timer = timestamp; 284 } 285 } 286 287 /* Verify whether we must check ANI */ 288 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { 289 aniflag = true; 290 common->ani.checkani_timer = timestamp; 291 } 292 293 /* Skip all processing if there's nothing to do. */ 294 if (longcal || shortcal || aniflag) { 295 /* Call ANI routine if necessary */ 296 if (aniflag) 297 ath9k_hw_ani_monitor(ah, ah->curchan); 298 299 /* Perform calibration if necessary */ 300 if (longcal || shortcal) { 301 common->ani.caldone = 302 ath9k_hw_calibrate(ah, 303 ah->curchan, 304 common->rx_chainmask, 305 longcal); 306 307 if (longcal) 308 common->ani.noise_floor = ath9k_hw_getchan_noise(ah, 309 ah->curchan); 310 311 ath_print(common, ATH_DBG_ANI, 312 " calibrate chan %u/%x nf: %d\n", 313 ah->curchan->channel, 314 ah->curchan->channelFlags, 315 common->ani.noise_floor); 316 } 317 } 318 319 ath9k_ps_restore(sc); 320 321 set_timer: 322 /* 323 * Set timer interval based on previous results. 324 * The interval must be the shortest necessary to satisfy ANI, 325 * short calibration and long calibration. 326 */ 327 cal_interval = ATH_LONG_CALINTERVAL; 328 if (sc->sc_ah->config.enable_ani) 329 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); 330 if (!common->ani.caldone) 331 cal_interval = min(cal_interval, (u32)short_cal_interval); 332 333 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); 334 } 335 336 static void ath_start_ani(struct ath_common *common) 337 { 338 unsigned long timestamp = jiffies_to_msecs(jiffies); 339 340 common->ani.longcal_timer = timestamp; 341 common->ani.shortcal_timer = timestamp; 342 common->ani.checkani_timer = timestamp; 343 344 mod_timer(&common->ani.timer, 345 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); 346 } 347 348 /* 349 * Update tx/rx chainmask. For legacy association, 350 * hard code chainmask to 1x1, for 11n association, use 351 * the chainmask configuration, for bt coexistence, use 352 * the chainmask configuration even in legacy mode. 353 */ 354 void ath_update_chainmask(struct ath_softc *sc, int is_ht) 355 { 356 struct ath_hw *ah = sc->sc_ah; 357 struct ath_common *common = ath9k_hw_common(ah); 358 359 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || 360 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { 361 common->tx_chainmask = ah->caps.tx_chainmask; 362 common->rx_chainmask = ah->caps.rx_chainmask; 363 } else { 364 common->tx_chainmask = 1; 365 common->rx_chainmask = 1; 366 } 367 368 ath_print(common, ATH_DBG_CONFIG, 369 "tx chmask: %d, rx chmask: %d\n", 370 common->tx_chainmask, 371 common->rx_chainmask); 372 } 373 374 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 375 { 376 struct ath_node *an; 377 378 an = (struct ath_node *)sta->drv_priv; 379 380 if (sc->sc_flags & SC_OP_TXAGGR) { 381 ath_tx_node_init(sc, an); 382 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 383 sta->ht_cap.ampdu_factor); 384 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); 385 an->last_rssi = ATH_RSSI_DUMMY_MARKER; 386 } 387 } 388 389 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 390 { 391 struct ath_node *an = (struct ath_node *)sta->drv_priv; 392 393 if (sc->sc_flags & SC_OP_TXAGGR) 394 ath_tx_node_cleanup(sc, an); 395 } 396 397 void ath9k_tasklet(unsigned long data) 398 { 399 struct ath_softc *sc = (struct ath_softc *)data; 400 struct ath_hw *ah = sc->sc_ah; 401 struct ath_common *common = ath9k_hw_common(ah); 402 403 u32 status = sc->intrstatus; 404 u32 rxmask; 405 406 ath9k_ps_wakeup(sc); 407 408 if ((status & ATH9K_INT_FATAL) || 409 !ath9k_hw_check_alive(ah)) { 410 ath_reset(sc, false); 411 ath9k_ps_restore(sc); 412 return; 413 } 414 415 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 416 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 417 ATH9K_INT_RXORN); 418 else 419 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 420 421 if (status & rxmask) { 422 spin_lock_bh(&sc->rx.rxflushlock); 423 424 /* Check for high priority Rx first */ 425 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 426 (status & ATH9K_INT_RXHP)) 427 ath_rx_tasklet(sc, 0, true); 428 429 ath_rx_tasklet(sc, 0, false); 430 spin_unlock_bh(&sc->rx.rxflushlock); 431 } 432 433 if (status & ATH9K_INT_TX) { 434 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 435 ath_tx_edma_tasklet(sc); 436 else 437 ath_tx_tasklet(sc); 438 } 439 440 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 441 /* 442 * TSF sync does not look correct; remain awake to sync with 443 * the next Beacon. 444 */ 445 ath_print(common, ATH_DBG_PS, 446 "TSFOOR - Sync with next Beacon\n"); 447 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 448 } 449 450 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 451 if (status & ATH9K_INT_GENTIMER) 452 ath_gen_timer_isr(sc->sc_ah); 453 454 /* re-enable hardware interrupt */ 455 ath9k_hw_set_interrupts(ah, ah->imask); 456 ath9k_ps_restore(sc); 457 } 458 459 irqreturn_t ath_isr(int irq, void *dev) 460 { 461 #define SCHED_INTR ( \ 462 ATH9K_INT_FATAL | \ 463 ATH9K_INT_RXORN | \ 464 ATH9K_INT_RXEOL | \ 465 ATH9K_INT_RX | \ 466 ATH9K_INT_RXLP | \ 467 ATH9K_INT_RXHP | \ 468 ATH9K_INT_TX | \ 469 ATH9K_INT_BMISS | \ 470 ATH9K_INT_CST | \ 471 ATH9K_INT_TSFOOR | \ 472 ATH9K_INT_GENTIMER) 473 474 struct ath_softc *sc = dev; 475 struct ath_hw *ah = sc->sc_ah; 476 enum ath9k_int status; 477 bool sched = false; 478 479 /* 480 * The hardware is not ready/present, don't 481 * touch anything. Note this can happen early 482 * on if the IRQ is shared. 483 */ 484 if (sc->sc_flags & SC_OP_INVALID) 485 return IRQ_NONE; 486 487 488 /* shared irq, not for us */ 489 490 if (!ath9k_hw_intrpend(ah)) 491 return IRQ_NONE; 492 493 /* 494 * Figure out the reason(s) for the interrupt. Note 495 * that the hal returns a pseudo-ISR that may include 496 * bits we haven't explicitly enabled so we mask the 497 * value to insure we only process bits we requested. 498 */ 499 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 500 status &= ah->imask; /* discard unasked-for bits */ 501 502 /* 503 * If there are no status bits set, then this interrupt was not 504 * for me (should have been caught above). 505 */ 506 if (!status) 507 return IRQ_NONE; 508 509 /* Cache the status */ 510 sc->intrstatus = status; 511 512 if (status & SCHED_INTR) 513 sched = true; 514 515 /* 516 * If a FATAL or RXORN interrupt is received, we have to reset the 517 * chip immediately. 518 */ 519 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 520 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 521 goto chip_reset; 522 523 if (status & ATH9K_INT_SWBA) 524 tasklet_schedule(&sc->bcon_tasklet); 525 526 if (status & ATH9K_INT_TXURN) 527 ath9k_hw_updatetxtriglevel(ah, true); 528 529 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 530 if (status & ATH9K_INT_RXEOL) { 531 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 532 ath9k_hw_set_interrupts(ah, ah->imask); 533 } 534 } 535 536 if (status & ATH9K_INT_MIB) { 537 /* 538 * Disable interrupts until we service the MIB 539 * interrupt; otherwise it will continue to 540 * fire. 541 */ 542 ath9k_hw_set_interrupts(ah, 0); 543 /* 544 * Let the hal handle the event. We assume 545 * it will clear whatever condition caused 546 * the interrupt. 547 */ 548 ath9k_hw_procmibevent(ah); 549 ath9k_hw_set_interrupts(ah, ah->imask); 550 } 551 552 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 553 if (status & ATH9K_INT_TIM_TIMER) { 554 /* Clear RxAbort bit so that we can 555 * receive frames */ 556 ath9k_setpower(sc, ATH9K_PM_AWAKE); 557 ath9k_hw_setrxabort(sc->sc_ah, 0); 558 sc->ps_flags |= PS_WAIT_FOR_BEACON; 559 } 560 561 chip_reset: 562 563 ath_debug_stat_interrupt(sc, status); 564 565 if (sched) { 566 /* turn off every interrupt except SWBA */ 567 ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); 568 tasklet_schedule(&sc->intr_tq); 569 } 570 571 return IRQ_HANDLED; 572 573 #undef SCHED_INTR 574 } 575 576 static u32 ath_get_extchanmode(struct ath_softc *sc, 577 struct ieee80211_channel *chan, 578 enum nl80211_channel_type channel_type) 579 { 580 u32 chanmode = 0; 581 582 switch (chan->band) { 583 case IEEE80211_BAND_2GHZ: 584 switch(channel_type) { 585 case NL80211_CHAN_NO_HT: 586 case NL80211_CHAN_HT20: 587 chanmode = CHANNEL_G_HT20; 588 break; 589 case NL80211_CHAN_HT40PLUS: 590 chanmode = CHANNEL_G_HT40PLUS; 591 break; 592 case NL80211_CHAN_HT40MINUS: 593 chanmode = CHANNEL_G_HT40MINUS; 594 break; 595 } 596 break; 597 case IEEE80211_BAND_5GHZ: 598 switch(channel_type) { 599 case NL80211_CHAN_NO_HT: 600 case NL80211_CHAN_HT20: 601 chanmode = CHANNEL_A_HT20; 602 break; 603 case NL80211_CHAN_HT40PLUS: 604 chanmode = CHANNEL_A_HT40PLUS; 605 break; 606 case NL80211_CHAN_HT40MINUS: 607 chanmode = CHANNEL_A_HT40MINUS; 608 break; 609 } 610 break; 611 default: 612 break; 613 } 614 615 return chanmode; 616 } 617 618 static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key, 619 struct ath9k_keyval *hk, const u8 *addr, 620 bool authenticator) 621 { 622 struct ath_hw *ah = common->ah; 623 const u8 *key_rxmic; 624 const u8 *key_txmic; 625 626 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; 627 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; 628 629 if (addr == NULL) { 630 /* 631 * Group key installation - only two key cache entries are used 632 * regardless of splitmic capability since group key is only 633 * used either for TX or RX. 634 */ 635 if (authenticator) { 636 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); 637 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic)); 638 } else { 639 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 640 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic)); 641 } 642 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr); 643 } 644 if (!common->splitmic) { 645 /* TX and RX keys share the same key cache entry. */ 646 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 647 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); 648 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr); 649 } 650 651 /* Separate key cache entries for TX and RX */ 652 653 /* TX key goes at first index, RX key at +32. */ 654 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); 655 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) { 656 /* TX MIC entry failed. No need to proceed further */ 657 ath_print(common, ATH_DBG_FATAL, 658 "Setting TX MIC Key Failed\n"); 659 return 0; 660 } 661 662 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 663 /* XXX delete tx key on failure? */ 664 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr); 665 } 666 667 static int ath_reserve_key_cache_slot_tkip(struct ath_common *common) 668 { 669 int i; 670 671 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) { 672 if (test_bit(i, common->keymap) || 673 test_bit(i + 64, common->keymap)) 674 continue; /* At least one part of TKIP key allocated */ 675 if (common->splitmic && 676 (test_bit(i + 32, common->keymap) || 677 test_bit(i + 64 + 32, common->keymap))) 678 continue; /* At least one part of TKIP key allocated */ 679 680 /* Found a free slot for a TKIP key */ 681 return i; 682 } 683 return -1; 684 } 685 686 static int ath_reserve_key_cache_slot(struct ath_common *common) 687 { 688 int i; 689 690 /* First, try to find slots that would not be available for TKIP. */ 691 if (common->splitmic) { 692 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) { 693 if (!test_bit(i, common->keymap) && 694 (test_bit(i + 32, common->keymap) || 695 test_bit(i + 64, common->keymap) || 696 test_bit(i + 64 + 32, common->keymap))) 697 return i; 698 if (!test_bit(i + 32, common->keymap) && 699 (test_bit(i, common->keymap) || 700 test_bit(i + 64, common->keymap) || 701 test_bit(i + 64 + 32, common->keymap))) 702 return i + 32; 703 if (!test_bit(i + 64, common->keymap) && 704 (test_bit(i , common->keymap) || 705 test_bit(i + 32, common->keymap) || 706 test_bit(i + 64 + 32, common->keymap))) 707 return i + 64; 708 if (!test_bit(i + 64 + 32, common->keymap) && 709 (test_bit(i, common->keymap) || 710 test_bit(i + 32, common->keymap) || 711 test_bit(i + 64, common->keymap))) 712 return i + 64 + 32; 713 } 714 } else { 715 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) { 716 if (!test_bit(i, common->keymap) && 717 test_bit(i + 64, common->keymap)) 718 return i; 719 if (test_bit(i, common->keymap) && 720 !test_bit(i + 64, common->keymap)) 721 return i + 64; 722 } 723 } 724 725 /* No partially used TKIP slots, pick any available slot */ 726 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) { 727 /* Do not allow slots that could be needed for TKIP group keys 728 * to be used. This limitation could be removed if we know that 729 * TKIP will not be used. */ 730 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) 731 continue; 732 if (common->splitmic) { 733 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) 734 continue; 735 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) 736 continue; 737 } 738 739 if (!test_bit(i, common->keymap)) 740 return i; /* Found a free slot for a key */ 741 } 742 743 /* No free slot found */ 744 return -1; 745 } 746 747 static int ath_key_config(struct ath_common *common, 748 struct ieee80211_vif *vif, 749 struct ieee80211_sta *sta, 750 struct ieee80211_key_conf *key) 751 { 752 struct ath_hw *ah = common->ah; 753 struct ath9k_keyval hk; 754 const u8 *mac = NULL; 755 int ret = 0; 756 int idx; 757 758 memset(&hk, 0, sizeof(hk)); 759 760 switch (key->alg) { 761 case ALG_WEP: 762 hk.kv_type = ATH9K_CIPHER_WEP; 763 break; 764 case ALG_TKIP: 765 hk.kv_type = ATH9K_CIPHER_TKIP; 766 break; 767 case ALG_CCMP: 768 hk.kv_type = ATH9K_CIPHER_AES_CCM; 769 break; 770 default: 771 return -EOPNOTSUPP; 772 } 773 774 hk.kv_len = key->keylen; 775 memcpy(hk.kv_val, key->key, key->keylen); 776 777 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 778 /* For now, use the default keys for broadcast keys. This may 779 * need to change with virtual interfaces. */ 780 idx = key->keyidx; 781 } else if (key->keyidx) { 782 if (WARN_ON(!sta)) 783 return -EOPNOTSUPP; 784 mac = sta->addr; 785 786 if (vif->type != NL80211_IFTYPE_AP) { 787 /* Only keyidx 0 should be used with unicast key, but 788 * allow this for client mode for now. */ 789 idx = key->keyidx; 790 } else 791 return -EIO; 792 } else { 793 if (WARN_ON(!sta)) 794 return -EOPNOTSUPP; 795 mac = sta->addr; 796 797 if (key->alg == ALG_TKIP) 798 idx = ath_reserve_key_cache_slot_tkip(common); 799 else 800 idx = ath_reserve_key_cache_slot(common); 801 if (idx < 0) 802 return -ENOSPC; /* no free key cache entries */ 803 } 804 805 if (key->alg == ALG_TKIP) 806 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac, 807 vif->type == NL80211_IFTYPE_AP); 808 else 809 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac); 810 811 if (!ret) 812 return -EIO; 813 814 set_bit(idx, common->keymap); 815 if (key->alg == ALG_TKIP) { 816 set_bit(idx + 64, common->keymap); 817 if (common->splitmic) { 818 set_bit(idx + 32, common->keymap); 819 set_bit(idx + 64 + 32, common->keymap); 820 } 821 } 822 823 return idx; 824 } 825 826 static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key) 827 { 828 struct ath_hw *ah = common->ah; 829 830 ath9k_hw_keyreset(ah, key->hw_key_idx); 831 if (key->hw_key_idx < IEEE80211_WEP_NKID) 832 return; 833 834 clear_bit(key->hw_key_idx, common->keymap); 835 if (key->alg != ALG_TKIP) 836 return; 837 838 clear_bit(key->hw_key_idx + 64, common->keymap); 839 if (common->splitmic) { 840 ath9k_hw_keyreset(ah, key->hw_key_idx + 32); 841 clear_bit(key->hw_key_idx + 32, common->keymap); 842 clear_bit(key->hw_key_idx + 64 + 32, common->keymap); 843 } 844 } 845 846 static void ath9k_bss_assoc_info(struct ath_softc *sc, 847 struct ieee80211_vif *vif, 848 struct ieee80211_bss_conf *bss_conf) 849 { 850 struct ath_hw *ah = sc->sc_ah; 851 struct ath_common *common = ath9k_hw_common(ah); 852 853 if (bss_conf->assoc) { 854 ath_print(common, ATH_DBG_CONFIG, 855 "Bss Info ASSOC %d, bssid: %pM\n", 856 bss_conf->aid, common->curbssid); 857 858 /* New association, store aid */ 859 common->curaid = bss_conf->aid; 860 ath9k_hw_write_associd(ah); 861 862 /* 863 * Request a re-configuration of Beacon related timers 864 * on the receipt of the first Beacon frame (i.e., 865 * after time sync with the AP). 866 */ 867 sc->ps_flags |= PS_BEACON_SYNC; 868 869 /* Configure the beacon */ 870 ath_beacon_config(sc, vif); 871 872 /* Reset rssi stats */ 873 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 874 875 ath_start_ani(common); 876 } else { 877 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); 878 common->curaid = 0; 879 /* Stop ANI */ 880 del_timer_sync(&common->ani.timer); 881 } 882 } 883 884 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) 885 { 886 struct ath_hw *ah = sc->sc_ah; 887 struct ath_common *common = ath9k_hw_common(ah); 888 struct ieee80211_channel *channel = hw->conf.channel; 889 int r; 890 891 ath9k_ps_wakeup(sc); 892 ath9k_hw_configpcipowersave(ah, 0, 0); 893 894 if (!ah->curchan) 895 ah->curchan = ath_get_curchannel(sc, sc->hw); 896 897 spin_lock_bh(&sc->sc_resetlock); 898 r = ath9k_hw_reset(ah, ah->curchan, false); 899 if (r) { 900 ath_print(common, ATH_DBG_FATAL, 901 "Unable to reset channel (%u MHz), " 902 "reset status %d\n", 903 channel->center_freq, r); 904 } 905 spin_unlock_bh(&sc->sc_resetlock); 906 907 ath_update_txpow(sc); 908 if (ath_startrecv(sc) != 0) { 909 ath_print(common, ATH_DBG_FATAL, 910 "Unable to restart recv logic\n"); 911 return; 912 } 913 914 if (sc->sc_flags & SC_OP_BEACONS) 915 ath_beacon_config(sc, NULL); /* restart beacons */ 916 917 /* Re-Enable interrupts */ 918 ath9k_hw_set_interrupts(ah, ah->imask); 919 920 /* Enable LED */ 921 ath9k_hw_cfg_output(ah, ah->led_pin, 922 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 923 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 924 925 ieee80211_wake_queues(hw); 926 ath9k_ps_restore(sc); 927 } 928 929 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) 930 { 931 struct ath_hw *ah = sc->sc_ah; 932 struct ieee80211_channel *channel = hw->conf.channel; 933 int r; 934 935 ath9k_ps_wakeup(sc); 936 ieee80211_stop_queues(hw); 937 938 /* Disable LED */ 939 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 940 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 941 942 /* Disable interrupts */ 943 ath9k_hw_set_interrupts(ah, 0); 944 945 ath_drain_all_txq(sc, false); /* clear pending tx frames */ 946 ath_stoprecv(sc); /* turn off frame recv */ 947 ath_flushrecv(sc); /* flush recv queue */ 948 949 if (!ah->curchan) 950 ah->curchan = ath_get_curchannel(sc, hw); 951 952 spin_lock_bh(&sc->sc_resetlock); 953 r = ath9k_hw_reset(ah, ah->curchan, false); 954 if (r) { 955 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 956 "Unable to reset channel (%u MHz), " 957 "reset status %d\n", 958 channel->center_freq, r); 959 } 960 spin_unlock_bh(&sc->sc_resetlock); 961 962 ath9k_hw_phy_disable(ah); 963 ath9k_hw_configpcipowersave(ah, 1, 1); 964 ath9k_ps_restore(sc); 965 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); 966 } 967 968 int ath_reset(struct ath_softc *sc, bool retry_tx) 969 { 970 struct ath_hw *ah = sc->sc_ah; 971 struct ath_common *common = ath9k_hw_common(ah); 972 struct ieee80211_hw *hw = sc->hw; 973 int r; 974 975 /* Stop ANI */ 976 del_timer_sync(&common->ani.timer); 977 978 ieee80211_stop_queues(hw); 979 980 ath9k_hw_set_interrupts(ah, 0); 981 ath_drain_all_txq(sc, retry_tx); 982 ath_stoprecv(sc); 983 ath_flushrecv(sc); 984 985 spin_lock_bh(&sc->sc_resetlock); 986 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); 987 if (r) 988 ath_print(common, ATH_DBG_FATAL, 989 "Unable to reset hardware; reset status %d\n", r); 990 spin_unlock_bh(&sc->sc_resetlock); 991 992 if (ath_startrecv(sc) != 0) 993 ath_print(common, ATH_DBG_FATAL, 994 "Unable to start recv logic\n"); 995 996 /* 997 * We may be doing a reset in response to a request 998 * that changes the channel so update any state that 999 * might change as a result. 1000 */ 1001 ath_cache_conf_rate(sc, &hw->conf); 1002 1003 ath_update_txpow(sc); 1004 1005 if (sc->sc_flags & SC_OP_BEACONS) 1006 ath_beacon_config(sc, NULL); /* restart beacons */ 1007 1008 ath9k_hw_set_interrupts(ah, ah->imask); 1009 1010 if (retry_tx) { 1011 int i; 1012 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1013 if (ATH_TXQ_SETUP(sc, i)) { 1014 spin_lock_bh(&sc->tx.txq[i].axq_lock); 1015 ath_txq_schedule(sc, &sc->tx.txq[i]); 1016 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 1017 } 1018 } 1019 } 1020 1021 ieee80211_wake_queues(hw); 1022 1023 /* Start ANI */ 1024 ath_start_ani(common); 1025 1026 return r; 1027 } 1028 1029 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) 1030 { 1031 int qnum; 1032 1033 switch (queue) { 1034 case 0: 1035 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO]; 1036 break; 1037 case 1: 1038 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI]; 1039 break; 1040 case 2: 1041 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; 1042 break; 1043 case 3: 1044 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK]; 1045 break; 1046 default: 1047 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; 1048 break; 1049 } 1050 1051 return qnum; 1052 } 1053 1054 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) 1055 { 1056 int qnum; 1057 1058 switch (queue) { 1059 case ATH9K_WME_AC_VO: 1060 qnum = 0; 1061 break; 1062 case ATH9K_WME_AC_VI: 1063 qnum = 1; 1064 break; 1065 case ATH9K_WME_AC_BE: 1066 qnum = 2; 1067 break; 1068 case ATH9K_WME_AC_BK: 1069 qnum = 3; 1070 break; 1071 default: 1072 qnum = -1; 1073 break; 1074 } 1075 1076 return qnum; 1077 } 1078 1079 /* XXX: Remove me once we don't depend on ath9k_channel for all 1080 * this redundant data */ 1081 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, 1082 struct ath9k_channel *ichan) 1083 { 1084 struct ieee80211_channel *chan = hw->conf.channel; 1085 struct ieee80211_conf *conf = &hw->conf; 1086 1087 ichan->channel = chan->center_freq; 1088 ichan->chan = chan; 1089 1090 if (chan->band == IEEE80211_BAND_2GHZ) { 1091 ichan->chanmode = CHANNEL_G; 1092 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; 1093 } else { 1094 ichan->chanmode = CHANNEL_A; 1095 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; 1096 } 1097 1098 if (conf_is_ht(conf)) 1099 ichan->chanmode = ath_get_extchanmode(sc, chan, 1100 conf->channel_type); 1101 } 1102 1103 /**********************/ 1104 /* mac80211 callbacks */ 1105 /**********************/ 1106 1107 static int ath9k_start(struct ieee80211_hw *hw) 1108 { 1109 struct ath_wiphy *aphy = hw->priv; 1110 struct ath_softc *sc = aphy->sc; 1111 struct ath_hw *ah = sc->sc_ah; 1112 struct ath_common *common = ath9k_hw_common(ah); 1113 struct ieee80211_channel *curchan = hw->conf.channel; 1114 struct ath9k_channel *init_channel; 1115 int r; 1116 1117 ath_print(common, ATH_DBG_CONFIG, 1118 "Starting driver with initial channel: %d MHz\n", 1119 curchan->center_freq); 1120 1121 mutex_lock(&sc->mutex); 1122 1123 if (ath9k_wiphy_started(sc)) { 1124 if (sc->chan_idx == curchan->hw_value) { 1125 /* 1126 * Already on the operational channel, the new wiphy 1127 * can be marked active. 1128 */ 1129 aphy->state = ATH_WIPHY_ACTIVE; 1130 ieee80211_wake_queues(hw); 1131 } else { 1132 /* 1133 * Another wiphy is on another channel, start the new 1134 * wiphy in paused state. 1135 */ 1136 aphy->state = ATH_WIPHY_PAUSED; 1137 ieee80211_stop_queues(hw); 1138 } 1139 mutex_unlock(&sc->mutex); 1140 return 0; 1141 } 1142 aphy->state = ATH_WIPHY_ACTIVE; 1143 1144 /* setup initial channel */ 1145 1146 sc->chan_idx = curchan->hw_value; 1147 1148 init_channel = ath_get_curchannel(sc, hw); 1149 1150 /* Reset SERDES registers */ 1151 ath9k_hw_configpcipowersave(ah, 0, 0); 1152 1153 /* 1154 * The basic interface to setting the hardware in a good 1155 * state is ``reset''. On return the hardware is known to 1156 * be powered up and with interrupts disabled. This must 1157 * be followed by initialization of the appropriate bits 1158 * and then setup of the interrupt mask. 1159 */ 1160 spin_lock_bh(&sc->sc_resetlock); 1161 r = ath9k_hw_reset(ah, init_channel, false); 1162 if (r) { 1163 ath_print(common, ATH_DBG_FATAL, 1164 "Unable to reset hardware; reset status %d " 1165 "(freq %u MHz)\n", r, 1166 curchan->center_freq); 1167 spin_unlock_bh(&sc->sc_resetlock); 1168 goto mutex_unlock; 1169 } 1170 spin_unlock_bh(&sc->sc_resetlock); 1171 1172 /* 1173 * This is needed only to setup initial state 1174 * but it's best done after a reset. 1175 */ 1176 ath_update_txpow(sc); 1177 1178 /* 1179 * Setup the hardware after reset: 1180 * The receive engine is set going. 1181 * Frame transmit is handled entirely 1182 * in the frame output path; there's nothing to do 1183 * here except setup the interrupt mask. 1184 */ 1185 if (ath_startrecv(sc) != 0) { 1186 ath_print(common, ATH_DBG_FATAL, 1187 "Unable to start recv logic\n"); 1188 r = -EIO; 1189 goto mutex_unlock; 1190 } 1191 1192 /* Setup our intr mask. */ 1193 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 1194 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 1195 ATH9K_INT_GLOBAL; 1196 1197 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 1198 ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP; 1199 else 1200 ah->imask |= ATH9K_INT_RX; 1201 1202 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) 1203 ah->imask |= ATH9K_INT_GTT; 1204 1205 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 1206 ah->imask |= ATH9K_INT_CST; 1207 1208 ath_cache_conf_rate(sc, &hw->conf); 1209 1210 sc->sc_flags &= ~SC_OP_INVALID; 1211 1212 /* Disable BMISS interrupt when we're not associated */ 1213 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); 1214 ath9k_hw_set_interrupts(ah, ah->imask); 1215 1216 ieee80211_wake_queues(hw); 1217 1218 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 1219 1220 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && 1221 !ah->btcoex_hw.enabled) { 1222 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, 1223 AR_STOMP_LOW_WLAN_WGHT); 1224 ath9k_hw_btcoex_enable(ah); 1225 1226 if (common->bus_ops->bt_coex_prep) 1227 common->bus_ops->bt_coex_prep(common); 1228 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 1229 ath9k_btcoex_timer_resume(sc); 1230 } 1231 1232 mutex_unlock: 1233 mutex_unlock(&sc->mutex); 1234 1235 return r; 1236 } 1237 1238 static int ath9k_tx(struct ieee80211_hw *hw, 1239 struct sk_buff *skb) 1240 { 1241 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1242 struct ath_wiphy *aphy = hw->priv; 1243 struct ath_softc *sc = aphy->sc; 1244 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1245 struct ath_tx_control txctl; 1246 int padpos, padsize; 1247 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1248 1249 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { 1250 ath_print(common, ATH_DBG_XMIT, 1251 "ath9k: %s: TX in unexpected wiphy state " 1252 "%d\n", wiphy_name(hw->wiphy), aphy->state); 1253 goto exit; 1254 } 1255 1256 if (sc->ps_enabled) { 1257 /* 1258 * mac80211 does not set PM field for normal data frames, so we 1259 * need to update that based on the current PS mode. 1260 */ 1261 if (ieee80211_is_data(hdr->frame_control) && 1262 !ieee80211_is_nullfunc(hdr->frame_control) && 1263 !ieee80211_has_pm(hdr->frame_control)) { 1264 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " 1265 "while in PS mode\n"); 1266 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1267 } 1268 } 1269 1270 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { 1271 /* 1272 * We are using PS-Poll and mac80211 can request TX while in 1273 * power save mode. Need to wake up hardware for the TX to be 1274 * completed and if needed, also for RX of buffered frames. 1275 */ 1276 ath9k_ps_wakeup(sc); 1277 ath9k_hw_setrxabort(sc->sc_ah, 0); 1278 if (ieee80211_is_pspoll(hdr->frame_control)) { 1279 ath_print(common, ATH_DBG_PS, 1280 "Sending PS-Poll to pick a buffered frame\n"); 1281 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 1282 } else { 1283 ath_print(common, ATH_DBG_PS, 1284 "Wake up to complete TX\n"); 1285 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 1286 } 1287 /* 1288 * The actual restore operation will happen only after 1289 * the sc_flags bit is cleared. We are just dropping 1290 * the ps_usecount here. 1291 */ 1292 ath9k_ps_restore(sc); 1293 } 1294 1295 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1296 1297 /* 1298 * As a temporary workaround, assign seq# here; this will likely need 1299 * to be cleaned up to work better with Beacon transmission and virtual 1300 * BSSes. 1301 */ 1302 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1303 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1304 sc->tx.seq_no += 0x10; 1305 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1306 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); 1307 } 1308 1309 /* Add the padding after the header if this is not already done */ 1310 padpos = ath9k_cmn_padpos(hdr->frame_control); 1311 padsize = padpos & 3; 1312 if (padsize && skb->len>padpos) { 1313 if (skb_headroom(skb) < padsize) 1314 return -1; 1315 skb_push(skb, padsize); 1316 memmove(skb->data, skb->data + padsize, padpos); 1317 } 1318 1319 /* Check if a tx queue is available */ 1320 1321 txctl.txq = ath_test_get_txq(sc, skb); 1322 if (!txctl.txq) 1323 goto exit; 1324 1325 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 1326 1327 if (ath_tx_start(hw, skb, &txctl) != 0) { 1328 ath_print(common, ATH_DBG_XMIT, "TX failed\n"); 1329 goto exit; 1330 } 1331 1332 return 0; 1333 exit: 1334 dev_kfree_skb_any(skb); 1335 return 0; 1336 } 1337 1338 static void ath9k_stop(struct ieee80211_hw *hw) 1339 { 1340 struct ath_wiphy *aphy = hw->priv; 1341 struct ath_softc *sc = aphy->sc; 1342 struct ath_hw *ah = sc->sc_ah; 1343 struct ath_common *common = ath9k_hw_common(ah); 1344 1345 mutex_lock(&sc->mutex); 1346 1347 aphy->state = ATH_WIPHY_INACTIVE; 1348 1349 cancel_delayed_work_sync(&sc->ath_led_blink_work); 1350 cancel_delayed_work_sync(&sc->tx_complete_work); 1351 1352 if (!sc->num_sec_wiphy) { 1353 cancel_delayed_work_sync(&sc->wiphy_work); 1354 cancel_work_sync(&sc->chan_work); 1355 } 1356 1357 if (sc->sc_flags & SC_OP_INVALID) { 1358 ath_print(common, ATH_DBG_ANY, "Device not present\n"); 1359 mutex_unlock(&sc->mutex); 1360 return; 1361 } 1362 1363 if (ath9k_wiphy_started(sc)) { 1364 mutex_unlock(&sc->mutex); 1365 return; /* another wiphy still in use */ 1366 } 1367 1368 /* Ensure HW is awake when we try to shut it down. */ 1369 ath9k_ps_wakeup(sc); 1370 1371 if (ah->btcoex_hw.enabled) { 1372 ath9k_hw_btcoex_disable(ah); 1373 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 1374 ath9k_btcoex_timer_pause(sc); 1375 } 1376 1377 /* make sure h/w will not generate any interrupt 1378 * before setting the invalid flag. */ 1379 ath9k_hw_set_interrupts(ah, 0); 1380 1381 if (!(sc->sc_flags & SC_OP_INVALID)) { 1382 ath_drain_all_txq(sc, false); 1383 ath_stoprecv(sc); 1384 ath9k_hw_phy_disable(ah); 1385 } else 1386 sc->rx.rxlink = NULL; 1387 1388 /* disable HAL and put h/w to sleep */ 1389 ath9k_hw_disable(ah); 1390 ath9k_hw_configpcipowersave(ah, 1, 1); 1391 ath9k_ps_restore(sc); 1392 1393 /* Finally, put the chip in FULL SLEEP mode */ 1394 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); 1395 1396 sc->sc_flags |= SC_OP_INVALID; 1397 1398 mutex_unlock(&sc->mutex); 1399 1400 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); 1401 } 1402 1403 static int ath9k_add_interface(struct ieee80211_hw *hw, 1404 struct ieee80211_vif *vif) 1405 { 1406 struct ath_wiphy *aphy = hw->priv; 1407 struct ath_softc *sc = aphy->sc; 1408 struct ath_hw *ah = sc->sc_ah; 1409 struct ath_common *common = ath9k_hw_common(ah); 1410 struct ath_vif *avp = (void *)vif->drv_priv; 1411 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; 1412 int ret = 0; 1413 1414 mutex_lock(&sc->mutex); 1415 1416 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && 1417 sc->nvifs > 0) { 1418 ret = -ENOBUFS; 1419 goto out; 1420 } 1421 1422 switch (vif->type) { 1423 case NL80211_IFTYPE_STATION: 1424 ic_opmode = NL80211_IFTYPE_STATION; 1425 break; 1426 case NL80211_IFTYPE_ADHOC: 1427 case NL80211_IFTYPE_AP: 1428 case NL80211_IFTYPE_MESH_POINT: 1429 if (sc->nbcnvifs >= ATH_BCBUF) { 1430 ret = -ENOBUFS; 1431 goto out; 1432 } 1433 ic_opmode = vif->type; 1434 break; 1435 default: 1436 ath_print(common, ATH_DBG_FATAL, 1437 "Interface type %d not yet supported\n", vif->type); 1438 ret = -EOPNOTSUPP; 1439 goto out; 1440 } 1441 1442 ath_print(common, ATH_DBG_CONFIG, 1443 "Attach a VIF of type: %d\n", ic_opmode); 1444 1445 /* Set the VIF opmode */ 1446 avp->av_opmode = ic_opmode; 1447 avp->av_bslot = -1; 1448 1449 sc->nvifs++; 1450 1451 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 1452 ath9k_set_bssid_mask(hw); 1453 1454 if (sc->nvifs > 1) 1455 goto out; /* skip global settings for secondary vif */ 1456 1457 if (ic_opmode == NL80211_IFTYPE_AP) { 1458 ath9k_hw_set_tsfadjust(ah, 1); 1459 sc->sc_flags |= SC_OP_TSF_RESET; 1460 } 1461 1462 /* Set the device opmode */ 1463 ah->opmode = ic_opmode; 1464 1465 /* 1466 * Enable MIB interrupts when there are hardware phy counters. 1467 * Note we only do this (at the moment) for station mode. 1468 */ 1469 if ((vif->type == NL80211_IFTYPE_STATION) || 1470 (vif->type == NL80211_IFTYPE_ADHOC) || 1471 (vif->type == NL80211_IFTYPE_MESH_POINT)) { 1472 if (ah->config.enable_ani) 1473 ah->imask |= ATH9K_INT_MIB; 1474 ah->imask |= ATH9K_INT_TSFOOR; 1475 } 1476 1477 ath9k_hw_set_interrupts(ah, ah->imask); 1478 1479 if (vif->type == NL80211_IFTYPE_AP || 1480 vif->type == NL80211_IFTYPE_ADHOC || 1481 vif->type == NL80211_IFTYPE_MONITOR) 1482 ath_start_ani(common); 1483 1484 out: 1485 mutex_unlock(&sc->mutex); 1486 return ret; 1487 } 1488 1489 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1490 struct ieee80211_vif *vif) 1491 { 1492 struct ath_wiphy *aphy = hw->priv; 1493 struct ath_softc *sc = aphy->sc; 1494 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1495 struct ath_vif *avp = (void *)vif->drv_priv; 1496 int i; 1497 1498 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); 1499 1500 mutex_lock(&sc->mutex); 1501 1502 /* Stop ANI */ 1503 del_timer_sync(&common->ani.timer); 1504 1505 /* Reclaim beacon resources */ 1506 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || 1507 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || 1508 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { 1509 ath9k_ps_wakeup(sc); 1510 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1511 ath9k_ps_restore(sc); 1512 } 1513 1514 ath_beacon_return(sc, avp); 1515 sc->sc_flags &= ~SC_OP_BEACONS; 1516 1517 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { 1518 if (sc->beacon.bslot[i] == vif) { 1519 printk(KERN_DEBUG "%s: vif had allocated beacon " 1520 "slot\n", __func__); 1521 sc->beacon.bslot[i] = NULL; 1522 sc->beacon.bslot_aphy[i] = NULL; 1523 } 1524 } 1525 1526 sc->nvifs--; 1527 1528 mutex_unlock(&sc->mutex); 1529 } 1530 1531 void ath9k_enable_ps(struct ath_softc *sc) 1532 { 1533 struct ath_hw *ah = sc->sc_ah; 1534 1535 sc->ps_enabled = true; 1536 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1537 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1538 ah->imask |= ATH9K_INT_TIM_TIMER; 1539 ath9k_hw_set_interrupts(ah, ah->imask); 1540 } 1541 } 1542 ath9k_hw_setrxabort(ah, 1); 1543 } 1544 1545 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1546 { 1547 struct ath_wiphy *aphy = hw->priv; 1548 struct ath_softc *sc = aphy->sc; 1549 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1550 struct ieee80211_conf *conf = &hw->conf; 1551 struct ath_hw *ah = sc->sc_ah; 1552 bool disable_radio; 1553 1554 mutex_lock(&sc->mutex); 1555 1556 /* 1557 * Leave this as the first check because we need to turn on the 1558 * radio if it was disabled before prior to processing the rest 1559 * of the changes. Likewise we must only disable the radio towards 1560 * the end. 1561 */ 1562 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1563 bool enable_radio; 1564 bool all_wiphys_idle; 1565 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1566 1567 spin_lock_bh(&sc->wiphy_lock); 1568 all_wiphys_idle = ath9k_all_wiphys_idle(sc); 1569 ath9k_set_wiphy_idle(aphy, idle); 1570 1571 enable_radio = (!idle && all_wiphys_idle); 1572 1573 /* 1574 * After we unlock here its possible another wiphy 1575 * can be re-renabled so to account for that we will 1576 * only disable the radio toward the end of this routine 1577 * if by then all wiphys are still idle. 1578 */ 1579 spin_unlock_bh(&sc->wiphy_lock); 1580 1581 if (enable_radio) { 1582 sc->ps_idle = false; 1583 ath_radio_enable(sc, hw); 1584 ath_print(common, ATH_DBG_CONFIG, 1585 "not-idle: enabling radio\n"); 1586 } 1587 } 1588 1589 /* 1590 * We just prepare to enable PS. We have to wait until our AP has 1591 * ACK'd our null data frame to disable RX otherwise we'll ignore 1592 * those ACKs and end up retransmitting the same null data frames. 1593 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1594 */ 1595 if (changed & IEEE80211_CONF_CHANGE_PS) { 1596 if (conf->flags & IEEE80211_CONF_PS) { 1597 sc->ps_flags |= PS_ENABLED; 1598 /* 1599 * At this point we know hardware has received an ACK 1600 * of a previously sent null data frame. 1601 */ 1602 if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { 1603 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; 1604 ath9k_enable_ps(sc); 1605 } 1606 } else { 1607 sc->ps_enabled = false; 1608 sc->ps_flags &= ~(PS_ENABLED | 1609 PS_NULLFUNC_COMPLETED); 1610 ath9k_setpower(sc, ATH9K_PM_AWAKE); 1611 if (!(ah->caps.hw_caps & 1612 ATH9K_HW_CAP_AUTOSLEEP)) { 1613 ath9k_hw_setrxabort(sc->sc_ah, 0); 1614 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1615 PS_WAIT_FOR_CAB | 1616 PS_WAIT_FOR_PSPOLL_DATA | 1617 PS_WAIT_FOR_TX_ACK); 1618 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1619 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1620 ath9k_hw_set_interrupts(sc->sc_ah, 1621 ah->imask); 1622 } 1623 } 1624 } 1625 } 1626 1627 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1628 if (conf->flags & IEEE80211_CONF_MONITOR) { 1629 ath_print(common, ATH_DBG_CONFIG, 1630 "HW opmode set to Monitor mode\n"); 1631 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; 1632 } 1633 } 1634 1635 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 1636 struct ieee80211_channel *curchan = hw->conf.channel; 1637 int pos = curchan->hw_value; 1638 1639 aphy->chan_idx = pos; 1640 aphy->chan_is_ht = conf_is_ht(conf); 1641 1642 if (aphy->state == ATH_WIPHY_SCAN || 1643 aphy->state == ATH_WIPHY_ACTIVE) 1644 ath9k_wiphy_pause_all_forced(sc, aphy); 1645 else { 1646 /* 1647 * Do not change operational channel based on a paused 1648 * wiphy changes. 1649 */ 1650 goto skip_chan_change; 1651 } 1652 1653 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 1654 curchan->center_freq); 1655 1656 /* XXX: remove me eventualy */ 1657 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); 1658 1659 ath_update_chainmask(sc, conf_is_ht(conf)); 1660 1661 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1662 ath_print(common, ATH_DBG_FATAL, 1663 "Unable to set channel\n"); 1664 mutex_unlock(&sc->mutex); 1665 return -EINVAL; 1666 } 1667 } 1668 1669 skip_chan_change: 1670 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1671 sc->config.txpowlimit = 2 * conf->power_level; 1672 ath_update_txpow(sc); 1673 } 1674 1675 spin_lock_bh(&sc->wiphy_lock); 1676 disable_radio = ath9k_all_wiphys_idle(sc); 1677 spin_unlock_bh(&sc->wiphy_lock); 1678 1679 if (disable_radio) { 1680 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); 1681 sc->ps_idle = true; 1682 ath_radio_disable(sc, hw); 1683 } 1684 1685 mutex_unlock(&sc->mutex); 1686 1687 return 0; 1688 } 1689 1690 #define SUPPORTED_FILTERS \ 1691 (FIF_PROMISC_IN_BSS | \ 1692 FIF_ALLMULTI | \ 1693 FIF_CONTROL | \ 1694 FIF_PSPOLL | \ 1695 FIF_OTHER_BSS | \ 1696 FIF_BCN_PRBRESP_PROMISC | \ 1697 FIF_FCSFAIL) 1698 1699 /* FIXME: sc->sc_full_reset ? */ 1700 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1701 unsigned int changed_flags, 1702 unsigned int *total_flags, 1703 u64 multicast) 1704 { 1705 struct ath_wiphy *aphy = hw->priv; 1706 struct ath_softc *sc = aphy->sc; 1707 u32 rfilt; 1708 1709 changed_flags &= SUPPORTED_FILTERS; 1710 *total_flags &= SUPPORTED_FILTERS; 1711 1712 sc->rx.rxfilter = *total_flags; 1713 ath9k_ps_wakeup(sc); 1714 rfilt = ath_calcrxfilter(sc); 1715 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1716 ath9k_ps_restore(sc); 1717 1718 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, 1719 "Set HW RX filter: 0x%x\n", rfilt); 1720 } 1721 1722 static int ath9k_sta_add(struct ieee80211_hw *hw, 1723 struct ieee80211_vif *vif, 1724 struct ieee80211_sta *sta) 1725 { 1726 struct ath_wiphy *aphy = hw->priv; 1727 struct ath_softc *sc = aphy->sc; 1728 1729 ath_node_attach(sc, sta); 1730 1731 return 0; 1732 } 1733 1734 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1735 struct ieee80211_vif *vif, 1736 struct ieee80211_sta *sta) 1737 { 1738 struct ath_wiphy *aphy = hw->priv; 1739 struct ath_softc *sc = aphy->sc; 1740 1741 ath_node_detach(sc, sta); 1742 1743 return 0; 1744 } 1745 1746 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, 1747 const struct ieee80211_tx_queue_params *params) 1748 { 1749 struct ath_wiphy *aphy = hw->priv; 1750 struct ath_softc *sc = aphy->sc; 1751 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1752 struct ath9k_tx_queue_info qi; 1753 int ret = 0, qnum; 1754 1755 if (queue >= WME_NUM_AC) 1756 return 0; 1757 1758 mutex_lock(&sc->mutex); 1759 1760 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1761 1762 qi.tqi_aifs = params->aifs; 1763 qi.tqi_cwmin = params->cw_min; 1764 qi.tqi_cwmax = params->cw_max; 1765 qi.tqi_burstTime = params->txop; 1766 qnum = ath_get_hal_qnum(queue, sc); 1767 1768 ath_print(common, ATH_DBG_CONFIG, 1769 "Configure tx [queue/halq] [%d/%d], " 1770 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1771 queue, qnum, params->aifs, params->cw_min, 1772 params->cw_max, params->txop); 1773 1774 ret = ath_txq_update(sc, qnum, &qi); 1775 if (ret) 1776 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); 1777 1778 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) 1779 if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret) 1780 ath_beaconq_config(sc); 1781 1782 mutex_unlock(&sc->mutex); 1783 1784 return ret; 1785 } 1786 1787 static int ath9k_set_key(struct ieee80211_hw *hw, 1788 enum set_key_cmd cmd, 1789 struct ieee80211_vif *vif, 1790 struct ieee80211_sta *sta, 1791 struct ieee80211_key_conf *key) 1792 { 1793 struct ath_wiphy *aphy = hw->priv; 1794 struct ath_softc *sc = aphy->sc; 1795 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1796 int ret = 0; 1797 1798 if (modparam_nohwcrypt) 1799 return -ENOSPC; 1800 1801 mutex_lock(&sc->mutex); 1802 ath9k_ps_wakeup(sc); 1803 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); 1804 1805 switch (cmd) { 1806 case SET_KEY: 1807 ret = ath_key_config(common, vif, sta, key); 1808 if (ret >= 0) { 1809 key->hw_key_idx = ret; 1810 /* push IV and Michael MIC generation to stack */ 1811 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1812 if (key->alg == ALG_TKIP) 1813 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1814 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) 1815 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; 1816 ret = 0; 1817 } 1818 break; 1819 case DISABLE_KEY: 1820 ath_key_delete(common, key); 1821 break; 1822 default: 1823 ret = -EINVAL; 1824 } 1825 1826 ath9k_ps_restore(sc); 1827 mutex_unlock(&sc->mutex); 1828 1829 return ret; 1830 } 1831 1832 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1833 struct ieee80211_vif *vif, 1834 struct ieee80211_bss_conf *bss_conf, 1835 u32 changed) 1836 { 1837 struct ath_wiphy *aphy = hw->priv; 1838 struct ath_softc *sc = aphy->sc; 1839 struct ath_hw *ah = sc->sc_ah; 1840 struct ath_common *common = ath9k_hw_common(ah); 1841 struct ath_vif *avp = (void *)vif->drv_priv; 1842 int slottime; 1843 int error; 1844 1845 mutex_lock(&sc->mutex); 1846 1847 if (changed & BSS_CHANGED_BSSID) { 1848 /* Set BSSID */ 1849 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1850 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); 1851 common->curaid = 0; 1852 ath9k_hw_write_associd(ah); 1853 1854 /* Set aggregation protection mode parameters */ 1855 sc->config.ath_aggr_prot = 0; 1856 1857 /* Only legacy IBSS for now */ 1858 if (vif->type == NL80211_IFTYPE_ADHOC) 1859 ath_update_chainmask(sc, 0); 1860 1861 ath_print(common, ATH_DBG_CONFIG, 1862 "BSSID: %pM aid: 0x%x\n", 1863 common->curbssid, common->curaid); 1864 1865 /* need to reconfigure the beacon */ 1866 sc->sc_flags &= ~SC_OP_BEACONS ; 1867 } 1868 1869 /* Enable transmission of beacons (AP, IBSS, MESH) */ 1870 if ((changed & BSS_CHANGED_BEACON) || 1871 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { 1872 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1873 error = ath_beacon_alloc(aphy, vif); 1874 if (!error) 1875 ath_beacon_config(sc, vif); 1876 } 1877 1878 if (changed & BSS_CHANGED_ERP_SLOT) { 1879 if (bss_conf->use_short_slot) 1880 slottime = 9; 1881 else 1882 slottime = 20; 1883 if (vif->type == NL80211_IFTYPE_AP) { 1884 /* 1885 * Defer update, so that connected stations can adjust 1886 * their settings at the same time. 1887 * See beacon.c for more details 1888 */ 1889 sc->beacon.slottime = slottime; 1890 sc->beacon.updateslot = UPDATE; 1891 } else { 1892 ah->slottime = slottime; 1893 ath9k_hw_init_global_settings(ah); 1894 } 1895 } 1896 1897 /* Disable transmission of beacons */ 1898 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) 1899 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1900 1901 if (changed & BSS_CHANGED_BEACON_INT) { 1902 sc->beacon_interval = bss_conf->beacon_int; 1903 /* 1904 * In case of AP mode, the HW TSF has to be reset 1905 * when the beacon interval changes. 1906 */ 1907 if (vif->type == NL80211_IFTYPE_AP) { 1908 sc->sc_flags |= SC_OP_TSF_RESET; 1909 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1910 error = ath_beacon_alloc(aphy, vif); 1911 if (!error) 1912 ath_beacon_config(sc, vif); 1913 } else { 1914 ath_beacon_config(sc, vif); 1915 } 1916 } 1917 1918 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 1919 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 1920 bss_conf->use_short_preamble); 1921 if (bss_conf->use_short_preamble) 1922 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 1923 else 1924 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; 1925 } 1926 1927 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 1928 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 1929 bss_conf->use_cts_prot); 1930 if (bss_conf->use_cts_prot && 1931 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 1932 sc->sc_flags |= SC_OP_PROTECT_ENABLE; 1933 else 1934 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; 1935 } 1936 1937 if (changed & BSS_CHANGED_ASSOC) { 1938 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 1939 bss_conf->assoc); 1940 ath9k_bss_assoc_info(sc, vif, bss_conf); 1941 } 1942 1943 mutex_unlock(&sc->mutex); 1944 } 1945 1946 static u64 ath9k_get_tsf(struct ieee80211_hw *hw) 1947 { 1948 u64 tsf; 1949 struct ath_wiphy *aphy = hw->priv; 1950 struct ath_softc *sc = aphy->sc; 1951 1952 mutex_lock(&sc->mutex); 1953 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1954 mutex_unlock(&sc->mutex); 1955 1956 return tsf; 1957 } 1958 1959 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 1960 { 1961 struct ath_wiphy *aphy = hw->priv; 1962 struct ath_softc *sc = aphy->sc; 1963 1964 mutex_lock(&sc->mutex); 1965 ath9k_hw_settsf64(sc->sc_ah, tsf); 1966 mutex_unlock(&sc->mutex); 1967 } 1968 1969 static void ath9k_reset_tsf(struct ieee80211_hw *hw) 1970 { 1971 struct ath_wiphy *aphy = hw->priv; 1972 struct ath_softc *sc = aphy->sc; 1973 1974 mutex_lock(&sc->mutex); 1975 1976 ath9k_ps_wakeup(sc); 1977 ath9k_hw_reset_tsf(sc->sc_ah); 1978 ath9k_ps_restore(sc); 1979 1980 mutex_unlock(&sc->mutex); 1981 } 1982 1983 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1984 struct ieee80211_vif *vif, 1985 enum ieee80211_ampdu_mlme_action action, 1986 struct ieee80211_sta *sta, 1987 u16 tid, u16 *ssn) 1988 { 1989 struct ath_wiphy *aphy = hw->priv; 1990 struct ath_softc *sc = aphy->sc; 1991 int ret = 0; 1992 1993 switch (action) { 1994 case IEEE80211_AMPDU_RX_START: 1995 if (!(sc->sc_flags & SC_OP_RXAGGR)) 1996 ret = -ENOTSUPP; 1997 break; 1998 case IEEE80211_AMPDU_RX_STOP: 1999 break; 2000 case IEEE80211_AMPDU_TX_START: 2001 ath9k_ps_wakeup(sc); 2002 ath_tx_aggr_start(sc, sta, tid, ssn); 2003 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2004 ath9k_ps_restore(sc); 2005 break; 2006 case IEEE80211_AMPDU_TX_STOP: 2007 ath9k_ps_wakeup(sc); 2008 ath_tx_aggr_stop(sc, sta, tid); 2009 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2010 ath9k_ps_restore(sc); 2011 break; 2012 case IEEE80211_AMPDU_TX_OPERATIONAL: 2013 ath9k_ps_wakeup(sc); 2014 ath_tx_aggr_resume(sc, sta, tid); 2015 ath9k_ps_restore(sc); 2016 break; 2017 default: 2018 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, 2019 "Unknown AMPDU action\n"); 2020 } 2021 2022 return ret; 2023 } 2024 2025 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 2026 struct survey_info *survey) 2027 { 2028 struct ath_wiphy *aphy = hw->priv; 2029 struct ath_softc *sc = aphy->sc; 2030 struct ath_hw *ah = sc->sc_ah; 2031 struct ath_common *common = ath9k_hw_common(ah); 2032 struct ieee80211_conf *conf = &hw->conf; 2033 2034 if (idx != 0) 2035 return -ENOENT; 2036 2037 survey->channel = conf->channel; 2038 survey->filled = SURVEY_INFO_NOISE_DBM; 2039 survey->noise = common->ani.noise_floor; 2040 2041 return 0; 2042 } 2043 2044 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2045 { 2046 struct ath_wiphy *aphy = hw->priv; 2047 struct ath_softc *sc = aphy->sc; 2048 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2049 2050 mutex_lock(&sc->mutex); 2051 if (ath9k_wiphy_scanning(sc)) { 2052 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " 2053 "same time\n"); 2054 /* 2055 * Do not allow the concurrent scanning state for now. This 2056 * could be improved with scanning control moved into ath9k. 2057 */ 2058 mutex_unlock(&sc->mutex); 2059 return; 2060 } 2061 2062 aphy->state = ATH_WIPHY_SCAN; 2063 ath9k_wiphy_pause_all_forced(sc, aphy); 2064 sc->sc_flags |= SC_OP_SCANNING; 2065 del_timer_sync(&common->ani.timer); 2066 cancel_delayed_work_sync(&sc->tx_complete_work); 2067 mutex_unlock(&sc->mutex); 2068 } 2069 2070 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2071 { 2072 struct ath_wiphy *aphy = hw->priv; 2073 struct ath_softc *sc = aphy->sc; 2074 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2075 2076 mutex_lock(&sc->mutex); 2077 aphy->state = ATH_WIPHY_ACTIVE; 2078 sc->sc_flags &= ~SC_OP_SCANNING; 2079 sc->sc_flags |= SC_OP_FULL_RESET; 2080 ath_start_ani(common); 2081 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 2082 ath_beacon_config(sc, NULL); 2083 mutex_unlock(&sc->mutex); 2084 } 2085 2086 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 2087 { 2088 struct ath_wiphy *aphy = hw->priv; 2089 struct ath_softc *sc = aphy->sc; 2090 struct ath_hw *ah = sc->sc_ah; 2091 2092 mutex_lock(&sc->mutex); 2093 ah->coverage_class = coverage_class; 2094 ath9k_hw_init_global_settings(ah); 2095 mutex_unlock(&sc->mutex); 2096 } 2097 2098 struct ieee80211_ops ath9k_ops = { 2099 .tx = ath9k_tx, 2100 .start = ath9k_start, 2101 .stop = ath9k_stop, 2102 .add_interface = ath9k_add_interface, 2103 .remove_interface = ath9k_remove_interface, 2104 .config = ath9k_config, 2105 .configure_filter = ath9k_configure_filter, 2106 .sta_add = ath9k_sta_add, 2107 .sta_remove = ath9k_sta_remove, 2108 .conf_tx = ath9k_conf_tx, 2109 .bss_info_changed = ath9k_bss_info_changed, 2110 .set_key = ath9k_set_key, 2111 .get_tsf = ath9k_get_tsf, 2112 .set_tsf = ath9k_set_tsf, 2113 .reset_tsf = ath9k_reset_tsf, 2114 .ampdu_action = ath9k_ampdu_action, 2115 .get_survey = ath9k_get_survey, 2116 .sw_scan_start = ath9k_sw_scan_start, 2117 .sw_scan_complete = ath9k_sw_scan_complete, 2118 .rfkill_poll = ath9k_rfkill_poll_state, 2119 .set_coverage_class = ath9k_set_coverage_class, 2120 }; 2121