1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_set_assoc_state(struct ath_softc *sc, 23 struct ieee80211_vif *vif); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 61 { 62 bool pending = false; 63 64 spin_lock_bh(&txq->axq_lock); 65 66 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 67 pending = true; 68 69 spin_unlock_bh(&txq->axq_lock); 70 return pending; 71 } 72 73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 74 { 75 unsigned long flags; 76 bool ret; 77 78 spin_lock_irqsave(&sc->sc_pm_lock, flags); 79 ret = ath9k_hw_setpower(sc->sc_ah, mode); 80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 81 82 return ret; 83 } 84 85 void ath9k_ps_wakeup(struct ath_softc *sc) 86 { 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 88 unsigned long flags; 89 enum ath9k_power_mode power_mode; 90 91 spin_lock_irqsave(&sc->sc_pm_lock, flags); 92 if (++sc->ps_usecount != 1) 93 goto unlock; 94 95 power_mode = sc->sc_ah->power_mode; 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 97 98 /* 99 * While the hardware is asleep, the cycle counters contain no 100 * useful data. Better clear them now so that they don't mess up 101 * survey data results. 102 */ 103 if (power_mode != ATH9K_PM_AWAKE) { 104 spin_lock(&common->cc_lock); 105 ath_hw_cycle_counters_update(common); 106 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 108 spin_unlock(&common->cc_lock); 109 } 110 111 unlock: 112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 113 } 114 115 void ath9k_ps_restore(struct ath_softc *sc) 116 { 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 118 enum ath9k_power_mode mode; 119 unsigned long flags; 120 bool reset; 121 122 spin_lock_irqsave(&sc->sc_pm_lock, flags); 123 if (--sc->ps_usecount != 0) 124 goto unlock; 125 126 if (sc->ps_idle) { 127 ath9k_hw_setrxabort(sc->sc_ah, 1); 128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 129 mode = ATH9K_PM_FULL_SLEEP; 130 } else if (sc->ps_enabled && 131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 132 PS_WAIT_FOR_CAB | 133 PS_WAIT_FOR_PSPOLL_DATA | 134 PS_WAIT_FOR_TX_ACK | 135 PS_WAIT_FOR_ANI))) { 136 mode = ATH9K_PM_NETWORK_SLEEP; 137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 138 ath9k_btcoex_stop_gen_timer(sc); 139 } else { 140 goto unlock; 141 } 142 143 spin_lock(&common->cc_lock); 144 ath_hw_cycle_counters_update(common); 145 spin_unlock(&common->cc_lock); 146 147 ath9k_hw_setpower(sc->sc_ah, mode); 148 149 unlock: 150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 151 } 152 153 static void __ath_cancel_work(struct ath_softc *sc) 154 { 155 cancel_work_sync(&sc->paprd_work); 156 cancel_work_sync(&sc->hw_check_work); 157 cancel_delayed_work_sync(&sc->tx_complete_work); 158 cancel_delayed_work_sync(&sc->hw_pll_work); 159 160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 161 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 162 cancel_work_sync(&sc->mci_work); 163 #endif 164 } 165 166 static void ath_cancel_work(struct ath_softc *sc) 167 { 168 __ath_cancel_work(sc); 169 cancel_work_sync(&sc->hw_reset_work); 170 } 171 172 static void ath_restart_work(struct ath_softc *sc) 173 { 174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 175 176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || 177 AR_SREV_9550(sc->sc_ah)) 178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 180 181 ath_start_rx_poll(sc, 3); 182 ath_start_ani(sc); 183 } 184 185 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) 186 { 187 struct ath_hw *ah = sc->sc_ah; 188 bool ret = true; 189 190 ieee80211_stop_queues(sc->hw); 191 192 sc->hw_busy_count = 0; 193 ath_stop_ani(sc); 194 del_timer_sync(&sc->rx_poll_timer); 195 196 ath9k_debug_samp_bb_mac(sc); 197 ath9k_hw_disable_interrupts(ah); 198 199 if (!ath_stoprecv(sc)) 200 ret = false; 201 202 if (!ath_drain_all_txq(sc, retry_tx)) 203 ret = false; 204 205 if (!flush) { 206 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 207 ath_rx_tasklet(sc, 1, true); 208 ath_rx_tasklet(sc, 1, false); 209 } else { 210 ath_flushrecv(sc); 211 } 212 213 return ret; 214 } 215 216 static bool ath_complete_reset(struct ath_softc *sc, bool start) 217 { 218 struct ath_hw *ah = sc->sc_ah; 219 struct ath_common *common = ath9k_hw_common(ah); 220 unsigned long flags; 221 222 if (ath_startrecv(sc) != 0) { 223 ath_err(common, "Unable to restart recv logic\n"); 224 return false; 225 } 226 227 ath9k_cmn_update_txpow(ah, sc->curtxpow, 228 sc->config.txpowlimit, &sc->curtxpow); 229 230 clear_bit(SC_OP_HW_RESET, &sc->sc_flags); 231 ath9k_hw_set_interrupts(ah); 232 ath9k_hw_enable_interrupts(ah); 233 234 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { 235 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) 236 goto work; 237 238 ath9k_set_beacon(sc); 239 240 if (ah->opmode == NL80211_IFTYPE_STATION && 241 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 242 spin_lock_irqsave(&sc->sc_pm_lock, flags); 243 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 244 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 245 } 246 work: 247 ath_restart_work(sc); 248 } 249 250 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) 251 ath_ant_comb_update(sc); 252 253 ieee80211_wake_queues(sc->hw); 254 255 return true; 256 } 257 258 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, 259 bool retry_tx) 260 { 261 struct ath_hw *ah = sc->sc_ah; 262 struct ath_common *common = ath9k_hw_common(ah); 263 struct ath9k_hw_cal_data *caldata = NULL; 264 bool fastcc = true; 265 bool flush = false; 266 int r; 267 268 __ath_cancel_work(sc); 269 270 spin_lock_bh(&sc->sc_pcu_lock); 271 272 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { 273 fastcc = false; 274 caldata = &sc->caldata; 275 } 276 277 if (!hchan) { 278 fastcc = false; 279 flush = true; 280 hchan = ah->curchan; 281 } 282 283 if (!ath_prepare_reset(sc, retry_tx, flush)) 284 fastcc = false; 285 286 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 287 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 288 289 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 290 if (r) { 291 ath_err(common, 292 "Unable to reset channel, reset status %d\n", r); 293 goto out; 294 } 295 296 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 297 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 298 ath9k_mci_set_txpower(sc, true, false); 299 300 if (!ath_complete_reset(sc, true)) 301 r = -EIO; 302 303 out: 304 spin_unlock_bh(&sc->sc_pcu_lock); 305 return r; 306 } 307 308 309 /* 310 * Set/change channels. If the channel is really being changed, it's done 311 * by reseting the chip. To accomplish this we must first cleanup any pending 312 * DMA, then restart stuff. 313 */ 314 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 315 struct ath9k_channel *hchan) 316 { 317 int r; 318 319 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 320 return -EIO; 321 322 r = ath_reset_internal(sc, hchan, false); 323 324 return r; 325 } 326 327 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 328 struct ieee80211_vif *vif) 329 { 330 struct ath_node *an; 331 u8 density; 332 an = (struct ath_node *)sta->drv_priv; 333 334 an->sc = sc; 335 an->sta = sta; 336 an->vif = vif; 337 338 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 339 ath_tx_node_init(sc, an); 340 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 341 sta->ht_cap.ampdu_factor); 342 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 343 an->mpdudensity = density; 344 } 345 } 346 347 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 348 { 349 struct ath_node *an = (struct ath_node *)sta->drv_priv; 350 351 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 352 ath_tx_node_cleanup(sc, an); 353 } 354 355 void ath9k_tasklet(unsigned long data) 356 { 357 struct ath_softc *sc = (struct ath_softc *)data; 358 struct ath_hw *ah = sc->sc_ah; 359 struct ath_common *common = ath9k_hw_common(ah); 360 enum ath_reset_type type; 361 unsigned long flags; 362 u32 status = sc->intrstatus; 363 u32 rxmask; 364 365 ath9k_ps_wakeup(sc); 366 spin_lock(&sc->sc_pcu_lock); 367 368 if ((status & ATH9K_INT_FATAL) || 369 (status & ATH9K_INT_BB_WATCHDOG)) { 370 371 if (status & ATH9K_INT_FATAL) 372 type = RESET_TYPE_FATAL_INT; 373 else 374 type = RESET_TYPE_BB_WATCHDOG; 375 376 ath9k_queue_reset(sc, type); 377 goto out; 378 } 379 380 spin_lock_irqsave(&sc->sc_pm_lock, flags); 381 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 382 /* 383 * TSF sync does not look correct; remain awake to sync with 384 * the next Beacon. 385 */ 386 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 387 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 388 } 389 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 390 391 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 392 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 393 ATH9K_INT_RXORN); 394 else 395 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 396 397 if (status & rxmask) { 398 /* Check for high priority Rx first */ 399 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 400 (status & ATH9K_INT_RXHP)) 401 ath_rx_tasklet(sc, 0, true); 402 403 ath_rx_tasklet(sc, 0, false); 404 } 405 406 if (status & ATH9K_INT_TX) { 407 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 408 ath_tx_edma_tasklet(sc); 409 else 410 ath_tx_tasklet(sc); 411 } 412 413 ath9k_btcoex_handle_interrupt(sc, status); 414 415 out: 416 /* re-enable hardware interrupt */ 417 ath9k_hw_enable_interrupts(ah); 418 419 spin_unlock(&sc->sc_pcu_lock); 420 ath9k_ps_restore(sc); 421 } 422 423 irqreturn_t ath_isr(int irq, void *dev) 424 { 425 #define SCHED_INTR ( \ 426 ATH9K_INT_FATAL | \ 427 ATH9K_INT_BB_WATCHDOG | \ 428 ATH9K_INT_RXORN | \ 429 ATH9K_INT_RXEOL | \ 430 ATH9K_INT_RX | \ 431 ATH9K_INT_RXLP | \ 432 ATH9K_INT_RXHP | \ 433 ATH9K_INT_TX | \ 434 ATH9K_INT_BMISS | \ 435 ATH9K_INT_CST | \ 436 ATH9K_INT_TSFOOR | \ 437 ATH9K_INT_GENTIMER | \ 438 ATH9K_INT_MCI) 439 440 struct ath_softc *sc = dev; 441 struct ath_hw *ah = sc->sc_ah; 442 struct ath_common *common = ath9k_hw_common(ah); 443 enum ath9k_int status; 444 bool sched = false; 445 446 /* 447 * The hardware is not ready/present, don't 448 * touch anything. Note this can happen early 449 * on if the IRQ is shared. 450 */ 451 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 452 return IRQ_NONE; 453 454 /* shared irq, not for us */ 455 456 if (!ath9k_hw_intrpend(ah)) 457 return IRQ_NONE; 458 459 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { 460 ath9k_hw_kill_interrupts(ah); 461 return IRQ_HANDLED; 462 } 463 464 /* 465 * Figure out the reason(s) for the interrupt. Note 466 * that the hal returns a pseudo-ISR that may include 467 * bits we haven't explicitly enabled so we mask the 468 * value to insure we only process bits we requested. 469 */ 470 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 471 status &= ah->imask; /* discard unasked-for bits */ 472 473 /* 474 * If there are no status bits set, then this interrupt was not 475 * for me (should have been caught above). 476 */ 477 if (!status) 478 return IRQ_NONE; 479 480 /* Cache the status */ 481 sc->intrstatus = status; 482 483 if (status & SCHED_INTR) 484 sched = true; 485 486 /* 487 * If a FATAL or RXORN interrupt is received, we have to reset the 488 * chip immediately. 489 */ 490 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 491 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 492 goto chip_reset; 493 494 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 495 (status & ATH9K_INT_BB_WATCHDOG)) { 496 497 spin_lock(&common->cc_lock); 498 ath_hw_cycle_counters_update(common); 499 ar9003_hw_bb_watchdog_dbg_info(ah); 500 spin_unlock(&common->cc_lock); 501 502 goto chip_reset; 503 } 504 #ifdef CONFIG_PM_SLEEP 505 if (status & ATH9K_INT_BMISS) { 506 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 507 ath_dbg(common, ANY, "during WoW we got a BMISS\n"); 508 atomic_inc(&sc->wow_got_bmiss_intr); 509 atomic_dec(&sc->wow_sleep_proc_intr); 510 } 511 } 512 #endif 513 if (status & ATH9K_INT_SWBA) 514 tasklet_schedule(&sc->bcon_tasklet); 515 516 if (status & ATH9K_INT_TXURN) 517 ath9k_hw_updatetxtriglevel(ah, true); 518 519 if (status & ATH9K_INT_RXEOL) { 520 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 521 ath9k_hw_set_interrupts(ah); 522 } 523 524 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 525 if (status & ATH9K_INT_TIM_TIMER) { 526 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 527 goto chip_reset; 528 /* Clear RxAbort bit so that we can 529 * receive frames */ 530 ath9k_setpower(sc, ATH9K_PM_AWAKE); 531 spin_lock(&sc->sc_pm_lock); 532 ath9k_hw_setrxabort(sc->sc_ah, 0); 533 sc->ps_flags |= PS_WAIT_FOR_BEACON; 534 spin_unlock(&sc->sc_pm_lock); 535 } 536 537 chip_reset: 538 539 ath_debug_stat_interrupt(sc, status); 540 541 if (sched) { 542 /* turn off every interrupt */ 543 ath9k_hw_disable_interrupts(ah); 544 tasklet_schedule(&sc->intr_tq); 545 } 546 547 return IRQ_HANDLED; 548 549 #undef SCHED_INTR 550 } 551 552 static int ath_reset(struct ath_softc *sc, bool retry_tx) 553 { 554 int r; 555 556 ath9k_ps_wakeup(sc); 557 558 r = ath_reset_internal(sc, NULL, retry_tx); 559 560 if (retry_tx) { 561 int i; 562 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 563 if (ATH_TXQ_SETUP(sc, i)) { 564 spin_lock_bh(&sc->tx.txq[i].axq_lock); 565 ath_txq_schedule(sc, &sc->tx.txq[i]); 566 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 567 } 568 } 569 } 570 571 ath9k_ps_restore(sc); 572 573 return r; 574 } 575 576 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 577 { 578 #ifdef CONFIG_ATH9K_DEBUGFS 579 RESET_STAT_INC(sc, type); 580 #endif 581 set_bit(SC_OP_HW_RESET, &sc->sc_flags); 582 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 583 } 584 585 void ath_reset_work(struct work_struct *work) 586 { 587 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 588 589 ath_reset(sc, true); 590 } 591 592 /**********************/ 593 /* mac80211 callbacks */ 594 /**********************/ 595 596 static int ath9k_start(struct ieee80211_hw *hw) 597 { 598 struct ath_softc *sc = hw->priv; 599 struct ath_hw *ah = sc->sc_ah; 600 struct ath_common *common = ath9k_hw_common(ah); 601 struct ieee80211_channel *curchan = hw->conf.channel; 602 struct ath9k_channel *init_channel; 603 int r; 604 605 ath_dbg(common, CONFIG, 606 "Starting driver with initial channel: %d MHz\n", 607 curchan->center_freq); 608 609 ath9k_ps_wakeup(sc); 610 mutex_lock(&sc->mutex); 611 612 init_channel = ath9k_cmn_get_curchannel(hw, ah); 613 614 /* Reset SERDES registers */ 615 ath9k_hw_configpcipowersave(ah, false); 616 617 /* 618 * The basic interface to setting the hardware in a good 619 * state is ``reset''. On return the hardware is known to 620 * be powered up and with interrupts disabled. This must 621 * be followed by initialization of the appropriate bits 622 * and then setup of the interrupt mask. 623 */ 624 spin_lock_bh(&sc->sc_pcu_lock); 625 626 atomic_set(&ah->intr_ref_cnt, -1); 627 628 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 629 if (r) { 630 ath_err(common, 631 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 632 r, curchan->center_freq); 633 ah->reset_power_on = false; 634 } 635 636 /* Setup our intr mask. */ 637 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 638 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 639 ATH9K_INT_GLOBAL; 640 641 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 642 ah->imask |= ATH9K_INT_RXHP | 643 ATH9K_INT_RXLP | 644 ATH9K_INT_BB_WATCHDOG; 645 else 646 ah->imask |= ATH9K_INT_RX; 647 648 ah->imask |= ATH9K_INT_GTT; 649 650 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 651 ah->imask |= ATH9K_INT_CST; 652 653 ath_mci_enable(sc); 654 655 clear_bit(SC_OP_INVALID, &sc->sc_flags); 656 sc->sc_ah->is_monitoring = false; 657 658 if (!ath_complete_reset(sc, false)) 659 ah->reset_power_on = false; 660 661 if (ah->led_pin >= 0) { 662 ath9k_hw_cfg_output(ah, ah->led_pin, 663 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 664 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 665 } 666 667 /* 668 * Reset key cache to sane defaults (all entries cleared) instead of 669 * semi-random values after suspend/resume. 670 */ 671 ath9k_cmn_init_crypto(sc->sc_ah); 672 673 spin_unlock_bh(&sc->sc_pcu_lock); 674 675 mutex_unlock(&sc->mutex); 676 677 ath9k_ps_restore(sc); 678 679 return 0; 680 } 681 682 static void ath9k_tx(struct ieee80211_hw *hw, 683 struct ieee80211_tx_control *control, 684 struct sk_buff *skb) 685 { 686 struct ath_softc *sc = hw->priv; 687 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 688 struct ath_tx_control txctl; 689 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 690 unsigned long flags; 691 692 if (sc->ps_enabled) { 693 /* 694 * mac80211 does not set PM field for normal data frames, so we 695 * need to update that based on the current PS mode. 696 */ 697 if (ieee80211_is_data(hdr->frame_control) && 698 !ieee80211_is_nullfunc(hdr->frame_control) && 699 !ieee80211_has_pm(hdr->frame_control)) { 700 ath_dbg(common, PS, 701 "Add PM=1 for a TX frame while in PS mode\n"); 702 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 703 } 704 } 705 706 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 707 /* 708 * We are using PS-Poll and mac80211 can request TX while in 709 * power save mode. Need to wake up hardware for the TX to be 710 * completed and if needed, also for RX of buffered frames. 711 */ 712 ath9k_ps_wakeup(sc); 713 spin_lock_irqsave(&sc->sc_pm_lock, flags); 714 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 715 ath9k_hw_setrxabort(sc->sc_ah, 0); 716 if (ieee80211_is_pspoll(hdr->frame_control)) { 717 ath_dbg(common, PS, 718 "Sending PS-Poll to pick a buffered frame\n"); 719 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 720 } else { 721 ath_dbg(common, PS, "Wake up to complete TX\n"); 722 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 723 } 724 /* 725 * The actual restore operation will happen only after 726 * the ps_flags bit is cleared. We are just dropping 727 * the ps_usecount here. 728 */ 729 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 730 ath9k_ps_restore(sc); 731 } 732 733 /* 734 * Cannot tx while the hardware is in full sleep, it first needs a full 735 * chip reset to recover from that 736 */ 737 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 738 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 739 goto exit; 740 } 741 742 memset(&txctl, 0, sizeof(struct ath_tx_control)); 743 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 744 txctl.sta = control->sta; 745 746 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 747 748 if (ath_tx_start(hw, skb, &txctl) != 0) { 749 ath_dbg(common, XMIT, "TX failed\n"); 750 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 751 goto exit; 752 } 753 754 return; 755 exit: 756 ieee80211_free_txskb(hw, skb); 757 } 758 759 static void ath9k_stop(struct ieee80211_hw *hw) 760 { 761 struct ath_softc *sc = hw->priv; 762 struct ath_hw *ah = sc->sc_ah; 763 struct ath_common *common = ath9k_hw_common(ah); 764 bool prev_idle; 765 766 mutex_lock(&sc->mutex); 767 768 ath_cancel_work(sc); 769 del_timer_sync(&sc->rx_poll_timer); 770 771 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 772 ath_dbg(common, ANY, "Device not present\n"); 773 mutex_unlock(&sc->mutex); 774 return; 775 } 776 777 /* Ensure HW is awake when we try to shut it down. */ 778 ath9k_ps_wakeup(sc); 779 780 spin_lock_bh(&sc->sc_pcu_lock); 781 782 /* prevent tasklets to enable interrupts once we disable them */ 783 ah->imask &= ~ATH9K_INT_GLOBAL; 784 785 /* make sure h/w will not generate any interrupt 786 * before setting the invalid flag. */ 787 ath9k_hw_disable_interrupts(ah); 788 789 spin_unlock_bh(&sc->sc_pcu_lock); 790 791 /* we can now sync irq and kill any running tasklets, since we already 792 * disabled interrupts and not holding a spin lock */ 793 synchronize_irq(sc->irq); 794 tasklet_kill(&sc->intr_tq); 795 tasklet_kill(&sc->bcon_tasklet); 796 797 prev_idle = sc->ps_idle; 798 sc->ps_idle = true; 799 800 spin_lock_bh(&sc->sc_pcu_lock); 801 802 if (ah->led_pin >= 0) { 803 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 804 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 805 } 806 807 ath_prepare_reset(sc, false, true); 808 809 if (sc->rx.frag) { 810 dev_kfree_skb_any(sc->rx.frag); 811 sc->rx.frag = NULL; 812 } 813 814 if (!ah->curchan) 815 ah->curchan = ath9k_cmn_get_curchannel(hw, ah); 816 817 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 818 ath9k_hw_phy_disable(ah); 819 820 ath9k_hw_configpcipowersave(ah, true); 821 822 spin_unlock_bh(&sc->sc_pcu_lock); 823 824 ath9k_ps_restore(sc); 825 826 set_bit(SC_OP_INVALID, &sc->sc_flags); 827 sc->ps_idle = prev_idle; 828 829 mutex_unlock(&sc->mutex); 830 831 ath_dbg(common, CONFIG, "Driver halt\n"); 832 } 833 834 bool ath9k_uses_beacons(int type) 835 { 836 switch (type) { 837 case NL80211_IFTYPE_AP: 838 case NL80211_IFTYPE_ADHOC: 839 case NL80211_IFTYPE_MESH_POINT: 840 return true; 841 default: 842 return false; 843 } 844 } 845 846 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 847 { 848 struct ath9k_vif_iter_data *iter_data = data; 849 int i; 850 851 if (iter_data->hw_macaddr) 852 for (i = 0; i < ETH_ALEN; i++) 853 iter_data->mask[i] &= 854 ~(iter_data->hw_macaddr[i] ^ mac[i]); 855 856 switch (vif->type) { 857 case NL80211_IFTYPE_AP: 858 iter_data->naps++; 859 break; 860 case NL80211_IFTYPE_STATION: 861 iter_data->nstations++; 862 break; 863 case NL80211_IFTYPE_ADHOC: 864 iter_data->nadhocs++; 865 break; 866 case NL80211_IFTYPE_MESH_POINT: 867 iter_data->nmeshes++; 868 break; 869 case NL80211_IFTYPE_WDS: 870 iter_data->nwds++; 871 break; 872 default: 873 break; 874 } 875 } 876 877 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 878 { 879 struct ath_softc *sc = data; 880 struct ath_vif *avp = (void *)vif->drv_priv; 881 882 if (vif->type != NL80211_IFTYPE_STATION) 883 return; 884 885 if (avp->primary_sta_vif) 886 ath9k_set_assoc_state(sc, vif); 887 } 888 889 /* Called with sc->mutex held. */ 890 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 891 struct ieee80211_vif *vif, 892 struct ath9k_vif_iter_data *iter_data) 893 { 894 struct ath_softc *sc = hw->priv; 895 struct ath_hw *ah = sc->sc_ah; 896 struct ath_common *common = ath9k_hw_common(ah); 897 898 /* 899 * Use the hardware MAC address as reference, the hardware uses it 900 * together with the BSSID mask when matching addresses. 901 */ 902 memset(iter_data, 0, sizeof(*iter_data)); 903 iter_data->hw_macaddr = common->macaddr; 904 memset(&iter_data->mask, 0xff, ETH_ALEN); 905 906 if (vif) 907 ath9k_vif_iter(iter_data, vif->addr, vif); 908 909 /* Get list of all active MAC addresses */ 910 ieee80211_iterate_active_interfaces_atomic( 911 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 912 ath9k_vif_iter, iter_data); 913 } 914 915 /* Called with sc->mutex held. */ 916 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 917 struct ieee80211_vif *vif) 918 { 919 struct ath_softc *sc = hw->priv; 920 struct ath_hw *ah = sc->sc_ah; 921 struct ath_common *common = ath9k_hw_common(ah); 922 struct ath9k_vif_iter_data iter_data; 923 enum nl80211_iftype old_opmode = ah->opmode; 924 925 ath9k_calculate_iter_data(hw, vif, &iter_data); 926 927 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 928 ath_hw_setbssidmask(common); 929 930 if (iter_data.naps > 0) { 931 ath9k_hw_set_tsfadjust(ah, true); 932 ah->opmode = NL80211_IFTYPE_AP; 933 } else { 934 ath9k_hw_set_tsfadjust(ah, false); 935 936 if (iter_data.nmeshes) 937 ah->opmode = NL80211_IFTYPE_MESH_POINT; 938 else if (iter_data.nwds) 939 ah->opmode = NL80211_IFTYPE_AP; 940 else if (iter_data.nadhocs) 941 ah->opmode = NL80211_IFTYPE_ADHOC; 942 else 943 ah->opmode = NL80211_IFTYPE_STATION; 944 } 945 946 ath9k_hw_setopmode(ah); 947 948 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 949 ah->imask |= ATH9K_INT_TSFOOR; 950 else 951 ah->imask &= ~ATH9K_INT_TSFOOR; 952 953 ath9k_hw_set_interrupts(ah); 954 955 /* 956 * If we are changing the opmode to STATION, 957 * a beacon sync needs to be done. 958 */ 959 if (ah->opmode == NL80211_IFTYPE_STATION && 960 old_opmode == NL80211_IFTYPE_AP && 961 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 962 ieee80211_iterate_active_interfaces_atomic( 963 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 964 ath9k_sta_vif_iter, sc); 965 } 966 } 967 968 static int ath9k_add_interface(struct ieee80211_hw *hw, 969 struct ieee80211_vif *vif) 970 { 971 struct ath_softc *sc = hw->priv; 972 struct ath_hw *ah = sc->sc_ah; 973 struct ath_common *common = ath9k_hw_common(ah); 974 975 mutex_lock(&sc->mutex); 976 977 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 978 sc->nvifs++; 979 980 ath9k_ps_wakeup(sc); 981 ath9k_calculate_summary_state(hw, vif); 982 ath9k_ps_restore(sc); 983 984 if (ath9k_uses_beacons(vif->type)) 985 ath9k_beacon_assign_slot(sc, vif); 986 987 mutex_unlock(&sc->mutex); 988 return 0; 989 } 990 991 static int ath9k_change_interface(struct ieee80211_hw *hw, 992 struct ieee80211_vif *vif, 993 enum nl80211_iftype new_type, 994 bool p2p) 995 { 996 struct ath_softc *sc = hw->priv; 997 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 998 999 ath_dbg(common, CONFIG, "Change Interface\n"); 1000 mutex_lock(&sc->mutex); 1001 1002 if (ath9k_uses_beacons(vif->type)) 1003 ath9k_beacon_remove_slot(sc, vif); 1004 1005 vif->type = new_type; 1006 vif->p2p = p2p; 1007 1008 ath9k_ps_wakeup(sc); 1009 ath9k_calculate_summary_state(hw, vif); 1010 ath9k_ps_restore(sc); 1011 1012 if (ath9k_uses_beacons(vif->type)) 1013 ath9k_beacon_assign_slot(sc, vif); 1014 1015 mutex_unlock(&sc->mutex); 1016 return 0; 1017 } 1018 1019 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1020 struct ieee80211_vif *vif) 1021 { 1022 struct ath_softc *sc = hw->priv; 1023 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1024 1025 ath_dbg(common, CONFIG, "Detach Interface\n"); 1026 1027 mutex_lock(&sc->mutex); 1028 1029 sc->nvifs--; 1030 1031 if (ath9k_uses_beacons(vif->type)) 1032 ath9k_beacon_remove_slot(sc, vif); 1033 1034 ath9k_ps_wakeup(sc); 1035 ath9k_calculate_summary_state(hw, NULL); 1036 ath9k_ps_restore(sc); 1037 1038 mutex_unlock(&sc->mutex); 1039 } 1040 1041 static void ath9k_enable_ps(struct ath_softc *sc) 1042 { 1043 struct ath_hw *ah = sc->sc_ah; 1044 struct ath_common *common = ath9k_hw_common(ah); 1045 1046 sc->ps_enabled = true; 1047 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1048 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1049 ah->imask |= ATH9K_INT_TIM_TIMER; 1050 ath9k_hw_set_interrupts(ah); 1051 } 1052 ath9k_hw_setrxabort(ah, 1); 1053 } 1054 ath_dbg(common, PS, "PowerSave enabled\n"); 1055 } 1056 1057 static void ath9k_disable_ps(struct ath_softc *sc) 1058 { 1059 struct ath_hw *ah = sc->sc_ah; 1060 struct ath_common *common = ath9k_hw_common(ah); 1061 1062 sc->ps_enabled = false; 1063 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1064 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1065 ath9k_hw_setrxabort(ah, 0); 1066 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1067 PS_WAIT_FOR_CAB | 1068 PS_WAIT_FOR_PSPOLL_DATA | 1069 PS_WAIT_FOR_TX_ACK); 1070 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1071 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1072 ath9k_hw_set_interrupts(ah); 1073 } 1074 } 1075 ath_dbg(common, PS, "PowerSave disabled\n"); 1076 } 1077 1078 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1079 { 1080 struct ath_softc *sc = hw->priv; 1081 struct ath_hw *ah = sc->sc_ah; 1082 struct ath_common *common = ath9k_hw_common(ah); 1083 struct ieee80211_conf *conf = &hw->conf; 1084 bool reset_channel = false; 1085 1086 ath9k_ps_wakeup(sc); 1087 mutex_lock(&sc->mutex); 1088 1089 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1090 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1091 if (sc->ps_idle) { 1092 ath_cancel_work(sc); 1093 ath9k_stop_btcoex(sc); 1094 } else { 1095 ath9k_start_btcoex(sc); 1096 /* 1097 * The chip needs a reset to properly wake up from 1098 * full sleep 1099 */ 1100 reset_channel = ah->chip_fullsleep; 1101 } 1102 } 1103 1104 /* 1105 * We just prepare to enable PS. We have to wait until our AP has 1106 * ACK'd our null data frame to disable RX otherwise we'll ignore 1107 * those ACKs and end up retransmitting the same null data frames. 1108 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1109 */ 1110 if (changed & IEEE80211_CONF_CHANGE_PS) { 1111 unsigned long flags; 1112 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1113 if (conf->flags & IEEE80211_CONF_PS) 1114 ath9k_enable_ps(sc); 1115 else 1116 ath9k_disable_ps(sc); 1117 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1118 } 1119 1120 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1121 if (conf->flags & IEEE80211_CONF_MONITOR) { 1122 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1123 sc->sc_ah->is_monitoring = true; 1124 } else { 1125 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1126 sc->sc_ah->is_monitoring = false; 1127 } 1128 } 1129 1130 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1131 struct ieee80211_channel *curchan = hw->conf.channel; 1132 int pos = curchan->hw_value; 1133 int old_pos = -1; 1134 unsigned long flags; 1135 1136 if (ah->curchan) 1137 old_pos = ah->curchan - &ah->channels[0]; 1138 1139 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", 1140 curchan->center_freq, conf->channel_type); 1141 1142 /* update survey stats for the old channel before switching */ 1143 spin_lock_irqsave(&common->cc_lock, flags); 1144 ath_update_survey_stats(sc); 1145 spin_unlock_irqrestore(&common->cc_lock, flags); 1146 1147 /* 1148 * Preserve the current channel values, before updating 1149 * the same channel 1150 */ 1151 if (ah->curchan && (old_pos == pos)) 1152 ath9k_hw_getnf(ah, ah->curchan); 1153 1154 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], 1155 curchan, conf->channel_type); 1156 1157 /* 1158 * If the operating channel changes, change the survey in-use flags 1159 * along with it. 1160 * Reset the survey data for the new channel, unless we're switching 1161 * back to the operating channel from an off-channel operation. 1162 */ 1163 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && 1164 sc->cur_survey != &sc->survey[pos]) { 1165 1166 if (sc->cur_survey) 1167 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 1168 1169 sc->cur_survey = &sc->survey[pos]; 1170 1171 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 1172 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 1173 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 1174 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 1175 } 1176 1177 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1178 ath_err(common, "Unable to set channel\n"); 1179 mutex_unlock(&sc->mutex); 1180 ath9k_ps_restore(sc); 1181 return -EINVAL; 1182 } 1183 1184 /* 1185 * The most recent snapshot of channel->noisefloor for the old 1186 * channel is only available after the hardware reset. Copy it to 1187 * the survey stats now. 1188 */ 1189 if (old_pos >= 0) 1190 ath_update_survey_nf(sc, old_pos); 1191 } 1192 1193 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1194 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1195 sc->config.txpowlimit = 2 * conf->power_level; 1196 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1197 sc->config.txpowlimit, &sc->curtxpow); 1198 } 1199 1200 mutex_unlock(&sc->mutex); 1201 ath9k_ps_restore(sc); 1202 1203 return 0; 1204 } 1205 1206 #define SUPPORTED_FILTERS \ 1207 (FIF_PROMISC_IN_BSS | \ 1208 FIF_ALLMULTI | \ 1209 FIF_CONTROL | \ 1210 FIF_PSPOLL | \ 1211 FIF_OTHER_BSS | \ 1212 FIF_BCN_PRBRESP_PROMISC | \ 1213 FIF_PROBE_REQ | \ 1214 FIF_FCSFAIL) 1215 1216 /* FIXME: sc->sc_full_reset ? */ 1217 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1218 unsigned int changed_flags, 1219 unsigned int *total_flags, 1220 u64 multicast) 1221 { 1222 struct ath_softc *sc = hw->priv; 1223 u32 rfilt; 1224 1225 changed_flags &= SUPPORTED_FILTERS; 1226 *total_flags &= SUPPORTED_FILTERS; 1227 1228 sc->rx.rxfilter = *total_flags; 1229 ath9k_ps_wakeup(sc); 1230 rfilt = ath_calcrxfilter(sc); 1231 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1232 ath9k_ps_restore(sc); 1233 1234 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1235 rfilt); 1236 } 1237 1238 static int ath9k_sta_add(struct ieee80211_hw *hw, 1239 struct ieee80211_vif *vif, 1240 struct ieee80211_sta *sta) 1241 { 1242 struct ath_softc *sc = hw->priv; 1243 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1244 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1245 struct ieee80211_key_conf ps_key = { }; 1246 1247 ath_node_attach(sc, sta, vif); 1248 1249 if (vif->type != NL80211_IFTYPE_AP && 1250 vif->type != NL80211_IFTYPE_AP_VLAN) 1251 return 0; 1252 1253 an->ps_key = ath_key_config(common, vif, sta, &ps_key); 1254 1255 return 0; 1256 } 1257 1258 static void ath9k_del_ps_key(struct ath_softc *sc, 1259 struct ieee80211_vif *vif, 1260 struct ieee80211_sta *sta) 1261 { 1262 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1263 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1264 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1265 1266 if (!an->ps_key) 1267 return; 1268 1269 ath_key_delete(common, &ps_key); 1270 } 1271 1272 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1273 struct ieee80211_vif *vif, 1274 struct ieee80211_sta *sta) 1275 { 1276 struct ath_softc *sc = hw->priv; 1277 1278 ath9k_del_ps_key(sc, vif, sta); 1279 ath_node_detach(sc, sta); 1280 1281 return 0; 1282 } 1283 1284 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1285 struct ieee80211_vif *vif, 1286 enum sta_notify_cmd cmd, 1287 struct ieee80211_sta *sta) 1288 { 1289 struct ath_softc *sc = hw->priv; 1290 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1291 1292 if (!sta->ht_cap.ht_supported) 1293 return; 1294 1295 switch (cmd) { 1296 case STA_NOTIFY_SLEEP: 1297 an->sleeping = true; 1298 ath_tx_aggr_sleep(sta, sc, an); 1299 break; 1300 case STA_NOTIFY_AWAKE: 1301 an->sleeping = false; 1302 ath_tx_aggr_wakeup(sc, an); 1303 break; 1304 } 1305 } 1306 1307 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1308 struct ieee80211_vif *vif, u16 queue, 1309 const struct ieee80211_tx_queue_params *params) 1310 { 1311 struct ath_softc *sc = hw->priv; 1312 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1313 struct ath_txq *txq; 1314 struct ath9k_tx_queue_info qi; 1315 int ret = 0; 1316 1317 if (queue >= IEEE80211_NUM_ACS) 1318 return 0; 1319 1320 txq = sc->tx.txq_map[queue]; 1321 1322 ath9k_ps_wakeup(sc); 1323 mutex_lock(&sc->mutex); 1324 1325 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1326 1327 qi.tqi_aifs = params->aifs; 1328 qi.tqi_cwmin = params->cw_min; 1329 qi.tqi_cwmax = params->cw_max; 1330 qi.tqi_burstTime = params->txop * 32; 1331 1332 ath_dbg(common, CONFIG, 1333 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1334 queue, txq->axq_qnum, params->aifs, params->cw_min, 1335 params->cw_max, params->txop); 1336 1337 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1338 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1339 if (ret) 1340 ath_err(common, "TXQ Update failed\n"); 1341 1342 mutex_unlock(&sc->mutex); 1343 ath9k_ps_restore(sc); 1344 1345 return ret; 1346 } 1347 1348 static int ath9k_set_key(struct ieee80211_hw *hw, 1349 enum set_key_cmd cmd, 1350 struct ieee80211_vif *vif, 1351 struct ieee80211_sta *sta, 1352 struct ieee80211_key_conf *key) 1353 { 1354 struct ath_softc *sc = hw->priv; 1355 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1356 int ret = 0; 1357 1358 if (ath9k_modparam_nohwcrypt) 1359 return -ENOSPC; 1360 1361 if ((vif->type == NL80211_IFTYPE_ADHOC || 1362 vif->type == NL80211_IFTYPE_MESH_POINT) && 1363 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1364 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1365 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1366 /* 1367 * For now, disable hw crypto for the RSN IBSS group keys. This 1368 * could be optimized in the future to use a modified key cache 1369 * design to support per-STA RX GTK, but until that gets 1370 * implemented, use of software crypto for group addressed 1371 * frames is a acceptable to allow RSN IBSS to be used. 1372 */ 1373 return -EOPNOTSUPP; 1374 } 1375 1376 mutex_lock(&sc->mutex); 1377 ath9k_ps_wakeup(sc); 1378 ath_dbg(common, CONFIG, "Set HW Key\n"); 1379 1380 switch (cmd) { 1381 case SET_KEY: 1382 if (sta) 1383 ath9k_del_ps_key(sc, vif, sta); 1384 1385 ret = ath_key_config(common, vif, sta, key); 1386 if (ret >= 0) { 1387 key->hw_key_idx = ret; 1388 /* push IV and Michael MIC generation to stack */ 1389 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1390 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1391 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1392 if (sc->sc_ah->sw_mgmt_crypto && 1393 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1394 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1395 ret = 0; 1396 } 1397 break; 1398 case DISABLE_KEY: 1399 ath_key_delete(common, key); 1400 break; 1401 default: 1402 ret = -EINVAL; 1403 } 1404 1405 ath9k_ps_restore(sc); 1406 mutex_unlock(&sc->mutex); 1407 1408 return ret; 1409 } 1410 1411 static void ath9k_set_assoc_state(struct ath_softc *sc, 1412 struct ieee80211_vif *vif) 1413 { 1414 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1415 struct ath_vif *avp = (void *)vif->drv_priv; 1416 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1417 unsigned long flags; 1418 1419 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1420 avp->primary_sta_vif = true; 1421 1422 /* 1423 * Set the AID, BSSID and do beacon-sync only when 1424 * the HW opmode is STATION. 1425 * 1426 * But the primary bit is set above in any case. 1427 */ 1428 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1429 return; 1430 1431 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1432 common->curaid = bss_conf->aid; 1433 ath9k_hw_write_associd(sc->sc_ah); 1434 1435 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1436 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1437 1438 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1439 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1440 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1441 1442 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1443 ath9k_mci_update_wlan_channels(sc, false); 1444 1445 ath_dbg(common, CONFIG, 1446 "Primary Station interface: %pM, BSSID: %pM\n", 1447 vif->addr, common->curbssid); 1448 } 1449 1450 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1451 { 1452 struct ath_softc *sc = data; 1453 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1454 1455 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) 1456 return; 1457 1458 if (bss_conf->assoc) 1459 ath9k_set_assoc_state(sc, vif); 1460 } 1461 1462 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1463 struct ieee80211_vif *vif, 1464 struct ieee80211_bss_conf *bss_conf, 1465 u32 changed) 1466 { 1467 #define CHECK_ANI \ 1468 (BSS_CHANGED_ASSOC | \ 1469 BSS_CHANGED_IBSS | \ 1470 BSS_CHANGED_BEACON_ENABLED) 1471 1472 struct ath_softc *sc = hw->priv; 1473 struct ath_hw *ah = sc->sc_ah; 1474 struct ath_common *common = ath9k_hw_common(ah); 1475 struct ath_vif *avp = (void *)vif->drv_priv; 1476 int slottime; 1477 1478 ath9k_ps_wakeup(sc); 1479 mutex_lock(&sc->mutex); 1480 1481 if (changed & BSS_CHANGED_ASSOC) { 1482 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1483 bss_conf->bssid, bss_conf->assoc); 1484 1485 if (avp->primary_sta_vif && !bss_conf->assoc) { 1486 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1487 avp->primary_sta_vif = false; 1488 1489 if (ah->opmode == NL80211_IFTYPE_STATION) 1490 clear_bit(SC_OP_BEACONS, &sc->sc_flags); 1491 } 1492 1493 ieee80211_iterate_active_interfaces_atomic( 1494 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1495 ath9k_bss_assoc_iter, sc); 1496 1497 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && 1498 ah->opmode == NL80211_IFTYPE_STATION) { 1499 memset(common->curbssid, 0, ETH_ALEN); 1500 common->curaid = 0; 1501 ath9k_hw_write_associd(sc->sc_ah); 1502 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1503 ath9k_mci_update_wlan_channels(sc, true); 1504 } 1505 } 1506 1507 if (changed & BSS_CHANGED_IBSS) { 1508 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1509 common->curaid = bss_conf->aid; 1510 ath9k_hw_write_associd(sc->sc_ah); 1511 } 1512 1513 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1514 (changed & BSS_CHANGED_BEACON_INT)) { 1515 if (ah->opmode == NL80211_IFTYPE_AP && 1516 bss_conf->enable_beacon) 1517 ath9k_set_tsfadjust(sc, vif); 1518 if (ath9k_allow_beacon_config(sc, vif)) 1519 ath9k_beacon_config(sc, vif, changed); 1520 } 1521 1522 if (changed & BSS_CHANGED_ERP_SLOT) { 1523 if (bss_conf->use_short_slot) 1524 slottime = 9; 1525 else 1526 slottime = 20; 1527 if (vif->type == NL80211_IFTYPE_AP) { 1528 /* 1529 * Defer update, so that connected stations can adjust 1530 * their settings at the same time. 1531 * See beacon.c for more details 1532 */ 1533 sc->beacon.slottime = slottime; 1534 sc->beacon.updateslot = UPDATE; 1535 } else { 1536 ah->slottime = slottime; 1537 ath9k_hw_init_global_settings(ah); 1538 } 1539 } 1540 1541 if (changed & CHECK_ANI) 1542 ath_check_ani(sc); 1543 1544 mutex_unlock(&sc->mutex); 1545 ath9k_ps_restore(sc); 1546 1547 #undef CHECK_ANI 1548 } 1549 1550 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1551 { 1552 struct ath_softc *sc = hw->priv; 1553 u64 tsf; 1554 1555 mutex_lock(&sc->mutex); 1556 ath9k_ps_wakeup(sc); 1557 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1558 ath9k_ps_restore(sc); 1559 mutex_unlock(&sc->mutex); 1560 1561 return tsf; 1562 } 1563 1564 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1565 struct ieee80211_vif *vif, 1566 u64 tsf) 1567 { 1568 struct ath_softc *sc = hw->priv; 1569 1570 mutex_lock(&sc->mutex); 1571 ath9k_ps_wakeup(sc); 1572 ath9k_hw_settsf64(sc->sc_ah, tsf); 1573 ath9k_ps_restore(sc); 1574 mutex_unlock(&sc->mutex); 1575 } 1576 1577 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1578 { 1579 struct ath_softc *sc = hw->priv; 1580 1581 mutex_lock(&sc->mutex); 1582 1583 ath9k_ps_wakeup(sc); 1584 ath9k_hw_reset_tsf(sc->sc_ah); 1585 ath9k_ps_restore(sc); 1586 1587 mutex_unlock(&sc->mutex); 1588 } 1589 1590 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1591 struct ieee80211_vif *vif, 1592 enum ieee80211_ampdu_mlme_action action, 1593 struct ieee80211_sta *sta, 1594 u16 tid, u16 *ssn, u8 buf_size) 1595 { 1596 struct ath_softc *sc = hw->priv; 1597 int ret = 0; 1598 1599 local_bh_disable(); 1600 1601 switch (action) { 1602 case IEEE80211_AMPDU_RX_START: 1603 break; 1604 case IEEE80211_AMPDU_RX_STOP: 1605 break; 1606 case IEEE80211_AMPDU_TX_START: 1607 ath9k_ps_wakeup(sc); 1608 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1609 if (!ret) 1610 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1611 ath9k_ps_restore(sc); 1612 break; 1613 case IEEE80211_AMPDU_TX_STOP: 1614 ath9k_ps_wakeup(sc); 1615 ath_tx_aggr_stop(sc, sta, tid); 1616 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1617 ath9k_ps_restore(sc); 1618 break; 1619 case IEEE80211_AMPDU_TX_OPERATIONAL: 1620 ath9k_ps_wakeup(sc); 1621 ath_tx_aggr_resume(sc, sta, tid); 1622 ath9k_ps_restore(sc); 1623 break; 1624 default: 1625 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1626 } 1627 1628 local_bh_enable(); 1629 1630 return ret; 1631 } 1632 1633 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1634 struct survey_info *survey) 1635 { 1636 struct ath_softc *sc = hw->priv; 1637 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1638 struct ieee80211_supported_band *sband; 1639 struct ieee80211_channel *chan; 1640 unsigned long flags; 1641 int pos; 1642 1643 spin_lock_irqsave(&common->cc_lock, flags); 1644 if (idx == 0) 1645 ath_update_survey_stats(sc); 1646 1647 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1648 if (sband && idx >= sband->n_channels) { 1649 idx -= sband->n_channels; 1650 sband = NULL; 1651 } 1652 1653 if (!sband) 1654 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1655 1656 if (!sband || idx >= sband->n_channels) { 1657 spin_unlock_irqrestore(&common->cc_lock, flags); 1658 return -ENOENT; 1659 } 1660 1661 chan = &sband->channels[idx]; 1662 pos = chan->hw_value; 1663 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1664 survey->channel = chan; 1665 spin_unlock_irqrestore(&common->cc_lock, flags); 1666 1667 return 0; 1668 } 1669 1670 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1671 { 1672 struct ath_softc *sc = hw->priv; 1673 struct ath_hw *ah = sc->sc_ah; 1674 1675 mutex_lock(&sc->mutex); 1676 ah->coverage_class = coverage_class; 1677 1678 ath9k_ps_wakeup(sc); 1679 ath9k_hw_init_global_settings(ah); 1680 ath9k_ps_restore(sc); 1681 1682 mutex_unlock(&sc->mutex); 1683 } 1684 1685 static void ath9k_flush(struct ieee80211_hw *hw, bool drop) 1686 { 1687 struct ath_softc *sc = hw->priv; 1688 struct ath_hw *ah = sc->sc_ah; 1689 struct ath_common *common = ath9k_hw_common(ah); 1690 int timeout = 200; /* ms */ 1691 int i, j; 1692 bool drain_txq; 1693 1694 mutex_lock(&sc->mutex); 1695 cancel_delayed_work_sync(&sc->tx_complete_work); 1696 1697 if (ah->ah_flags & AH_UNPLUGGED) { 1698 ath_dbg(common, ANY, "Device has been unplugged!\n"); 1699 mutex_unlock(&sc->mutex); 1700 return; 1701 } 1702 1703 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 1704 ath_dbg(common, ANY, "Device not present\n"); 1705 mutex_unlock(&sc->mutex); 1706 return; 1707 } 1708 1709 for (j = 0; j < timeout; j++) { 1710 bool npend = false; 1711 1712 if (j) 1713 usleep_range(1000, 2000); 1714 1715 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1716 if (!ATH_TXQ_SETUP(sc, i)) 1717 continue; 1718 1719 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1720 1721 if (npend) 1722 break; 1723 } 1724 1725 if (!npend) 1726 break; 1727 } 1728 1729 if (drop) { 1730 ath9k_ps_wakeup(sc); 1731 spin_lock_bh(&sc->sc_pcu_lock); 1732 drain_txq = ath_drain_all_txq(sc, false); 1733 spin_unlock_bh(&sc->sc_pcu_lock); 1734 1735 if (!drain_txq) 1736 ath_reset(sc, false); 1737 1738 ath9k_ps_restore(sc); 1739 ieee80211_wake_queues(hw); 1740 } 1741 1742 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 1743 mutex_unlock(&sc->mutex); 1744 } 1745 1746 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 1747 { 1748 struct ath_softc *sc = hw->priv; 1749 int i; 1750 1751 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1752 if (!ATH_TXQ_SETUP(sc, i)) 1753 continue; 1754 1755 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 1756 return true; 1757 } 1758 return false; 1759 } 1760 1761 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 1762 { 1763 struct ath_softc *sc = hw->priv; 1764 struct ath_hw *ah = sc->sc_ah; 1765 struct ieee80211_vif *vif; 1766 struct ath_vif *avp; 1767 struct ath_buf *bf; 1768 struct ath_tx_status ts; 1769 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1770 int status; 1771 1772 vif = sc->beacon.bslot[0]; 1773 if (!vif) 1774 return 0; 1775 1776 if (!vif->bss_conf.enable_beacon) 1777 return 0; 1778 1779 avp = (void *)vif->drv_priv; 1780 1781 if (!sc->beacon.tx_processed && !edma) { 1782 tasklet_disable(&sc->bcon_tasklet); 1783 1784 bf = avp->av_bcbuf; 1785 if (!bf || !bf->bf_mpdu) 1786 goto skip; 1787 1788 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 1789 if (status == -EINPROGRESS) 1790 goto skip; 1791 1792 sc->beacon.tx_processed = true; 1793 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 1794 1795 skip: 1796 tasklet_enable(&sc->bcon_tasklet); 1797 } 1798 1799 return sc->beacon.tx_last; 1800 } 1801 1802 static int ath9k_get_stats(struct ieee80211_hw *hw, 1803 struct ieee80211_low_level_stats *stats) 1804 { 1805 struct ath_softc *sc = hw->priv; 1806 struct ath_hw *ah = sc->sc_ah; 1807 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 1808 1809 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 1810 stats->dot11RTSFailureCount = mib_stats->rts_bad; 1811 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 1812 stats->dot11RTSSuccessCount = mib_stats->rts_good; 1813 return 0; 1814 } 1815 1816 static u32 fill_chainmask(u32 cap, u32 new) 1817 { 1818 u32 filled = 0; 1819 int i; 1820 1821 for (i = 0; cap && new; i++, cap >>= 1) { 1822 if (!(cap & BIT(0))) 1823 continue; 1824 1825 if (new & BIT(0)) 1826 filled |= BIT(i); 1827 1828 new >>= 1; 1829 } 1830 1831 return filled; 1832 } 1833 1834 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 1835 { 1836 switch (val & 0x7) { 1837 case 0x1: 1838 case 0x3: 1839 case 0x7: 1840 return true; 1841 case 0x2: 1842 return (ah->caps.rx_chainmask == 1); 1843 default: 1844 return false; 1845 } 1846 } 1847 1848 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 1849 { 1850 struct ath_softc *sc = hw->priv; 1851 struct ath_hw *ah = sc->sc_ah; 1852 1853 if (ah->caps.rx_chainmask != 1) 1854 rx_ant |= tx_ant; 1855 1856 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 1857 return -EINVAL; 1858 1859 sc->ant_rx = rx_ant; 1860 sc->ant_tx = tx_ant; 1861 1862 if (ah->caps.rx_chainmask == 1) 1863 return 0; 1864 1865 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 1866 if (AR_SREV_9100(ah)) 1867 ah->rxchainmask = 0x7; 1868 else 1869 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 1870 1871 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 1872 ath9k_reload_chainmask_settings(sc); 1873 1874 return 0; 1875 } 1876 1877 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 1878 { 1879 struct ath_softc *sc = hw->priv; 1880 1881 *tx_ant = sc->ant_tx; 1882 *rx_ant = sc->ant_rx; 1883 return 0; 1884 } 1885 1886 #ifdef CONFIG_PM_SLEEP 1887 1888 static void ath9k_wow_map_triggers(struct ath_softc *sc, 1889 struct cfg80211_wowlan *wowlan, 1890 u32 *wow_triggers) 1891 { 1892 if (wowlan->disconnect) 1893 *wow_triggers |= AH_WOW_LINK_CHANGE | 1894 AH_WOW_BEACON_MISS; 1895 if (wowlan->magic_pkt) 1896 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; 1897 1898 if (wowlan->n_patterns) 1899 *wow_triggers |= AH_WOW_USER_PATTERN_EN; 1900 1901 sc->wow_enabled = *wow_triggers; 1902 1903 } 1904 1905 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) 1906 { 1907 struct ath_hw *ah = sc->sc_ah; 1908 struct ath_common *common = ath9k_hw_common(ah); 1909 struct ath9k_hw_capabilities *pcaps = &ah->caps; 1910 int pattern_count = 0; 1911 int i, byte_cnt; 1912 u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; 1913 u8 dis_deauth_mask[MAX_PATTERN_SIZE]; 1914 1915 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); 1916 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); 1917 1918 /* 1919 * Create Dissassociate / Deauthenticate packet filter 1920 * 1921 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes 1922 * +--------------+----------+---------+--------+--------+---- 1923 * + Frame Control+ Duration + DA + SA + BSSID + 1924 * +--------------+----------+---------+--------+--------+---- 1925 * 1926 * The above is the management frame format for disassociate/ 1927 * deauthenticate pattern, from this we need to match the first byte 1928 * of 'Frame Control' and DA, SA, and BSSID fields 1929 * (skipping 2nd byte of FC and Duration feild. 1930 * 1931 * Disassociate pattern 1932 * -------------------- 1933 * Frame control = 00 00 1010 1934 * DA, SA, BSSID = x:x:x:x:x:x 1935 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x 1936 * | x:x:x:x:x:x -- 22 bytes 1937 * 1938 * Deauthenticate pattern 1939 * ---------------------- 1940 * Frame control = 00 00 1100 1941 * DA, SA, BSSID = x:x:x:x:x:x 1942 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x 1943 * | x:x:x:x:x:x -- 22 bytes 1944 */ 1945 1946 /* Create Disassociate Pattern first */ 1947 1948 byte_cnt = 0; 1949 1950 /* Fill out the mask with all FF's */ 1951 1952 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) 1953 dis_deauth_mask[i] = 0xff; 1954 1955 /* copy the first byte of frame control field */ 1956 dis_deauth_pattern[byte_cnt] = 0xa0; 1957 byte_cnt++; 1958 1959 /* skip 2nd byte of frame control and Duration field */ 1960 byte_cnt += 3; 1961 1962 /* 1963 * need not match the destination mac address, it can be a broadcast 1964 * mac address or an unicast to this station 1965 */ 1966 byte_cnt += 6; 1967 1968 /* copy the source mac address */ 1969 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 1970 1971 byte_cnt += 6; 1972 1973 /* copy the bssid, its same as the source mac address */ 1974 1975 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); 1976 1977 /* Create Disassociate pattern mask */ 1978 1979 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { 1980 1981 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { 1982 /* 1983 * for AR9280, because of hardware limitation, the 1984 * first 4 bytes have to be matched for all patterns. 1985 * the mask for disassociation and de-auth pattern 1986 * matching need to enable the first 4 bytes. 1987 * also the duration field needs to be filled. 1988 */ 1989 dis_deauth_mask[0] = 0xf0; 1990 1991 /* 1992 * fill in duration field 1993 FIXME: what is the exact value ? 1994 */ 1995 dis_deauth_pattern[2] = 0xff; 1996 dis_deauth_pattern[3] = 0xff; 1997 } else { 1998 dis_deauth_mask[0] = 0xfe; 1999 } 2000 2001 dis_deauth_mask[1] = 0x03; 2002 dis_deauth_mask[2] = 0xc0; 2003 } else { 2004 dis_deauth_mask[0] = 0xef; 2005 dis_deauth_mask[1] = 0x3f; 2006 dis_deauth_mask[2] = 0x00; 2007 dis_deauth_mask[3] = 0xfc; 2008 } 2009 2010 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); 2011 2012 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2013 pattern_count, byte_cnt); 2014 2015 pattern_count++; 2016 /* 2017 * for de-authenticate pattern, only the first byte of the frame 2018 * control field gets changed from 0xA0 to 0xC0 2019 */ 2020 dis_deauth_pattern[0] = 0xC0; 2021 2022 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, 2023 pattern_count, byte_cnt); 2024 2025 } 2026 2027 static void ath9k_wow_add_pattern(struct ath_softc *sc, 2028 struct cfg80211_wowlan *wowlan) 2029 { 2030 struct ath_hw *ah = sc->sc_ah; 2031 struct ath9k_wow_pattern *wow_pattern = NULL; 2032 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; 2033 int mask_len; 2034 s8 i = 0; 2035 2036 if (!wowlan->n_patterns) 2037 return; 2038 2039 /* 2040 * Add the new user configured patterns 2041 */ 2042 for (i = 0; i < wowlan->n_patterns; i++) { 2043 2044 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); 2045 2046 if (!wow_pattern) 2047 return; 2048 2049 /* 2050 * TODO: convert the generic user space pattern to 2051 * appropriate chip specific/802.11 pattern. 2052 */ 2053 2054 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); 2055 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); 2056 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); 2057 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, 2058 patterns[i].pattern_len); 2059 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); 2060 wow_pattern->pattern_len = patterns[i].pattern_len; 2061 2062 /* 2063 * just need to take care of deauth and disssoc pattern, 2064 * make sure we don't overwrite them. 2065 */ 2066 2067 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, 2068 wow_pattern->mask_bytes, 2069 i + 2, 2070 wow_pattern->pattern_len); 2071 kfree(wow_pattern); 2072 2073 } 2074 2075 } 2076 2077 static int ath9k_suspend(struct ieee80211_hw *hw, 2078 struct cfg80211_wowlan *wowlan) 2079 { 2080 struct ath_softc *sc = hw->priv; 2081 struct ath_hw *ah = sc->sc_ah; 2082 struct ath_common *common = ath9k_hw_common(ah); 2083 u32 wow_triggers_enabled = 0; 2084 int ret = 0; 2085 2086 mutex_lock(&sc->mutex); 2087 2088 ath_cancel_work(sc); 2089 ath_stop_ani(sc); 2090 del_timer_sync(&sc->rx_poll_timer); 2091 2092 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 2093 ath_dbg(common, ANY, "Device not present\n"); 2094 ret = -EINVAL; 2095 goto fail_wow; 2096 } 2097 2098 if (WARN_ON(!wowlan)) { 2099 ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); 2100 ret = -EINVAL; 2101 goto fail_wow; 2102 } 2103 2104 if (!device_can_wakeup(sc->dev)) { 2105 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); 2106 ret = 1; 2107 goto fail_wow; 2108 } 2109 2110 /* 2111 * none of the sta vifs are associated 2112 * and we are not currently handling multivif 2113 * cases, for instance we have to seperately 2114 * configure 'keep alive frame' for each 2115 * STA. 2116 */ 2117 2118 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 2119 ath_dbg(common, WOW, "None of the STA vifs are associated\n"); 2120 ret = 1; 2121 goto fail_wow; 2122 } 2123 2124 if (sc->nvifs > 1) { 2125 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); 2126 ret = 1; 2127 goto fail_wow; 2128 } 2129 2130 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); 2131 2132 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", 2133 wow_triggers_enabled); 2134 2135 ath9k_ps_wakeup(sc); 2136 2137 ath9k_stop_btcoex(sc); 2138 2139 /* 2140 * Enable wake up on recieving disassoc/deauth 2141 * frame by default. 2142 */ 2143 ath9k_wow_add_disassoc_deauth_pattern(sc); 2144 2145 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) 2146 ath9k_wow_add_pattern(sc, wowlan); 2147 2148 spin_lock_bh(&sc->sc_pcu_lock); 2149 /* 2150 * To avoid false wake, we enable beacon miss interrupt only 2151 * when we go to sleep. We save the current interrupt mask 2152 * so we can restore it after the system wakes up 2153 */ 2154 sc->wow_intr_before_sleep = ah->imask; 2155 ah->imask &= ~ATH9K_INT_GLOBAL; 2156 ath9k_hw_disable_interrupts(ah); 2157 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; 2158 ath9k_hw_set_interrupts(ah); 2159 ath9k_hw_enable_interrupts(ah); 2160 2161 spin_unlock_bh(&sc->sc_pcu_lock); 2162 2163 /* 2164 * we can now sync irq and kill any running tasklets, since we already 2165 * disabled interrupts and not holding a spin lock 2166 */ 2167 synchronize_irq(sc->irq); 2168 tasklet_kill(&sc->intr_tq); 2169 2170 ath9k_hw_wow_enable(ah, wow_triggers_enabled); 2171 2172 ath9k_ps_restore(sc); 2173 ath_dbg(common, ANY, "WoW enabled in ath9k\n"); 2174 atomic_inc(&sc->wow_sleep_proc_intr); 2175 2176 fail_wow: 2177 mutex_unlock(&sc->mutex); 2178 return ret; 2179 } 2180 2181 static int ath9k_resume(struct ieee80211_hw *hw) 2182 { 2183 struct ath_softc *sc = hw->priv; 2184 struct ath_hw *ah = sc->sc_ah; 2185 struct ath_common *common = ath9k_hw_common(ah); 2186 u32 wow_status; 2187 2188 mutex_lock(&sc->mutex); 2189 2190 ath9k_ps_wakeup(sc); 2191 2192 spin_lock_bh(&sc->sc_pcu_lock); 2193 2194 ath9k_hw_disable_interrupts(ah); 2195 ah->imask = sc->wow_intr_before_sleep; 2196 ath9k_hw_set_interrupts(ah); 2197 ath9k_hw_enable_interrupts(ah); 2198 2199 spin_unlock_bh(&sc->sc_pcu_lock); 2200 2201 wow_status = ath9k_hw_wow_wakeup(ah); 2202 2203 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { 2204 /* 2205 * some devices may not pick beacon miss 2206 * as the reason they woke up so we add 2207 * that here for that shortcoming. 2208 */ 2209 wow_status |= AH_WOW_BEACON_MISS; 2210 atomic_dec(&sc->wow_got_bmiss_intr); 2211 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); 2212 } 2213 2214 atomic_dec(&sc->wow_sleep_proc_intr); 2215 2216 if (wow_status) { 2217 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", 2218 ath9k_hw_wow_event_to_string(wow_status), wow_status); 2219 } 2220 2221 ath_restart_work(sc); 2222 ath9k_start_btcoex(sc); 2223 2224 ath9k_ps_restore(sc); 2225 mutex_unlock(&sc->mutex); 2226 2227 return 0; 2228 } 2229 2230 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) 2231 { 2232 struct ath_softc *sc = hw->priv; 2233 2234 mutex_lock(&sc->mutex); 2235 device_init_wakeup(sc->dev, 1); 2236 device_set_wakeup_enable(sc->dev, enabled); 2237 mutex_unlock(&sc->mutex); 2238 } 2239 2240 #endif 2241 2242 struct ieee80211_ops ath9k_ops = { 2243 .tx = ath9k_tx, 2244 .start = ath9k_start, 2245 .stop = ath9k_stop, 2246 .add_interface = ath9k_add_interface, 2247 .change_interface = ath9k_change_interface, 2248 .remove_interface = ath9k_remove_interface, 2249 .config = ath9k_config, 2250 .configure_filter = ath9k_configure_filter, 2251 .sta_add = ath9k_sta_add, 2252 .sta_remove = ath9k_sta_remove, 2253 .sta_notify = ath9k_sta_notify, 2254 .conf_tx = ath9k_conf_tx, 2255 .bss_info_changed = ath9k_bss_info_changed, 2256 .set_key = ath9k_set_key, 2257 .get_tsf = ath9k_get_tsf, 2258 .set_tsf = ath9k_set_tsf, 2259 .reset_tsf = ath9k_reset_tsf, 2260 .ampdu_action = ath9k_ampdu_action, 2261 .get_survey = ath9k_get_survey, 2262 .rfkill_poll = ath9k_rfkill_poll_state, 2263 .set_coverage_class = ath9k_set_coverage_class, 2264 .flush = ath9k_flush, 2265 .tx_frames_pending = ath9k_tx_frames_pending, 2266 .tx_last_beacon = ath9k_tx_last_beacon, 2267 .get_stats = ath9k_get_stats, 2268 .set_antenna = ath9k_set_antenna, 2269 .get_antenna = ath9k_get_antenna, 2270 2271 #ifdef CONFIG_PM_SLEEP 2272 .suspend = ath9k_suspend, 2273 .resume = ath9k_resume, 2274 .set_wakeup = ath9k_set_wakeup, 2275 #endif 2276 2277 #ifdef CONFIG_ATH9K_DEBUGFS 2278 .get_et_sset_count = ath9k_get_et_sset_count, 2279 .get_et_stats = ath9k_get_et_stats, 2280 .get_et_strings = ath9k_get_et_strings, 2281 #endif 2282 2283 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 2284 .sta_add_debugfs = ath9k_sta_add_debugfs, 2285 .sta_remove_debugfs = ath9k_sta_remove_debugfs, 2286 #endif 2287 }; 2288