1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 23 { 24 /* 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 26 * 0 for no restriction 27 * 1 for 1/4 us 28 * 2 for 1/2 us 29 * 3 for 1 us 30 * 4 for 2 us 31 * 5 for 4 us 32 * 6 for 8 us 33 * 7 for 16 us 34 */ 35 switch (mpdudensity) { 36 case 0: 37 return 0; 38 case 1: 39 case 2: 40 case 3: 41 /* Our lower layer calculations limit our precision to 42 1 microsecond */ 43 return 1; 44 case 4: 45 return 2; 46 case 5: 47 return 4; 48 case 6: 49 return 8; 50 case 7: 51 return 16; 52 default: 53 return 0; 54 } 55 } 56 57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq, 58 bool sw_pending) 59 { 60 bool pending = false; 61 62 spin_lock_bh(&txq->axq_lock); 63 64 if (txq->axq_depth) { 65 pending = true; 66 goto out; 67 } 68 69 if (!sw_pending) 70 goto out; 71 72 if (txq->mac80211_qnum >= 0) { 73 struct ath_acq *acq; 74 75 acq = &sc->cur_chan->acq[txq->mac80211_qnum]; 76 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old)) 77 pending = true; 78 } 79 out: 80 spin_unlock_bh(&txq->axq_lock); 81 return pending; 82 } 83 84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 85 { 86 unsigned long flags; 87 bool ret; 88 89 spin_lock_irqsave(&sc->sc_pm_lock, flags); 90 ret = ath9k_hw_setpower(sc->sc_ah, mode); 91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 92 93 return ret; 94 } 95 96 void ath_ps_full_sleep(struct timer_list *t) 97 { 98 struct ath_softc *sc = from_timer(sc, t, sleep_timer); 99 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 100 unsigned long flags; 101 bool reset; 102 103 spin_lock_irqsave(&common->cc_lock, flags); 104 ath_hw_cycle_counters_update(common); 105 spin_unlock_irqrestore(&common->cc_lock, flags); 106 107 ath9k_hw_setrxabort(sc->sc_ah, 1); 108 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 109 110 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 111 } 112 113 void ath9k_ps_wakeup(struct ath_softc *sc) 114 { 115 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 116 unsigned long flags; 117 enum ath9k_power_mode power_mode; 118 119 spin_lock_irqsave(&sc->sc_pm_lock, flags); 120 if (++sc->ps_usecount != 1) 121 goto unlock; 122 123 del_timer_sync(&sc->sleep_timer); 124 power_mode = sc->sc_ah->power_mode; 125 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 126 127 /* 128 * While the hardware is asleep, the cycle counters contain no 129 * useful data. Better clear them now so that they don't mess up 130 * survey data results. 131 */ 132 if (power_mode != ATH9K_PM_AWAKE) { 133 spin_lock(&common->cc_lock); 134 ath_hw_cycle_counters_update(common); 135 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 136 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 137 spin_unlock(&common->cc_lock); 138 } 139 140 unlock: 141 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 142 } 143 144 void ath9k_ps_restore(struct ath_softc *sc) 145 { 146 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 147 enum ath9k_power_mode mode; 148 unsigned long flags; 149 150 spin_lock_irqsave(&sc->sc_pm_lock, flags); 151 if (--sc->ps_usecount != 0) 152 goto unlock; 153 154 if (sc->ps_idle) { 155 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 156 goto unlock; 157 } 158 159 if (sc->ps_enabled && 160 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 161 PS_WAIT_FOR_CAB | 162 PS_WAIT_FOR_PSPOLL_DATA | 163 PS_WAIT_FOR_TX_ACK | 164 PS_WAIT_FOR_ANI))) { 165 mode = ATH9K_PM_NETWORK_SLEEP; 166 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 167 ath9k_btcoex_stop_gen_timer(sc); 168 } else { 169 goto unlock; 170 } 171 172 spin_lock(&common->cc_lock); 173 ath_hw_cycle_counters_update(common); 174 spin_unlock(&common->cc_lock); 175 176 ath9k_hw_setpower(sc->sc_ah, mode); 177 178 unlock: 179 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 180 } 181 182 static void __ath_cancel_work(struct ath_softc *sc) 183 { 184 cancel_work_sync(&sc->paprd_work); 185 cancel_delayed_work_sync(&sc->hw_check_work); 186 cancel_delayed_work_sync(&sc->hw_pll_work); 187 188 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 189 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 190 cancel_work_sync(&sc->mci_work); 191 #endif 192 } 193 194 void ath_cancel_work(struct ath_softc *sc) 195 { 196 __ath_cancel_work(sc); 197 cancel_work_sync(&sc->hw_reset_work); 198 } 199 200 void ath_restart_work(struct ath_softc *sc) 201 { 202 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work, 203 ATH_HW_CHECK_POLL_INT); 204 205 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 206 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 207 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 208 209 ath_start_ani(sc); 210 } 211 212 static bool ath_prepare_reset(struct ath_softc *sc) 213 { 214 struct ath_hw *ah = sc->sc_ah; 215 bool ret = true; 216 217 ieee80211_stop_queues(sc->hw); 218 ath_stop_ani(sc); 219 ath9k_hw_disable_interrupts(ah); 220 221 if (AR_SREV_9300_20_OR_LATER(ah)) { 222 ret &= ath_stoprecv(sc); 223 ret &= ath_drain_all_txq(sc); 224 } else { 225 ret &= ath_drain_all_txq(sc); 226 ret &= ath_stoprecv(sc); 227 } 228 229 return ret; 230 } 231 232 static bool ath_complete_reset(struct ath_softc *sc, bool start) 233 { 234 struct ath_hw *ah = sc->sc_ah; 235 struct ath_common *common = ath9k_hw_common(ah); 236 unsigned long flags; 237 238 ath9k_calculate_summary_state(sc, sc->cur_chan); 239 ath_startrecv(sc); 240 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, 241 sc->cur_chan->txpower, 242 &sc->cur_chan->cur_txpower); 243 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 244 245 if (!sc->cur_chan->offchannel && start) { 246 /* restore per chanctx TSF timer */ 247 if (sc->cur_chan->tsf_val) { 248 u32 offset; 249 250 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, 251 NULL); 252 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); 253 } 254 255 256 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 257 goto work; 258 259 if (ah->opmode == NL80211_IFTYPE_STATION && 260 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 261 spin_lock_irqsave(&sc->sc_pm_lock, flags); 262 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 263 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 264 } else { 265 ath9k_set_beacon(sc); 266 } 267 work: 268 ath_restart_work(sc); 269 ath_txq_schedule_all(sc); 270 } 271 272 sc->gtt_cnt = 0; 273 274 ath9k_hw_set_interrupts(ah); 275 ath9k_hw_enable_interrupts(ah); 276 ieee80211_wake_queues(sc->hw); 277 ath9k_p2p_ps_timer(sc); 278 279 return true; 280 } 281 282 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 283 { 284 struct ath_hw *ah = sc->sc_ah; 285 struct ath_common *common = ath9k_hw_common(ah); 286 struct ath9k_hw_cal_data *caldata = NULL; 287 bool fastcc = true; 288 int r; 289 290 __ath_cancel_work(sc); 291 292 disable_irq(sc->irq); 293 tasklet_disable(&sc->intr_tq); 294 tasklet_disable(&sc->bcon_tasklet); 295 spin_lock_bh(&sc->sc_pcu_lock); 296 297 if (!sc->cur_chan->offchannel) { 298 fastcc = false; 299 caldata = &sc->cur_chan->caldata; 300 } 301 302 if (!hchan) { 303 fastcc = false; 304 hchan = ah->curchan; 305 } 306 307 if (!ath_prepare_reset(sc)) 308 fastcc = false; 309 310 if (ath9k_is_chanctx_enabled()) 311 fastcc = false; 312 313 spin_lock_bh(&sc->chan_lock); 314 sc->cur_chandef = sc->cur_chan->chandef; 315 spin_unlock_bh(&sc->chan_lock); 316 317 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 318 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 319 320 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 321 if (r) { 322 ath_err(common, 323 "Unable to reset channel, reset status %d\n", r); 324 325 ath9k_hw_enable_interrupts(ah); 326 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 327 328 goto out; 329 } 330 331 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 332 sc->cur_chan->offchannel) 333 ath9k_mci_set_txpower(sc, true, false); 334 335 if (!ath_complete_reset(sc, true)) 336 r = -EIO; 337 338 out: 339 enable_irq(sc->irq); 340 spin_unlock_bh(&sc->sc_pcu_lock); 341 tasklet_enable(&sc->bcon_tasklet); 342 tasklet_enable(&sc->intr_tq); 343 344 return r; 345 } 346 347 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 348 struct ieee80211_vif *vif) 349 { 350 struct ath_node *an; 351 an = (struct ath_node *)sta->drv_priv; 352 353 an->sc = sc; 354 an->sta = sta; 355 an->vif = vif; 356 memset(&an->key_idx, 0, sizeof(an->key_idx)); 357 358 ath_tx_node_init(sc, an); 359 360 ath_dynack_node_init(sc->sc_ah, an); 361 } 362 363 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 364 { 365 struct ath_node *an = (struct ath_node *)sta->drv_priv; 366 ath_tx_node_cleanup(sc, an); 367 368 ath_dynack_node_deinit(sc->sc_ah, an); 369 } 370 371 void ath9k_tasklet(unsigned long data) 372 { 373 struct ath_softc *sc = (struct ath_softc *)data; 374 struct ath_hw *ah = sc->sc_ah; 375 struct ath_common *common = ath9k_hw_common(ah); 376 enum ath_reset_type type; 377 unsigned long flags; 378 u32 status; 379 u32 rxmask; 380 381 spin_lock_irqsave(&sc->intr_lock, flags); 382 status = sc->intrstatus; 383 sc->intrstatus = 0; 384 spin_unlock_irqrestore(&sc->intr_lock, flags); 385 386 ath9k_ps_wakeup(sc); 387 spin_lock(&sc->sc_pcu_lock); 388 389 if (status & ATH9K_INT_FATAL) { 390 type = RESET_TYPE_FATAL_INT; 391 ath9k_queue_reset(sc, type); 392 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 393 goto out; 394 } 395 396 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 397 (status & ATH9K_INT_BB_WATCHDOG)) { 398 spin_lock_irqsave(&common->cc_lock, flags); 399 ath_hw_cycle_counters_update(common); 400 ar9003_hw_bb_watchdog_dbg_info(ah); 401 spin_unlock_irqrestore(&common->cc_lock, flags); 402 403 if (ar9003_hw_bb_watchdog_check(ah)) { 404 type = RESET_TYPE_BB_WATCHDOG; 405 ath9k_queue_reset(sc, type); 406 407 ath_dbg(common, RESET, 408 "BB_WATCHDOG: Skipping interrupts\n"); 409 goto out; 410 } 411 } 412 413 if (status & ATH9K_INT_GTT) { 414 sc->gtt_cnt++; 415 416 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 417 type = RESET_TYPE_TX_GTT; 418 ath9k_queue_reset(sc, type); 419 ath_dbg(common, RESET, 420 "GTT: Skipping interrupts\n"); 421 goto out; 422 } 423 } 424 425 spin_lock_irqsave(&sc->sc_pm_lock, flags); 426 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 427 /* 428 * TSF sync does not look correct; remain awake to sync with 429 * the next Beacon. 430 */ 431 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 432 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 433 } 434 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 435 436 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 437 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 438 ATH9K_INT_RXORN); 439 else 440 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 441 442 if (status & rxmask) { 443 /* Check for high priority Rx first */ 444 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 445 (status & ATH9K_INT_RXHP)) 446 ath_rx_tasklet(sc, 0, true); 447 448 ath_rx_tasklet(sc, 0, false); 449 } 450 451 if (status & ATH9K_INT_TX) { 452 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 453 /* 454 * For EDMA chips, TX completion is enabled for the 455 * beacon queue, so if a beacon has been transmitted 456 * successfully after a GTT interrupt, the GTT counter 457 * gets reset to zero here. 458 */ 459 sc->gtt_cnt = 0; 460 461 ath_tx_edma_tasklet(sc); 462 } else { 463 ath_tx_tasklet(sc); 464 } 465 466 wake_up(&sc->tx_wait); 467 } 468 469 if (status & ATH9K_INT_GENTIMER) 470 ath_gen_timer_isr(sc->sc_ah); 471 472 ath9k_btcoex_handle_interrupt(sc, status); 473 474 /* re-enable hardware interrupt */ 475 ath9k_hw_resume_interrupts(ah); 476 out: 477 spin_unlock(&sc->sc_pcu_lock); 478 ath9k_ps_restore(sc); 479 } 480 481 irqreturn_t ath_isr(int irq, void *dev) 482 { 483 #define SCHED_INTR ( \ 484 ATH9K_INT_FATAL | \ 485 ATH9K_INT_BB_WATCHDOG | \ 486 ATH9K_INT_RXORN | \ 487 ATH9K_INT_RXEOL | \ 488 ATH9K_INT_RX | \ 489 ATH9K_INT_RXLP | \ 490 ATH9K_INT_RXHP | \ 491 ATH9K_INT_TX | \ 492 ATH9K_INT_BMISS | \ 493 ATH9K_INT_CST | \ 494 ATH9K_INT_GTT | \ 495 ATH9K_INT_TSFOOR | \ 496 ATH9K_INT_GENTIMER | \ 497 ATH9K_INT_MCI) 498 499 struct ath_softc *sc = dev; 500 struct ath_hw *ah = sc->sc_ah; 501 struct ath_common *common = ath9k_hw_common(ah); 502 enum ath9k_int status; 503 u32 sync_cause = 0; 504 bool sched = false; 505 506 /* 507 * The hardware is not ready/present, don't 508 * touch anything. Note this can happen early 509 * on if the IRQ is shared. 510 */ 511 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags)) 512 return IRQ_NONE; 513 514 /* shared irq, not for us */ 515 if (!ath9k_hw_intrpend(ah)) 516 return IRQ_NONE; 517 518 /* 519 * Figure out the reason(s) for the interrupt. Note 520 * that the hal returns a pseudo-ISR that may include 521 * bits we haven't explicitly enabled so we mask the 522 * value to insure we only process bits we requested. 523 */ 524 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 525 ath9k_debug_sync_cause(sc, sync_cause); 526 status &= ah->imask; /* discard unasked-for bits */ 527 528 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 529 return IRQ_HANDLED; 530 531 /* 532 * If there are no status bits set, then this interrupt was not 533 * for me (should have been caught above). 534 */ 535 if (!status) 536 return IRQ_NONE; 537 538 /* Cache the status */ 539 spin_lock(&sc->intr_lock); 540 sc->intrstatus |= status; 541 spin_unlock(&sc->intr_lock); 542 543 if (status & SCHED_INTR) 544 sched = true; 545 546 /* 547 * If a FATAL interrupt is received, we have to reset the chip 548 * immediately. 549 */ 550 if (status & ATH9K_INT_FATAL) 551 goto chip_reset; 552 553 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 554 (status & ATH9K_INT_BB_WATCHDOG)) 555 goto chip_reset; 556 557 if (status & ATH9K_INT_SWBA) 558 tasklet_schedule(&sc->bcon_tasklet); 559 560 if (status & ATH9K_INT_TXURN) 561 ath9k_hw_updatetxtriglevel(ah, true); 562 563 if (status & ATH9K_INT_RXEOL) { 564 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 565 ath9k_hw_set_interrupts(ah); 566 } 567 568 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 569 if (status & ATH9K_INT_TIM_TIMER) { 570 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 571 goto chip_reset; 572 /* Clear RxAbort bit so that we can 573 * receive frames */ 574 ath9k_setpower(sc, ATH9K_PM_AWAKE); 575 spin_lock(&sc->sc_pm_lock); 576 ath9k_hw_setrxabort(sc->sc_ah, 0); 577 sc->ps_flags |= PS_WAIT_FOR_BEACON; 578 spin_unlock(&sc->sc_pm_lock); 579 } 580 581 chip_reset: 582 583 ath_debug_stat_interrupt(sc, status); 584 585 if (sched) { 586 /* turn off every interrupt */ 587 ath9k_hw_kill_interrupts(ah); 588 tasklet_schedule(&sc->intr_tq); 589 } 590 591 return IRQ_HANDLED; 592 593 #undef SCHED_INTR 594 } 595 596 /* 597 * This function is called when a HW reset cannot be deferred 598 * and has to be immediate. 599 */ 600 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan) 601 { 602 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 603 int r; 604 605 ath9k_hw_kill_interrupts(sc->sc_ah); 606 set_bit(ATH_OP_HW_RESET, &common->op_flags); 607 608 ath9k_ps_wakeup(sc); 609 r = ath_reset_internal(sc, hchan); 610 ath9k_ps_restore(sc); 611 612 return r; 613 } 614 615 /* 616 * When a HW reset can be deferred, it is added to the 617 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before 618 * queueing. 619 */ 620 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 621 { 622 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 623 #ifdef CONFIG_ATH9K_DEBUGFS 624 RESET_STAT_INC(sc, type); 625 #endif 626 ath9k_hw_kill_interrupts(sc->sc_ah); 627 set_bit(ATH_OP_HW_RESET, &common->op_flags); 628 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 629 } 630 631 void ath_reset_work(struct work_struct *work) 632 { 633 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 634 635 ath9k_ps_wakeup(sc); 636 ath_reset_internal(sc, NULL); 637 ath9k_ps_restore(sc); 638 } 639 640 /**********************/ 641 /* mac80211 callbacks */ 642 /**********************/ 643 644 static int ath9k_start(struct ieee80211_hw *hw) 645 { 646 struct ath_softc *sc = hw->priv; 647 struct ath_hw *ah = sc->sc_ah; 648 struct ath_common *common = ath9k_hw_common(ah); 649 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; 650 struct ath_chanctx *ctx = sc->cur_chan; 651 struct ath9k_channel *init_channel; 652 int r; 653 654 ath_dbg(common, CONFIG, 655 "Starting driver with initial channel: %d MHz\n", 656 curchan->center_freq); 657 658 ath9k_ps_wakeup(sc); 659 mutex_lock(&sc->mutex); 660 661 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); 662 sc->cur_chandef = hw->conf.chandef; 663 664 /* Reset SERDES registers */ 665 ath9k_hw_configpcipowersave(ah, false); 666 667 /* 668 * The basic interface to setting the hardware in a good 669 * state is ``reset''. On return the hardware is known to 670 * be powered up and with interrupts disabled. This must 671 * be followed by initialization of the appropriate bits 672 * and then setup of the interrupt mask. 673 */ 674 spin_lock_bh(&sc->sc_pcu_lock); 675 676 atomic_set(&ah->intr_ref_cnt, -1); 677 678 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 679 if (r) { 680 ath_err(common, 681 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 682 r, curchan->center_freq); 683 ah->reset_power_on = false; 684 } 685 686 /* Setup our intr mask. */ 687 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 688 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 689 ATH9K_INT_GLOBAL; 690 691 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 692 ah->imask |= ATH9K_INT_RXHP | 693 ATH9K_INT_RXLP; 694 else 695 ah->imask |= ATH9K_INT_RX; 696 697 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 698 ah->imask |= ATH9K_INT_BB_WATCHDOG; 699 700 /* 701 * Enable GTT interrupts only for AR9003/AR9004 chips 702 * for now. 703 */ 704 if (AR_SREV_9300_20_OR_LATER(ah)) 705 ah->imask |= ATH9K_INT_GTT; 706 707 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 708 ah->imask |= ATH9K_INT_CST; 709 710 ath_mci_enable(sc); 711 712 clear_bit(ATH_OP_INVALID, &common->op_flags); 713 sc->sc_ah->is_monitoring = false; 714 715 if (!ath_complete_reset(sc, false)) 716 ah->reset_power_on = false; 717 718 if (ah->led_pin >= 0) { 719 ath9k_hw_set_gpio(ah, ah->led_pin, 720 (ah->config.led_active_high) ? 1 : 0); 721 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL, 722 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 723 } 724 725 /* 726 * Reset key cache to sane defaults (all entries cleared) instead of 727 * semi-random values after suspend/resume. 728 */ 729 ath9k_cmn_init_crypto(sc->sc_ah); 730 731 ath9k_hw_reset_tsf(ah); 732 733 spin_unlock_bh(&sc->sc_pcu_lock); 734 735 ath9k_rng_start(sc); 736 737 mutex_unlock(&sc->mutex); 738 739 ath9k_ps_restore(sc); 740 741 return 0; 742 } 743 744 static void ath9k_tx(struct ieee80211_hw *hw, 745 struct ieee80211_tx_control *control, 746 struct sk_buff *skb) 747 { 748 struct ath_softc *sc = hw->priv; 749 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 750 struct ath_tx_control txctl; 751 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 752 unsigned long flags; 753 754 if (sc->ps_enabled) { 755 /* 756 * mac80211 does not set PM field for normal data frames, so we 757 * need to update that based on the current PS mode. 758 */ 759 if (ieee80211_is_data(hdr->frame_control) && 760 !ieee80211_is_nullfunc(hdr->frame_control) && 761 !ieee80211_has_pm(hdr->frame_control)) { 762 ath_dbg(common, PS, 763 "Add PM=1 for a TX frame while in PS mode\n"); 764 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 765 } 766 } 767 768 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 769 /* 770 * We are using PS-Poll and mac80211 can request TX while in 771 * power save mode. Need to wake up hardware for the TX to be 772 * completed and if needed, also for RX of buffered frames. 773 */ 774 ath9k_ps_wakeup(sc); 775 spin_lock_irqsave(&sc->sc_pm_lock, flags); 776 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 777 ath9k_hw_setrxabort(sc->sc_ah, 0); 778 if (ieee80211_is_pspoll(hdr->frame_control)) { 779 ath_dbg(common, PS, 780 "Sending PS-Poll to pick a buffered frame\n"); 781 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 782 } else { 783 ath_dbg(common, PS, "Wake up to complete TX\n"); 784 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 785 } 786 /* 787 * The actual restore operation will happen only after 788 * the ps_flags bit is cleared. We are just dropping 789 * the ps_usecount here. 790 */ 791 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 792 ath9k_ps_restore(sc); 793 } 794 795 /* 796 * Cannot tx while the hardware is in full sleep, it first needs a full 797 * chip reset to recover from that 798 */ 799 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 800 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 801 goto exit; 802 } 803 804 memset(&txctl, 0, sizeof(struct ath_tx_control)); 805 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 806 txctl.sta = control->sta; 807 808 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 809 810 if (ath_tx_start(hw, skb, &txctl) != 0) { 811 ath_dbg(common, XMIT, "TX failed\n"); 812 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed); 813 goto exit; 814 } 815 816 return; 817 exit: 818 ieee80211_free_txskb(hw, skb); 819 } 820 821 static void ath9k_stop(struct ieee80211_hw *hw) 822 { 823 struct ath_softc *sc = hw->priv; 824 struct ath_hw *ah = sc->sc_ah; 825 struct ath_common *common = ath9k_hw_common(ah); 826 bool prev_idle; 827 828 ath9k_deinit_channel_context(sc); 829 830 mutex_lock(&sc->mutex); 831 832 ath9k_rng_stop(sc); 833 834 ath_cancel_work(sc); 835 836 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 837 ath_dbg(common, ANY, "Device not present\n"); 838 mutex_unlock(&sc->mutex); 839 return; 840 } 841 842 /* Ensure HW is awake when we try to shut it down. */ 843 ath9k_ps_wakeup(sc); 844 845 spin_lock_bh(&sc->sc_pcu_lock); 846 847 /* prevent tasklets to enable interrupts once we disable them */ 848 ah->imask &= ~ATH9K_INT_GLOBAL; 849 850 /* make sure h/w will not generate any interrupt 851 * before setting the invalid flag. */ 852 ath9k_hw_disable_interrupts(ah); 853 854 spin_unlock_bh(&sc->sc_pcu_lock); 855 856 /* we can now sync irq and kill any running tasklets, since we already 857 * disabled interrupts and not holding a spin lock */ 858 synchronize_irq(sc->irq); 859 tasklet_kill(&sc->intr_tq); 860 tasklet_kill(&sc->bcon_tasklet); 861 862 prev_idle = sc->ps_idle; 863 sc->ps_idle = true; 864 865 spin_lock_bh(&sc->sc_pcu_lock); 866 867 if (ah->led_pin >= 0) { 868 ath9k_hw_set_gpio(ah, ah->led_pin, 869 (ah->config.led_active_high) ? 0 : 1); 870 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL); 871 } 872 873 ath_prepare_reset(sc); 874 875 if (sc->rx.frag) { 876 dev_kfree_skb_any(sc->rx.frag); 877 sc->rx.frag = NULL; 878 } 879 880 if (!ah->curchan) 881 ah->curchan = ath9k_cmn_get_channel(hw, ah, 882 &sc->cur_chan->chandef); 883 884 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 885 886 set_bit(ATH_OP_INVALID, &common->op_flags); 887 888 ath9k_hw_phy_disable(ah); 889 890 ath9k_hw_configpcipowersave(ah, true); 891 892 spin_unlock_bh(&sc->sc_pcu_lock); 893 894 ath9k_ps_restore(sc); 895 896 sc->ps_idle = prev_idle; 897 898 mutex_unlock(&sc->mutex); 899 900 ath_dbg(common, CONFIG, "Driver halt\n"); 901 } 902 903 static bool ath9k_uses_beacons(int type) 904 { 905 switch (type) { 906 case NL80211_IFTYPE_AP: 907 case NL80211_IFTYPE_ADHOC: 908 case NL80211_IFTYPE_MESH_POINT: 909 return true; 910 default: 911 return false; 912 } 913 } 914 915 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data, 916 struct ieee80211_vif *vif) 917 { 918 /* Use the first (configured) interface, but prefering AP interfaces. */ 919 if (!iter_data->primary_beacon_vif) { 920 iter_data->primary_beacon_vif = vif; 921 } else { 922 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP && 923 vif->type == NL80211_IFTYPE_AP) 924 iter_data->primary_beacon_vif = vif; 925 } 926 927 iter_data->beacons = true; 928 iter_data->nbcnvifs += 1; 929 } 930 931 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, 932 u8 *mac, struct ieee80211_vif *vif) 933 { 934 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 935 int i; 936 937 if (iter_data->has_hw_macaddr) { 938 for (i = 0; i < ETH_ALEN; i++) 939 iter_data->mask[i] &= 940 ~(iter_data->hw_macaddr[i] ^ mac[i]); 941 } else { 942 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 943 iter_data->has_hw_macaddr = true; 944 } 945 946 if (!vif->bss_conf.use_short_slot) 947 iter_data->slottime = 20; 948 949 switch (vif->type) { 950 case NL80211_IFTYPE_AP: 951 iter_data->naps++; 952 if (vif->bss_conf.enable_beacon) 953 ath9k_vif_iter_set_beacon(iter_data, vif); 954 break; 955 case NL80211_IFTYPE_STATION: 956 iter_data->nstations++; 957 if (avp->assoc && !iter_data->primary_sta) 958 iter_data->primary_sta = vif; 959 break; 960 case NL80211_IFTYPE_OCB: 961 iter_data->nocbs++; 962 break; 963 case NL80211_IFTYPE_ADHOC: 964 iter_data->nadhocs++; 965 if (vif->bss_conf.enable_beacon) 966 ath9k_vif_iter_set_beacon(iter_data, vif); 967 break; 968 case NL80211_IFTYPE_MESH_POINT: 969 iter_data->nmeshes++; 970 if (vif->bss_conf.enable_beacon) 971 ath9k_vif_iter_set_beacon(iter_data, vif); 972 break; 973 case NL80211_IFTYPE_WDS: 974 iter_data->nwds++; 975 break; 976 default: 977 break; 978 } 979 } 980 981 static void ath9k_update_bssid_mask(struct ath_softc *sc, 982 struct ath_chanctx *ctx, 983 struct ath9k_vif_iter_data *iter_data) 984 { 985 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 986 struct ath_vif *avp; 987 int i; 988 989 if (!ath9k_is_chanctx_enabled()) 990 return; 991 992 list_for_each_entry(avp, &ctx->vifs, list) { 993 if (ctx->nvifs_assigned != 1) 994 continue; 995 996 if (!iter_data->has_hw_macaddr) 997 continue; 998 999 ether_addr_copy(common->curbssid, avp->bssid); 1000 1001 /* perm_addr will be used as the p2p device address. */ 1002 for (i = 0; i < ETH_ALEN; i++) 1003 iter_data->mask[i] &= 1004 ~(iter_data->hw_macaddr[i] ^ 1005 sc->hw->wiphy->perm_addr[i]); 1006 } 1007 } 1008 1009 /* Called with sc->mutex held. */ 1010 void ath9k_calculate_iter_data(struct ath_softc *sc, 1011 struct ath_chanctx *ctx, 1012 struct ath9k_vif_iter_data *iter_data) 1013 { 1014 struct ath_vif *avp; 1015 1016 /* 1017 * The hardware will use primary station addr together with the 1018 * BSSID mask when matching addresses. 1019 */ 1020 memset(iter_data, 0, sizeof(*iter_data)); 1021 eth_broadcast_addr(iter_data->mask); 1022 iter_data->slottime = 9; 1023 1024 list_for_each_entry(avp, &ctx->vifs, list) 1025 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); 1026 1027 ath9k_update_bssid_mask(sc, ctx, iter_data); 1028 } 1029 1030 static void ath9k_set_assoc_state(struct ath_softc *sc, 1031 struct ieee80211_vif *vif, bool changed) 1032 { 1033 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1034 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 1035 unsigned long flags; 1036 1037 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1038 1039 ether_addr_copy(common->curbssid, avp->bssid); 1040 common->curaid = avp->aid; 1041 ath9k_hw_write_associd(sc->sc_ah); 1042 1043 if (changed) { 1044 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1045 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1046 1047 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1048 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1049 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1050 } 1051 1052 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1053 ath9k_mci_update_wlan_channels(sc, false); 1054 1055 ath_dbg(common, CONFIG, 1056 "Primary Station interface: %pM, BSSID: %pM\n", 1057 vif->addr, common->curbssid); 1058 } 1059 1060 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1061 static void ath9k_set_offchannel_state(struct ath_softc *sc) 1062 { 1063 struct ath_hw *ah = sc->sc_ah; 1064 struct ath_common *common = ath9k_hw_common(ah); 1065 struct ieee80211_vif *vif = NULL; 1066 1067 ath9k_ps_wakeup(sc); 1068 1069 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) 1070 vif = sc->offchannel.scan_vif; 1071 else 1072 vif = sc->offchannel.roc_vif; 1073 1074 if (WARN_ON(!vif)) 1075 goto exit; 1076 1077 eth_zero_addr(common->curbssid); 1078 eth_broadcast_addr(common->bssidmask); 1079 memcpy(common->macaddr, vif->addr, ETH_ALEN); 1080 common->curaid = 0; 1081 ah->opmode = vif->type; 1082 ah->imask &= ~ATH9K_INT_SWBA; 1083 ah->imask &= ~ATH9K_INT_TSFOOR; 1084 ah->slottime = 9; 1085 1086 ath_hw_setbssidmask(common); 1087 ath9k_hw_setopmode(ah); 1088 ath9k_hw_write_associd(sc->sc_ah); 1089 ath9k_hw_set_interrupts(ah); 1090 ath9k_hw_init_global_settings(ah); 1091 1092 exit: 1093 ath9k_ps_restore(sc); 1094 } 1095 #endif 1096 1097 /* Called with sc->mutex held. */ 1098 void ath9k_calculate_summary_state(struct ath_softc *sc, 1099 struct ath_chanctx *ctx) 1100 { 1101 struct ath_hw *ah = sc->sc_ah; 1102 struct ath_common *common = ath9k_hw_common(ah); 1103 struct ath9k_vif_iter_data iter_data; 1104 1105 ath_chanctx_check_active(sc, ctx); 1106 1107 if (ctx != sc->cur_chan) 1108 return; 1109 1110 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1111 if (ctx == &sc->offchannel.chan) 1112 return ath9k_set_offchannel_state(sc); 1113 #endif 1114 1115 ath9k_ps_wakeup(sc); 1116 ath9k_calculate_iter_data(sc, ctx, &iter_data); 1117 1118 if (iter_data.has_hw_macaddr) 1119 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN); 1120 1121 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1122 ath_hw_setbssidmask(common); 1123 1124 if (iter_data.naps > 0) { 1125 ath9k_hw_set_tsfadjust(ah, true); 1126 ah->opmode = NL80211_IFTYPE_AP; 1127 } else { 1128 ath9k_hw_set_tsfadjust(ah, false); 1129 if (iter_data.beacons) 1130 ath9k_beacon_ensure_primary_slot(sc); 1131 1132 if (iter_data.nmeshes) 1133 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1134 else if (iter_data.nocbs) 1135 ah->opmode = NL80211_IFTYPE_OCB; 1136 else if (iter_data.nwds) 1137 ah->opmode = NL80211_IFTYPE_AP; 1138 else if (iter_data.nadhocs) 1139 ah->opmode = NL80211_IFTYPE_ADHOC; 1140 else 1141 ah->opmode = NL80211_IFTYPE_STATION; 1142 } 1143 1144 ath9k_hw_setopmode(ah); 1145 1146 ctx->switch_after_beacon = false; 1147 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1148 ah->imask |= ATH9K_INT_TSFOOR; 1149 else { 1150 ah->imask &= ~ATH9K_INT_TSFOOR; 1151 if (iter_data.naps == 1 && iter_data.beacons) 1152 ctx->switch_after_beacon = true; 1153 } 1154 1155 if (ah->opmode == NL80211_IFTYPE_STATION) { 1156 bool changed = (iter_data.primary_sta != ctx->primary_sta); 1157 1158 if (iter_data.primary_sta) { 1159 iter_data.primary_beacon_vif = iter_data.primary_sta; 1160 iter_data.beacons = true; 1161 ath9k_set_assoc_state(sc, iter_data.primary_sta, 1162 changed); 1163 ctx->primary_sta = iter_data.primary_sta; 1164 } else { 1165 ctx->primary_sta = NULL; 1166 eth_zero_addr(common->curbssid); 1167 common->curaid = 0; 1168 ath9k_hw_write_associd(sc->sc_ah); 1169 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1170 ath9k_mci_update_wlan_channels(sc, true); 1171 } 1172 } 1173 sc->nbcnvifs = iter_data.nbcnvifs; 1174 ath9k_beacon_config(sc, iter_data.primary_beacon_vif, 1175 iter_data.beacons); 1176 ath9k_hw_set_interrupts(ah); 1177 1178 if (ah->slottime != iter_data.slottime) { 1179 ah->slottime = iter_data.slottime; 1180 ath9k_hw_init_global_settings(ah); 1181 } 1182 1183 if (iter_data.primary_sta) 1184 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1185 else 1186 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1187 1188 ath_dbg(common, CONFIG, 1189 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n", 1190 common->macaddr, common->curbssid, common->bssidmask); 1191 1192 ath9k_ps_restore(sc); 1193 } 1194 1195 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1196 { 1197 int *power = data; 1198 1199 if (vif->bss_conf.txpower == INT_MIN) 1200 return; 1201 1202 if (*power < vif->bss_conf.txpower) 1203 *power = vif->bss_conf.txpower; 1204 } 1205 1206 /* Called with sc->mutex held. */ 1207 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif) 1208 { 1209 int power; 1210 struct ath_hw *ah = sc->sc_ah; 1211 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 1212 1213 ath9k_ps_wakeup(sc); 1214 if (ah->tpc_enabled) { 1215 power = (vif) ? vif->bss_conf.txpower : -1; 1216 ieee80211_iterate_active_interfaces_atomic( 1217 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1218 ath9k_tpc_vif_iter, &power); 1219 if (power == -1) 1220 power = sc->hw->conf.power_level; 1221 } else { 1222 power = sc->hw->conf.power_level; 1223 } 1224 sc->cur_chan->txpower = 2 * power; 1225 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); 1226 sc->cur_chan->cur_txpower = reg->max_power_level; 1227 ath9k_ps_restore(sc); 1228 } 1229 1230 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, 1231 struct ieee80211_vif *vif) 1232 { 1233 int i; 1234 1235 if (!ath9k_is_chanctx_enabled()) 1236 return; 1237 1238 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1239 vif->hw_queue[i] = i; 1240 1241 if (vif->type == NL80211_IFTYPE_AP || 1242 vif->type == NL80211_IFTYPE_MESH_POINT) 1243 vif->cab_queue = hw->queues - 2; 1244 else 1245 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1246 } 1247 1248 static int ath9k_add_interface(struct ieee80211_hw *hw, 1249 struct ieee80211_vif *vif) 1250 { 1251 struct ath_softc *sc = hw->priv; 1252 struct ath_hw *ah = sc->sc_ah; 1253 struct ath_common *common = ath9k_hw_common(ah); 1254 struct ath_vif *avp = (void *)vif->drv_priv; 1255 struct ath_node *an = &avp->mcast_node; 1256 1257 mutex_lock(&sc->mutex); 1258 if (IS_ENABLED(CONFIG_ATH9K_TX99)) { 1259 if (sc->cur_chan->nvifs >= 1) { 1260 mutex_unlock(&sc->mutex); 1261 return -EOPNOTSUPP; 1262 } 1263 sc->tx99_vif = vif; 1264 } 1265 1266 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1267 sc->cur_chan->nvifs++; 1268 1269 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled()) 1270 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE; 1271 1272 if (ath9k_uses_beacons(vif->type)) 1273 ath9k_beacon_assign_slot(sc, vif); 1274 1275 avp->vif = vif; 1276 if (!ath9k_is_chanctx_enabled()) { 1277 avp->chanctx = sc->cur_chan; 1278 list_add_tail(&avp->list, &avp->chanctx->vifs); 1279 } 1280 1281 ath9k_calculate_summary_state(sc, avp->chanctx); 1282 1283 ath9k_assign_hw_queues(hw, vif); 1284 1285 ath9k_set_txpower(sc, vif); 1286 1287 an->sc = sc; 1288 an->sta = NULL; 1289 an->vif = vif; 1290 an->no_ps_filter = true; 1291 ath_tx_node_init(sc, an); 1292 1293 mutex_unlock(&sc->mutex); 1294 return 0; 1295 } 1296 1297 static int ath9k_change_interface(struct ieee80211_hw *hw, 1298 struct ieee80211_vif *vif, 1299 enum nl80211_iftype new_type, 1300 bool p2p) 1301 { 1302 struct ath_softc *sc = hw->priv; 1303 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1304 struct ath_vif *avp = (void *)vif->drv_priv; 1305 1306 mutex_lock(&sc->mutex); 1307 1308 if (IS_ENABLED(CONFIG_ATH9K_TX99)) { 1309 mutex_unlock(&sc->mutex); 1310 return -EOPNOTSUPP; 1311 } 1312 1313 ath_dbg(common, CONFIG, "Change Interface\n"); 1314 1315 if (ath9k_uses_beacons(vif->type)) 1316 ath9k_beacon_remove_slot(sc, vif); 1317 1318 vif->type = new_type; 1319 vif->p2p = p2p; 1320 1321 if (ath9k_uses_beacons(vif->type)) 1322 ath9k_beacon_assign_slot(sc, vif); 1323 1324 ath9k_assign_hw_queues(hw, vif); 1325 ath9k_calculate_summary_state(sc, avp->chanctx); 1326 1327 ath9k_set_txpower(sc, vif); 1328 1329 mutex_unlock(&sc->mutex); 1330 return 0; 1331 } 1332 1333 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1334 struct ieee80211_vif *vif) 1335 { 1336 struct ath_softc *sc = hw->priv; 1337 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1338 struct ath_vif *avp = (void *)vif->drv_priv; 1339 1340 ath_dbg(common, CONFIG, "Detach Interface\n"); 1341 1342 mutex_lock(&sc->mutex); 1343 1344 ath9k_p2p_remove_vif(sc, vif); 1345 1346 sc->cur_chan->nvifs--; 1347 sc->tx99_vif = NULL; 1348 if (!ath9k_is_chanctx_enabled()) 1349 list_del(&avp->list); 1350 1351 if (ath9k_uses_beacons(vif->type)) 1352 ath9k_beacon_remove_slot(sc, vif); 1353 1354 ath_tx_node_cleanup(sc, &avp->mcast_node); 1355 1356 ath9k_calculate_summary_state(sc, avp->chanctx); 1357 1358 ath9k_set_txpower(sc, NULL); 1359 1360 mutex_unlock(&sc->mutex); 1361 } 1362 1363 static void ath9k_enable_ps(struct ath_softc *sc) 1364 { 1365 struct ath_hw *ah = sc->sc_ah; 1366 struct ath_common *common = ath9k_hw_common(ah); 1367 1368 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 1369 return; 1370 1371 sc->ps_enabled = true; 1372 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1373 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1374 ah->imask |= ATH9K_INT_TIM_TIMER; 1375 ath9k_hw_set_interrupts(ah); 1376 } 1377 ath9k_hw_setrxabort(ah, 1); 1378 } 1379 ath_dbg(common, PS, "PowerSave enabled\n"); 1380 } 1381 1382 static void ath9k_disable_ps(struct ath_softc *sc) 1383 { 1384 struct ath_hw *ah = sc->sc_ah; 1385 struct ath_common *common = ath9k_hw_common(ah); 1386 1387 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 1388 return; 1389 1390 sc->ps_enabled = false; 1391 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1392 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1393 ath9k_hw_setrxabort(ah, 0); 1394 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1395 PS_WAIT_FOR_CAB | 1396 PS_WAIT_FOR_PSPOLL_DATA | 1397 PS_WAIT_FOR_TX_ACK); 1398 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1399 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1400 ath9k_hw_set_interrupts(ah); 1401 } 1402 } 1403 ath_dbg(common, PS, "PowerSave disabled\n"); 1404 } 1405 1406 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1407 { 1408 struct ath_softc *sc = hw->priv; 1409 struct ath_hw *ah = sc->sc_ah; 1410 struct ath_common *common = ath9k_hw_common(ah); 1411 struct ieee80211_conf *conf = &hw->conf; 1412 struct ath_chanctx *ctx = sc->cur_chan; 1413 1414 ath9k_ps_wakeup(sc); 1415 mutex_lock(&sc->mutex); 1416 1417 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1418 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1419 if (sc->ps_idle) { 1420 ath_cancel_work(sc); 1421 ath9k_stop_btcoex(sc); 1422 } else { 1423 ath9k_start_btcoex(sc); 1424 /* 1425 * The chip needs a reset to properly wake up from 1426 * full sleep 1427 */ 1428 ath_chanctx_set_channel(sc, ctx, &ctx->chandef); 1429 } 1430 } 1431 1432 /* 1433 * We just prepare to enable PS. We have to wait until our AP has 1434 * ACK'd our null data frame to disable RX otherwise we'll ignore 1435 * those ACKs and end up retransmitting the same null data frames. 1436 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1437 */ 1438 if (changed & IEEE80211_CONF_CHANGE_PS) { 1439 unsigned long flags; 1440 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1441 if (conf->flags & IEEE80211_CONF_PS) 1442 ath9k_enable_ps(sc); 1443 else 1444 ath9k_disable_ps(sc); 1445 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1446 } 1447 1448 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1449 if (conf->flags & IEEE80211_CONF_MONITOR) { 1450 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1451 sc->sc_ah->is_monitoring = true; 1452 } else { 1453 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1454 sc->sc_ah->is_monitoring = false; 1455 } 1456 } 1457 1458 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { 1459 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); 1460 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); 1461 } 1462 1463 mutex_unlock(&sc->mutex); 1464 ath9k_ps_restore(sc); 1465 1466 return 0; 1467 } 1468 1469 #define SUPPORTED_FILTERS \ 1470 (FIF_ALLMULTI | \ 1471 FIF_CONTROL | \ 1472 FIF_PSPOLL | \ 1473 FIF_OTHER_BSS | \ 1474 FIF_BCN_PRBRESP_PROMISC | \ 1475 FIF_PROBE_REQ | \ 1476 FIF_FCSFAIL) 1477 1478 /* FIXME: sc->sc_full_reset ? */ 1479 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1480 unsigned int changed_flags, 1481 unsigned int *total_flags, 1482 u64 multicast) 1483 { 1484 struct ath_softc *sc = hw->priv; 1485 struct ath_chanctx *ctx; 1486 u32 rfilt; 1487 1488 changed_flags &= SUPPORTED_FILTERS; 1489 *total_flags &= SUPPORTED_FILTERS; 1490 1491 spin_lock_bh(&sc->chan_lock); 1492 ath_for_each_chanctx(sc, ctx) 1493 ctx->rxfilter = *total_flags; 1494 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1495 sc->offchannel.chan.rxfilter = *total_flags; 1496 #endif 1497 spin_unlock_bh(&sc->chan_lock); 1498 1499 ath9k_ps_wakeup(sc); 1500 rfilt = ath_calcrxfilter(sc); 1501 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1502 ath9k_ps_restore(sc); 1503 1504 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1505 rfilt); 1506 } 1507 1508 static int ath9k_sta_add(struct ieee80211_hw *hw, 1509 struct ieee80211_vif *vif, 1510 struct ieee80211_sta *sta) 1511 { 1512 struct ath_softc *sc = hw->priv; 1513 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1514 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1515 struct ieee80211_key_conf ps_key = { }; 1516 int key; 1517 1518 ath_node_attach(sc, sta, vif); 1519 1520 if (vif->type != NL80211_IFTYPE_AP && 1521 vif->type != NL80211_IFTYPE_AP_VLAN) 1522 return 0; 1523 1524 key = ath_key_config(common, vif, sta, &ps_key); 1525 if (key > 0) { 1526 an->ps_key = key; 1527 an->key_idx[0] = key; 1528 } 1529 1530 return 0; 1531 } 1532 1533 static void ath9k_del_ps_key(struct ath_softc *sc, 1534 struct ieee80211_vif *vif, 1535 struct ieee80211_sta *sta) 1536 { 1537 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1538 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1539 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1540 1541 if (!an->ps_key) 1542 return; 1543 1544 ath_key_delete(common, &ps_key); 1545 an->ps_key = 0; 1546 an->key_idx[0] = 0; 1547 } 1548 1549 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1550 struct ieee80211_vif *vif, 1551 struct ieee80211_sta *sta) 1552 { 1553 struct ath_softc *sc = hw->priv; 1554 1555 ath9k_del_ps_key(sc, vif, sta); 1556 ath_node_detach(sc, sta); 1557 1558 return 0; 1559 } 1560 1561 static int ath9k_sta_state(struct ieee80211_hw *hw, 1562 struct ieee80211_vif *vif, 1563 struct ieee80211_sta *sta, 1564 enum ieee80211_sta_state old_state, 1565 enum ieee80211_sta_state new_state) 1566 { 1567 struct ath_softc *sc = hw->priv; 1568 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1569 int ret = 0; 1570 1571 if (old_state == IEEE80211_STA_NOTEXIST && 1572 new_state == IEEE80211_STA_NONE) { 1573 ret = ath9k_sta_add(hw, vif, sta); 1574 ath_dbg(common, CONFIG, 1575 "Add station: %pM\n", sta->addr); 1576 } else if (old_state == IEEE80211_STA_NONE && 1577 new_state == IEEE80211_STA_NOTEXIST) { 1578 ret = ath9k_sta_remove(hw, vif, sta); 1579 ath_dbg(common, CONFIG, 1580 "Remove station: %pM\n", sta->addr); 1581 } 1582 1583 if (ath9k_is_chanctx_enabled()) { 1584 if (vif->type == NL80211_IFTYPE_STATION) { 1585 if (old_state == IEEE80211_STA_ASSOC && 1586 new_state == IEEE80211_STA_AUTHORIZED) 1587 ath_chanctx_event(sc, vif, 1588 ATH_CHANCTX_EVENT_AUTHORIZED); 1589 } 1590 } 1591 1592 return ret; 1593 } 1594 1595 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1596 struct ath_node *an, 1597 bool set) 1598 { 1599 int i; 1600 1601 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1602 if (!an->key_idx[i]) 1603 continue; 1604 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1605 } 1606 } 1607 1608 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1609 struct ieee80211_vif *vif, 1610 enum sta_notify_cmd cmd, 1611 struct ieee80211_sta *sta) 1612 { 1613 struct ath_softc *sc = hw->priv; 1614 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1615 1616 switch (cmd) { 1617 case STA_NOTIFY_SLEEP: 1618 an->sleeping = true; 1619 ath_tx_aggr_sleep(sta, sc, an); 1620 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1621 break; 1622 case STA_NOTIFY_AWAKE: 1623 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1624 an->sleeping = false; 1625 ath_tx_aggr_wakeup(sc, an); 1626 break; 1627 } 1628 } 1629 1630 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1631 struct ieee80211_vif *vif, u16 queue, 1632 const struct ieee80211_tx_queue_params *params) 1633 { 1634 struct ath_softc *sc = hw->priv; 1635 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1636 struct ath_txq *txq; 1637 struct ath9k_tx_queue_info qi; 1638 int ret = 0; 1639 1640 if (queue >= IEEE80211_NUM_ACS) 1641 return 0; 1642 1643 txq = sc->tx.txq_map[queue]; 1644 1645 ath9k_ps_wakeup(sc); 1646 mutex_lock(&sc->mutex); 1647 1648 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1649 1650 qi.tqi_aifs = params->aifs; 1651 qi.tqi_cwmin = params->cw_min; 1652 qi.tqi_cwmax = params->cw_max; 1653 qi.tqi_burstTime = params->txop * 32; 1654 1655 ath_dbg(common, CONFIG, 1656 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1657 queue, txq->axq_qnum, params->aifs, params->cw_min, 1658 params->cw_max, params->txop); 1659 1660 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1661 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1662 if (ret) 1663 ath_err(common, "TXQ Update failed\n"); 1664 1665 mutex_unlock(&sc->mutex); 1666 ath9k_ps_restore(sc); 1667 1668 return ret; 1669 } 1670 1671 static int ath9k_set_key(struct ieee80211_hw *hw, 1672 enum set_key_cmd cmd, 1673 struct ieee80211_vif *vif, 1674 struct ieee80211_sta *sta, 1675 struct ieee80211_key_conf *key) 1676 { 1677 struct ath_softc *sc = hw->priv; 1678 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1679 struct ath_node *an = NULL; 1680 int ret = 0, i; 1681 1682 if (ath9k_modparam_nohwcrypt) 1683 return -ENOSPC; 1684 1685 if ((vif->type == NL80211_IFTYPE_ADHOC || 1686 vif->type == NL80211_IFTYPE_MESH_POINT) && 1687 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1688 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1689 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1690 /* 1691 * For now, disable hw crypto for the RSN IBSS group keys. This 1692 * could be optimized in the future to use a modified key cache 1693 * design to support per-STA RX GTK, but until that gets 1694 * implemented, use of software crypto for group addressed 1695 * frames is a acceptable to allow RSN IBSS to be used. 1696 */ 1697 return -EOPNOTSUPP; 1698 } 1699 1700 mutex_lock(&sc->mutex); 1701 ath9k_ps_wakeup(sc); 1702 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1703 if (sta) 1704 an = (struct ath_node *)sta->drv_priv; 1705 1706 switch (cmd) { 1707 case SET_KEY: 1708 if (sta) 1709 ath9k_del_ps_key(sc, vif, sta); 1710 1711 key->hw_key_idx = 0; 1712 ret = ath_key_config(common, vif, sta, key); 1713 if (ret >= 0) { 1714 key->hw_key_idx = ret; 1715 /* push IV and Michael MIC generation to stack */ 1716 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1717 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1718 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1719 if (sc->sc_ah->sw_mgmt_crypto_tx && 1720 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1721 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1722 ret = 0; 1723 } 1724 if (an && key->hw_key_idx) { 1725 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1726 if (an->key_idx[i]) 1727 continue; 1728 an->key_idx[i] = key->hw_key_idx; 1729 break; 1730 } 1731 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1732 } 1733 break; 1734 case DISABLE_KEY: 1735 ath_key_delete(common, key); 1736 if (an) { 1737 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1738 if (an->key_idx[i] != key->hw_key_idx) 1739 continue; 1740 an->key_idx[i] = 0; 1741 break; 1742 } 1743 } 1744 key->hw_key_idx = 0; 1745 break; 1746 default: 1747 ret = -EINVAL; 1748 } 1749 1750 ath9k_ps_restore(sc); 1751 mutex_unlock(&sc->mutex); 1752 1753 return ret; 1754 } 1755 1756 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1757 struct ieee80211_vif *vif, 1758 struct ieee80211_bss_conf *bss_conf, 1759 u32 changed) 1760 { 1761 #define CHECK_ANI \ 1762 (BSS_CHANGED_ASSOC | \ 1763 BSS_CHANGED_IBSS | \ 1764 BSS_CHANGED_BEACON_ENABLED) 1765 1766 struct ath_softc *sc = hw->priv; 1767 struct ath_hw *ah = sc->sc_ah; 1768 struct ath_common *common = ath9k_hw_common(ah); 1769 struct ath_vif *avp = (void *)vif->drv_priv; 1770 int slottime; 1771 1772 ath9k_ps_wakeup(sc); 1773 mutex_lock(&sc->mutex); 1774 1775 if (changed & BSS_CHANGED_ASSOC) { 1776 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1777 bss_conf->bssid, bss_conf->assoc); 1778 1779 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); 1780 avp->aid = bss_conf->aid; 1781 avp->assoc = bss_conf->assoc; 1782 1783 ath9k_calculate_summary_state(sc, avp->chanctx); 1784 } 1785 1786 if ((changed & BSS_CHANGED_IBSS) || 1787 (changed & BSS_CHANGED_OCB)) { 1788 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1789 common->curaid = bss_conf->aid; 1790 ath9k_hw_write_associd(sc->sc_ah); 1791 } 1792 1793 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1794 (changed & BSS_CHANGED_BEACON_INT) || 1795 (changed & BSS_CHANGED_BEACON_INFO)) { 1796 ath9k_calculate_summary_state(sc, avp->chanctx); 1797 } 1798 1799 if ((avp->chanctx == sc->cur_chan) && 1800 (changed & BSS_CHANGED_ERP_SLOT)) { 1801 if (bss_conf->use_short_slot) 1802 slottime = 9; 1803 else 1804 slottime = 20; 1805 1806 if (vif->type == NL80211_IFTYPE_AP) { 1807 /* 1808 * Defer update, so that connected stations can adjust 1809 * their settings at the same time. 1810 * See beacon.c for more details 1811 */ 1812 sc->beacon.slottime = slottime; 1813 sc->beacon.updateslot = UPDATE; 1814 } else { 1815 ah->slottime = slottime; 1816 ath9k_hw_init_global_settings(ah); 1817 } 1818 } 1819 1820 if (changed & BSS_CHANGED_P2P_PS) 1821 ath9k_p2p_bss_info_changed(sc, vif); 1822 1823 if (changed & CHECK_ANI) 1824 ath_check_ani(sc); 1825 1826 if (changed & BSS_CHANGED_TXPOWER) { 1827 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n", 1828 vif->addr, bss_conf->txpower, bss_conf->txpower_type); 1829 ath9k_set_txpower(sc, vif); 1830 } 1831 1832 mutex_unlock(&sc->mutex); 1833 ath9k_ps_restore(sc); 1834 1835 #undef CHECK_ANI 1836 } 1837 1838 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1839 { 1840 struct ath_softc *sc = hw->priv; 1841 struct ath_vif *avp = (void *)vif->drv_priv; 1842 u64 tsf; 1843 1844 mutex_lock(&sc->mutex); 1845 ath9k_ps_wakeup(sc); 1846 /* Get current TSF either from HW or kernel time. */ 1847 if (sc->cur_chan == avp->chanctx) { 1848 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1849 } else { 1850 tsf = sc->cur_chan->tsf_val + 1851 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL); 1852 } 1853 tsf += le64_to_cpu(avp->tsf_adjust); 1854 ath9k_ps_restore(sc); 1855 mutex_unlock(&sc->mutex); 1856 1857 return tsf; 1858 } 1859 1860 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1861 struct ieee80211_vif *vif, 1862 u64 tsf) 1863 { 1864 struct ath_softc *sc = hw->priv; 1865 struct ath_vif *avp = (void *)vif->drv_priv; 1866 1867 mutex_lock(&sc->mutex); 1868 ath9k_ps_wakeup(sc); 1869 tsf -= le64_to_cpu(avp->tsf_adjust); 1870 ktime_get_raw_ts64(&avp->chanctx->tsf_ts); 1871 if (sc->cur_chan == avp->chanctx) 1872 ath9k_hw_settsf64(sc->sc_ah, tsf); 1873 avp->chanctx->tsf_val = tsf; 1874 ath9k_ps_restore(sc); 1875 mutex_unlock(&sc->mutex); 1876 } 1877 1878 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1879 { 1880 struct ath_softc *sc = hw->priv; 1881 struct ath_vif *avp = (void *)vif->drv_priv; 1882 1883 mutex_lock(&sc->mutex); 1884 1885 ath9k_ps_wakeup(sc); 1886 ktime_get_raw_ts64(&avp->chanctx->tsf_ts); 1887 if (sc->cur_chan == avp->chanctx) 1888 ath9k_hw_reset_tsf(sc->sc_ah); 1889 avp->chanctx->tsf_val = 0; 1890 ath9k_ps_restore(sc); 1891 1892 mutex_unlock(&sc->mutex); 1893 } 1894 1895 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1896 struct ieee80211_vif *vif, 1897 struct ieee80211_ampdu_params *params) 1898 { 1899 struct ath_softc *sc = hw->priv; 1900 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1901 bool flush = false; 1902 int ret = 0; 1903 struct ieee80211_sta *sta = params->sta; 1904 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1905 enum ieee80211_ampdu_mlme_action action = params->action; 1906 u16 tid = params->tid; 1907 u16 *ssn = ¶ms->ssn; 1908 struct ath_atx_tid *atid; 1909 1910 mutex_lock(&sc->mutex); 1911 1912 switch (action) { 1913 case IEEE80211_AMPDU_RX_START: 1914 break; 1915 case IEEE80211_AMPDU_RX_STOP: 1916 break; 1917 case IEEE80211_AMPDU_TX_START: 1918 if (ath9k_is_chanctx_enabled()) { 1919 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { 1920 ret = -EBUSY; 1921 break; 1922 } 1923 } 1924 ath9k_ps_wakeup(sc); 1925 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1926 if (!ret) 1927 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 1928 ath9k_ps_restore(sc); 1929 break; 1930 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1931 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1932 flush = true; 1933 /* fall through */ 1934 case IEEE80211_AMPDU_TX_STOP_CONT: 1935 ath9k_ps_wakeup(sc); 1936 ath_tx_aggr_stop(sc, sta, tid); 1937 if (!flush) 1938 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1939 ath9k_ps_restore(sc); 1940 break; 1941 case IEEE80211_AMPDU_TX_OPERATIONAL: 1942 atid = ath_node_to_tid(an, tid); 1943 atid->baw_size = IEEE80211_MIN_AMPDU_BUF << 1944 sta->ht_cap.ampdu_factor; 1945 break; 1946 default: 1947 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1948 } 1949 1950 mutex_unlock(&sc->mutex); 1951 1952 return ret; 1953 } 1954 1955 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1956 struct survey_info *survey) 1957 { 1958 struct ath_softc *sc = hw->priv; 1959 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1960 struct ieee80211_supported_band *sband; 1961 struct ieee80211_channel *chan; 1962 unsigned long flags; 1963 int pos; 1964 1965 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 1966 return -EOPNOTSUPP; 1967 1968 spin_lock_irqsave(&common->cc_lock, flags); 1969 if (idx == 0) 1970 ath_update_survey_stats(sc); 1971 1972 sband = hw->wiphy->bands[NL80211_BAND_2GHZ]; 1973 if (sband && idx >= sband->n_channels) { 1974 idx -= sband->n_channels; 1975 sband = NULL; 1976 } 1977 1978 if (!sband) 1979 sband = hw->wiphy->bands[NL80211_BAND_5GHZ]; 1980 1981 if (!sband || idx >= sband->n_channels) { 1982 spin_unlock_irqrestore(&common->cc_lock, flags); 1983 return -ENOENT; 1984 } 1985 1986 chan = &sband->channels[idx]; 1987 pos = chan->hw_value; 1988 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1989 survey->channel = chan; 1990 spin_unlock_irqrestore(&common->cc_lock, flags); 1991 1992 return 0; 1993 } 1994 1995 static void ath9k_enable_dynack(struct ath_softc *sc) 1996 { 1997 #ifdef CONFIG_ATH9K_DYNACK 1998 u32 rfilt; 1999 struct ath_hw *ah = sc->sc_ah; 2000 2001 ath_dynack_reset(ah); 2002 2003 ah->dynack.enabled = true; 2004 rfilt = ath_calcrxfilter(sc); 2005 ath9k_hw_setrxfilter(ah, rfilt); 2006 #endif 2007 } 2008 2009 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, 2010 s16 coverage_class) 2011 { 2012 struct ath_softc *sc = hw->priv; 2013 struct ath_hw *ah = sc->sc_ah; 2014 2015 if (IS_ENABLED(CONFIG_ATH9K_TX99)) 2016 return; 2017 2018 mutex_lock(&sc->mutex); 2019 2020 if (coverage_class >= 0) { 2021 ah->coverage_class = coverage_class; 2022 if (ah->dynack.enabled) { 2023 u32 rfilt; 2024 2025 ah->dynack.enabled = false; 2026 rfilt = ath_calcrxfilter(sc); 2027 ath9k_hw_setrxfilter(ah, rfilt); 2028 } 2029 ath9k_ps_wakeup(sc); 2030 ath9k_hw_init_global_settings(ah); 2031 ath9k_ps_restore(sc); 2032 } else if (!ah->dynack.enabled) { 2033 ath9k_enable_dynack(sc); 2034 } 2035 2036 mutex_unlock(&sc->mutex); 2037 } 2038 2039 static bool ath9k_has_tx_pending(struct ath_softc *sc, 2040 bool sw_pending) 2041 { 2042 int i, npend = 0; 2043 2044 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2045 if (!ATH_TXQ_SETUP(sc, i)) 2046 continue; 2047 2048 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i], 2049 sw_pending); 2050 if (npend) 2051 break; 2052 } 2053 2054 return !!npend; 2055 } 2056 2057 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2058 u32 queues, bool drop) 2059 { 2060 struct ath_softc *sc = hw->priv; 2061 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2062 2063 if (ath9k_is_chanctx_enabled()) { 2064 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2065 goto flush; 2066 2067 /* 2068 * If MCC is active, extend the flush timeout 2069 * and wait for the HW/SW queues to become 2070 * empty. This needs to be done outside the 2071 * sc->mutex lock to allow the channel scheduler 2072 * to switch channel contexts. 2073 * 2074 * The vif queues have been stopped in mac80211, 2075 * so there won't be any incoming frames. 2076 */ 2077 __ath9k_flush(hw, queues, drop, true, true); 2078 return; 2079 } 2080 flush: 2081 mutex_lock(&sc->mutex); 2082 __ath9k_flush(hw, queues, drop, true, false); 2083 mutex_unlock(&sc->mutex); 2084 } 2085 2086 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop, 2087 bool sw_pending, bool timeout_override) 2088 { 2089 struct ath_softc *sc = hw->priv; 2090 struct ath_hw *ah = sc->sc_ah; 2091 struct ath_common *common = ath9k_hw_common(ah); 2092 int timeout; 2093 bool drain_txq; 2094 2095 cancel_delayed_work_sync(&sc->hw_check_work); 2096 2097 if (ah->ah_flags & AH_UNPLUGGED) { 2098 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2099 return; 2100 } 2101 2102 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 2103 ath_dbg(common, ANY, "Device not present\n"); 2104 return; 2105 } 2106 2107 spin_lock_bh(&sc->chan_lock); 2108 if (timeout_override) 2109 timeout = HZ / 5; 2110 else 2111 timeout = sc->cur_chan->flush_timeout; 2112 spin_unlock_bh(&sc->chan_lock); 2113 2114 ath_dbg(common, CHAN_CTX, 2115 "Flush timeout: %d\n", jiffies_to_msecs(timeout)); 2116 2117 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending), 2118 timeout) > 0) 2119 drop = false; 2120 2121 if (drop) { 2122 ath9k_ps_wakeup(sc); 2123 spin_lock_bh(&sc->sc_pcu_lock); 2124 drain_txq = ath_drain_all_txq(sc); 2125 spin_unlock_bh(&sc->sc_pcu_lock); 2126 2127 if (!drain_txq) 2128 ath_reset(sc, NULL); 2129 2130 ath9k_ps_restore(sc); 2131 } 2132 2133 ieee80211_queue_delayed_work(hw, &sc->hw_check_work, 2134 ATH_HW_CHECK_POLL_INT); 2135 } 2136 2137 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2138 { 2139 struct ath_softc *sc = hw->priv; 2140 2141 return ath9k_has_tx_pending(sc, true); 2142 } 2143 2144 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2145 { 2146 struct ath_softc *sc = hw->priv; 2147 struct ath_hw *ah = sc->sc_ah; 2148 struct ieee80211_vif *vif; 2149 struct ath_vif *avp; 2150 struct ath_buf *bf; 2151 struct ath_tx_status ts; 2152 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2153 int status; 2154 2155 vif = sc->beacon.bslot[0]; 2156 if (!vif) 2157 return 0; 2158 2159 if (!vif->bss_conf.enable_beacon) 2160 return 0; 2161 2162 avp = (void *)vif->drv_priv; 2163 2164 if (!sc->beacon.tx_processed && !edma) { 2165 tasklet_disable(&sc->bcon_tasklet); 2166 2167 bf = avp->av_bcbuf; 2168 if (!bf || !bf->bf_mpdu) 2169 goto skip; 2170 2171 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2172 if (status == -EINPROGRESS) 2173 goto skip; 2174 2175 sc->beacon.tx_processed = true; 2176 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2177 2178 skip: 2179 tasklet_enable(&sc->bcon_tasklet); 2180 } 2181 2182 return sc->beacon.tx_last; 2183 } 2184 2185 static int ath9k_get_stats(struct ieee80211_hw *hw, 2186 struct ieee80211_low_level_stats *stats) 2187 { 2188 struct ath_softc *sc = hw->priv; 2189 struct ath_hw *ah = sc->sc_ah; 2190 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2191 2192 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2193 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2194 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2195 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2196 return 0; 2197 } 2198 2199 static u32 fill_chainmask(u32 cap, u32 new) 2200 { 2201 u32 filled = 0; 2202 int i; 2203 2204 for (i = 0; cap && new; i++, cap >>= 1) { 2205 if (!(cap & BIT(0))) 2206 continue; 2207 2208 if (new & BIT(0)) 2209 filled |= BIT(i); 2210 2211 new >>= 1; 2212 } 2213 2214 return filled; 2215 } 2216 2217 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2218 { 2219 if (AR_SREV_9300_20_OR_LATER(ah)) 2220 return true; 2221 2222 switch (val & 0x7) { 2223 case 0x1: 2224 case 0x3: 2225 case 0x7: 2226 return true; 2227 case 0x2: 2228 return (ah->caps.rx_chainmask == 1); 2229 default: 2230 return false; 2231 } 2232 } 2233 2234 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2235 { 2236 struct ath_softc *sc = hw->priv; 2237 struct ath_hw *ah = sc->sc_ah; 2238 2239 if (ah->caps.rx_chainmask != 1) 2240 rx_ant |= tx_ant; 2241 2242 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2243 return -EINVAL; 2244 2245 sc->ant_rx = rx_ant; 2246 sc->ant_tx = tx_ant; 2247 2248 if (ah->caps.rx_chainmask == 1) 2249 return 0; 2250 2251 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2252 if (AR_SREV_9100(ah)) 2253 ah->rxchainmask = 0x7; 2254 else 2255 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2256 2257 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2258 ath9k_cmn_reload_chainmask(ah); 2259 2260 return 0; 2261 } 2262 2263 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2264 { 2265 struct ath_softc *sc = hw->priv; 2266 2267 *tx_ant = sc->ant_tx; 2268 *rx_ant = sc->ant_rx; 2269 return 0; 2270 } 2271 2272 static void ath9k_sw_scan_start(struct ieee80211_hw *hw, 2273 struct ieee80211_vif *vif, 2274 const u8 *mac_addr) 2275 { 2276 struct ath_softc *sc = hw->priv; 2277 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2278 set_bit(ATH_OP_SCANNING, &common->op_flags); 2279 } 2280 2281 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw, 2282 struct ieee80211_vif *vif) 2283 { 2284 struct ath_softc *sc = hw->priv; 2285 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2286 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2287 } 2288 2289 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 2290 2291 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc) 2292 { 2293 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2294 2295 if (sc->offchannel.roc_vif) { 2296 ath_dbg(common, CHAN_CTX, 2297 "%s: Aborting RoC\n", __func__); 2298 2299 del_timer_sync(&sc->offchannel.timer); 2300 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2301 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT); 2302 } 2303 2304 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { 2305 ath_dbg(common, CHAN_CTX, 2306 "%s: Aborting HW scan\n", __func__); 2307 2308 del_timer_sync(&sc->offchannel.timer); 2309 ath_scan_complete(sc, true); 2310 } 2311 } 2312 2313 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2314 struct ieee80211_scan_request *hw_req) 2315 { 2316 struct cfg80211_scan_request *req = &hw_req->req; 2317 struct ath_softc *sc = hw->priv; 2318 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2319 int ret = 0; 2320 2321 mutex_lock(&sc->mutex); 2322 2323 if (WARN_ON(sc->offchannel.scan_req)) { 2324 ret = -EBUSY; 2325 goto out; 2326 } 2327 2328 ath9k_ps_wakeup(sc); 2329 set_bit(ATH_OP_SCANNING, &common->op_flags); 2330 sc->offchannel.scan_vif = vif; 2331 sc->offchannel.scan_req = req; 2332 sc->offchannel.scan_idx = 0; 2333 2334 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", 2335 vif->addr); 2336 2337 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2338 ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); 2339 ath_offchannel_next(sc); 2340 } 2341 2342 out: 2343 mutex_unlock(&sc->mutex); 2344 2345 return ret; 2346 } 2347 2348 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, 2349 struct ieee80211_vif *vif) 2350 { 2351 struct ath_softc *sc = hw->priv; 2352 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2353 2354 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); 2355 2356 mutex_lock(&sc->mutex); 2357 del_timer_sync(&sc->offchannel.timer); 2358 ath_scan_complete(sc, true); 2359 mutex_unlock(&sc->mutex); 2360 } 2361 2362 static int ath9k_remain_on_channel(struct ieee80211_hw *hw, 2363 struct ieee80211_vif *vif, 2364 struct ieee80211_channel *chan, int duration, 2365 enum ieee80211_roc_type type) 2366 { 2367 struct ath_softc *sc = hw->priv; 2368 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2369 int ret = 0; 2370 2371 mutex_lock(&sc->mutex); 2372 2373 if (WARN_ON(sc->offchannel.roc_vif)) { 2374 ret = -EBUSY; 2375 goto out; 2376 } 2377 2378 ath9k_ps_wakeup(sc); 2379 sc->offchannel.roc_vif = vif; 2380 sc->offchannel.roc_chan = chan; 2381 sc->offchannel.roc_duration = duration; 2382 2383 ath_dbg(common, CHAN_CTX, 2384 "RoC request on vif: %pM, type: %d duration: %d\n", 2385 vif->addr, type, duration); 2386 2387 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2388 ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); 2389 ath_offchannel_next(sc); 2390 } 2391 2392 out: 2393 mutex_unlock(&sc->mutex); 2394 2395 return ret; 2396 } 2397 2398 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw, 2399 struct ieee80211_vif *vif) 2400 { 2401 struct ath_softc *sc = hw->priv; 2402 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2403 2404 mutex_lock(&sc->mutex); 2405 2406 ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); 2407 del_timer_sync(&sc->offchannel.timer); 2408 2409 if (sc->offchannel.roc_vif) { 2410 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2411 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL); 2412 } 2413 2414 mutex_unlock(&sc->mutex); 2415 2416 return 0; 2417 } 2418 2419 static int ath9k_add_chanctx(struct ieee80211_hw *hw, 2420 struct ieee80211_chanctx_conf *conf) 2421 { 2422 struct ath_softc *sc = hw->priv; 2423 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2424 struct ath_chanctx *ctx, **ptr; 2425 int pos; 2426 2427 mutex_lock(&sc->mutex); 2428 2429 ath_for_each_chanctx(sc, ctx) { 2430 if (ctx->assigned) 2431 continue; 2432 2433 ptr = (void *) conf->drv_priv; 2434 *ptr = ctx; 2435 ctx->assigned = true; 2436 pos = ctx - &sc->chanctx[0]; 2437 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; 2438 2439 ath_dbg(common, CHAN_CTX, 2440 "Add channel context: %d MHz\n", 2441 conf->def.chan->center_freq); 2442 2443 ath_chanctx_set_channel(sc, ctx, &conf->def); 2444 2445 mutex_unlock(&sc->mutex); 2446 return 0; 2447 } 2448 2449 mutex_unlock(&sc->mutex); 2450 return -ENOSPC; 2451 } 2452 2453 2454 static void ath9k_remove_chanctx(struct ieee80211_hw *hw, 2455 struct ieee80211_chanctx_conf *conf) 2456 { 2457 struct ath_softc *sc = hw->priv; 2458 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2459 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2460 2461 mutex_lock(&sc->mutex); 2462 2463 ath_dbg(common, CHAN_CTX, 2464 "Remove channel context: %d MHz\n", 2465 conf->def.chan->center_freq); 2466 2467 ctx->assigned = false; 2468 ctx->hw_queue_base = 0; 2469 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); 2470 2471 mutex_unlock(&sc->mutex); 2472 } 2473 2474 static void ath9k_change_chanctx(struct ieee80211_hw *hw, 2475 struct ieee80211_chanctx_conf *conf, 2476 u32 changed) 2477 { 2478 struct ath_softc *sc = hw->priv; 2479 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2480 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2481 2482 mutex_lock(&sc->mutex); 2483 ath_dbg(common, CHAN_CTX, 2484 "Change channel context: %d MHz\n", 2485 conf->def.chan->center_freq); 2486 ath_chanctx_set_channel(sc, ctx, &conf->def); 2487 mutex_unlock(&sc->mutex); 2488 } 2489 2490 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, 2491 struct ieee80211_vif *vif, 2492 struct ieee80211_chanctx_conf *conf) 2493 { 2494 struct ath_softc *sc = hw->priv; 2495 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2496 struct ath_vif *avp = (void *)vif->drv_priv; 2497 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2498 int i; 2499 2500 ath9k_cancel_pending_offchannel(sc); 2501 2502 mutex_lock(&sc->mutex); 2503 2504 ath_dbg(common, CHAN_CTX, 2505 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", 2506 vif->addr, vif->type, vif->p2p, 2507 conf->def.chan->center_freq); 2508 2509 avp->chanctx = ctx; 2510 ctx->nvifs_assigned++; 2511 list_add_tail(&avp->list, &ctx->vifs); 2512 ath9k_calculate_summary_state(sc, ctx); 2513 for (i = 0; i < IEEE80211_NUM_ACS; i++) 2514 vif->hw_queue[i] = ctx->hw_queue_base + i; 2515 2516 mutex_unlock(&sc->mutex); 2517 2518 return 0; 2519 } 2520 2521 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, 2522 struct ieee80211_vif *vif, 2523 struct ieee80211_chanctx_conf *conf) 2524 { 2525 struct ath_softc *sc = hw->priv; 2526 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2527 struct ath_vif *avp = (void *)vif->drv_priv; 2528 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2529 int ac; 2530 2531 ath9k_cancel_pending_offchannel(sc); 2532 2533 mutex_lock(&sc->mutex); 2534 2535 ath_dbg(common, CHAN_CTX, 2536 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", 2537 vif->addr, vif->type, vif->p2p, 2538 conf->def.chan->center_freq); 2539 2540 avp->chanctx = NULL; 2541 ctx->nvifs_assigned--; 2542 list_del(&avp->list); 2543 ath9k_calculate_summary_state(sc, ctx); 2544 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2545 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; 2546 2547 mutex_unlock(&sc->mutex); 2548 } 2549 2550 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, 2551 struct ieee80211_vif *vif, 2552 u16 duration) 2553 { 2554 struct ath_softc *sc = hw->priv; 2555 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2556 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; 2557 struct ath_beacon_config *cur_conf; 2558 struct ath_chanctx *go_ctx; 2559 unsigned long timeout; 2560 bool changed = false; 2561 u32 beacon_int; 2562 2563 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2564 return; 2565 2566 if (!avp->chanctx) 2567 return; 2568 2569 mutex_lock(&sc->mutex); 2570 2571 spin_lock_bh(&sc->chan_lock); 2572 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) 2573 changed = true; 2574 spin_unlock_bh(&sc->chan_lock); 2575 2576 if (!changed) 2577 goto out; 2578 2579 ath9k_cancel_pending_offchannel(sc); 2580 2581 go_ctx = ath_is_go_chanctx_present(sc); 2582 2583 if (go_ctx) { 2584 /* 2585 * Wait till the GO interface gets a chance 2586 * to send out an NoA. 2587 */ 2588 spin_lock_bh(&sc->chan_lock); 2589 sc->sched.mgd_prepare_tx = true; 2590 cur_conf = &go_ctx->beacon; 2591 beacon_int = TU_TO_USEC(cur_conf->beacon_interval); 2592 spin_unlock_bh(&sc->chan_lock); 2593 2594 timeout = usecs_to_jiffies(beacon_int * 2); 2595 init_completion(&sc->go_beacon); 2596 2597 mutex_unlock(&sc->mutex); 2598 2599 if (wait_for_completion_timeout(&sc->go_beacon, 2600 timeout) == 0) { 2601 ath_dbg(common, CHAN_CTX, 2602 "Failed to send new NoA\n"); 2603 2604 spin_lock_bh(&sc->chan_lock); 2605 sc->sched.mgd_prepare_tx = false; 2606 spin_unlock_bh(&sc->chan_lock); 2607 } 2608 2609 mutex_lock(&sc->mutex); 2610 } 2611 2612 ath_dbg(common, CHAN_CTX, 2613 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n", 2614 __func__, vif->addr); 2615 2616 spin_lock_bh(&sc->chan_lock); 2617 sc->next_chan = avp->chanctx; 2618 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; 2619 spin_unlock_bh(&sc->chan_lock); 2620 2621 ath_chanctx_set_next(sc, true); 2622 out: 2623 mutex_unlock(&sc->mutex); 2624 } 2625 2626 void ath9k_fill_chanctx_ops(void) 2627 { 2628 if (!ath9k_is_chanctx_enabled()) 2629 return; 2630 2631 ath9k_ops.hw_scan = ath9k_hw_scan; 2632 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; 2633 ath9k_ops.remain_on_channel = ath9k_remain_on_channel; 2634 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; 2635 ath9k_ops.add_chanctx = ath9k_add_chanctx; 2636 ath9k_ops.remove_chanctx = ath9k_remove_chanctx; 2637 ath9k_ops.change_chanctx = ath9k_change_chanctx; 2638 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; 2639 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; 2640 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; 2641 } 2642 2643 #endif 2644 2645 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2646 int *dbm) 2647 { 2648 struct ath_softc *sc = hw->priv; 2649 struct ath_vif *avp = (void *)vif->drv_priv; 2650 2651 mutex_lock(&sc->mutex); 2652 if (avp->chanctx) 2653 *dbm = avp->chanctx->cur_txpower; 2654 else 2655 *dbm = sc->cur_chan->cur_txpower; 2656 mutex_unlock(&sc->mutex); 2657 2658 *dbm /= 2; 2659 2660 return 0; 2661 } 2662 2663 struct ieee80211_ops ath9k_ops = { 2664 .tx = ath9k_tx, 2665 .start = ath9k_start, 2666 .stop = ath9k_stop, 2667 .add_interface = ath9k_add_interface, 2668 .change_interface = ath9k_change_interface, 2669 .remove_interface = ath9k_remove_interface, 2670 .config = ath9k_config, 2671 .configure_filter = ath9k_configure_filter, 2672 .sta_state = ath9k_sta_state, 2673 .sta_notify = ath9k_sta_notify, 2674 .conf_tx = ath9k_conf_tx, 2675 .bss_info_changed = ath9k_bss_info_changed, 2676 .set_key = ath9k_set_key, 2677 .get_tsf = ath9k_get_tsf, 2678 .set_tsf = ath9k_set_tsf, 2679 .reset_tsf = ath9k_reset_tsf, 2680 .ampdu_action = ath9k_ampdu_action, 2681 .get_survey = ath9k_get_survey, 2682 .rfkill_poll = ath9k_rfkill_poll_state, 2683 .set_coverage_class = ath9k_set_coverage_class, 2684 .flush = ath9k_flush, 2685 .tx_frames_pending = ath9k_tx_frames_pending, 2686 .tx_last_beacon = ath9k_tx_last_beacon, 2687 .release_buffered_frames = ath9k_release_buffered_frames, 2688 .get_stats = ath9k_get_stats, 2689 .set_antenna = ath9k_set_antenna, 2690 .get_antenna = ath9k_get_antenna, 2691 2692 #ifdef CONFIG_ATH9K_WOW 2693 .suspend = ath9k_suspend, 2694 .resume = ath9k_resume, 2695 .set_wakeup = ath9k_set_wakeup, 2696 #endif 2697 2698 #ifdef CONFIG_ATH9K_DEBUGFS 2699 .get_et_sset_count = ath9k_get_et_sset_count, 2700 .get_et_stats = ath9k_get_et_stats, 2701 .get_et_strings = ath9k_get_et_strings, 2702 #endif 2703 2704 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2705 .sta_add_debugfs = ath9k_sta_add_debugfs, 2706 #endif 2707 .sw_scan_start = ath9k_sw_scan_start, 2708 .sw_scan_complete = ath9k_sw_scan_complete, 2709 .get_txpower = ath9k_get_txpower, 2710 .wake_tx_queue = ath9k_wake_tx_queue, 2711 }; 2712